TWI578411B - 晶片封裝體的製造方法 - Google Patents

晶片封裝體的製造方法 Download PDF

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TWI578411B
TWI578411B TW103112450A TW103112450A TWI578411B TW I578411 B TWI578411 B TW I578411B TW 103112450 A TW103112450 A TW 103112450A TW 103112450 A TW103112450 A TW 103112450A TW I578411 B TWI578411 B TW I578411B
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Taiwan
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layer
chip package
semiconductor substrate
manufacturing
forming
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TW103112450A
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TW201539587A (zh
Inventor
何彥仕
劉滄宇
林佳昇
張義民
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精材科技股份有限公司
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Priority to TW103112450A priority Critical patent/TWI578411B/zh
Priority to CN201510143980.5A priority patent/CN104979426A/zh
Priority to US14/676,478 priority patent/US9685354B2/en
Priority to US14/676,738 priority patent/US9611143B2/en
Publication of TW201539587A publication Critical patent/TW201539587A/zh
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Publication of TWI578411B publication Critical patent/TWI578411B/zh

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    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
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    • B81C1/00896—Temporary protection during separation into individual elements
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Description

晶片封裝體的製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種晶片封裝體的製造方法。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
具有感測功能之晶片封裝體的感測裝置在傳統的製作過程中以及在使用晶片封裝體之感測功能的過程中容易受到汙染或破壞，造成感測裝置的效能降低，進而降低晶片封裝體的可靠度或品質。
因此，有必要尋求一種新穎的晶片封裝體的製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體的製造方法，包括提供一基底及一蓋層，其中基底內具有一感測裝置鄰近於基底的一第一表面。透過一黏著層將蓋層貼附於基底的第一表面上，其中黏著層覆蓋感測裝置。沿著一方向，對基底、黏著層及蓋層進行一切割製程，以形成獨立的晶片封裝體。
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
120‧‧‧晶片區
140‧‧‧導電墊
160‧‧‧感測裝置
180‧‧‧黏著層
200‧‧‧蓋層
310‧‧‧第一開口
320‧‧‧絕緣層
340‧‧‧重佈線層
360‧‧‧鈍化保護層
380‧‧‧第二開口
400‧‧‧導電結構
420‧‧‧保護層
500‧‧‧電路板
540‧‧‧接觸墊
560‧‧‧焊線
L‧‧‧切割道
第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖。
第3及4圖係繪示出根據本發明不同實施例之晶片封裝體的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理 感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完 成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
以下配合第1A至1E圖說明本發明一實施例之晶片 封裝體的製造方法，其中第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
請參照第1A圖，提供一基底100，其具有一第一表 面100a及與其相對的一第二表面100b，且包括複數晶片區120。在一實施例中，基底100可為一矽基底或其他半導體基底。在另一實施例中，基底100為一矽晶圓，以利於進行晶圓級封裝製程。
在本實施例中，基底100的每一晶片區120內具有複數導電墊，其可鄰近於第一表面100a。為簡化圖式，此處僅 繪示出相鄰的兩個晶片區120以及分別位於基底100的單一晶片區120內的兩個導電墊140。在一實施例中，導電墊140可為單層導電層或具有多層之導電層結構。此處，僅以單層導電層作為範例說明。
在本實施例中，基底100的每一晶片區120內具有 一感測裝置160，其可鄰近於基底100的第一表面100a。在一實施例中，感測裝置160可包括影像感測元件。在另一實施例中，感測裝置160用以感測生物特徵，且可包括一指紋辨識元件。 又另一實施例中，感測裝置160用以感測環境特徵，且可包括一溫度感測元件、一溼度感測元件、一壓力感測元件或其他適合的感測元件。在一實施例中，感測裝置160可透過內連線結構(未繪示)而與導電墊140電性連接。
接著，可透過一黏著層180，將一蓋層200貼附於 基底100的第一表面100a上。在本實施例中，黏著層180覆蓋感測裝置160，且黏著層180與感測裝置160之間不具有空隙。在一實施例中，蓋層200與感測裝置160之間僅具有黏著層180，而不具有其他間隔層(或稱作圍堰(dam)。在一實施例中，黏著層180可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的黏著材料。再者，蓋層200包括玻璃、氮化鋁(AlN)、膠帶、藍寶石(Sapphire)或其他適合的保護材料。
請參照第1B圖，以蓋層200作為承載基板，對基底 100的第二表面100b進行薄化製程(例如，蝕刻製程、銑削 (milling)製程、機械研磨(mechanical grinding)製程或化學機械研磨(chemical mechanical polishing)製程)，以減少基底100的厚度。
接著，可透過微影製程及蝕刻製程(例如，乾蝕刻 製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，在基底100的每一晶片區120內形成複數第一開口310。第一開口310自基底100的第二表面100b朝第一表面100a延伸，且分別暴露出鄰近於第一表面100a的對應的導電墊140。
接著，可透過沉積製程(例如，塗佈製程、物理氣 相沈積製程、化學氣相沈積製程或其他適合的製程)，在基底100的第二表面100b上順應性形成一絕緣層320，其延伸至基底100的第一開口310內。在本實施例中，絕緣層320可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
請參照第1C圖，可透過微影製程及蝕刻製程(例 如，乾蝕刻製程、濕蝕刻製程、電漿蝕刻製程、反應性離子蝕刻製程或其他適合的製程)，去除第一開口310的底部上的絕緣層320，以暴露出導電墊140的表面。接著，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層320上形成圖案化的重佈線層340。
重佈線層340順應性延伸至基底100的第一開口 310的底部，且與暴露出的導電墊140直接接觸，以電性連接至導電墊140，並透過絕緣層320與基底100電性隔離。因此，第一開口310內的重佈線層340也稱為矽通孔電極(through silicon via，TSV)。在一實施例中，重佈線層340可包括銅、鋁、金、鉑、鎳、錫、前述之組合、導電高分子材料、導電陶瓷材料(例如，氧化銦錫或氧化銦鋅)或其他適合的導電材料。
在另一實施例中，基底100的第一開口310可暴露 出導電墊140的側壁，且重佈線層340透過絕緣層320與基底100電性隔離，並與暴露出的導電墊140的側壁直接接觸，而以T型接觸(T-contact)的方式電性連接至導電墊140。又另一實施例中，基底100的第一開口310可至少穿過導電墊140，使得重佈線層340可與導電墊140的內部直接接觸，而以環型接觸(ring-contact)的方式電性連接至導電墊140。
接著，可透過沉積製程，在重佈線層340上形成一 鈍化保護層360，且填入基底100的第一開口310內，以覆蓋重佈線層340。接著，可透過微影製程及蝕刻製程，在每一晶片區120的鈍化保護層360內形成複數第二開口380，以暴露出位於基底100的第二表面100b上的重佈線層340的一部分。在本實施例中，鈍化保護層360可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在另一實施例中，鈍化保護層360可包括光阻 材料，且可透過曝光製程及顯影製程，在鈍化保護層360內形成第二開口380。
請參照第1D圖，在鈍化保護層360的第二開口380 內形成導電結構(例如，焊球、凸塊或導電柱)400，以直接接觸暴露出的重佈線層340，而與圖案化的重佈線層340電性連接。 舉例來說，可透過電鍍製程、網版印刷製程或其他適合的製程，在鈍化保護層360的第二開口380內形成焊料(solder)，且進行迴焊(reflow)製程，以形成導電結構400。另外，雖然未繪示於圖式中，但從上視方向來看，導電結構400可在基底100的第二表面100b上排列成一矩陣。在本實施例中，導電結構400可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。
接著，在鈍化保護層360及導電結構400上形成一 保護層420(例如，膠帶)，以提供平坦的表面及保護導電結構400。接著，以保護層420作為支撐，沿著相鄰晶片區120之間的切割道L，且沿著自蓋層200朝基底100的方向，對基底100、黏著層180及蓋層200進行切割製程，並去除保護層420，以形成複數獨立的晶片封裝體，如第1E圖所示。在上述實施例中，蓋層200由透光材料(例如，玻璃、藍寶石或其他適合的透光材料)所構成，有利於沿著自蓋層200朝基底100的方向進行切割製程，進而提升對位的精準度。
在另一實施例中，如第2圖所示，亦可直接利用蓋 層200提供平坦的表面，沿著自基底100朝蓋層200的方向進行上述切割製程，而無需額外形成保護導電結構400的保護層(例 如，第1D圖中的保護層420)。再者，蓋層200由非透光材料(例如，氮化鋁、膠帶或其他適合的非透光材料)所構成時，可預先在基底100的第二表面100b上方形成對準標記(alignment mark)，以提升切割製程的精準度。舉例來說，在形成鈍化保護層360的第二開口380的步驟中，可同時在鈍化保護層360內形成作為對準標記的孔洞(未繪示)，以利於後續沿著自基底100朝蓋層200的方向進行切割製程。
在本實施例中，可進一步在獨立的晶片封裝體的 基底100的第二表面100b上提供一電路板(未繪示)，且透過導電結構400將重佈線層340及導電墊140電性連接至電路板的接觸墊(未繪示)。
請參照第3及4圖，其繪示出根據本發明不同實施 例之晶片封裝體的剖面示意圖，其中相同於第1E圖中的部件係使用相同的標號並省略其說明。第3圖中的晶片封裝體之製造方法類似於第1E圖中的晶片封裝體之製造方法，差異在於第3圖中的晶片封裝體之製造方法未包括在鈍化保護層360的第二開口380內形成第1E圖中的導電結構400，而在進行切割製程之後，仍暴露出位於基底100的第二表面100b上的重佈線層340的一部分。再者，另一差異在於第3圖中的晶片封裝體之製造方法更包括在進行切割製程之後，在基底100的第二表面100b上提供一電路板(例如，軟性印刷電路板(flexible print circuit，FPC))500，且進行打線接合(wire bond)製程，在暴露出的重佈線層340上形成對應的焊線560，並將焊線560延伸至電路板500內的接觸墊540上，以將基底100內的導電墊140電性連接至電 路板500內對應的接觸墊540。另外，雖然第3圖中的焊線560分別自感測裝置160相對兩側的基底100的第二表面100b上延伸至電路板500上，然而可以理解的是，各個焊線560可皆自感測裝置160的同一側或分別自感測裝置160的相鄰兩側延伸至電路板500上。
再者，第4圖中的晶片封裝體之製造方法類似於第 1E圖中的晶片封裝體之製造方法，差異在於第4圖中的晶片封裝體之製造方法中形成第一開口310的步驟更包括透過同一蝕刻製程，同時去除基底100的側壁的一部分，以暴露出黏著層180的一部分，使得晶片封裝體具有階梯狀的側壁。
在其他實施例中，可結合第3及4圖中的晶片封裝 體之製造方法的實施例。舉例來說，在形成獨立的晶片封裝體之前，未在第4圖中的晶片封裝體的鈍化保護層360的第二開口380內形成導電結構400，而在形成獨立的晶片封裝體之後，仍暴露出位於基底100的第二表面100b上的重佈線層340的一部分。接著，可進一步在第4圖中的晶片封裝體的基底100的第二表面100b上提供第3圖中的電路板500，且在暴露出的重佈線層340上及電路板500內對應的接觸墊540上形成第3圖中的焊線560，以透過焊線560，將基底100內的導電墊140電性連接至電路板500內的接觸墊540。
根據本發明的上述實施例，透過黏著層180將蓋層 200貼附於基底100的第一表面100a上，且蓋層200及黏著層180覆蓋基底100的第一表面100a上的感測裝置160而與感測裝置160之間不具有空隙，能夠在晶片封裝體的製作過程中以及在 使用晶片封裝體之感測功能的過程中保護感測裝置，避免受到汙染或破壞，因此可改善感測裝置的感測效能，進而提升晶片封裝體的可靠度或品質。
再者，採用晶圓級製程來製作晶片封裝體，可大 量生產晶片封裝體，進而降低成本並節省製程時間。另外，由於使用矽通孔電極、環型接觸或T型接觸作為具有感測裝置之基底的外部電性連接的路徑，而不需使用焊線及導線架，能夠節省成本，並使得晶片封裝體的尺寸能夠進一步縮小。
雖然本發明已以較佳實施例揭露如上，然其並非 用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施例。
100‧‧‧基底
100a‧‧‧第一表面
100b‧‧‧第二表面
120‧‧‧晶片區
140‧‧‧導電墊
160‧‧‧感測裝置
180‧‧‧黏著層
200‧‧‧蓋層
310‧‧‧第一開口
320‧‧‧絕緣層
340‧‧‧重佈線層
360‧‧‧鈍化保護層
380‧‧‧第二開口
400‧‧‧導電結構
420‧‧‧保護層
L‧‧‧切割道

Claims (11)

  1. 一種晶片封裝體的製造方法，包括：提供一半導體基底及一蓋層，其中該半導體基底內具有一感測裝置和一導電墊鄰近於該半導體基底的一第一表面；透過一黏著層將該蓋層貼附於該半導體基底的該第一表面上，其中該黏著層覆蓋該感測裝置；以及沿著一方向，對該半導體基底、該黏著層及該蓋層進行一切割製程，以形成獨立的晶片封裝體。
  2. 如申請專利範圍第1項所述之晶片封裝體的製造方法，其中該感測裝置與該黏著層之間不具有空隙。
  3. 如申請專利範圍第1項所述之晶片封裝體的製造方法，其中該方向為自該蓋層朝該半導體基底。
  4. 如申請專利範圍第1項所述之晶片封裝體的製造方法，其中該方向為自該半導體基底朝該蓋層。
  5. 如申請專利範圍第1項所述之晶片封裝體的製造方法，其中該蓋層包括玻璃、氮化鋁、膠帶或藍寶石。
  6. 如申請專利範圍第1項所述之晶片封裝體的製造方法，更包括在進行該切割製程之前，在該半導體基底相對於該第一表面的一第二表面上形成一導電結構以及覆蓋該導電結構的一保護層。
  7. 如申請專利範圍第1項所述之晶片封裝體的製造方法，其中在進行該切割製程之前，該晶片封裝體的製造方法更包括：在該半導體基底內形成一第一開口，其自該半導體基底相 對於該第一表面的一第二表面朝該第一表面延伸，且暴露出該導電墊；在該第二表面上形成一絕緣層，並延伸至該第一開口內；在該絕緣層上形成一重佈線層，並接觸暴露出的該導電墊；以及在該重佈線層上形成一鈍化保護層，並暴露出位於該第二表面上一部分的該重佈線層。
  8. 如申請專利範圍第7項所述之晶片封裝體的製造方法，更包括在進行該切割製程之前，在暴露出的該重佈線層上形成焊球、凸塊或導電柱。
  9. 如申請專利範圍第7項所述之晶片封裝體的製造方法，更包括在進行該切割製程之後，在暴露出的該重佈線層上形成焊線。
  10. 如申請專利範圍第7項所述之晶片封裝體的製造方法，形成該第一開口的步驟更包括去除該半導體基底的側壁的一部分，以暴露出該黏著層的一部分。
  11. 如申請專利範圍第7項所述之晶片封裝體的製造方法，更包括在進行該切割製程之前，薄化該半導體基底。
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