TWI529892B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI529892B
TWI529892B TW103127225A TW103127225A TWI529892B TW I529892 B TWI529892 B TW I529892B TW 103127225 A TW103127225 A TW 103127225A TW 103127225 A TW103127225 A TW 103127225A TW I529892 B TWI529892 B TW I529892B
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Taiwan
Prior art keywords
bump
device substrate
chip package
insulating layer
electrically connected
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TW103127225A
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English (en)
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TW201543636A (zh
Inventor
劉建宏
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精材科技股份有限公司
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Application filed by 精材科技股份有限公司 filed Critical 精材科技股份有限公司
Priority to TW103127225A priority Critical patent/TWI529892B/zh
Priority to CN201410461293.3A priority patent/CN105097744A/zh
Priority to US14/706,896 priority patent/US9761510B2/en
Publication of TW201543636A publication Critical patent/TW201543636A/zh
Application granted granted Critical
Publication of TWI529892B publication Critical patent/TWI529892B/zh

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Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝技術，特別為有關於一種晶片封裝體及其製造方法。
晶片封裝製程是形成電子產品過程中之重要步驟。晶片封裝體除了將晶片保護於其中，使其免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
晶片封裝體通常與其他積體電路晶片各自獨立地設置於電路板上，再透過打線彼此電性連接。
然而，上述製造方法限制了電路板的尺寸，進而導致電子產品的尺寸難以進一步縮小。
因此，有必要尋求一種新穎的晶片封裝體及其製造方法，其能夠解決或改善上述的問題。
本發明實施例係提供一種晶片封裝體，包括一第一裝置基底，貼附於一第二裝置基底的一第一表面上。一第三裝置基底貼附於第二裝置基底相對於第一表面的一第二表面上。一絕緣層覆蓋第一裝置基底、第二裝置基底及第三裝置基底，其中絕緣層內具有至少一開口。至少一凸塊設置於開口的底部下方。一重佈線層設置於絕緣層上，且經由開口電性連接 至凸塊。
本發明實施例係提供一種晶片封裝體的製造方法，包括將一第一裝置基底貼附於一第二裝置基底的一第一表面上。將一第三裝置基底貼附於第二裝置基底相對於第一表面的一第二表面上。形成至少一凸塊及一絕緣層，其中絕緣層覆蓋第一裝置基底、第二裝置基底及第三裝置基底，且具有至少一開口，使凸塊形成於開口的底部下方。在絕緣層上形成一重佈線層，其經由開口電性連接至凸塊。
100‧‧‧第一裝置基底
110、210、310‧‧‧元件區
120‧‧‧晶片區
130‧‧‧第一接合墊
140‧‧‧第一導電墊
150、160、250、260、360‧‧‧內連線結構
200‧‧‧第二裝置基底
200a‧‧‧第一表面
200b‧‧‧第二表面
230‧‧‧第二接合墊
240‧‧‧第二導電墊
300‧‧‧第三裝置基底
330‧‧‧第三接合墊
340‧‧‧第三導電墊
370‧‧‧第一凸塊
380‧‧‧導電結構
400、520‧‧‧絕緣層
420、540‧‧‧開口
440、560‧‧‧重佈線層
460‧‧‧鈍化保護層
480‧‧‧開口
500‧‧‧第二凸塊
510a‧‧‧第三凸塊
510b‧‧‧第四凸塊
I‧‧‧可見界面
第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
第2及3圖係繪示出根據本發明不同實施例之晶片封裝體的剖面示意圖。
第4A至4F圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖。
第5至8圖係繪示出根據本發明其他實施例之晶片封裝體的剖面示意圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定型式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅 為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝微機電系統晶片。然其應用不限於此，例如在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System，MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線、電容及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package，WSP)製程對影像感測元件、發光二極體(light-emitting diodes，LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體 電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。
請參照第1E圖，其繪示出根據本發明一實施例之晶片封裝體的剖面示意圖。在本實施例中，晶片封裝體包括一第一裝置基底100、一第二裝置基底200、一第三裝置基底300、一絕緣層400、複數第一凸塊370及一圖案化的重佈線層440。在一實施例中，第一裝置基底100可為一矽基底或其他半導體基底。在本實施例中，第一裝置基底100內包括一個或一個以上的第一接合墊130及第一導電墊140，其可鄰近於第一裝置基底100的上表面。在一實施例中，第一接合墊130及第一導電墊140可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明，且僅繪示出第一裝置基底100內的兩個第一接合墊130及兩個第一導電墊140作為範例說明。
在本實施例中，第一裝置基底100可為包括一元件區110的晶片，且元件區110內包括一電子元件(未繪示)。在一實施例中，元件區110內的電子元件可透過第一裝置基底100內的內連線結構而與第一接合墊130及第一導電墊140電性連接。為簡化圖式，此處僅以虛線150及160分別表示第一接合墊130及第一導電墊140與元件區110之間的內連線結構。
第二裝置基底200具有一第一表面200a及與其相對的一第二表面200b，且可透過一黏著層(未繪示)將第二裝置基底200的第一表面200a貼附於第一裝置基底100的上表面。在一實施例中，第二裝置基底200可為一矽基底或其他半導體基 底。在本實施例中，第二裝置基底200內包括一個或一個以上的第二導電墊240，其可鄰近於第二表面200b。再者，第二導電墊240的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第二裝置基底200內由單層導電層所構成的一個第二導電墊240作為範例說明。
在本實施例中，第二裝置基底200可為包括一元件區210的晶片，且元件區210內包括一電子元件(未繪示)。相似地，元件區210內的電子元件可透過第二裝置基底200的內連線結構(如虛線260所示)而與第二導電墊240電性連接。
第三裝置基底300可透過另一黏著層(未繪示)貼附於第二裝置基底200的第二表面200b上。在一實施例中，第三裝置基底300可為一矽基底或其他半導體基底。在本實施例中，第三裝置基底300內包括一個或一個以上的第三導電墊340，其可鄰近於第三裝置基底300的上表面(即，相對於第二表面100b的表面)。再者，第三導電墊340的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第三裝置基底300內由單層導電層所構成的一個第三導電墊340作為範例說明。
在本實施例中，第三裝置基底300可為包括一元件區310的晶片，且元件區310內包括一電子元件(未繪示)。相似地，元件區310內的電子元件可透過第三裝置基底300的內連線結構(如虛線360所示)而與第三導電墊340電性連接。
在本實施例中，元件區110、210及310內的電子元件可為積體/整合被動元件(Integrated passive device，IPD)、磁性元件、無線射頻(Radio Frequency，RF)元件、振盪器 (oscillator)、微機電系統、感測元件或其他適合的電子元件。
在本實施例中，第二裝置基底200的尺寸大於第三裝置基底300的尺寸且小於第一裝置基底100的尺寸。再者，當第二裝置基底200的尺寸足夠大時，可在第二裝置基底200的第二表面200b上設置一個以上具有不同積體電路功能的第三裝置基底300。再者，當第一裝置基底100的尺寸足夠大時，可在第一裝置基底100上設置一個以上具有不同積體電路功能的第二裝置基底200。
絕緣層400覆蓋第一裝置基底100、第二裝置基底200及第三裝置基底300，且絕緣層400內具有複數開口420。在本實施例中，開口420對應於第一裝置基底100內的第一接合墊130。在本實施例中，絕緣層400可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂(polyimide)、苯環丁烯(butylcyclobutene，BCB)、聚對二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(acrylates))或其他適合的絕緣材料。
第一凸塊370設置於絕緣層400內的開口420的底部下方，且開口420暴露出第一凸塊370。。在本實施例中，第一凸塊370對應設置於第一裝置基底100內的第一接合墊130上，並與其電性連接。在本實施例中，第一凸塊370為接合球。在其他實施例中，第一凸塊370也可為導電柱或其他適合的導電結構。在本實施例中，第一凸塊270可包括金或其他適合的導電材料。
複數導電結構380設置於絕緣層400內，其分別將第二裝置基底200內的第二導電墊240及第三裝置基底300內的第三導電墊340電性連接至第一裝置基底100內對應的第一導電墊140。舉例來說，其中一個導電結構380設置於對應的第一導電墊140及第二導電墊240上，並使元件區110及210內的電子元件彼此電性連接。再者，另一個導電結構380設置於對應的第一導電墊140及第三導電墊340上，並使元件區110及310內的電子元件彼此電性連接。在本實施例中，導電結構380由設置於導電墊上的接合球(bonding ball)及延伸於接合球之間的接線(wire)所構成。再者，導電結構380可包括金或其他適合的導電材料。在一實施例中，第一凸塊370的材料相同於導電結構380的材料。
圖案化的重佈線層440設置於絕緣層400上，且填入絕緣層400的開口420內，以經由開口420電性連接至位於開口420底部下方的第一凸塊370。在本實施例中，重佈線層440填滿絕緣層400的開口420。在其他實施例中，重佈線層440可順應性設置於開口420的側壁及底部，而未填滿絕緣層400的開口420。在一實施例中，重佈線層440可包括銅、鋁、金、鉑、鎳、錫、前述之組合或其他適合的導電材料。
一鈍化保護(passivation)層460設置於重佈線層440及絕緣層400上，且具有複數開口480，暴露出位於絕緣層400上的重佈線層440的一部分。在本實施例中，鈍化保護層460可包括環氧樹脂、綠漆(solder mask)、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子 材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)、光阻材料或其他適合的絕緣材料。
複數第二凸塊500對應地設置於鈍化保護層460的開口480內，以直接接觸暴露出的重佈線層440，而與重佈線層440電性連接。在本實施例中，第二凸塊500可排列為一矩陣(未繪示)，以利於後續能提供穩固的接合。可以理解的是，導電結構380、第一凸塊370及第二凸塊500的位置係取決於設計需求而不限定於此。
在本實施例中，第二凸塊500可為凸塊(例如，接合球或導電柱)或其他適合的導電結構，且可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。舉例來說，第二凸塊500可為焊球(solder ball)。在一實施例中，第一凸塊370及第二凸塊500皆為接合球，且第二凸塊500的尺寸大於第一凸塊370的尺寸。在一實施例中，第二凸塊500的材料不同於第一凸塊370的材料。
請參照第2及3圖，其繪示出根據本發明不同實施例之晶片封裝體的剖面示意圖，其中相同於前述第1E圖的實施例的部件係使用相同的標號並省略其說明。第2圖中的晶片封裝體之結構類似於第1E圖中的晶片封裝體之結構，差異在於第2圖中的第一裝置基底100內不具有第1E圖中的第一接合墊130，而第二裝置基底200內具有兩個第二接合墊230及兩個第二導電墊240，其可分別透過第二裝置基底200內的內連線結構(如虛線250及260所示)而與元件區210內的電子元件電性連接，且第二接合墊230的結構類似於第一接合墊130的結構。再 者，第2圖中的兩個第一凸塊370對應設置於第二裝置基底200內的兩個第二接合墊230上，並與其電性連接。
第2圖中的第三裝置基底300內具有兩個第三導電墊340透過第三裝置基底300的內連線結構(如虛線360所示)而與元件區310內的電子元件電性連接。再者，絕緣層400內包括三個導電結構380，其分別將第一裝置基底100內的兩個第一導電墊140、第二裝置基底200內的兩個第二導電墊240及第三裝置基底300內的兩個第三導電墊340的其中兩者彼此電性連接。
再者，第3圖中的晶片封裝體之結構類似於第2圖中的晶片封裝體之結構，差異在於第3圖中的第一裝置基底100內具有一個第一接合墊130，且一個第一凸塊370設置於第一裝置基底100內的第一接合墊130上並與其電性連接，而另一個第一凸塊370設置於第二裝置基底200內的第二接合墊230上並與其電性連接。可以理解的是，上述實施例中接合墊、導電墊及導電結構的位置及數量僅為範例說明，本發明並未侷限於此。
根據本發明的上述實施例，可將多個不同尺寸的裝置基底/晶片彼此垂直堆疊而將其整合於同一晶片封裝體內，使得單一晶片封裝體具有多種積體電路功能，因此可縮小後續接合的電路板的尺寸，進而能夠進一步縮小電子產品的尺寸。
以下配合第1A至1E圖說明本發明一實施例之晶片封裝體的製造方法，其中第1A至1E圖係繪示出根據本發明一實施例之晶片封裝體的製造方法的剖面示意圖。
請參照第1A圖，提供一第一裝置基底100。第一裝 置基底100包括複數晶片區。在一實施例中，第一裝置基底100可為一矽基底或其他半導體基底。舉例來說，第一裝置基底100可為一矽晶圓，以利於進行晶圓級封裝製程。
在本實施例中，第一裝置基底100的每一晶片區內具有一個或一個以上的第一接合墊及第一導電墊，其可鄰近於第一裝置基底100的上表面。為簡化圖式，此處僅繪示出第一裝置基底100的單一晶片區120以及位於其中的兩個第一接合墊130及兩個第一導電墊140。在一實施例中，第一接合墊130及第一導電墊140可為單層導電層或具有多層之導電層結構。此處，僅以單層導電層作為範例說明。
在本實施例中，每一晶片區120的第一裝置基底100內包括一元件區110，且元件區110內可包括一電子元件(未繪示)。在一實施例中，元件區110內的電子元件可透過第一裝置基底100內的內連線結構而與第一接合墊130及第一導電墊140電性連接。為簡化圖式，此處僅以虛線150及160分別表示第一接合墊130及第一導電墊140與元件區110之間的內連線結構。
接著，在每一晶片區120內的第一裝置基底100上提供一第二裝置基底200及一第三裝置基底300。舉例來說，可透過黏著層(未繪示)分別將第二裝置基底200的一第一表面200a貼附於第一裝置基底100的上表面上，且將第三裝置基底300貼附於第二裝置基底200相對於第一表面200a的一第二表面200b上。
在一實施例中，第二裝置基底200可為一矽基底或 其他半導體基底。在本實施例中，第二裝置基底200內包括一個或一個以上的第二導電墊240，其可鄰近於第二表面200b。再者，第二導電墊240的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第二裝置基底200內由單層導電層所構成的一個第二導電墊240作為範例說明。
在本實施例中，第二裝置基底200內包括一元件區210，且元件區210內可包括一電子元件(未繪示)。相似地，元件區210內的電子元件可透過第二裝置基底200的內連線結構(如虛線260所示)而與第二導電墊240電性連接。
在其他實施例中，如第2及3圖所示，第二裝置基底200內可更包括一個或一個以上的第二接合墊230，其可透過第二裝置基底200內的內連線結構(如虛線250所示)而與元件區210內的電子元件電性連接。
在一實施例中，第三裝置基底300可為一矽基底或其他半導體基底。在本實施例中，第三裝置基底300內包括一個或一個以上的第三導電墊340，其可鄰近於第三裝置基底300的上表面(即，相對於第二表面100b的表面)。再者，第三導電墊340的結構類似於第一導電墊140的結構。為簡化圖式，此處僅繪示出第三裝置基底300內由單層導電層所構成的一個第三導電墊340作為範例說明。
在本實施例中，第三裝置基底300內包括一元件區310，且元件區310內可包括一電子元件(未繪示)。相似地，元件區310內的電子元件可透過第三裝置基底300的內連線結構(如虛線360所示)而與第三導電墊340電性連接。
在本實施例中，元件區110、210及310內的電子元件可為積體/整合被動元件、磁性元件、無線射頻元件、振盪器、微機電系統、感測元件或其他適合的電子元件。
在本實施例中，第二裝置基底200的尺寸大於第三裝置基底300的尺寸且小於第一裝置基底100的尺寸。再者，當第二裝置基底200的尺寸足夠大時，可在第二裝置基底200的第二表面200b上形成一個以上具有不同積體電路功能的第三裝置基底300。再者，當第一裝置基底100的尺寸足夠大時，可在第一裝置基底100上形成一個以上具有不同積體電路功能的第二裝置基底200。
請參照第1B圖，可透過打線接合(Wire Bonding)製程，將複數第一凸塊370形成於第一裝置基底100內對應的第一接合墊130上，並與其電性連接，且形成複數導電結構380，以分別將第二裝置基底200內的第二導電墊240及第三裝置基底300內的第三導電墊340電性連接至第一裝置基底100內對應的第一導電墊140。舉例來說，其中一個導電結構380設置於對應的第一導電墊140及第二導電墊240上，並使元件區110及210內的電子元件彼此電性連接。再者，另一個導電結構380設置於對應的第一導電墊140及第三導電墊340上，並使元件區110及310內的電子元件彼此電性連接。在一實施例中，可透過同一打線接合製程，形成第一凸塊370及導電結構380。在其他實施例中，可透過個別的打線接合製程，分別形成第一凸塊370及導電結構380。
在另一實施例中，如第2圖所示，兩個第一凸塊370 可皆形成於第二裝置基底200內對應的第二接合墊230上，並與其電性連接。又另一實施例中，如第3圖所示，可將一個第一凸塊370形成於第一裝置基底100內的第一接合墊130上並與其電性連接，而將另一個第一凸塊370形成於第二裝置基底200內的第二接合墊230上並與其電性連接。
在第2及3圖的實施例中，第三裝置基底300內包括兩個第三導電墊340，且可在第一裝置基底100上形成三個導電結構380，以分別將第一裝置基底100內的兩個第一導電墊140、第二裝置基底200內的兩個第二導電墊240及第三裝置基底300內的兩個第三導電墊340的其中兩者彼此電性連接。舉例來說，兩個導電結構380分別將第三裝置基底300內的兩個第三導電墊340電性連接至第一裝置基底100內對應的第一導電墊140及第二裝置基底200內對應的第二導電墊240，而另一個導電結構380則將第一裝置基底100內的另一個第一導電墊140對應地電性連接至第二裝置基底200內的另一個第二導電墊240。在其他實施例中，可取決於設計需求而選擇性形成導電結構380，本發明並不限定於此。
在本實施例中，第一凸塊370為接合球。在其他實施例中，第一凸塊370也可為導電柱或其他適合的導電結構。在本實施例中，第一凸塊370可包括金或其他適合的導電材料。
根據本發明實施例，第一凸塊370由能夠與接合墊的材料直接共晶接合的材料(例如，金)所構成，因此第一凸塊370可直接形成於接合墊上，且可採用打線接合製程而非迴焊製程來形成第一凸塊370，因此能夠簡化製程。
在本實施例中，導電結構380由設置於導電墊上的接合球及延伸於接合球之間的接線所構成。再者，導電結構380可包括金或其他適合的導電材料。在一實施例中，第一凸塊370的材料相同於導電結構380的材料。
請參照第1C圖，可透過模塑成型(molding)製程或沉積製程(例如，印刷製程、塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一裝置基底100上形成一絕緣層400，以覆蓋第一裝置基底100、第二裝置基底200及第三裝置基底300，並使得導電結構380形成於絕緣層400內。在本實施例中，絕緣層400可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。
接著，可透過雷射鑽孔(laser drilling)製程或微影及蝕刻製程(例如，乾蝕刻製程或濕蝕刻製程)，在絕緣層400內形成複數開口420。在本實施例中，開口420對應於第一裝置基底100內的第一接合墊130，使得第一凸塊370形成於絕緣層400內的開口420的底部下方，且開口420暴露出第一凸塊370。
在另一實施例中，如第2圖所示，開口420皆對應於第二裝置基底200內的第二接合墊230。又另一實施例中，如第3圖所示，開口420可分別對應於第一裝置基底100內的第一接合墊130以及第二裝置基底200內的第二接合墊230。
在本實施例中，第一接合墊130及第二接合墊230上的第一凸塊370可於形成開口420的製程(例如，雷射鑽孔製 程)中作為緩衝層，以避免上述製程破壞第一接合墊130及第二接合墊230，因此能夠提升晶片封裝體的可靠度或品質。再者，由於第一接合墊130及第二接合墊230上設置有第一凸塊370，因此可降低開口420的深度，進而可降低開口420的深寬比(aspect ratio，AR)而有利於製作開口420。另外，當開口420對應於第二裝置基底200內的第二接合墊230時，可更進一步降低開口420的深度。
請參照第1D圖，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層400上形成圖案化的重佈線層440，且填入絕緣層400的開口420內，以經由開口420電性連接至位於開口420底部下方的第一凸塊370。在本實施例中，重佈線層440填滿絕緣層400的開口420。在其他實施例中，重佈線層440可順應性形成於開口420的側壁及底部，而未填滿絕緣層400的開口420。在一實施例中，重佈線層440可包括銅、鋁、金、鉑、鎳、錫、前述之組合或其他適合的導電材料。
接著，可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在重佈線層440及絕緣層400上形成一鈍化保護層460。在本實施例中，鈍化保護層460可包括環氧樹脂、綠漆、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在 另一實施例中，鈍化保護層460可包括光阻材料，且可透過微影製程，在鈍化保護層460內形成開口480。
請參照第1E圖，可透過微影製程及蝕刻製程，在每一晶片區120的鈍化保護層460內形成複數開口480，以暴露出位於絕緣層400上的重佈線層440的一部分。接著，將第二凸塊500對應地設置於鈍化保護層460的開口480內，以直接接觸暴露出的重佈線層440，而與重佈線層440電性連接。在本實施例中，第二凸塊500可排列為一矩陣(未繪示)，以利於後續能提供穩固的接合。可以理解的是，導電結構380、第一凸塊370及第二凸塊500的位置係取決於設計需求而不限定於此。
在本實施例中，第二凸塊500可為凸塊(例如，接合球或導電柱)或其他適合的導電結構。舉例來說，可透過電鍍製程、網版印刷製程或其他適合的製程，在鈍化保護層460的開口480內形成焊料，且進行迴焊製程而形成焊球，以作為第二凸塊500。在本實施例中，第二凸塊500可包括錫、鉛、銅、金、鎳、前述之組合或其他適合的導電材料。
在一實施例中，第一凸塊370及第二凸塊500皆為接合球，且第二凸塊500的尺寸大於第一凸塊370的尺寸。在一實施例中，第二凸塊500的材料不同於第一凸塊370的材料。在一實施例中，第二凸塊500的形成方法不同於第一凸塊370的形成方法。舉例來說，第二凸塊500透過迴焊製程所形成，而第一凸塊370透過打線接合製程所形成。
接著，可沿著相鄰晶片區120之間的切割道(未繪示)，對第一裝置基底100及絕緣層400進行切割製程，以形成 複數獨立的晶片封裝體。在本實施例中，可進一步在獨立的晶片封裝體上提供一電路板(未繪示)，且透過第二凸塊500將第一裝置基底100、第二裝置基底200及第三裝置基底300內的元件區110、210及310內的電子元件電性連接至電路板。
根據本發明的上述實施例，可將多個不同尺寸的裝置基底/晶片彼此垂直堆疊，進而將其整合於同一晶片封裝體內，使得單一晶片封裝體具有多種積體電路功能，因此可縮小後續接合的電路板的尺寸。如此一來，能夠進一步縮小電子產品的尺寸。再者，由於採用接線(即，導電結構380)將裝置基底內的電子元件彼此電性連接，且透過絕緣層400的開口420內的重佈線層440及第一凸塊370作為晶片封裝體外部電性連接的路徑，而無需於裝置基底內形成矽通孔電極，因此可簡化製程且降低成本。另外，採用晶圓級製程來製作晶片封裝體，可大量生產晶片封裝體，進而降低成本並節省製程時間。
以下配合第4A至4F圖說明本發明另一實施例之晶片封裝體的製造方法，其中第4A至4F圖係繪示出根據本發明另一實施例之晶片封裝體的製造方法的剖面示意圖，且第4A至4F圖中相同於前述第1A至1E圖的實施例的部件係使用相同的標號並省略其說明。
請參照第4A圖，提供垂直堆疊的一第一裝置基底100及一第二裝置基底200。在本實施例中，第二裝置基底200的第一表面200a接合於第一裝置基底100的上表面。在一實施例中，每一晶片區120內的第一裝置基底100與第二裝置基底200之間可具有一接合環(bonding ring，未繪示)以及位於接合 環中的內連線結構(未繪示)，而第一裝置基底100的元件區110與第二裝置基底200的元件區210可透過接合環中的內連線結構彼此電性連接。在一實施例中，第一裝置基底100的元件區110內可包括特定應用積體電路元件(Application-specific integrated circuit，ASIC)或其他適合的電子元件。再者，第二裝置基底200的元件區210內可包括微機電系統(Micro Electro Mechanical System，MEMS)或其他適合的電子元件。
請參照第4B圖，對第二裝置基底200進行切割製程，並暴露出第一裝置基底100內的第一接合墊130。舉例來說，第一裝置基底100及第二裝置基底200皆為半導體晶圓，且第二裝置基底200的晶片區對應於第一裝置基底100的晶片區120。沿著第二裝置基底200的晶片區之間的切割道(未繪示)進行切割製程，去除第二裝置基底200遮蔽第一接合墊130的部分，以暴露出下方的第一接合墊130，且使得第二裝置基底200分離成對應於晶片區120的複數晶片。在一實施例中，分離的晶片仍覆蓋第一裝置基底100與第二裝置基底200之間的接合環(未繪示)。
在其他實施例中，可先將第二裝置基底200分離成複數晶片，再將其分別接合於對應的晶片區120內的第一裝置基底100上。
接著，在每一晶片區120內的第二裝置基底200上提供一第三裝置基底300。舉例來說，可透過黏著層(未繪示)將第三裝置基底300貼附於第二裝置基底200相對於第一表面200a的第二表面200b上。在本實施例中，第三裝置基底300內 包括一個或一個以上的第三接合墊330，其可鄰近於第三裝置基底300的上表面(即，相對於第二表面100b的表面)。相似地，第三接合墊330可為單層導電層或具有多層之導電層結構。為簡化圖式，此處僅以單層導電層作為範例說明，且僅繪示出第三裝置基底300內的四個第三接合墊330作為範例說明。在本實施例中，第三裝置基底300的元件區310內的電子元件(未繪示)可透過第三裝置基底300內的內連線結構(如虛線350所示)而與第三接合墊330電性連接。
請參照第4C圖，可透過打線接合製程，將複數第一凸塊370形成於第一裝置基底100內對應的第一接合墊130上，並與其電性連接。再者，可透過打線接合製程，將複數第三凸塊510a及第四凸塊510b形成於第三裝置基底300內對應的第三接合墊330上，並與其電性連接。在本實施例中，第三凸塊510a及第四凸塊510b為接合球。在其他實施例中，第三凸塊510a及第四凸塊510b也可為導電柱或其他適合的導電結構。在本實施例中，第三凸塊510a及第四凸塊510b可包括金或其他適合的導電材料。再者，第三凸塊510a及第四凸塊510b的材料相同於第一凸塊370的材料。
接著，可透過模塑成型製程或沉積製程(例如，印刷製程、塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在第一裝置基底100上形成一絕緣層400，以覆蓋第一裝置基底100、第二裝置基底200、第三裝置基底300、第一凸塊370、第三凸塊510a及第四凸塊510b。
請參照第4D圖，對絕緣層400進行機械研磨 (mechanical grinding)製程或化學機械研磨(chemical mechanical polishing)製程，以減少絕緣層400的厚度，並暴露出第三凸塊510a及第四凸塊510b。在本實施例中，上述研磨製程將第三凸塊510a及第四凸塊510b的頂部局部去除，使得第三凸塊510a及第四凸塊510b具有平坦的上表面，且第三凸塊510a及第四凸塊510b的尺寸小於第一凸塊370的尺寸。
接著，可透過雷射鑽孔製程或微影及蝕刻製程，在絕緣層400內形成複數開口420。在本實施例中，開口420對應於第一裝置基底100內的第一接合墊130，使得第一凸塊370形成於絕緣層400內的開口420的底部下方，且開口420暴露出第一凸塊370的一部份。
在本實施例中，上述研磨製程減少了絕緣層400的厚度，使得開口420的深度降低，進而降低了開口420的深寬比，因此有利於製作開口420。
請參照第4E圖，可透過沉積製程(例如，塗佈製程、物理氣相沉積製程、化學氣相沉積製程、電鍍製程、無電鍍製程或其他適合的製程)、微影製程及蝕刻製程，在絕緣層400上形成圖案化的重佈線層440，且填入絕緣層400的開口420內，進而經由開口420電性連接至位於開口420底部下方的第一凸塊370。在本實施例中，絕緣層400上的重佈線層440延伸至覆蓋至少一部分的第三凸塊510a，並與其電性連接。
接著，可透過模塑成型製程或沉積製程(例如，印刷製程、塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在絕緣層400上形成另一絕緣層520，以覆 蓋重佈線層440、第三凸塊510a及第四凸塊510b。在本實施例中，絕緣層520可包括環氧樹脂、無機材料(例如，氧化矽、氮化矽、氮氧化矽、金屬氧化物或前述之組合)、有機高分子材料(例如，聚醯亞胺樹脂、苯環丁烯、聚對二甲苯、萘聚合物、氟碳化物、丙烯酸酯)或其他適合的絕緣材料。在一實施例中，絕緣層520的材料不同於絕緣層400的材料，使得絕緣層400與絕緣層520之間具有一可見界面I。在其他實施例中，絕緣層520的材料可相同於絕緣層400的材料。
接著，可透過雷射鑽孔製程或微影及蝕刻製程，在絕緣層520內形成複數開口540。在本實施例中，開口540對應於第三裝置基底300內未與重佈線層440電性接觸的第三接合墊330(即，開口540對應於第四凸塊510b)，使得第四凸塊510b形成於絕緣層520內的開口540的底部下方，且開口540暴露出第四凸塊510b的一部份。在本實施例中，開口540的深度小於開口420的深度。
在本實施例中，第四凸塊510b可於形成開口540的製程(例如，雷射鑽孔製程)中作為緩衝層，以避免上述製程破壞第三接合墊330。再者，由於第三接合墊330上設置有第四凸塊510b，因此可降低開口540的深度，進而降低開口540的深寬比。
請參照第4F圖，可透過沉積製程、微影製程及蝕刻製程，在絕緣層520上形成圖案化的另一重佈線層560，且填入絕緣層520的開口540內，以經由開口540電性連接至位於開口540底部下方的第四凸塊510b。在本實施例中，重佈線層560 填滿絕緣層520的開口540。在其他實施例中，重佈線層560可順應性形成於開口540的側壁及底部，而未填滿開口540。在一實施例中，重佈線層560可包括銅、鋁、金、鉑、鎳、錫、前述之組合或其他適合的導電材料。
可透過沉積製程(例如，塗佈製程、物理氣相沈積製程、化學氣相沈積製程或其他適合的製程)，在重佈線層560及絕緣層520上形成一鈍化保護層460，並透過微影製程及蝕刻製程，在每一晶片區120的鈍化保護層460內形成複數開口480，以暴露出位於絕緣層520上的重佈線層560的一部分。
接著，將第二凸塊500對應地設置於鈍化保護層460的開口480內，以直接接觸暴露出的重佈線層560，且與其電性連接。在一實施例中，第二凸塊500、第三凸塊510a及第四凸塊510b皆為接合球，且第二凸塊500的尺寸大於第三凸塊510a及第四凸塊510b的尺寸。在一實施例中，第二凸塊500的材料不同於第三凸塊510a及第四凸塊510b的材料。在一實施例中，第二凸塊500的形成方法不同於第三凸塊510a及第四凸塊510b的形成方法。舉例來說，第二凸塊500透過迴焊製程所形成，而第三凸塊510a及第四凸塊510b透過打線接合製程所形成。
接著，可沿著相鄰晶片區120之間的切割道(未繪示)，對第一裝置基底100及絕緣層400及520進行切割製程，以形成複數獨立的晶片封裝體。
當接合於第一裝置基底上的第二或第三裝置基底的數量越多，則將裝置基底中的電子元件彼此電性連接的接線 的數量也越多，造成製造成本及時間大幅增加。再者，過多的接線形成於裝置基底上會導致後續形成的絕緣層難以順利地覆蓋裝置基底。
在第4A至4F圖的實施例中，採用第一凸塊370、重佈線層440及第三凸塊510a取代接線(例如，第1E、2至3圖中的導電結構380)，能夠在同一製程中同時將所有晶片區120內的裝置基底中的電子元件彼此電性連接，因此有效降低製造成本及時間，且有利於形成絕緣層400，進而降低製程的難度且提升晶片封裝體的可靠度。
第5至8圖係繪示出根據本發明其他實施例之晶片封裝體的剖面示意圖，其中相同於前述第1A至1E及4A至4F圖的實施例的部件係使用相同的標號並省略其說明。第5圖中的晶片封裝體之結構類似於第4F圖中的晶片封裝體之結構，差異在於第5圖中的第一凸塊370形成於第二裝置基底200內的第二接合墊230上，而非第一裝置基底100內的第一接合墊130上。如此一來，可降低絕緣層400的開口420的深度，進而降低開口420的深寬比。
第6圖中的晶片封裝體之結構類似於第5圖中的晶片封裝體之結構，差異在於第6圖中的第四凸塊510b形成於第一裝置基底100內的第一接合墊130上，而非第三裝置基底300內的第三接合墊330上。再者，可在絕緣層400內形成另一開口420，暴露出第四凸塊510b，且重佈線層560形成於開口420內，使得第二凸塊500經由開口420內的重佈線層560而電性連接至位於第一裝置基底100上的第四凸塊510b。如此一來，可無須 形成絕緣層520，進而簡化製程。
第7圖中的晶片封裝體之結構類似於第6圖中的晶片封裝體之結構，差異在於第7圖中的第四凸塊510b形成於第二裝置基底200內的第二接合墊230上，而非第一裝置基底100內的第一接合墊130上。如此一來，可降低暴露出第四凸塊510b的開口420的深度，進而降低其深寬比。再者，還可透過同一製程，同時形成第一凸塊370及第四凸塊510b上方的開口420，且亦可透過同一製程，同時形成重佈線層440及560，因此能夠進一步簡化製程。
然而在其他實施例中，當第四凸塊510b形成於第二接合墊230上時，也可將第7圖中的第一凸塊370形成於第一裝置基底100內的第一接合墊130上。
第8圖中的晶片封裝體之結構類似於第7圖中的晶片封裝體之結構，差異在於第8圖中的第一凸塊370及第四凸塊510b皆形成於第一裝置基底100內的第一接合墊130上，而非皆形成於第二裝置基底200內的第二接合墊230上。如此一來，同樣可透過同一製程，同時形成第一凸塊370及第四凸塊510b上方的開口420，且亦可透過同一製程，形成重佈線層440及560。
可以理解的是，第4F及5至8圖中的第一凸塊370、第二凸塊500、第三凸塊510a及第四凸塊510b的位置係取決於設計需求而不限定於此。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可更動與組合上述各種實施 例。
100‧‧‧第一裝置基底
110、210、310‧‧‧元件區
120‧‧‧晶片區
130‧‧‧第一接合墊
140‧‧‧第一導電墊
150、160、260、360‧‧‧內連線結構
200‧‧‧第二裝置基底
200a‧‧‧第一表面
200b‧‧‧第二表面
240‧‧‧第二導電墊
300‧‧‧第三裝置基底
340‧‧‧第三導電墊
370‧‧‧第一凸塊
380‧‧‧導電結構
400‧‧‧絕緣層
420‧‧‧開口
440‧‧‧重佈線層
460‧‧‧鈍化保護層
480‧‧‧開口
500‧‧‧第二凸塊

Claims (34)

  1. 一種晶片封裝體，包括：一第一裝置基底，貼附於一第二裝置基底的一第一表面上；一第三裝置基底，貼附於該第二裝置基底相對於該第一表面的一第二表面上；一絕緣層，覆蓋該第一裝置基底、該第二裝置基底及該第三裝置基底，其中該絕緣層內具有至少一開口；至少一第一凸塊，設置於該至少一開口的底部下方；以及一重佈線層，設置於該絕緣層上，且經由該至少一開口電性連接至該至少一第一凸塊。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該第二裝置基底的尺寸大於該第三裝置基底的尺寸且小於該第一裝置基底的尺寸。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該至少一第一凸塊設置於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該至少一第一凸塊設置於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。
  5. 如申請專利範圍第1項所述之晶片封裝體，包括複數第一凸塊，且該絕緣層內具有複數開口，其中該等第一凸塊對應設置於該等開口的底部下方，且其中該等第一凸塊的其中一者設置於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊，且該等第一凸塊的其中另一者 設置於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。
  6. 如申請專利範圍第1項所述之晶片封裝體，更包括複數導電結構，設置於該絕緣層內，其分別將該第二裝置基底內的一第二導電墊及該第三裝置基底內的一第三導電墊電性連接至該第一裝置基底內對應的一第一導電墊。
  7. 如申請專利範圍第1項所述之晶片封裝體，更包括複數導電結構，設置於該絕緣層內，其分別將該第一裝置基底內的複數第一導電墊、該第二裝置基底內的複數第二導電墊及該第三裝置基底內的複數第三導電墊的其中兩者彼此電性連接。
  8. 如申請專利範圍第1項所述之晶片封裝體，更包括一第二凸塊，設置於該絕緣層上的該重佈線層上。
  9. 如申請專利範圍第8項所述之晶片封裝體，其中該第二凸塊的材料不同於該至少一第一凸塊的材料。
  10. 如申請專利範圍第8項所述之晶片封裝體，其中該至少一第一凸塊及該第二凸塊為接合球，且該第二凸塊的尺寸大於該至少一第一凸塊的尺寸。
  11. 如申請專利範圍第1項所述之晶片封裝體，更包括一第三凸塊，設置於該第三裝置基底上，並電性連接至該第三裝置基底內的一第三接合墊，其中該絕緣層上的該重佈線層覆蓋且電性連接該第三凸塊。
  12. 如申請專利範圍第11項所述之晶片封裝體，其中該第三凸塊為接合球，且該第三凸塊具有平坦的上表面。
  13. 如申請專利範圍第11項所述之晶片封裝體，更包括：一第四凸塊，設置於該第一裝置基底與該重佈線層之間；以及一另一重佈線層，設置於該絕緣層上，且電性連接至該第四凸塊。
  14. 如申請專利範圍第13項所述之晶片封裝體，更包括一第二凸塊，設置於該另一重佈線層上，其中該第二凸塊的材料不同於該第三凸塊及該第四凸塊的材料以及該至少一第一凸塊的材料。
  15. 如申請專利範圍第13項所述之晶片封裝體，更包括一第二凸塊，設置於該另一重佈線層上，其中該第二凸塊、該第三凸塊及該第四凸塊為接合球，且該第二凸塊的尺寸大於該第三凸塊及該第四凸塊的尺寸。
  16. 如申請專利範圍第13項所述之晶片封裝體，其中該第四凸塊設置於該第三裝置基底上，且電性連接至該第三裝置基底內的一另一第三接合墊，且其中該晶片封裝體更包括一另一絕緣層，覆蓋該絕緣層及該重佈線層，且具有一開口，暴露出該第四凸塊，該另一重佈線層經由該另一絕緣層內的該開口電性連接至該第四凸塊。
  17. 如申請專利範圍第16項所述之晶片封裝體，其中該第三凸塊及該第四凸塊為接合球，且該第三凸塊及該第四凸塊具有平坦的上表面。
  18. 如申請專利範圍第13項所述之晶片封裝體，其中該第四凸塊電性連接至該第一裝置基底內的一第一接合墊或該第二裝置基底內的一第二接合墊，且其中該絕緣層具有複數開 口，該等開口的其中一者暴露出該第四凸塊，且該另一重佈線層經由上述該等開口的其中一者電性連接至該第四凸塊。
  19. 一種晶片封裝體的製造方法，包括：將一第一裝置基底貼附於一第二裝置基底的一第一表面上；將一第三裝置基底貼附於該第二裝置基底相對於該第一表面的一第二表面上；形成至少一第一凸塊及一絕緣層，其中該絕緣層覆蓋該第一裝置基底、該第二裝置基底及該第三裝置基底，且具有至少一開口，使該至少一第一凸塊形成於該至少一開口的底部下方；以及在該絕緣層上形成一重佈線層，其經由該至少一開口電性連接至該至少一第一凸塊。
  20. 如申請專利範圍第19項所述之晶片封裝體的製造方法，其中該第二裝置基底的尺寸大於該第三裝置基底的尺寸且小於該第一裝置基底的尺寸。
  21. 如申請專利範圍第19項所述之晶片封裝體的製造方法，其中該至少一第一凸塊位於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊。
  22. 如申請專利範圍第19項所述之晶片封裝體的製造方法，其中該至少一第一凸塊位於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。
  23. 如申請專利範圍第19項所述之晶片封裝體的製造方法，包 括形成複數第一凸塊，且該絕緣層內具有複數開口，使該等第一凸塊對應設置於該等開口的底部下方，其中該等第一凸塊的其中一者位於該第一裝置基底上，並電性連接至該第一裝置基底內的一第一接合墊，且該等第一凸塊的其中另一者位於該第二裝置基底上，並電性連接至該第二裝置基底內的一第二接合墊。
  24. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括在該絕緣層內形成複數導電結構，以分別將該第二裝置基底內的一第二導電墊及該第三裝置基底內的一第三導電墊電性連接至該第一裝置基底內對應的一第一導電墊。
  25. 如申請專利範圍第19項所述之晶片封裝體的製造方法，在該絕緣層內形成複數導電結構，以分別將該第一裝置基底內的複數第一導電墊、該第二裝置基底內的複數第二導電墊及該第三裝置基底內的複數第三導電墊的其中兩者彼此電性連接。
  26. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括在該絕緣層上的該重佈線層上形成一第二凸塊。
  27. 如申請專利範圍第26項所述之晶片封裝體的製造方法，其中該第二凸塊的材料不同於該至少一第一凸塊的材料。
  28. 如申請專利範圍第26項所述之晶片封裝體的製造方法，其中該至少一第一凸塊及該第二凸塊為接合球，且該第二凸塊的尺寸大於該至少一第一凸塊的尺寸。
  29. 如申請專利範圍第26項所述之晶片封裝體的製造方法，其中該第二凸塊的形成方法不同於該至少一第一凸塊的形成 方法。
  30. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括在該第三裝置基底上形成一第三凸塊，其電性連接至該第三裝置基底內的一第三接合墊，其中該絕緣層上的該重佈線層覆蓋且電性連接該第三凸塊。
  31. 如申請專利範圍第30項所述之晶片封裝體的製造方法，更包括：在該第一裝置基底與該重佈線層之間形成一第四凸塊；以及在該絕緣層上形成一另一重佈線層，其電性連接至該第四凸塊。
  32. 如申請專利範圍第31項所述之晶片封裝體的製造方法，更包括在該另一重佈線層上形成一第二凸塊，其中該第二凸塊的形成方法不同於該第三凸塊及該第四凸塊的形成方法。
  33. 如申請專利範圍第31項所述之晶片封裝體的製造方法，其中該第四凸塊位於該第三裝置基底上，且電性連接至該第三裝置基底內的一另一第三接合墊，且其中該晶片封裝體的製造方法更包括形成一另一絕緣層，以覆蓋該絕緣層及該重佈線層，該另一絕緣層具有一開口，暴露出該第四凸塊，且該另一重佈線層經由該另一絕緣層內的該開口電性連接至該第四凸塊。
  34. 如申請專利範圍第31項所述之晶片封裝體的製造方法，其中該第四凸塊電性連接至該第一裝置基底內的一第一接合 墊或該第二裝置基底內的一第二接合墊，且其中該絕緣層具有複數開口，該等開口的其中一者暴露出該第四凸塊，且該另一重佈線層經由上述該等開口的其中一者電性連接至該第四凸塊。
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