TWI569451B - Thin film transistor, method of manufacturing the same, and device having the same - Google Patents
Thin film transistor, method of manufacturing the same, and device having the same Download PDFInfo
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- TWI569451B TWI569451B TW100132169A TW100132169A TWI569451B TW I569451 B TWI569451 B TW I569451B TW 100132169 A TW100132169 A TW 100132169A TW 100132169 A TW100132169 A TW 100132169A TW I569451 B TWI569451 B TW I569451B
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- Prior art keywords
- field
- film
- thin film
- film transistor
- electron affinity
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Description
本發明係有關一種具備氧化物半導體膜的薄膜電晶體及其製造方法者。又，本發明係有關一種使用該薄膜電晶體的顯示裝置、影像感測器及X射線數位攝影裝置等之裝置者。The present invention relates to a thin film transistor having an oxide semiconductor film and a method of manufacturing the same. Further, the present invention relates to a display device, an image sensor, and an X-ray digital photographing device using the thin film transistor.
近年來，盛行將In-Ga-Zn-O系(IGZO)的氧化物半導體薄膜使用於通道層的薄膜電晶體之研究‧開發。上述氧化物薄膜係可低溫成膜，且呈現比非晶矽還高的遷移率，而且相對於可視光呈透明，因而可在塑膠板或薄膜等之基板上形成撓性的透明薄膜電晶體。In recent years, research on the use of an In-Ga-Zn-O-based (IGZO) oxide semiconductor thin film for a thin film transistor of a channel layer has been widely developed. The oxide thin film is formed at a low temperature and exhibits a higher mobility than amorphous germanium, and is transparent to visible light, so that a flexible transparent thin film transistor can be formed on a substrate such as a plastic plate or a film.
表1呈現各種電晶體特性的遷移率、處理溫度等之比較表。Table 1 presents a comparison table of mobility, processing temperature, and the like of various transistor characteristics.
以往的多晶矽薄膜電晶體可獲得100cm2/Vs左右的遷移率，但是處理溫度是非常高的450℃以上，因而僅能形成耐熱性高的基板，不適合於廉價、大面積、撓性化。又，由於非晶矽薄膜電晶體能以300℃左右的較低溫形成，故基板的選擇性比多晶矽來得廣泛，但頂多只能獲得1cm2/Vs左右的遷移率，不適合於高精細的顯示器之用途。一方面，以低溫成膜的觀點而言，有機薄膜電晶體是可在100℃以下形成，因而使用耐熱性低的塑膠薄膜基板等之撓性顯示器的用途等之應用受到期待，但遷移率僅能獲得和非晶矽相同程度的結果。In the conventional polycrystalline germanium thin film transistor, a mobility of about 100 cm 2 /Vs is obtained. However, since the processing temperature is very high at 450 ° C or higher, only a substrate having high heat resistance can be formed, and it is not suitable for low cost, large area, and flexibility. Moreover, since the amorphous germanium thin film transistor can be formed at a relatively low temperature of about 300 ° C, the selectivity of the substrate is wider than that of the polycrystalline germanium, but at most, the mobility of about 1 cm 2 /Vs can be obtained, which is not suitable for a high-definition display. Use. On the other hand, from the viewpoint of film formation at a low temperature, the organic thin film transistor can be formed at 100 ° C or lower, and the use of a flexible display such as a plastic film substrate having low heat resistance is expected, but the mobility is only expected. The same degree of results as amorphous enamel can be obtained.
亦即，難以實現可在300℃左右以下的較低溫形成且具有100cm2/Vs左右以上的高遷移率之薄膜電晶體。That is, it is difficult to realize a thin film transistor which can be formed at a relatively low temperature of about 300 ° C or lower and has a high mobility of about 100 cm 2 /Vs or more.
有關使電晶體的載子遷移率提升的方法，提案一種使電子親和力不同的異種半導體接合而將量子井作為電晶體通道利用的HEMT(High Electron Mobility Transistor：高電子遷移率電晶體)構造。作了有關製造在氧化物半導體薄膜電晶體中以ZnMgO夾入ZnO而成的HEMT構造裝置，可獲得140cm2/Vs的高遷移率之文獻報告(非專利文獻1)。Regarding a method for increasing the carrier mobility of a transistor, a HEMT (High Electron Mobility Transistor) structure in which a heterogeneous semiconductor having different electron affinities is bonded and a quantum well is used as a transistor channel is proposed. A HEMT construction apparatus in which ZnO is sandwiched between ZnO and MgO in an oxide semiconductor thin film transistor, and a high mobility of 140 cm 2 /Vs is obtained (Non-Patent Document 1).
又，提案一種在使用了IGZO系的氧化物半導體薄膜之薄膜電晶體中，將物理量不同的IGZO膜作成多層構造而作為活性層使用的薄膜電晶體。在專利文獻1中針對一場效型電晶體作了記載，該場效型電晶體之特徵為：含有非晶質氧化物的活性層是包含第1領域和比第1領域還靠近閘極絕緣膜的第2領域的2層構造，且第2領域的氧濃度比第1領域的氧濃度還高。且記載著藉由作成此種構造，閘極絕緣膜側的活性層之電阻變高，因而通道被形成於非晶質氧化物的內部，可減少漏洩電流。Further, a thin film transistor in which an IGZO film having a different physical quantity is formed into a multilayer structure and used as an active layer in a thin film transistor using an IGZO-based oxide semiconductor thin film is proposed. Patent Document 1 describes a field effect transistor in which an active layer containing an amorphous oxide is included in the first field and is closer to the gate insulating film than the first field. The two-layer structure of the second field, and the oxygen concentration in the second field is higher than the oxygen concentration in the first field. It is described that by such a structure, the electric resistance of the active layer on the gate insulating film side is increased, and thus the channel is formed inside the amorphous oxide, and the leakage current can be reduced.
又，專利文獻2提案一種具有由IGZO系的氧化物半導體薄膜和a-Si薄膜的多層構造所構成的活性層之薄膜電晶體。且有藉由將能帶隙小的a-Si膜利用能隙較大的IGZO膜挾入，載子會集中於層厚方向的活性層中心之a-Si部分，且電場效應遷移率比以往的a-Si膜還要上升之記載。Further, Patent Document 2 proposes a thin film transistor having an active layer composed of a multilayer structure of an IGZO-based oxide semiconductor thin film and an a-Si thin film. Furthermore, by inserting an a-Si film having a small band gap into the IGZO film having a large energy gap, the carrier concentrates on the a-Si portion of the active layer center in the layer thickness direction, and the electric field effect mobility is higher than that of the prior art. The a-Si film is still rising.
專利文獻3中揭示一種有關使用電場效應遷移率高、呈現高ON/OFF比的非晶質氧化物半導體的場效型電晶體方面，在活性層和源極/汲極電極之間具備包含有Ga含有率是比活性層的氧化物之Ga含有率還高的氧化物之電阻層的構成。Patent Document 3 discloses a field effect type transistor in which an amorphous oxide semiconductor having a high electric field effect mobility and exhibiting a high ON/OFF ratio is used, and the active layer and the source/drain electrode are included. The Ga content is a structure of a resistive layer of an oxide which is higher than the Ga content of the oxide of the active layer.
[專利文獻1]特開2006-165529號公報[Patent Document 1] JP-A-2006-165529
[專利文獻2]特開2009-170905號公報[Patent Document 2] JP-A-2009-170905
[專利文獻3]特開2010-073881號公報[Patent Document 3] JP-A-2010-073881
[非專利文獻1]K. Koike et al.,Applied Physics Letters,87(2005) 112106[Non-Patent Document 1] K. Koike et al., Applied Physics Letters, 87 (2005) 112106
然而，以專利文獻1而言，並非藉活性層的電子親和力差而朝載子遷移層供予載子的設計。又，雖有可減少漏洩電流的記載，但無法獲得足夠的載子密度，結果會有所謂無法獲得足夠的遷移率之問題點。However, in Patent Document 1, the design of the carrier is not supplied to the carrier transport layer by the difference in electron affinity of the active layer. Further, although there is a description that the leakage current can be reduced, a sufficient carrier density cannot be obtained, and as a result, there is a problem that a sufficient mobility cannot be obtained.
在非專利文獻1中為獲得高遷移率，利用基於分子束磊晶法(MBE法)的磊晶成長製造異種構造場效電晶體(HEMT)，有必要使基板和半導體膜層之格子不整合極小。因此有必要將基板溫度加熱超過700℃，有所謂使基材的選擇性顯著降低的問題點。In Non-Patent Document 1, in order to obtain high mobility, a heterogeneous structure field effect transistor (HEMT) is fabricated by epitaxial growth by molecular beam epitaxy (MBE method), and it is necessary to unmerge the lattice of the substrate and the semiconductor film layer. Very small. Therefore, it is necessary to heat the substrate temperature to over 700 ° C, and there is a problem that the selectivity of the substrate is remarkably lowered.
以專利文獻2而言，由於將遷移率是比氧化物半導體還低1位數左右的非晶質矽使用在屬量子井部的載子遷移層，故無法獲得足夠的遷移率。又，屬氧化物半導體的IGZO膜和稱為非氧化物的a-Si之異種半導體材料接合著，具有所謂無法獲得良好的接合界面之問題點。In Patent Document 2, since the amorphous ruthenium having a mobility lower than that of the oxide semiconductor by about one digit is used in the carrier-transporting layer of the quantum well portion, sufficient mobility cannot be obtained. Further, an IGZO film belonging to an oxide semiconductor and a dissimilar semiconductor material called a-Si which is a non-oxide are bonded, and there is a problem that a good bonding interface cannot be obtained.
專利文獻3中雖提案一種在不損及成為活性層的IGZO膜之載子濃度下，在電極層和活性層之間***電阻層以作為提升On/Off比的手段，但未考慮基於電子親和力的設計，由於足夠的載子未從電阻層朝活性層流入，故有所謂無法獲得超過以往的IGZO單膜的遷移率那様的電場效應遷移率之問題點。Patent Document 3 proposes a method of inserting a resistive layer between the electrode layer and the active layer as a means of increasing the On/Off ratio without impairing the carrier concentration of the IGZO film serving as the active layer, but does not consider electron affinity based. In the design, since sufficient carriers do not flow from the resistance layer toward the active layer, there is a problem that the electric field effect mobility exceeding the mobility of the conventional IGZO single film cannot be obtained.
本發明係有鑒於上述事情而完成者，目的在於提供一種有關氧化物半導體、特別是IGZO系的氧化物半導體能以低溫(例如300℃以下)製造、呈現高電場效應遷移率的薄膜電晶體及其製造方法者。又，本發明係以提供一種具備在通道層具有高電子遷移率的薄膜電晶體之裝置為目的。The present invention has been made in view of the above circumstances, and an object thereof is to provide a thin film transistor in which an oxide semiconductor, particularly an IGZO-based oxide semiconductor can be produced at a low temperature (for example, 300 ° C or lower) and exhibits high electric field effect mobility and Its manufacturing method. Further, the present invention has an object of providing a device having a thin film transistor having a high electron mobility in a channel layer.
本發明的薄膜電晶體係於基板上具有活性層、源極電極、汲極電極、閘極絕緣膜、及閘極電極的薄膜電晶體，其特徵為：前述活性層係包含隔著前述閘極絕緣膜而配置在前述閘極電極側之具有第1電子親和力的第1領域、及配置在前述閘極電極遠側之具有小於前述第1電子親和力之第2電子親和力的第2領域，在前述活性層的膜厚方向建構以前述第1領域作為井層、前述第2領域和前述閘極絕緣膜作成障壁層的方井位能(Square-well potential)，前述活性層係a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體層(此處a、b、c分別為a≧0、b≧0、c≧0且a+b≠0、b+c≠0、c+a≠0)，前述第2領域的b/(a+b)係大於前述第1領域的b/(a+b)。The thin film electromorphic system of the present invention has a thin film transistor having an active layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode on the substrate, wherein the active layer includes the gate In the first field having the first electron affinity on the gate electrode side and the second field having the second electron affinity lower than the first electron affinity on the gate electrode side, the insulating film is disposed on the gate electrode side The film thickness direction of the active layer is constructed by using the first field as the well layer, the second field, and the gate insulating film as a barrier layer, and the active layer a (In 2 O 3 ) an oxide semiconductor layer composed of ‧b(Ga 2 O 3 )‧c(ZnO) (where a, b, and c are a≧0, b≧0, c≧0, and a+b≠0, respectively) b+c≠0, c+a≠0), b/(a+b) in the second field is larger than b/(a+b) in the first field.
圖1呈現半導體電子構造的參數。電子親和力(χ)係意味著賦與一個電子所需的能，半導體的情況是指從傳導體下端(EC)迄至真空準位(EVac)為止的能差。電子親和力係如圖1所示，可由離子化位能(I)和帶隙能(Eg)之差求得。離子化位能(I)可由光電子分光測定，而帶隙能(Eg)可由透過頻譜測定及反射頻譜測定獲得。Figure 1 presents the parameters of a semiconductor electronic construction. The electron affinity (χ) means the energy required to impart an electron, and the case of a semiconductor refers to the difference in energy from the lower end of the conductor (E C ) to the vacuum level (E Vac ). The electron affinity is as shown in Fig. 1, and can be obtained from the difference between ionization potential energy (I) and band gap energy (Eg). The ionization potential energy (I) can be determined by photoelectron spectroscopy, and the band gap energy (Eg) can be obtained by transmission spectrum measurement and reflection spectrum measurement.
亦即，本發明的薄膜電晶體為，如圖2(A)所示該位能構造，由a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體層係自該閘極電極側(圖2(A)中為閘極絕緣膜側)沿膜厚方向包含第1領域A1、第2領域A2，第1領域A1的電子親和力χ1大於第2領域的電子親和力χ2而構成方井位能，將前述第2領域的b/(a+b)設成大於前述第1領域的b/(a+b)，藉以賦與第1領域A1和第2領域A2的電子親和力差。That is, the thin film transistor of the present invention is an oxide composed of a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO) as shown in Fig. 2(A). based semiconductor layer from the gate electrode side (in FIG. 2 (a) is a gate insulating film side) comprising a first field in the thickness direction a 1, the second field a 2, a first field of the electron affinity [chi] 1 1 The electron affinity χ 2 larger than the second field constitutes a square well position, and b/(a+b) in the second field is set to be larger than b/(a+b) in the first field, thereby giving the first position The electron affinity of the field A 1 and the second field A 2 is poor.
此外，此處，「領域」係指表示膜厚方向的3次元的領域(部分)。此外，氧化物半導體層的第1、第2領域設為利用同種的材料所構成。所謂同種是意味著構成膜的元素種相同且陽離子組成比、氧濃度不同者，或者在構成元素的一部分摻雜有不同的元素者。例如，彼此Ga/(In+Ga)不同的IGZO膜是同種，而IGZO膜與Zn的一部分摻雜有Mg而成的IGZO膜是同種。In addition, "field" here means the field (part) which shows the 3rd dimension of the film thickness direction. Further, the first and second fields of the oxide semiconductor layer are formed of the same material. The same species means that the elements constituting the film are the same, the cation composition ratio, the oxygen concentration are different, or a part of the constituent elements are doped with different elements. For example, an IGZO film different from each other in Ga/(In+Ga) is the same kind, and an IGZO film is the same as an IGZO film in which a part of Zn is doped with Mg.
領域A1、A2中藉由變調b/(a+b)可賦與各領域間位能差(電子親和力差)。又，藉由將領域A1的氧濃度設成大於領域A2的氧濃度，更可賦與電子親和力差。本發明中亦可使b/(a+b)和氧濃度同時地調變。In the fields A 1 and A 2 , by shifting b/(a+b), the potential difference (electron affinity difference) between the fields can be assigned. Further, by setting the oxygen concentration of the field A 1 to be larger than the oxygen concentration of the field A 2 , it is possible to impart a difference in electron affinity. In the present invention, b/(a+b) and oxygen concentration can also be modulated simultaneously.
此處，調變前述第1、第2領域中之陽離子組成比，及/或，基於氧濃度調變的電子親和力差是0.17eV以上1.3eV以下者較佳，再者，以第1、第2領域中之電子親和力差是0.32eV以上1.3eV以下者較佳。Here, the cation composition ratio in the first and second fields is adjusted, and/or the electron affinity difference based on the oxygen concentration modulation is preferably 0.17 eV or more and 1.3 eV or less, and further, the first and the The difference in electron affinity in the field of 2 is preferably 0.32 eV or more and 1.3 eV or less.
當第1、第2領域的電子親和力差是0.17eV以上時，載子有效率地從第2領域朝第1領域流入，可獲得高載子濃度和遷移率。When the difference in electron affinity between the first and second domains is 0.17 eV or more, the carrier efficiently flows from the second region to the first region, and high carrier concentration and mobility can be obtained.
又，在本發明的薄膜電晶體中，當使電子親和力差繼續增大時，可見供給至第1領域的載子量上升，遷移率會有繼續增大的舉動。當維持氧化物半導體層中的In、Ga、Zn當中的Zn組成比固定並變調b/(a+b)以繼續增大電子親和力差時，最大能獲得大概1.3eV的電子親和力差。欲獲得1.3eV以上的電子親和力差時，例如有大幅變調活性層中的Zn量之手法，但大幅變調Zn量時，由於氧化物半導體層中的非晶質構造會變不穩定，招致TFT特性的不穩定性、不均一性，故上述電子親和力差以1.3eV以下者較佳。Further, in the thin film transistor of the present invention, when the electron affinity difference is further increased, it is seen that the amount of carriers supplied to the first field increases, and the mobility tends to continue to increase. When the Zn composition ratio among In, Ga, and Zn in the oxide semiconductor layer is maintained and b/(a+b) is adjusted to continue to increase the electron affinity difference, an electron affinity difference of about 1.3 eV can be obtained at the maximum. When it is desired to obtain a difference in electron affinity of 1.3 eV or more, for example, a method of greatly changing the amount of Zn in the active layer, but greatly changing the amount of Zn, the amorphous structure in the oxide semiconductor layer becomes unstable, resulting in TFT characteristics. The instability and the heterogeneity are preferred, and the difference in the electron affinity is preferably 1.3 eV or less.
本發明的薄膜電晶體中，以氧化物半導體層是非晶質膜者較佳。In the thin film transistor of the present invention, it is preferred that the oxide semiconductor layer is an amorphous film.
而前述氧化物半導體層是否為非晶質，可利用X射線繞射測定來確認。亦即，在藉由X射線繞射測定未檢出呈現結晶構造的明確峰值之情況，可判斷其氧化物半導體層是非晶質。Whether or not the oxide semiconductor layer is amorphous can be confirmed by X-ray diffraction measurement. That is, in the case where the clear peak of the crystal structure is not detected by the X-ray diffraction measurement, it can be judged that the oxide semiconductor layer is amorphous.
本發明的薄膜電晶體為，將a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體使用在活性層，第1領域A1的b/(a+b))小於0.5者較佳。In the thin film transistor of the present invention, an oxide semiconductor composed of a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO) is used in the active layer, and b/(a of the first field A 1 is used . +b)) Less than 0.5 is preferred.
更佳為，第1領域A1的b/(a+b)小於0.4，且第2領域A2的b/(a+b)是0.6以上者。More preferably, b/(a+b) in the first field A 1 is less than 0.4, and b/(a+b) in the second field A 2 is 0.6 or more.
本發明的薄膜電晶體中，以前述基板是具可撓性者較佳。In the thin film transistor of the present invention, it is preferable that the substrate is flexible.
作為具有可撓性的基板，可例舉飽和聚酯/聚對苯二甲酸乙二酯(PET)系樹脂基板、聚萘二甲酸乙二酯(PEN)樹脂基板、交聯反丁烯二酸二酯系樹脂基板、聚碳酸酯(PC)系樹脂基板、聚醚碸(PES)樹脂基板、聚碸(PSF、PSU)樹脂基板、聚芳香酯(PAR)樹脂基板、環狀聚烯烴(COP、COC)樹脂基板、纖維素系樹脂基板、聚醯亞胺(PI)樹脂基板、聚醯胺醯亞胺(PAI)樹脂基板、馬來醯亞胺-環烯樹脂基板、聚醯胺(PA)樹脂基板、丙烯酸系樹脂基板、氟系樹脂基板、環氧系樹脂基板、聚矽氧系樹脂薄膜基板、聚苯唑系樹脂基板、環氧硫化物化合物基板、液晶聚合物(LCP)基板、氰酸酯系樹脂基板、芳香族醚系樹脂基板、與氧化矽粒子之複合塑膠材料所構成的基板、與金屬奈米粒子、無機氧化物奈米粒子、無機氮化物奈米粒子等之奈米粒子的複合塑膠材料所構成的基板、與金屬系‧無機系的奈米纖維及微纖維之複合塑膠材料所構成的基板、與碳纖維、奈米碳管的複合塑膠材料所構成的基板、與玻璃碎片、玻璃纖維、玻璃珠的複合塑膠材料所構成的基板、與具有黏土礦物或雲母衍生結晶構造的粒子之複合塑膠材料所構成的基板、在薄玻璃和上述單獨有機材料之間具有至少1次的接合界面之積層塑膠材料所構成的基板、透過交互積層無機層(例如，SiO2、Al2O3、SiOxNy)和有機層而具備有至少1次以上的接合界面之障壁性能的複合材料所構成的基板、不鏽鋼基板、積層不鏽鋼和異種金屬而成的金屬多層基板、鋁基板、透過在表面施作氧化處理(例如，陽極氧化處理)而提升表面的絕緣性之帶有氧化被膜的鋁基板等。The flexible substrate may, for example, be a saturated polyester/polyethylene terephthalate (PET) resin substrate, a polyethylene naphthalate (PEN) resin substrate, or a crosslinked fumaric acid. Diester resin substrate, polycarbonate (PC) resin substrate, polyether fluorene (PES) resin substrate, polyfluorene (PSF, PSU) resin substrate, polyarylate (PAR) resin substrate, cyclic polyolefin (COP) , COC) resin substrate, cellulose resin substrate, polyimine (PI) resin substrate, polyamidimide (PAI) resin substrate, maleimide-cycloolefin resin substrate, polyamine (PA) a resin substrate, an acrylic resin substrate, a fluorine resin substrate, an epoxy resin substrate, a polyoxyn resin film substrate, a polybenzophenone resin substrate, an epoxy sulfide compound substrate, a liquid crystal polymer (LCP) substrate, A substrate composed of a cyanate-based resin substrate, an aromatic ether-based resin substrate, and a composite plastic material of cerium oxide particles, and a nano-particle such as a metal nanoparticle, an inorganic oxide nanoparticle, or an inorganic nitride nanoparticle Substrate composed of composite plastic materials of particles, and metal systems and inorganic systems a substrate composed of a composite plastic material of nanofibers and microfibers, a substrate composed of a composite plastic material of carbon fibers and carbon nanotubes, a substrate composed of a composite plastic material of glass chips, glass fibers, and glass beads, and a substrate composed of a composite plastic material having particles of a clay mineral or a mica-derived crystal structure, a substrate composed of a laminated plastic material having at least one joint interface between the thin glass and the above-mentioned individual organic material, and an interbedded inorganic layer (for example, SiO 2 , Al 2 O 3 , SiO x N y ) and an organic layer, and a substrate made of a composite material having a barrier property of at least one bonding interface, a stainless steel substrate, a laminated stainless steel, and a dissimilar metal The metal multilayer substrate, the aluminum substrate, and an aluminum substrate with an oxide film that is oxidized (for example, anodized) on the surface to enhance the insulation of the surface.
本發明的第1薄膜電晶體的製造方法係於基板上具有活性層、源極電極、汲極電極、閘極絕緣膜、及閘極電極的薄膜電晶體的製造方法，其特徵為：包含成膜步驟，該成膜步驟為：以前述活性層包含隔著前述閘極絕緣膜而配置在前述閘極電極側之具有第1電子親和力的第1領域、及配置在前述閘極電極遠側之具有小於前述第1電子親和力之第2電子親和力的第2領域，且在該活性層的膜厚方向建構以前述第1領域作為井層、前述第2領域和前述閘極絕緣膜作為障壁層的方井位能之方式，利用濺鍍法成膜作為前述活性層之a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體層(此處a、b、c分別為a≧0、b≧0、c≧0且a+b≠0、b+c≠0、c+a≠0)；及在該成膜步驟中，於成膜室內以第1氧分壓/氬分壓下成膜前述第1領域，於前述成膜室內以第2氧分壓/氬分壓下成膜組成比是大於第1領域的b/(a+b)之b/(a+b)的前述第2領域。A method for producing a first thin film transistor of the present invention is a method for producing a thin film transistor having an active layer, a source electrode, a gate electrode, a gate insulating film, and a gate electrode on a substrate, characterized in that it comprises In the film forming step, the active layer includes a first region having a first electron affinity disposed on the gate electrode side via the gate insulating film, and a distal side disposed on the gate electrode In the second field having a second electron affinity lower than the first electron affinity, the first region is used as the well layer, the second region, and the gate insulating film are used as the barrier layer in the film thickness direction of the active layer. In the manner of square well energy, an oxide semiconductor layer composed of a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO) as the active layer is formed by sputtering (here a, b, c are respectively a≧0, b≧0, c≧0 and a+b≠0, b+c≠0, c+a≠0); and in the film forming step, in the film forming chamber (1) The first field of film formation under the partial pressure of oxygen/argon partial pressure, and the film formation ratio under the second oxygen partial pressure/argon partial pressure in the deposition chamber is greater than the first The second field of b/(a+b) of b/(a+b) in the field.
此處，以前述第2氧分壓/氬分壓設成小於前述第1氧分壓/氬分壓者較佳。Here, it is preferable that the second oxygen partial pressure/argon partial pressure is set to be smaller than the first oxygen partial pressure/argon partial pressure.
本發明的第2薄膜電晶體的製造方法係於基板上具有活性層、源極電極、汲極電極、閘極絕緣膜、及閘極電極之薄膜電晶體的製造方法，其特徵為：包含成膜步驟，該成膜步驟為：以前述活性層包含隔著前述閘極絕緣膜而配置在前述閘極電極側之具有第1電子親和力的第1領域、及配置在前述閘極電極遠側之具有小於前述第1電子親和力之第2電子親和力的第2領域，且在活性層的膜厚方向建構以前述第1領域作為井層、前述第2領域和前述閘極絕緣膜作為障壁層的方井位能之方式，利用濺鍍法成膜作為前述活性層之a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體層(此處a、b、c分別為a≧0、b≧0、c≧0且a+b≠0、b+c≠0、c+a≠0)；及該成膜步驟係包含成膜前述第1領域及比第1領域的b/(a+b)還大的b/(a+b)之組成比的前述第2領域之步驟，在成膜前述第1領域中及/或成膜該第1領域之後，將含氧自由基照射該第1領域的成膜面之步驟。A method for producing a second thin film transistor of the present invention is a method for producing a thin film transistor having an active layer, a source electrode, a gate electrode, a gate insulating film, and a gate electrode on a substrate, characterized in that it comprises In the film forming step, the active layer includes a first region having a first electron affinity disposed on the gate electrode side via the gate insulating film, and a distal side disposed on the gate electrode In the second field having a second electron affinity lower than the first electron affinity, the first region is used as the well layer, the second region and the gate insulating film are used as the barrier layer in the film thickness direction of the active layer. In the well energy mode, an oxide semiconductor layer composed of a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO) as the active layer is formed by sputtering (here, a, b) And c are respectively a≧0, b≧0, c≧0, and a+b≠0, b+c≠0, c+a≠0); and the film forming step includes film forming the first field and ratio The step of the second field in which the b/(a+b) of the first field is larger than the composition ratio of b/(a+b) is formed in the first field and/or film formation in the film formation. After the first field, the oxygen-containing radical of the irradiation field of the first step of the film formation surface.
本發明的第3薄膜電晶體的製造方法係在基板上具有活性層、源極電極、汲極電極、閘極絕緣膜、及閘極電極之薄膜電晶體的製造方法，其特徵為：包含成膜步驟，該成膜步驟為：以前述活性層包含隔著前述閘極絕緣膜而配置在前述閘極電極側之具有第1電子親和力的第1領域、及配置在前述閘極電極遠側之具有小於前述第1電子親和力之第2電子親和力的第2領域，且在活性層的膜厚方向建構以前述第1領域作為井層、前述第2領域和前述閘極絕緣膜作為障壁層的方井位能之方式，利用濺鍍法成膜作為前述活性層之a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體層(此處a、b、c分別為a≧0、b≧0、c≧0且a+b≠0、b+c≠0、c+a≠0)；該成膜步驟係包含成膜前述第1領域及比第1領域的b/(a+b)還大的b/(a+b)之組成比的前述第2領域之步驟，在成膜前述第1領域中及/或成膜該第1領域之後，在臭氧環境中將紫外線照射於該第1領域的成膜面之步驟。A method for producing a third thin film transistor of the present invention is a method for producing a thin film transistor having an active layer, a source electrode, a gate electrode, a gate insulating film, and a gate electrode on a substrate, characterized in that it comprises In the film forming step, the active layer includes a first region having a first electron affinity disposed on the gate electrode side via the gate insulating film, and a distal side disposed on the gate electrode In the second field having a second electron affinity lower than the first electron affinity, the first region is used as the well layer, the second region and the gate insulating film are used as the barrier layer in the film thickness direction of the active layer. In the well energy mode, an oxide semiconductor layer composed of a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO) as the active layer is formed by sputtering (here, a, b) And c are a≧0, b≧0, c≧0, and a+b≠0, b+c≠0, c+a≠0); the film forming step includes forming the first field and the first The step of the second field of the b/(a+b) large b/(a+b) composition ratio in the first field, in the first field of film formation and/or film formation After the field 1, the step of forming the surface of the ultraviolet irradiation in an ozone environment in the field in the first.
此外，在本發明的第1至第3薄膜電晶體的製造方法中，以任一皆是在前述成膜步驟之間，不讓成膜基板曝露於大氣中者較佳。Further, in the method for producing the first to third thin film transistors of the present invention, it is preferred that the film formation substrate is not exposed to the atmosphere between the film formation steps.
本發明的顯示裝置之特徵為：具備本發明的薄膜電晶體。The display device of the present invention is characterized by comprising the thin film transistor of the present invention.
本發明影像感測器之特徵為：具備本發明的薄膜電晶體。The image sensor of the present invention is characterized by comprising the thin film transistor of the present invention.
本發明的X射線感測器之特徵為：具備本發明的薄膜電晶體。The X-ray sensor of the present invention is characterized by comprising the thin film transistor of the present invention.
本發明的X射線數位攝影裝置之特徵為：具備本發明的X射線感測器。The X-ray digital photographing apparatus of the present invention is characterized by comprising the X-ray sensor of the present invention.
本發明的薄膜電晶體為，a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體層之第1領域是和電子親和力更小的第2領域相接，第1領域的傳導帶下端係形成以第2領域及閘極絕緣膜作為位能障壁的方井位能構造。其結果，引起電子載子朝第1領域流入，由於在未變化第1領域的組成比、氧缺損量之下可提高載子密度，故可作成具有高遷移率者。In the thin film transistor of the present invention, the first field of the oxide semiconductor layer composed of a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO) is a second field phase having a lower electron affinity. In the first field, the lower end of the conduction band forms a square well energy structure in which the second field and the gate insulating film are used as the potential barrier. As a result, the electron carrier is caused to flow into the first region, and since the carrier density can be increased without changing the composition ratio of the first field or the oxygen deficiency amount, it is possible to produce a high mobility.
一般而言，為提高氧化物半導體中的載子密度，係增加氧缺損量，但過剩的氧缺損同時相對於載子成為散亂體，會成為降低遷移率的要因。本發明中，由於無需增加成為井層的第1領域中之氧缺損量，所以除因方井位能構造而增加載子以外，還抑制了成為通道層的第1領域中之氧缺損所致遷移率降低，更可提升遷移率。In general, in order to increase the density of a carrier in an oxide semiconductor, the amount of oxygen deficiency is increased. However, an excessive oxygen deficiency is a disordered body with respect to a carrier, and this causes a decrease in mobility. In the present invention, since it is not necessary to increase the oxygen deficiency amount in the first field which is a well layer, in addition to the increase in the carrier due to the square well energy structure, the oxygen deficiency in the first field which becomes the channel layer is suppressed. Reduced mobility and increased mobility.
本發明的薄膜電晶體係a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成的氧化物半導體層由於第1、第2領域中以同種的材料形成，所以成為通道層的第1領域與和異種材料接觸的情況相較下，在界面的缺陷密度減低，可提供從均一性、穩定性、可靠性的觀點均優異的薄膜電晶體。又同時，由於成為通道層的第1領域未被曝露於外氣，所以減低與經時或元件放置的環境下相依存之元件特性劣化。The oxide semiconductor layer composed of the thin film electro-crystal system a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO) of the present invention is formed of the same material in the first and second fields, so In the first field of the channel layer, compared with the case of contact with a dissimilar material, the defect density at the interface is reduced, and a thin film transistor excellent in uniformity, stability, and reliability can be provided. At the same time, since the first region which becomes the channel layer is not exposed to the outside air, the deterioration of the characteristics of the components which depend on the environment with time or component placement is reduced.
本發明中，若氧化物半導體層是非晶質膜，則能以300℃以下的低溫成膜，容易形成在像塑膠基板那樣具可撓性的樹脂基板上。因此更容易適用於使用帶有薄膜電晶體的塑膠基板之撓性顯示器。再者，非晶質膜容易大面積地容易形成均一的膜，由於未存在像多結晶那樣的粒界故容易抑制元件特性的不均。In the present invention, when the oxide semiconductor layer is an amorphous film, it can be formed at a low temperature of 300 ° C or lower, and can be easily formed on a flexible resin substrate such as a plastic substrate. Therefore, it is easier to apply to a flexible display using a plastic substrate with a thin film transistor. Further, the amorphous film is likely to easily form a uniform film over a large area, and since there is no grain boundary like polycrystal, it is easy to suppress unevenness in device characteristics.
本發明的顯示裝置係備有具高遷移率之本發明的薄膜電晶體，因而可實現低消耗電力且高品質的顯示。The display device of the present invention is provided with the thin film transistor of the present invention having high mobility, thereby achieving low power consumption and high quality display.
本發明的X射線感測器由於具備可靠性優異之本發明的薄膜電晶體，故S/N高，可實現高感度特性。Since the X-ray sensor of the present invention has the thin film transistor of the present invention excellent in reliability, the S/N is high and high sensitivity characteristics can be realized.
本發明的X射線數位攝影裝置由於其X射線感測器具備具有高遷移率的電晶體，故可獲得輕量且具撓性，且寬動態範圍的畫像，從該高速性特別適合於動畫攝影。Since the X-ray digital measuring device of the present invention has a transistor having a high mobility, the X-ray sensor can provide a lightweight and flexible image with a wide dynamic range, which is particularly suitable for animated photography. .
以下，參照圖面針對本發明的實施形態作說明。Hereinafter, embodiments of the present invention will be described with reference to the drawings.
＜薄膜電晶體＞<Thin Film Transistor>
圖3(A)至(D)係顯示本發明的第1～第4實施形態的薄膜電晶體1～4之構成的剖面圖。在圖3(A)～(D)的各薄膜電晶體中，賦與共通的要素相同的符號。3(A) to 3(D) are cross-sectional views showing the structures of the thin film transistors 1 to 4 of the first to fourth embodiments of the present invention. In the thin film transistors of FIGS. 3(A) to (D), the same reference numerals are given to the common elements.
本發明的實施形態之薄膜電晶體1～4為，在基板11上具有活性層12、源極電極13、汲極電極14、閘極絕緣膜15、及閘極電極16，活性層12備有在膜厚方向構成方井位能的第1、第2領域A1、A2(參照圖3(A)～(D))。In the thin film transistors 1 to 4 according to the embodiment of the present invention, the active layer 12, the source electrode 13, the drain electrode 14, the gate insulating film 15, and the gate electrode 16 are provided on the substrate 11, and the active layer 12 is provided. The first and second fields A 1 and A 2 of the square well energy are formed in the film thickness direction (see FIGS. 3(A) to (D)).
活性層12係由以a(In2O3)‧b(Ga2O3)‧c(ZnO)所表示的氧化物半導體層(IGZO層)所構成，第1領域A1為，成為方井位能(參照圖2(A))的井部之具有第1電子親和力χ1的領域，第2領域A2為，配置在比第1領域A1離閘極電極16還遠側之具有比第1電子親和力χ1還小的第2電子親和力χ2，且陽離子組成比b/(a+b)是比第1領域還大的領域。The active layer 12 is composed of an oxide semiconductor layer (IGZO layer) represented by a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO), and the first field A 1 is a square well. In the field where the potential of the well (see FIG. 2(A)) has the first electron affinity χ 1 , the second field A 2 is arranged to be farther than the first field A 1 from the gate electrode 16 The first electron affinity χ 1 is smaller than the second electron affinity χ2, and the cation composition ratio b/(a+b) is a field larger than the first field.
又，本發明的薄膜電晶體1～4中，第1、第2領域係被連續成膜，第1、第2領域間不被挿入電極層等之氧化物半導體層以外的層。Further, in the thin film transistors 1 to 4 of the present invention, the first and second fields are continuously formed, and the layers other than the oxide semiconductor layer such as the electrode layer are not inserted between the first and second domains.
領域A1、A2中藉由變調b/(a+b)可賦與各領域間位能差(電子親和力差)。又，藉由將領域A1的氧濃度設成大於領域A2的氧濃度，更可賦與電子親和力差，可有效率地讓載子集中在位能井部。同時藉由提高領域A1的氧濃度抑制不純物散亂所致遷移率之降低，更可提升遷移率。本發明中亦可使b/(a+b)和氧濃度同時地調變。In the fields A 1 and A 2 , by shifting b/(a+b), the potential difference (electron affinity difference) between the fields can be assigned. Further, by setting the oxygen concentration of the field A 1 to be larger than the oxygen concentration of the field A 2 , it is possible to impart a difference in electron affinity, and it is possible to efficiently concentrate the carriers in the well. At the same time, by increasing the oxygen concentration in the field A 1 to suppress the decrease in mobility caused by the scattering of impurities, the mobility can be improved. In the present invention, b/(a+b) and oxygen concentration can also be modulated simultaneously.
圖3(A)所示的第1實施形態的薄膜電晶體1係頂閘極-頂接觸型的電晶體，圖3(B)所示的第2實施形態的薄膜電晶體2係頂閘極-底接觸型的電晶體，圖3(C)所示的第3實施形態的薄膜電晶體3係底閘極-頂接觸型的電晶體，圖3(D)所示的第4實施形態的薄膜電晶體4係底閘極-底接觸型的電晶體。The thin film transistor 1 of the first embodiment shown in Fig. 3(A) is a top gate-top contact type transistor, and the thin film transistor 2 of the second embodiment shown in Fig. 3(B) is a top gate. - a bottom contact type transistor, the thin film transistor 3 of the third embodiment shown in FIG. 3(C) is a bottom gate-top contact type transistor, and the fourth embodiment shown in FIG. 3(D) The thin film transistor 4 is a bottom-bottom contact type transistor.
圖3(A)～(D)所示的實施形態雖然閘極、源極及汲極電極之相對於活性層(IGZO層)的配置不同，但被賦與相同符號的各要素之機能相同，可適應同樣的材料。In the embodiment shown in FIGS. 3(A) to 3(D), the arrangement of the gate, the source, and the drain electrode with respect to the active layer (IGZO layer) is the same, but the functions of the elements having the same reference numerals are the same. Can adapt to the same material.
以下，詳述各構成要素。Hereinafter, each component will be described in detail.
(基板)(substrate)
有關用以形成薄膜電晶體1的基板11之形狀、構造、大小等，並無特別限制，可因應目的而適當地選擇。基板的構造可以是單層構造，亦可為積層構造。作為基板11，例如，可使用YSZ(釔安定氧化鋯)或玻璃等之無機材料、樹脂或樹脂複合材料等所構成的基板。其中考量輕量及具可撓性時，以由樹脂或樹脂複合材料所構成的基板較佳。具體而言，可使用由聚對苯二甲酸丁二酯、聚對苯二甲酸乙二酯、聚萘二甲酸乙二酯、聚對其二丁酸乙酯、聚苯乙烯、聚碳酸酯、聚碸、聚醚、聚芳香酯、烯丙基二甘醇碳酸酯、聚醯胺、聚醯亞胺、聚醯胺醯亞胺、聚醚醯亞胺、聚苯唑、聚苯硫醚、多環烯烴、原冰片烯樹脂、聚三氟氯乙烯等之氟樹脂、液晶聚合物、丙烯酸樹脂、環氧樹脂、聚矽氧樹脂、離子聚合物樹脂、氰酸酯樹脂、交聯反丁烯二酸二酯、環狀聚烯烴、芳香族醚、馬來醯亞胺一環烯、纖維素、環氧硫化物化合物等之合成樹脂所構成的基板、已提及之合成樹脂等和氧化矽粒子之複合塑膠材料所構成的基板、已提及之合成樹脂等和金屬奈米粒子、無機氧化物奈米粒子或無機氮化物奈米粒子等之複合塑膠材料所構成的基板、已提及之合成樹脂等和碳繊維或奈米碳管之複合塑膠材料所構成的基板、已提及之合成樹脂等和玻璃碎片、玻璃纖維或玻璃珠之複合塑膠材料所構成的基板、已提及之合成樹脂等和具有黏土礦物或雲母衍生結晶構造的粒子之複合塑膠材料所構成的基板、在薄玻璃和已提及之任一合成樹脂之間具有至少1次的接合界面之積層塑膠基板、藉由交互地積層無機層和有機層(已提及之合成樹脂)而具有至少有1次以上的接合界面之障壁性能的複合材料所構成的基板、將不鏽鋼基板或不鏽鋼和異種金屬積層所成的金屬多層基板、鋁基板或表面施以氧化處理(例如陽極氧化處理)而提升表面絕緣性之帶有氧化皮膜的鋁基板等。The shape, structure, size, and the like of the substrate 11 for forming the thin film transistor 1 are not particularly limited, and may be appropriately selected depending on the purpose. The structure of the substrate may be a single layer structure or a laminate structure. As the substrate 11, for example, a substrate made of an inorganic material such as YSZ (yttrium zirconia) or glass, a resin, or a resin composite material can be used. In the case where lightweight and flexible are considered, a substrate composed of a resin or a resin composite material is preferred. Specifically, polybutylene terephthalate, polyethylene terephthalate, polyethylene naphthalate, poly(ethylene dibutyrate), polystyrene, polycarbonate, Polyfluorene, polyether, polyaryl ester, allyl diglycol carbonate, polyamine, polyimide, polyamidimide, polyether phthalimide, polybenzoazole, polyphenylene sulfide, Polycyclic olefin, raw borneol resin, fluororesin such as polychlorotrifluoroethylene, liquid crystal polymer, acrylic resin, epoxy resin, polyoxynoxy resin, ionic polymer resin, cyanate resin, crosslinked butene A substrate composed of a synthetic resin such as a diacid diester, a cyclic polyolefin, an aromatic ether, a maleimine monocycloolefin, a cellulose or an epoxy sulfide compound, a synthetic resin as mentioned, and cerium oxide particles a substrate composed of a composite plastic material, a synthetic resin as mentioned, and a composite plastic material such as metal nanoparticles, inorganic oxide nanoparticles or inorganic nitride nanoparticles, and the like Resin and other composite plastic materials of carbon or nano carbon tubes a substrate composed of a substrate, a synthetic resin or the like, and a composite plastic material of glass cullet, glass fiber or glass beads, a synthetic resin as mentioned, and a composite plastic material having particles of a clay mineral or a mica-derived crystal structure. a substrate, a laminated plastic substrate having at least one bonding interface between the thin glass and any of the synthetic resins mentioned, by alternately laminating an inorganic layer and an organic layer (the synthetic resin already mentioned) a substrate composed of a composite material having at least one barrier property of a joint interface, a metal multilayer substrate formed of a stainless steel substrate or a stainless steel and a dissimilar metal layer, an aluminum substrate or a surface subjected to an oxidation treatment (for example, anodizing treatment) An aluminum substrate with an oxide film that enhances surface insulation.
此外，作為樹脂基板，以耐熱性、尺寸穩定性、耐溶劑性、電氣絕緣性、加工性、低通氣性、及低吸濕性等優異者較佳。樹脂基板亦可具備用以防止水分或氧之透過的氣體障壁層或用以提升樹脂基板的平坦性或與下部電極之密接性的底塗層等。Further, the resin substrate is preferably excellent in heat resistance, dimensional stability, solvent resistance, electrical insulating properties, workability, low air permeability, and low moisture absorption. The resin substrate may be provided with a gas barrier layer for preventing the permeation of moisture or oxygen, or an undercoat layer for improving the flatness of the resin substrate or the adhesion to the lower electrode.
又，基板的厚度係以50μm以上500μm以下者較佳。當基板的厚度是50μm以上時，基板自體的平坦性更加提升。當基板的厚度是500μm以下時，基板自體的可撓性更加提升，更容易作為撓性裝置用基板使用。此外，由於具有足夠的平坦性及可撓性的厚度係依構成基板的材料而有不同，雖有必要因應於基板材料而設定該厚度，但大概其範圍是在50μm-500μm的範圍。Further, the thickness of the substrate is preferably 50 μm or more and 500 μm or less. When the thickness of the substrate is 50 μm or more, the flatness of the substrate itself is further improved. When the thickness of the substrate is 500 μm or less, the flexibility of the substrate itself is further enhanced, and it is more likely to be used as a substrate for a flexible device. Further, since the thickness having sufficient flatness and flexibility varies depending on the material constituting the substrate, it is necessary to set the thickness in accordance with the substrate material, but the range is preferably in the range of 50 μm to 500 μm.
(活性層)(active layer)
活性層12係由IGZO膜，更詳言之是由a(In2O3)‧b(Ga2O3)‧c(ZnO)所構成，具備各自有第1、第2電子親和力χ1，χ2的第1、第2領域A1、A2，第1電子親和力χ1大於第2電子親和力χ2，且領域A2中的b/a+b大於領域A1中的b/(a+b)。The active layer 12 is composed of an IGZO film, more specifically, a(In 2 O 3 )‧b(Ga 2 O 3 )‧c(ZnO), and has first and second electron affinities χ 1 . [chi] of 12, and the second field of a 1, a 2, a first electron affinity [chi] 1 is greater than the second electron affinity [chi] 2, and field a 2 of b / a + b is greater than the field a in 1 b / (a +b).
為了在積層方向形成方井位能時，藉由在各領域間調變b/(a+b)而賦與各領域的電子親和力差。又，第1領域A1和第2領域A2的位能為，藉由將第2領域A2的氧濃度設成低於第1領域A1的氧濃度亦可賦與形成方井位能的電子親和力差。在各領域是依共通的元素及組成比所構成的情況，氧濃度越高則電子親和力越大。In order to form a well position energy in the lamination direction, the electron affinity of each field is poor by modulating b/(a+b) between fields. Further, the potential of the first field A 1 and the second field A 2 can be set to form a well position by setting the oxygen concentration of the second field A 2 to be lower than the oxygen concentration of the first field A 1 . Poor electronic affinity. In each case, it is composed of common elements and composition ratios, and the higher the oxygen concentration, the greater the electron affinity.
此處，係調變前述第1、第2領域中之b/(a+b)，及基於氧濃度調變的電子親和力差為0.17eV以上1.3eV以下者較佳，再者，以第1、第2領域中的電子親和力差是0.32eV以上1.3eV以下者較佳。Here, b/(a+b) in the first and second fields, and an electron affinity difference based on oxygen concentration modulation are preferably 0.17 eV or more and 1.3 eV or less, and further, the first The electron affinity difference in the second field is preferably 0.32 eV or more and 1.3 eV or less.
當第1、第2領域的電子親和力差是0.17eV以上時，載子有效率地從第2領域朝第1領域流入，可獲得高載子濃度和高遷移率。When the difference in electron affinity between the first and second domains is 0.17 eV or more, the carrier efficiently flows into the first region from the second region, and a high carrier concentration and a high mobility can be obtained.
又，在本發明的薄膜電晶體中，當使電子親和力差繼續增大時，可見供給至第1領域的載子量上升，遷移率會有繼續增大的舉動。當維持氧化物半導體層中的In、Ga、Zn當中的Zn組成比固定並變調b/(a+b)以繼續增大電子親和力差時，最大能獲得大概1.3eV的電子親和力差。而在欲獲得1.3eV以上的電子親和力差時，例如有大幅變調活性層中的Zn量之手法，但大幅變調Zn量時，由於氧化物半導體層中的非晶質構造會招致變不穩定，招致TFT特性的不穩定性，不均一性，故上述電子親和力差以1.3eV以下者較佳。Further, in the thin film transistor of the present invention, when the electron affinity difference is further increased, it is seen that the amount of carriers supplied to the first field increases, and the mobility tends to continue to increase. When the Zn composition ratio among In, Ga, and Zn in the oxide semiconductor layer is maintained and b/(a+b) is adjusted to continue to increase the electron affinity difference, an electron affinity difference of about 1.3 eV can be obtained at the maximum. When the electron affinity of 1.3 eV or more is desired to be obtained, for example, there is a method of greatly changing the amount of Zn in the active layer, but when the amount of Zn is largely adjusted, the amorphous structure in the oxide semiconductor layer may become unstable. The instability of the TFT characteristics and the heterogeneity are caused, so that the difference in the electron affinity is preferably 1.3 eV or less.
氧濃度之控制為，具體而言可藉由在成膜第2領域時以氧分壓相對低的條件成膜，而針對成膜第1領域時以氧分壓相對高的條件成膜，或者，藉由在成膜第1領域後施作照射氧自由基或臭氧之處理而促進膜的氧化，減低第1領域中的氧缺損量等來進行。The oxygen concentration is controlled by, in particular, film formation under conditions in which the partial pressure of oxygen is relatively low in the second field of film formation, and film formation under conditions in which the oxygen partial pressure is relatively high in the first field of film formation, or In the first field of film formation, irradiation with oxygen radicals or ozone is carried out to promote oxidation of the film, and the amount of oxygen deficiency in the first field is reduced.
此外，以第1領域的氧缺損量極少者較佳。在將以往氧化物半導體層作為通道層使用的情況，為提高遷移率有有必要將載子密度增加某種程度，以有意地形成氧缺損，亦即逐漸降低氧濃度。然而氧缺損一多時，會有所謂氧缺陷自體相對於載子成為散亂體而招致遷移率降低之問題。本發明中作為通道層的載子由於是第2領域所供給，故即便是形成第1領域的氧缺損量極少的狀態仍有足夠的載子密度，可獲得伴隨該載子密度之遷移率。Further, it is preferable that the amount of oxygen deficiency in the first field is extremely small. In the case where a conventional oxide semiconductor layer is used as a channel layer, in order to increase the mobility, it is necessary to increase the carrier density to some extent to intentionally form an oxygen deficiency, that is, to gradually decrease the oxygen concentration. However, when there is a large amount of oxygen deficiency, there is a problem that the so-called oxygen-defective self-body becomes a scattered body with respect to the carrier, which causes a decrease in mobility. In the present invention, since the carrier as the channel layer is supplied in the second field, even when the amount of oxygen deficiency in the first field is extremely small, a sufficient carrier density is obtained, and the mobility accompanying the carrier density can be obtained.
本發明的薄膜電晶體係以前述氧化物半導體層之第1領域A1的b/(a+b)設成小於第2領域A2的b/(a+b)者較佳。再者，以第1領域A1的b/(a+b)是0.5以下者較佳。更好為，第1領域A1的 a/a+b是0.6以上且第2領域A2的b/a+b是0.6以上者。The thin film electro-crystal system of the present invention is preferably such that b/(a+b) of the first field A1 of the oxide semiconductor layer is smaller than b/(a+b) of the second field A 2 . Further, b/(a+b) in the first field A 1 is preferably 0.5 or less. More preferably, a/a+b of the first field A 1 is 0.6 or more and b/a+b of the second field A 2 is 0.6 or more.
藉由加大第1領域和第2領域的b/(a+b)之差，傳導帶下端的能差變大，可有效率地使電子載子局部存在於第1領域。By increasing the difference between b/(a+b) in the first field and the second field, the energy difference at the lower end of the conduction band becomes large, and the electron carrier can be efficiently present locally in the first field.
又，本發明中構成活性層的第1領域之Zn/In+Ga(相當於前述的一般式中的2c/(a+b))以0.5以上者較佳，第2領域的2c/(a+b)以0.5以下者較佳。隨著2c/(a+b)變大，光學吸收端係偏移至長波長側，帶隙係因2c/(a+b)變大而變窄。因此，在第1領域配置2c/(a+b)相對大的IGZO層，在第2領域配置2c/(a+b)相對小的IGZO層，藉此可獲得傳導帶下端的能差，可使電子載子局部存在於第1領域。控制2c/(a+b)的手法係藉由適用將b/(a+b)的差設大的膜而可形成更深的方井位能構造，當然b/(a+b)在各領域亦可在相同的情況中使用。Further, in the first aspect of the present invention, Zn/In+Ga (corresponding to 2c/(a+b) in the above general formula) which is an active layer is preferably 0.5 or more, and 2c/(a in the second field). +b) It is preferably 0.5 or less. As 2c/(a+b) becomes larger, the optical absorption end shifts to the longer wavelength side, and the band gap becomes narrower as 2c/(a+b) becomes larger. Therefore, an IGZO layer having a relatively large 2c/(a+b) is disposed in the first field, and an IGZO layer having a relatively small 2c/(a+b) is disposed in the second field, whereby the energy difference at the lower end of the conduction band can be obtained. The electron carrier is locally present in the first field. The method of controlling 2c/(a+b) can form a deeper square well energy structure by applying a film having a large difference of b/(a+b), of course b/(a+b) in various fields. It can also be used in the same situation.
又，藉由IGZO所構成的氧化物半導體層之Zn的一部分摻雜帶隙更廣的元素離子，可獲得更深的方井位能構造。具體而言，藉由摻雜Mg而將膜的帶隙設大。例如，藉由僅於第2領域摻雜Mg，可獲得更深的方井位能構造。又，在第1領域和第2領域之間呈具有b/(a+b)及2c/(a+b)的差之狀態，藉由於各領域摻雜Mg，與僅控制In、Ga、Zn的組成比之系列相較下，可維持井障壁的高度而使全體的帶隙加寬。Further, a part of Zn of the oxide semiconductor layer composed of IGZO is doped with element ions having a wider band gap, and a deeper well potential structure can be obtained. Specifically, the band gap of the film is made large by doping Mg. For example, by doping Mg only in the second field, a deeper well potential structure can be obtained. Further, between the first field and the second field, there is a difference of b/(a+b) and 2c/(a+b), and since each field is doped with Mg, only In, Ga, and Zn are controlled. Compared with the series, the composition of the well barrier can be maintained to widen the entire band gap.
有機EL所用的藍色發光層係呈現在λ=450nm左右具有峰值的寬頻帶響應的發光，在假設IGZO膜的光學帶隙較窄，且於該領域具有光學吸收的情況，會產生所謂引起電晶體的臨界值移位之問題。因此，特別是有機EL驅動用的薄膜電晶體方面，以通道層所用的材料之帶隙更大者較佳。The blue light-emitting layer used in the organic EL exhibits a broad-band response light having a peak at around λ = 450 nm. It is assumed that the optical band gap of the IGZO film is narrow, and optical absorption in the field causes a so-called electric generation. The problem of shifting the critical value of the crystal. Therefore, in particular, in the case of a thin film transistor for organic EL driving, a band gap of a material for a channel layer is larger.
當IGZO中加大b/(a+b)時則光學吸收端偏移至短波長側，雖帶隙寬廣，但同時地會因為b/(a+b)之大的組成而降低電氣傳導性。亦即，單獨將b/(a+b)大的IGZO膜使用於薄膜電晶體之情況，無法獲得所期望那樣的電晶體特性(具體而言，是超過數十～100cm2/Vs那樣的遷移率)(參照圖15(c))。在本發明中，係藉由使用將帶隙廣之b/(a+b)大的IGZO層(第2領域)和相對地帶隙窄之b/(a+b)小的IGZO層(第1領域)接合成的構造，形成由閘極絕緣膜和活性層所構成之方井位能，可使載子局部存在於第1領域。When b/(a+b) is increased in IGZO, the optical absorption end shifts to the short wavelength side. Although the band gap is wide, the electrical conductivity is reduced at the same time due to the large composition of b/(a+b). . In other words, when an IGZO film having a large b/(a+b) is used alone in a thin film transistor, it is impossible to obtain a desired crystal characteristic (specifically, a migration exceeding tens to 100 cm 2 /Vs). Rate) (Refer to Fig. 15 (c)). In the present invention, an IGZO layer (the second field) having a large b/(a+b) band gap and a small b/(a+b) having a relatively narrow band gap are used (first). The field is formed into a structure in which a square well energy composed of a gate insulating film and an active layer is formed, and the carrier can be locally present in the first field.
第1領域的載子密度可藉由第2領域的氧缺損量控制或陽離子摻雜而任意地控制。在欲增加載子密度之際，以增加第2領域的氧缺損量，或摻雜容易成為相對價數大的陽離子之材料(例如Ti、Zr、Hf、Ta等)即可。但是，摻雜價數大的陽離子之情況，由於氧化物半導體膜的構成元素數增加，因而在成膜處理的單純化、低成本化的面來說是不利，故以氧濃度(氧缺損量)來控制載子密度者較佳。The carrier density in the first field can be arbitrarily controlled by the oxygen deficiency amount control or the cation doping in the second field. When it is desired to increase the density of the carrier, the amount of oxygen deficiency in the second field may be increased, or the material (for example, Ti, Zr, Hf, Ta, or the like) which is likely to be a cation having a relatively large valence may be added. However, in the case of a cation having a large number of valences, the number of constituent elements of the oxide semiconductor film is increased, so that it is disadvantageous in the simplification and cost reduction of the film formation process, so the oxygen concentration (oxygen deficiency amount) It is better to control the carrier density.
此外，從可在300℃以下的溫度成膜這點，氧化物半導體層係以非晶質者較佳。例如，非晶質IGZO膜係可在基板溫度200℃以下成膜。Further, from the viewpoint that the film can be formed at a temperature of 300 ° C or lower, the oxide semiconductor layer is preferably amorphous. For example, an amorphous IGZO film can be formed at a substrate temperature of 200 ° C or lower.
活性層12之合計的膜厚(總膜厚)係以10～200nm左右者較佳。The total film thickness (total film thickness) of the active layer 12 is preferably from about 10 to 200 nm.
(源極‧汲極電極)(source ‧ 汲 electrode)
只要源極電極13和汲極電極14皆是具有高導電性者即可，並無特別制限，例如可將Al、Mo、Cr、Ta、Ti、Au、Ag等之金屬、Al-Nd、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等之金屬氧化物導電膜等作為單層或2層以上的積層構造使用。As long as the source electrode 13 and the drain electrode 14 are both highly conductive, there is no particular limitation. For example, metals such as Al, Mo, Cr, Ta, Ti, Au, Ag, etc., Al-Nd, and oxidation may be used. A metal oxide conductive film such as tin, zinc oxide, indium oxide, indium tin oxide (ITO) or indium zinc oxide (IZO) is used as a single layer or a laminated structure of two or more layers.
源極電極13和汲極電極14均能依據考慮到與例如印刷方式、塗布方式等之濕式方式、真空蒸鍍法、濺鍍法、離子電鍍法等之物理方式、CVD、電漿CVD法等之化學方式等中所使用的材料之適應性所適當選擇的方法進行成膜即可。Both the source electrode 13 and the drain electrode 14 can be physically, CVD, or plasma CVD in consideration of a wet method such as a printing method or a coating method, a vacuum vapor deposition method, a sputtering method, an ion plating method, or the like. The film may be formed by a method appropriately selected for the suitability of the material used in the chemical method or the like.
在利用上述金屬構成源極電極13和汲極電極14的情況，當考慮基於成膜性、蝕刻或掀離法的圖案性及導電性等時，該厚度以設為10nm以上1000nm以下者較佳，設為50nm以上100nm以下者更佳。In the case where the source electrode 13 and the drain electrode 14 are formed of the above-described metal, it is preferable to set the thickness to 10 nm or more and 1000 nm or less when considering the pattern property and conductivity based on the film formation property, the etching or the peeling method. It is more preferable to set it as 50 nm or more and 100 nm or less.
(閘極絕緣膜)(gate insulating film)
作為閘極絕緣膜15，以具有高絕緣性者較佳，例如可由SiO2、SiNx、SiON、Al2O3、Y2O3、Ta2O5、HfO2等之絕緣膜或至少包含二個以上彼等的化合物之絕緣膜等所構成。As the gate insulating film 15, it is preferable to have high insulating properties, for example, an insulating film of SiO 2 , SiN x , SiON, Al 2 O 3 , Y 2 O 3 , Ta 2 O 5 , HfO 2 or the like or at least An insulating film or the like of two or more of the compounds.
閘極絕緣膜15只要是依據與印刷方式、塗布方式等之濕式方式、真空蒸鍍法、濺鍍法、離子電鍍法等之物理方式、CVD、電漿CVD法等之化學方式等中所使用的材料之適應性所適當選擇的方法進行成膜即可。The gate insulating film 15 is a chemical method such as a wet method such as a printing method or a coating method, a vacuum vapor deposition method, a sputtering method, or an ion plating method, or a chemical method such as CVD or plasma CVD. It is sufficient to form a film by a method appropriately selected for the suitability of the material to be used.
此外，為降低漏洩電流及提升耐電壓性，閘極絕緣膜15有需要足夠的厚度，但另一方面，厚度過大則會招致驅動電壓上升。閘極絕緣膜15的厚度係因材質而異，但以10nm～10μm較佳，50nm～1000nm更佳，100nm～400nm特佳。Further, in order to reduce the leakage current and improve the withstand voltage, the gate insulating film 15 needs to have a sufficient thickness, but on the other hand, if the thickness is too large, the driving voltage rises. The thickness of the gate insulating film 15 varies depending on the material, but is preferably 10 nm to 10 μm, more preferably 50 nm to 1000 nm, and particularly preferably 100 nm to 400 nm.
(閘極電極)(gate electrode)
作為閘極電極16，只要是具有高導電性者即可，並無特別制限，例如可將Al、Mo、Cr、Ta、Ti、Au、Ag等之金屬、Al-Nd、氧化錫、氧化鋅、氧化銦、氧化銦錫(ITO)、氧化鋅銦(IZO)等之金屬氧化物導電膜等作為單層或2層以上的積層構造使用。The gate electrode 16 is not particularly limited as long as it has high conductivity. For example, a metal such as Al, Mo, Cr, Ta, Ti, Au, or Ag, Al-Nd, tin oxide, or zinc oxide can be used. A metal oxide conductive film such as indium oxide, indium tin oxide (ITO) or indium zinc oxide (IZO) is used as a single layer or a laminated structure of two or more layers.
閘極電極16只要是依據與例如印刷方式、塗布方式等之濕式方式、真空蒸鍍法、濺鍍法、離子電鍍法等之物理方式、CVD、電漿CVD法等之化學方式等中所使用的材料之適應性所適當選擇的方法進行成膜即可。The gate electrode 16 is a chemical method such as a wet method such as a printing method or a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, or a chemical method such as a CVD or plasma CVD method. It is sufficient to form a film by a method appropriately selected for the suitability of the material to be used.
在利用上述金屬構成閘極電極16之情況，當考慮基於成膜性、蝕刻或掀離法的圖案性及導電性等時，該厚度以設為10nm以上1000nm以下者較佳，以設為50nm以上200nm以下者更佳。In the case where the gate electrode 16 is formed of the above-described metal, it is preferable to set the thickness to 10 nm or more and 1000 nm or less, and to set it as 50 nm, in consideration of patterning property, conductivity, or the like based on film formation property, etching or peeling method. Above 200nm is better.
(薄膜電晶體的製造方法)(Manufacturing method of thin film transistor)
茲針對圖3(A)所示的頂閘極-頂接觸型之薄膜電晶體1的製造方法作簡單說明。準備基板11，在基板11上利用濺鍍法等之成膜手法將活性層(IGZO膜)12按第2領域A2、第1領域A1的順序成膜。其次將活性層12圖案化。圖案化係採用光微影成像及蝕刻方式進行。具體而言，在殘存的部分利用光微影成像形成光阻圖案，利用鹽酸、硝酸、稀硫酸、或磷酸、硝酸及乙酸的混合液等之酸溶液進行蝕刻而形成圖案。A method of manufacturing the top gate-top contact type thin film transistor 1 shown in Fig. 3(A) will be briefly described. The substrate 11 is prepared, and the active layer (IGZO film) 12 is formed on the substrate 11 in the order of the second field A 2 and the first field A 1 by a film formation method such as a sputtering method. Next, the active layer 12 is patterned. The patterning is performed by photolithography and etching. Specifically, a photoresist pattern is formed by photolithography in a remaining portion, and is patterned by etching with an acid solution such as hydrochloric acid, nitric acid, dilute sulfuric acid, or a mixed solution of phosphoric acid, nitric acid, and acetic acid.
其次，在活性層12之上形成用以形成源極‧汲極電極13、14的金屬膜。接著將金屬膜利用蝕刻或掀離法圖案化成規定的形狀，形成源極電極13和汲極電極14。此時，以源極‧汲極電極13、14及未圖示之連接於彼等電極之配線同時地圖案化者較佳。Next, a metal film for forming the source ‧ drain electrodes 13, 14 is formed on the active layer 12. Next, the metal film is patterned into a predetermined shape by etching or detachment, and the source electrode 13 and the drain electrode 14 are formed. In this case, it is preferable to simultaneously pattern the source electrodes ‧ the electrodes 13 and 14 and the wirings connected to the electrodes (not shown).
在形成源極‧汲極電極13、14及配線之後，形成閘極絕緣膜15。閘極絕緣膜15係利用光微影成像及蝕刻而被圖案化形成規定的形狀。After the source electrodes ‧ the electrodes 13 and 14 and the wiring are formed, the gate insulating film 15 is formed. The gate insulating film 15 is patterned into a predetermined shape by photolithography and etching.
在形成閘極絕緣膜15之後，形成閘極電極16。將電極膜成膜後，利用蝕刻或掀離法圖案化成規定的形狀，形成閘極電極16。此時，以將閘極電極16及閘極配線同時地圖案化者較佳。After the gate insulating film 15 is formed, the gate electrode 16 is formed. After the electrode film is formed into a film, it is patterned into a predetermined shape by etching or detachment to form the gate electrode 16. In this case, it is preferable to simultaneously pattern the gate electrode 16 and the gate wiring.
藉由以上的程序，可製造圖3A所示的薄膜電晶體1。By the above procedure, the thin film transistor 1 shown in Fig. 3A can be manufactured.
(活性層之成膜步驟)(film formation step of active layer)
其次，針對活性層的成膜步驟作更詳細說明。活性層12之合計的膜厚(總膜厚)以10～200nm左右較佳，以各領域未曝露於大氣中之情況下連續地成膜者較佳。藉由未曝露於大氣中之情況下連續地成膜，結果，可獲得更優異的電晶體特性。又，由於可削減成膜步驟數目，故亦能減低製造成本。Next, the film formation step of the active layer will be described in more detail. The total film thickness (total film thickness) of the active layer 12 is preferably about 10 to 200 nm, and it is preferable to continuously form a film in the case where each field is not exposed to the atmosphere. By continuously forming a film without being exposed to the atmosphere, as a result, more excellent transistor characteristics can be obtained. Moreover, since the number of film forming steps can be reduced, the manufacturing cost can also be reduced.
此處，針對圖3(C)(D)所示那樣的底閘極型之薄膜電晶體製造時作說明。如同已述及，在製造底閘極型的薄膜電晶體時以第1領域A1、第2領域A2的順序成膜。此外，在製造頂閘極型的薄膜電晶體時，活性層係以第2領域A2、第1領域A1的順序成膜。Here, the case of the bottom gate type thin film transistor as shown in FIG. 3(C)(D) will be described. As described above, in the case of manufacturing a bottom gate type thin film transistor, a film is formed in the order of the first field A 1 and the second field A 2 . Further, in the case of manufacturing a top gate type thin film transistor, the active layer is formed in the order of the second field A 2 and the first field A 1 .
首先，成膜第1領域A1。此處，例如，作為第1領域A1，係將Ga/(In+Ga)=0.25，Zn/(In+Ga)=0.5的IGZO膜形成膜厚10nm。First, the first field A 1 is formed . Here, for example, as the first field A 1 , an IGZO film having Ga/(In+Ga)=0.25 and Zn/(In+Ga)=0.5 is formed to have a film thickness of 10 nm.
有關以可成為上述那樣的金屬元素之組成比般地進行成膜的手法方面，只要是濺鍍成膜，則可為將In、Ga、Zn、或彼等的氧化物或者彼等的複合氧化物之標靶組合使用的共濺鍍，亦可為預先使既成膜之IGZO膜中的金屬元素的組成比成為上述那様的複合氧化物標靶的單獨濺鍍。成膜中的基板溫度雖可因應基板任意地選擇，但在使用撓性基板的情況以基板溫度是更接近於室溫者較佳。The method of forming a film by the composition ratio of the metal element as described above may be an oxide of In, Ga, Zn, or the like or a composite thereof as long as it is formed by sputtering. The co-sputtering used for the combination of the targets may be a single sputtering in which the composition ratio of the metal elements in the film-forming IGZO film is previously set to be the composite oxide target of the above-mentioned ruthenium. Although the substrate temperature in the film formation can be arbitrarily selected in accordance with the substrate, in the case of using the flexible substrate, it is preferable that the substrate temperature is closer to room temperature.
提高第1領域的載子密度之情況為，相對地降低成膜時的成膜室內之氧分壓以降低膜中的氧濃度。例如設成膜時的氧分壓/氬分壓為0.005。反之在將電子載子密度設低的情況，係將成膜時的成膜室內之氧分壓相對地設高(例如設成膜時的氧分壓/氬分壓為0.05)、或在成膜中或成膜後照射氧自由基、或者在臭氧環境中將紫外線照射於該成膜基板表面等，藉以提高膜中的氧濃度。The case where the carrier density in the first field is increased is such that the partial pressure of oxygen in the deposition chamber at the time of film formation is relatively lowered to lower the oxygen concentration in the film. For example, the oxygen partial pressure/argon partial pressure at the time of film formation is 0.005. On the other hand, when the electron carrier density is set to be low, the oxygen partial pressure in the deposition chamber at the time of film formation is relatively high (for example, the oxygen partial pressure at the time of film formation/the partial pressure of argon is 0.05), or The oxygen concentration in the film is increased by irradiating oxygen radicals in the film or after film formation, or irradiating ultraviolet rays on the surface of the film formation substrate in an ozone atmosphere.
其次，進行第2領域的成膜。第2領域的成膜可採用是在成膜第1領域後，暫時停止成膜，在變更施加於成膜室內之氧分壓及標靶的電力之後再開始成膜的方法，亦可採用在不停止成膜之下加速施加於成膜室內之氧分壓及標靶的電力或和緩地變更之方法。又，可採用標靶是沿用第1領域成膜時所用的標靶，並變化投入電力的手法，亦可採用在從成膜第1領域切換至成膜第2領域之際停止朝第1領域成膜所用的標靶進行電力投入，且對不同的標靶進行電力施加的手法，亦可採用除了第1領域的成膜所用的標靶以外，再追加複數個標靶並進行電力施加之手法。Next, film formation in the second field is carried out. The film formation in the second field may be a method in which the film formation is temporarily stopped after the first field of film formation, and the film is formed by changing the oxygen partial pressure applied to the deposition chamber and the power of the target, and may be used. The method of accelerating the partial pressure of oxygen applied to the inside of the film forming chamber and the power of the target or changing it gently is not stopped. In addition, the target can be used as a target used for film formation in the first field, and the method of changing the input power can be used, and the first field can be stopped when switching from the first field of film formation to the second field of film formation. In the method of applying power to a target for film formation and applying electric power to different targets, a method of adding a plurality of targets and applying electric power in addition to the target used for film formation in the first field may be employed. .
此處，作為第2領域，例如是將金屬元素的組成比是Ga/(In+Ga)=0.75，Zn/(In+Ga)=0.5的IGZO膜形成膜厚30nm。Here, as a second field, for example, an IGZO film having a composition ratio of a metal element of Ga/(In+Ga)=0.75 and Zn/(In+Ga)=0.5 is formed to have a film thickness of 30 nm.
成膜中的基板溫度雖可因應基板任意地選擇，但在使用撓性基板的情況，基板溫度以更接近室溫者較佳。Although the substrate temperature in the film formation can be arbitrarily selected depending on the substrate, when the flexible substrate is used, the substrate temperature is preferably closer to room temperature.
提高第2領域的載子密度之情況為，將成膜時的成膜室內之氧分壓相對地降低，以降低膜中的氧濃度。例如成膜時的氧分壓/氬分壓設為0.005。反之在降低電子載子密度的情況，將成膜時的成膜室內之氧分壓相對地提高(例如成膜時的氧分壓/氬分壓設為0.05)、或在成膜中或成膜後照射氧自由基、或是在臭氧環境中將紫外線照射於該成膜基板表面等藉以提高膜中的氧濃度。本發明的實施形態中，將第1領域的氧濃度設成比第2領域的氧濃度高者更佳。The case where the carrier density in the second field is increased is such that the oxygen partial pressure in the deposition chamber at the time of film formation is relatively lowered to lower the oxygen concentration in the film. For example, the oxygen partial pressure/argon partial pressure at the time of film formation is set to 0.005. On the other hand, when the electron carrier density is lowered, the partial pressure of oxygen in the film forming chamber at the time of film formation is relatively increased (for example, the partial pressure of oxygen at the time of film formation/partial pressure of argon is set to 0.05), or in film formation or formation. The oxygen concentration in the film is increased by irradiating oxygen radicals after the film or by irradiating ultraviolet rays on the surface of the film formation substrate in an ozone atmosphere. In the embodiment of the present invention, the oxygen concentration in the first field is set to be higher than the oxygen concentration in the second field.
此外，在氧自由基之照射或臭氧環境中藉由紫外線照射以提高膜中的氧濃度之際，可在成膜第1領域及第2領域中及成膜後雙方再進行，亦可僅在成膜第2領域後進行。又，氧自由基照射時的基板溫度雖可因應基板而任意地選擇，但在使用撓性基板的情況基板溫度以更接近室溫者較佳。In addition, when the oxygen concentration in the film is increased by ultraviolet irradiation or irradiation in an ozone atmosphere, it can be carried out in both the first field and the second field of film formation and after film formation, or only in the case of film formation. Film formation was carried out in the second field. Further, the substrate temperature at the time of oxygen radical irradiation can be arbitrarily selected depending on the substrate. However, when the flexible substrate is used, the substrate temperature is preferably closer to room temperature.
再者，亦可在氧化物半導體層形成後施作退火處理。退火之際的環境可因應膜而任意地選擇，退火溫度亦可因應基板而任意地選擇，但在使用撓性基板的情況以低溫(例如200℃以下)作退火者較佳。另一方面，在使用具高耐熱性的基板之情況，亦能以接近500℃的高溫施作退火處理。Further, an annealing treatment may be performed after the formation of the oxide semiconductor layer. The environment during annealing can be arbitrarily selected depending on the film, and the annealing temperature can be arbitrarily selected depending on the substrate. However, in the case of using a flexible substrate, it is preferable to use a low temperature (for example, 200 ° C or lower) for annealing. On the other hand, in the case of using a substrate having high heat resistance, annealing treatment can be performed at a high temperature of approximately 500 °C.
此外，圖4係顯示將Ga/(In+Ga)=0.75之IGZO膜和Ga/(In+Ga)=0.25的IGZO膜積層5層後之積層膜的剖面STEM像，同圖(A)係積層之後不久(退火處理前)，同圖(B)係以退火溫度250℃作處理者，同圖(C)係以退火溫度500℃作處理者。從圖4可確認即使以500℃進行退火處理仍可維持積層構造。4 is a cross-sectional STEM image of a laminated film in which an IGZO film of Ga/(In+Ga)=0.75 and an IGZO film of Ga/(In+Ga)=0.25 are laminated, and the same is shown in FIG. Shortly after the lamination (before annealing), the same figure (B) is treated at an annealing temperature of 250 ° C, and the same drawing (C) is treated at an annealing temperature of 500 ° C. It can be confirmed from Fig. 4 that the laminated structure can be maintained even if the annealing treatment is performed at 500 °C.
此外，本發明者們係進行以下的實驗而確認了可藉由陽離子組成比及/或氧濃度使IGZO層的電子親和力變化、及藉由作成方井位能構造而可將能隙小的IGZO層作為井層使用。In addition, the inventors of the present invention confirmed that the electron affinity of the IGZO layer can be changed by the cation composition ratio and/or the oxygen concentration, and the IGZO having a small energy gap can be formed by forming a square well potential structure. The layer is used as a well layer.
電子親和力χ係如前述是由離子化位能I和帶隙能Eg之差所決定。帶隙能Eg係能進行光的反射率及透過率測定，使用Tauc plot算出。此處的帶隙能Eg係指直接遷移的值。又，離子化位能I可從光電子分光測定求取。The electron affinity system is determined by the difference between the ionization potential energy I and the band gap energy Eg as described above. The band gap energy Eg system can measure the reflectance and transmittance of light, and is calculated using Tauc plot. The band gap energy Eg herein refers to the value of direct migration. Further, the ionization potential energy I can be obtained from photoelectron spectroscopy.
(電子親和力χ的陽離子組成比依存)(The cation composition ratio of electron affinity χ is dependent)
製造陽離子組成比不同的樣本1～5，進行上述各測定以調査電子親和力χ對陽離子組成比之依存性。Samples 1 to 5 having different cation composition ratios were produced, and each of the above measurements was carried out to investigate the dependence of the electron affinity χ on the cation composition ratio.
首先，將IGZO膜設為測定對象，製造陽離子組成比不同的IGZO膜樣本1～5。樣本1～5係陽離子組成比Ga/(In+Ga)不同的IGZO膜分別成膜於基板上者。任一樣本都是使用合成石英玻璃基板(科發倫材料公司製品，品號T-4040)作為基板。First, an IGZO film was used as a measurement target, and IGZO film samples 1 to 5 having different cation composition ratios were produced. Samples 1 to 5 are IGZO films having a different cation composition than Ga/(In+Ga) formed on the substrate. For each of the samples, a synthetic quartz glass substrate (product of Kodak Materials Co., product number T-4040) was used as the substrate.
樣本1係在基板上成膜100nm厚度的Ga/(In+Ga)=0，Zn/(In+Ga)=0.5的IGZO膜。成膜時的氧分壓/氬分壓=0.01，以採用In2O3標靶、Ga2O3標靶及ZnO標靶的共濺鍍(co-sputter)進行。此外，成膜時的基板溫度設成室溫，成膜時的成膜室內壓力係藉由自動控制排氣閥之開度而始終保持4.4×10-1Pa。In the sample 1, an IGZO film having a thickness of 100 nm of Ga/(In+Ga)=0 and Zn/(In+Ga)=0.5 was formed on the substrate. The oxygen partial pressure at the time of film formation/argon partial pressure = 0.01 was carried out by co-sputter using an In 2 O 3 target, a Ga 2 O 3 target, and a ZnO target. Further, the substrate temperature at the time of film formation was set to room temperature, and the pressure in the film formation chamber at the time of film formation was always maintained at 4.4 × 10 -1 Pa by automatically controlling the opening degree of the exhaust valve.
樣本2～5係除了Ga/(In+Ga)的值不同這點以外，其餘是以和樣本1同樣的製造程序所製造。樣本2係設Ga/(In+Ga)=0.25，樣本3係設Ga/(In+Ga)=0.5，樣本4係設Ga/(In+Ga)=0.75，而樣本5係設Ga/(In+Ga)=1。Samples 2 to 5 were produced in the same manufacturing procedure as Sample 1 except that the value of Ga/(In+Ga) was different. Sample 2 is set to Ga/(In+Ga)=0.25, sample 3 is set to Ga/(In+Ga)=0.5, sample 4 is set to Ga/(In+Ga)=0.75, and sample 5 is set to Ga/( In+Ga)=1.
此外，各樣本1～5中的Ga/(In+Ga)及Zn/(In+Ga)之控制係藉由調整投入於In2O3、Ga2O3、ZnO各標靶的電力值而進行。Further, the control of Ga/(In+Ga) and Zn/(In+Ga) in each of the samples 1 to 5 is adjusted by adjusting the electric power values of the targets of In 2 O 3 , Ga 2 O 3 , and ZnO. get on.
從針對各樣本1～5所進行之反射率及透過率測定的結果所獲得之Tauc plot顯示在圖5。可知Ga/(In+Ga)變越大則帶隙能亦變大。The Tauc plot obtained from the results of the reflectance and transmittance measurements performed for each of the samples 1 to 5 is shown in Fig. 5. It can be seen that the band gap energy is also increased as Ga/(In+Ga) becomes larger.
圖6係表示從圖5所示的Tauc plot導出的各樣本之帶隙能。由該結果可清楚瞭解當Ga/(In+Ga)從0至1變大時，帶隙能從1.2變大至1.3eV左右。Fig. 6 is a graph showing the band gap energy of each sample derived from the Tauc plot shown in Fig. 5. From this result, it is clear that when Ga/(In+Ga) becomes larger from 0 to 1, the band gap energy is increased from 1.2 to about 1.3 eV.
圖7係表示有關基於各樣本1～5的光電子分光測定之激發光能和規格化光電子產率。圖7的圖表中意味著各個曲線之上升的激發光能，亦即開始放出光電子的能值是離子化位能。Fig. 7 is a graph showing the excitation light energy and the normalized photoelectron yield of the photoelectron spectroscopy measurement based on each of the samples 1 to 5. In the graph of Fig. 7, the excitation light energy of the rise of each curve, that is, the energy value at which the photoelectrons are started to be emitted, is the ionization potential energy.
圖8係表示從圖7的圖表所求得之各樣本1～5的離子化位能之圖表。從圖8明白Ga/(In+Ga)是0.5附近離子化位能取最大值，隨著偏離該處而離子化位能變小。Fig. 8 is a graph showing the ionization potential of each of the samples 1 to 5 obtained from the graph of Fig. 7. It is understood from Fig. 8 that Ga/(In+Ga) is a maximum value of the ionization potential in the vicinity of 0.5, and the ionization potential becomes smaller as it deviates from this.
由先前求得之帶隙能Eg和離子化位能I的差求得各樣本1～5的電子親和力χ。其次所示的表2係將各樣本的組成比、氧分壓/氬分壓、能隙Eg、離子化位能I及電子親和力χ作成一覽表。The electron affinity χ of each of the samples 1 to 5 was obtained from the difference between the band gap energy Eg and the ionization potential energy I obtained previously. Table 2, which is shown next, is a list of the composition ratio of each sample, the oxygen partial pressure/argon partial pressure, the energy gap Eg, the ionization potential energy I, and the electron affinity χ.
[表2][Table 2]
圖9係表示從上述結果獲得之電子親和力對Ga/(In+Ga)依存性。可知電子親和力χ在Ga/(In+Ga)是0.25附近取最大值，隨著偏離該處而變小，瞭解到當Ga/(In+Ga)從0.25變大到1時則電子親和力從1.2變小到1.3eV左右。Fig. 9 is a graph showing the dependence of the electron affinity obtained from the above results on Ga/(In + Ga). It can be seen that the electron affinity χ takes a maximum value near Ga/(In+Ga) of 0.25, and becomes smaller as it deviates from this point. It is understood that when Ga/(In+Ga) is increased from 0.25 to 1, the electron affinity is from 1.2. It is reduced to about 1.3eV.
如以上所述，明白藉由變化Ga/In+Ga能變化電子親和力。因此，在IGZO所構成的氧化物半導體層中，例如在未進行領域A1、A2的氧濃度調變之情況，可知藉由將領域A1的Ga/(In+Ga)設為0.25，領域A2的Ga/In+Ga設為0.75，可作成領域A1、A2的位能差0.48eV的井型構造。As described above, it is understood that the electron affinity can be changed by changing Ga/In+Ga. Therefore, in the oxide semiconductor layer formed of IGZO, for example, when the oxygen concentration of the domains A 1 and A 2 is not changed, it is understood that the Ga/(In+Ga) of the domain A 1 is 0.25. The Ga/In+Ga of the field A 2 is set to 0.75, and a well structure having a potential difference of 0.48 eV in the fields A 1 and A 2 can be obtained.
(電子親和力χ的氧濃度依存)(Electronic affinity depends on the oxygen concentration)
製造氧濃度不同的樣本6～9，調査進行了同樣的測定之電子親和力χ對氧濃度的依存性。Samples 6 to 9 having different oxygen concentrations were produced, and the dependence of the electron affinity χ on the oxygen concentration in the same measurement was investigated.
樣本6～9係和上述同樣地將IGZO膜設為測定對象，以同樣的製造程序及在同樣的基板上成膜所獲得。樣本6係Ga/(In+Ga)=0.75，Zn/(In+Ga)=0.5，且設成膜時的氧分壓/氬分壓=0。樣本7係設樣本6中之成膜時的氧分壓/氬分壓=0.01。樣本8係Ga/(In+Ga)=0.25，Zn/(In+Ga)=0.5，且設成膜時的氧分壓/氬分壓=0。樣本9係設樣本8中之成膜時的氧分壓/氬分壓=0.01。所製造之樣本6至9的組成比、氧分壓/氬分壓及後述的能隙等呈現於表3。Samples 6 to 9 were obtained by measuring the IGZO film in the same manner as described above, and forming the film on the same substrate. The sample 6 was Ga/(In+Ga)=0.75, Zn/(In+Ga)=0.5, and the oxygen partial pressure/argon partial pressure at the time of film formation was set to 0. The sample 7 was set to have an oxygen partial pressure/argon partial pressure = 0.01 at the time of film formation in the sample 6. The sample 8 was Ga/(In+Ga)=0.25, Zn/(In+Ga)=0.5, and the oxygen partial pressure/argon partial pressure at the time of film formation was set to 0. In the sample 9, the oxygen partial pressure/argon partial pressure at the time of film formation in the sample 8 was set to 0.01. The composition ratio of the produced samples 6 to 9, the oxygen partial pressure/argon partial pressure, and the energy gap described later are shown in Table 3.
[表3][table 3]
針對各樣本6～9所進行的反射率及透過率測定之結果的Tauc plot顯示於圖10(A)及(B)。圖10(A)是針對Ga/(In+Ga)是0.75的樣本6及7，圖10(B)是針對Ga/(In+Ga)是0.25的樣本8，9之Tauc plot。瞭解到任一情況，即使變化成膜時的氧分壓/氬分壓，帶隙能Eg還是没有大的變化。The Tauc plot of the results of the reflectance and transmittance measured for each of the samples 6 to 9 is shown in Figs. 10(A) and (B). Fig. 10(A) shows samples 6 and 7 for Ga/(In+Ga) of 0.75, and Fig. 10(B) shows Tauc plot for samples 8,9 with Ga/(In+Ga) of 0.25. Knowing either case, even if the oxygen partial pressure/argon partial pressure at the time of film formation was changed, the band gap energy Eg did not change much.
圖11係以氧分壓/氬分壓作為橫軸而繪製從圖10(A)及圖10(B)所示的Tauc plot導出之各樣本的帶隙能。從該結果可明白即使變化氧分壓/氬分壓，帶隙能幾乎沒變化。Fig. 11 is a graph showing the band gap energy of each sample derived from the Tauc plot shown in Figs. 10(A) and 10(B) with the oxygen partial pressure/argon partial pressure as the horizontal axis. From this result, it is understood that the band gap energy hardly changes even if the oxygen partial pressure/argon partial pressure is changed.
圖12(A)係表示針對樣本6，7，圖12(B)係針對樣本8，9之基於光電子分光測定的激發光能和規格化光電子產率，圖13係表示從圖12(A)及圖12(B)的圖表所求得之各樣本的離子化位能。由圖13所示的結果可知，即使是Ga/(In+Ga)的值不同的情況，随著成膜時的氧分壓/氬分壓變大，離子化位能會變大。Fig. 12(A) shows the excitation light energy and the normalized photoelectron yield based on the photoelectron spectroscopy for the samples 8, 9 for the samples 6, 7 and Fig. 12(B), and Fig. 13 shows the Fig. 12(A). And the ionization potential of each sample obtained from the graph of Fig. 12(B). As is clear from the results shown in FIG. 13, even when the value of Ga/(In+Ga) is different, the ionization potential is increased as the oxygen partial pressure/argon partial pressure at the time of film formation becomes large.
由先前求得之帶隙能Eg和離子化位能I的差求得各樣本6～9的電子親和力χ(參照表3)。The electron affinity χ of each of the samples 6 to 9 was determined from the difference between the band gap energy Eg and the ionization potential I obtained previously (refer to Table 3).
圖14係表示從上述結果所獲得之電子親和力對成膜時的氧分壓/氬分壓依存性。明白成膜時的氧分壓/氬分壓越大電子親和力χ越大。瞭解到當成膜時的氧分壓/氬分壓從0變大到0.01時則Ga/(In+Ga)的值在0.75，0.25任一情況，電子親和力皆變大0.2eV左右。Fig. 14 is a graph showing the dependence of the electron affinity obtained from the above results on the oxygen partial pressure/argon partial pressure dependence at the time of film formation. It is understood that the larger the oxygen partial pressure/argon partial pressure at the time of film formation, the larger the electron affinity χ. It is understood that when the oxygen partial pressure/argon partial pressure at the time of film formation is increased from 0 to 0.01, the value of Ga/(In+Ga) is 0.75, 0.25, and the electron affinity is increased by about 0.2 eV.
如以上所述，藉由變化成膜時的氧分壓/氬分壓，能變化電子親和力，更詳言之，明白藉由將氧分壓/氬分壓設大可加大電子親和力。As described above, the electron affinity can be changed by changing the oxygen partial pressure/argon partial pressure at the time of film formation, and more specifically, it is understood that the electron affinity can be increased by setting the oxygen partial pressure/argon partial pressure to be large.
因此，在IGZO所構成的氧化物半導體層中，例如，藉由調變領域A1、領域A2的b/(a+b)所賦與之電子親和力差以外，藉由將領域A1成膜時的氧分壓/氬分壓設成大於領域A2成膜時的氧分壓/氬分壓，可獲得更大的電子親和力差。Therefore, in the oxide semiconductor layer formed of IGZO, for example, the domain A 1 is formed by the difference in electron affinity imparted by b/(a+b) of the modulation domain A 1 and the domain A 2 . The oxygen partial pressure/argon partial pressure at the time of film formation is set to be larger than the partial pressure of oxygen/argon partial pressure at the time of film formation in the field A 2 , and a larger difference in electron affinity can be obtained.
此外，一般而言，由於在成膜時的氧分壓/氬分壓大的情況膜中的氧濃度高，反之在成膜時的氧分壓/氬分壓小的情況氧濃度變低，所以上述結果係意味著随著膜中的氧濃度變高，電子親和力會變大。In addition, in general, the oxygen concentration in the film is high when the oxygen partial pressure/argon partial pressure at the time of film formation is large, and the oxygen concentration is low when the oxygen partial pressure/argon partial pressure at the time of film formation is small. Therefore, the above results mean that as the oxygen concentration in the film becomes higher, the electron affinity becomes larger.
本實驗中，在提高膜內的氧濃度之手法方面，雖採用所謂加大成膜時的氧分壓/氬分壓之方法，除此之外，採用使氧自由基照射於成膜面之在臭氧環境中照射紫外線於成膜面等之方法同樣亦能提高膜內的氧濃度。In this experiment, in order to increase the oxygen concentration in the film, a method of increasing the oxygen partial pressure/argon partial pressure at the time of film formation is employed, and in addition, oxygen radicals are irradiated onto the film formation surface. The method of irradiating ultraviolet rays on the film formation surface or the like in an ozone atmosphere can also increase the oxygen concentration in the film.
上述之Ga/(In+Ga)的調變和膜中氧濃度的調變可同時地適用，例如，藉由作成以第1領域A1是Ga/(In+Ga)=0.25的組成比且膜中氧濃度高(成膜時的氧分壓/氬分壓=0.01)IGZO膜(表3中的樣本9)，以第2領域A2是Ga/(In+Ga)=0.75附近的組成比且膜中氧濃度低(成膜時的氧分壓/氬分壓=0)IGZO膜(表3中的樣本6)夾入的構造，可獲得比僅組成比或僅氧濃度調變的情況還深的井型障壁構造(電子親和力差Δχ=0.65)。The above-described modulation of Ga/(In+Ga) and the modulation of the oxygen concentration in the film can be simultaneously applied, for example, by forming a composition ratio of Ga/(In+Ga)=0.25 in the first field A 1 and The oxygen concentration in the film was high (oxygen partial pressure at the time of film formation/argon partial pressure = 0.01) IGZO film (sample 9 in Table 3), and the composition in the second field A 2 was Ga/(In+Ga)=0.75. The structure in which the oxygen concentration in the film is low (oxygen partial pressure at the time of film formation/argon partial pressure = 0) IGZO film (sample 6 in Table 3) is sandwiched, and only a composition ratio or only oxygen concentration modulation can be obtained. A deep well type barrier structure (electron affinity difference Δχ = 0.65).
此處，茲針對IGZO膜中的載子濃度、遷移率所進行的實驗作說明。載子濃度及遷移率可藉由霍爾效應及比電阻之測定求得。Here, an experiment conducted on the carrier concentration and mobility in the IGZO film will be described. The carrier concentration and mobility can be determined by measuring the Hall effect and the specific resistance.
圖15(A)～(C)係分別表示變化氧分壓/氬分壓而製造之IGZO膜中的比電阻、載子密度、及遷移率對Ga/(In+Ga)依存性者。圖15中係有關●是氧分壓/氬分壓為0.01，█是氧分壓/氬分壓為0.005，而▲是氧分壓/氬分壓為0的樣本之資料。15(A) to 15(C) show the dependence of specific resistance, carrier density, and mobility on Ga/(In+Ga) in the IGZO film produced by changing the partial pressure of oxygen/argon partial pressure. In Fig. 15, the correlation is that the oxygen partial pressure/argon partial pressure is 0.01, █ is the oxygen partial pressure/argon partial pressure of 0.005, and ▲ is the sample of the oxygen partial pressure/argon partial pressure of 0.
供作測定的樣本係以和上述同樣的方法所製造者。而霍爾效應及比電阻的測定係採用了霍爾測定裝置(東陽技術製，霍爾效應‧比電阻測定裝置Resitest 8300)。The sample to be measured is manufactured in the same manner as described above. The Hall effect and the specific resistance were measured by a Hall measuring device (manufactured by Toyo Technologies, Hall effect ‧ specific resistance measuring device Resitest 8300).
由圖15(B)可知藉由變化Ga/(In+Ga)或氧分壓/氬分壓能獨立地控制載子密度。例如藉由將Ga/(In+Ga)設成一定且僅變化氧分壓/氬分壓，可在未變化膜的帶隙之下僅任意地調整膜中的載子濃度。但在氧分壓/氬分壓為0時，可知藉由變化Ga/(In+Ga)可任意地控制載子濃度，但如圖15(C)所示的遷移率係維持低的狀態。由該結果可知，僅增加氧缺損量、增加載子濃度並無法獲得提升所期望的遷移率。From Fig. 15(B), it is understood that the carrier density can be independently controlled by changing Ga / (In + Ga) or oxygen partial pressure / argon partial pressure. For example, by setting Ga/(In+Ga) to be constant and changing only the oxygen partial pressure/argon partial pressure, the carrier concentration in the film can be arbitrarily adjusted only under the band gap of the unaltered film. However, when the oxygen partial pressure/argon partial pressure was 0, it was found that the carrier concentration can be arbitrarily controlled by changing Ga/(In+Ga), but the mobility shown in FIG. 15(C) is maintained low. From this result, it is understood that only increasing the oxygen deficiency amount and increasing the carrier concentration fail to obtain the desired mobility.
其次，針對比較IGZO的單層膜和積層構造之載子濃度、遷移率的結果作說明。Next, the results of comparing the carrier concentration and mobility of the monolayer film and the laminated structure of IGZO will be described.
在積層構造方面，係在基板上將樣本7的組成比(0.25)-氧分壓/氬分壓(0.01)的IGZO膜成膜10nm後，連續地將樣本6的組成比(0.75)-氧分壓/氬分壓(0)成膜50nm而製造出霍爾元件。In the aspect of the laminated structure, after the film of the sample 7 has a composition ratio (0.25)-oxygen partial pressure/argon partial pressure (0.01) of the IGZO film formed by filming 10 nm, the composition ratio of the sample 6 (0.75)-oxygen is continuously performed. The Hall element was fabricated by dividing the pressure/argon partial pressure (0) into a film of 50 nm.
在單膜方面，分別準備樣本7(IGZO-0.25-0.01)、樣本6(IGZO-0.75-0)各自之單膜的霍爾元件。In the case of a single film, Hall elements of a single film of each of Sample 7 (IGZO-0.25-0.01) and Sample 6 (IGZO-0.75-0) were prepared.
與各領域之單膜的載子濃度相較、或與從積層單膜的情況之單純平均所預測的載子濃度值相較下，積層構造係載子密度增大，遷移率增大。此乃意味著形成方井位能而電子在井層移動。The carrier density of the laminated structure is increased and the mobility is increased as compared with the carrier concentration of the single film in each field or the carrier concentration value predicted from the simple average of the case of the laminated single film. This means that the square well is formed and the electrons move in the well.
以上所說明之本發明的薄膜電晶體之用途並未特限定，例如適合作為電氣光學裝置的顯示裝置(例如液晶顯示裝置，有機EL(Electro Luminescence)顯示裝置，無機EL顯示裝置等)中之驅動元件。The use of the thin film transistor of the present invention described above is not particularly limited, and is suitable, for example, as a display device (for example, a liquid crystal display device, an organic EL (Electro Luminescence) display device, an inorganic EL display device, etc.) as an electro-optical device. element.
再者，本發明的電子元件係適合被用在採用樹脂基板之能藉低溫處理製造的撓性顯示器等之裝置、CCD(Charge Coupled Device)、CMOS(Complementary Metal Oxide Semiconductor)等之影像感測器、X射線感測器等之各種感測器、MEMS(Micro Electro Mechanical System)等之各種電子裝置中的驅動元件(驅動回路)。Further, the electronic component of the present invention is suitable for use in a device such as a flexible display manufactured by a low temperature process using a resin substrate, a CCD (Charge Coupled Device), or a CMOS (Complementary Metal Oxide Semiconductor) image sensor. A drive element (drive circuit) in various types of sensors such as X-ray sensors and various electronic devices such as MEMS (Micro Electro Mechanical System).
採用了本發明的薄膜電晶體之本發明的顯示裝置及感測器皆因低消耗電力而呈現良好特性。此外，此處所說的「特性」係指在顯示裝置的情況是顯示特性，而在感測器的情況是感度特性。The display device and the sensor of the present invention using the thin film transistor of the present invention exhibit good characteristics due to low power consumption. In addition, "characteristic" as used herein means a display characteristic in the case of a display device, and a sensitivity characteristic in the case of a sensor.
＜液晶顯示裝置＞<Liquid crystal display device>
圖16係表示本發明的電氣光學裝置之一實施形態的液晶顯示裝置之其一部分的概略剖面圖，圖17係表示其電氣配線的概略構成圖。Fig. 16 is a schematic cross-sectional view showing a part of a liquid crystal display device according to an embodiment of the electro-optical device of the present invention, and Fig. 17 is a schematic configuration view showing the electric wiring.
如圖16所示，本實施形態的液晶顯示裝置5係具備圖3A所示之頂閘極型的薄膜電晶體1、在被電晶體1的鈍化層54所保護的閘極電極16上被畫素下部電極55及其對向上部電極56包夾的液晶層57、以及用以對應各畫素而發出不同色的RGB濾色器58，且在TFT10的基板11側及濾色器58上分別具備偏光板59a、59b的構成。As shown in FIG. 16, the liquid crystal display device 5 of the present embodiment is provided with a top gate type thin film transistor 1 shown in FIG. 3A, and is drawn on the gate electrode 16 protected by the passivation layer 54 of the transistor 1. The lower electrode 55 and the liquid crystal layer 57 sandwiching the upper electrode 56 and the RGB color filter 58 for emitting different colors corresponding to the respective pixels are respectively disposed on the substrate 11 side of the TFT 10 and the color filter 58. The polarizing plates 59a and 59b are provided.
又，如圖17所示，本實施形態的液晶顯示裝置5係具備相互平行的複數條閘極配線51、及與該閘極配線51交叉之相互平行的資料配線52。此處的閘極配線51和資料配線52係電氣絕緣。在閘極配線51和資料配線52之交叉部附近備有薄膜電晶體1。Further, as shown in FIG. 17, the liquid crystal display device 5 of the present embodiment includes a plurality of gate wirings 51 that are parallel to each other, and a data wiring 52 that is parallel to the gate wiring 51. Here, the gate wiring 51 and the data wiring 52 are electrically insulated. A thin film transistor 1 is provided in the vicinity of the intersection of the gate wiring 51 and the data wiring 52.
薄膜電晶體1的閘極電極16係連接於閘極配線51，薄膜電晶體1的源極電極13係連接於資料配線52。又，薄膜電晶體1的汲極電極14係經由設置在閘極絕緣膜15的接觸孔19(導電體埋入於接觸孔19)而連接於畫素下部電極55。該畫素下部電極55係和被接地的對向電極56構成電容器53。The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 51, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 52. Further, the drain electrode 14 of the thin film transistor 1 is connected to the pixel lower electrode 55 via a contact hole 19 provided in the gate insulating film 15 (the conductor is buried in the contact hole 19). The pixel lower electrode 55 and the grounded counter electrode 56 constitute a capacitor 53.
圖16所示之本實施形態的液晶裝置中，雖設為具備頂閘極型的薄膜電晶體者，但在本發明的顯示裝置即液晶裝置中所用的薄膜電晶體不限定為頂閘極型，亦可為底閘極型的薄膜電晶體。In the liquid crystal device of the present embodiment shown in FIG. 16, the thin film transistor used in the liquid crystal device of the display device of the present invention is not limited to the top gate type. It can also be a bottom gate type thin film transistor.
本發明的薄膜電晶體由於具有高遷移率，故可在液晶顯示裝置中進行高精細、高速應答、高反差等之高品質顯示，亦適合於大畫面化。又，在活性層的IGZO是非晶質的情況可抑制元件特性的不均，實現大畫面且無光斑的優異顯示品質。而且特性偏移少，因而能減低閘極電壓，甚至能減低顯示裝置的消耗電力。又，依據本發明，能使用作為半導體層之可低溫(例如200℃以下)成膜的非晶質IGZO膜製造薄膜電晶體，因而可使用樹脂基板(塑膠基板)作為基板。因此，依據本發明，可提供顯示品質優異的撓性液晶顯示裝置。Since the thin film transistor of the present invention has high mobility, it can perform high-quality display such as high definition, high-speed response, high contrast, and the like in a liquid crystal display device, and is also suitable for a large screen. Further, when the IGZO of the active layer is amorphous, it is possible to suppress unevenness in device characteristics, and to realize an excellent display quality of a large screen and no flare. Moreover, the characteristic offset is small, so that the gate voltage can be reduced, and the power consumption of the display device can be reduced. Moreover, according to the present invention, a thin film transistor can be produced using an amorphous IGZO film which can form a film at a low temperature (for example, 200 ° C or lower) as a semiconductor layer, and thus a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, it is possible to provide a flexible liquid crystal display device having excellent display quality.
＜有機EL顯示裝置＞<Organic EL display device>
圖18係表示本發明的電氣光學裝置之一實施形態的主動矩陣方式之有機EL顯示裝置之其一部分的概略剖面圖，圖19係表示電氣配線的概略構成圖。18 is a schematic cross-sectional view showing a part of an active matrix type organic EL display device according to an embodiment of the electro-optical device of the present invention, and FIG. 19 is a schematic configuration view of the electric wiring.
有機EL顯示裝置的驅動方式有單純矩陣方式和主動矩陣方式2種。單純矩陣方式雖有能以低成本製造的優點，但由於是一次選擇1條掃描線使畫素發光，故掃描線數和每掃描線的發光時間成反比。因此變得難以高精細化、大畫面化。主動矩陣方式係依各畫素而形成電晶體、電容器，故製造成本變高，但没有如單純矩陣方式讓掃描線數增加的問題，故適合於高精細化、大畫面化。There are two types of driving methods for the organic EL display device: a simple matrix method and an active matrix method. Although the simple matrix method has the advantage of being able to manufacture at a low cost, since the pixel is selected by one scanning line at a time, the number of scanning lines is inversely proportional to the light emission time per scanning line. Therefore, it becomes difficult to achieve high definition and large screen. Since the active matrix method forms a transistor and a capacitor in accordance with each pixel, the manufacturing cost is high, but there is no problem that the number of scanning lines is increased as in the simple matrix method, so it is suitable for high definition and large screen.
本實施形態的主動矩陣方式之有機EL顯示裝置6為，圖3A所示的頂閘極型之薄膜電晶體1在具備鈍化層61a的基板60上是作為驅動用電晶體1a及開關用電晶體1b而配置，在該電晶體1a及1b上具備有被下部電極62及上部電極63所包夾之由有機發光層64所構成的有機發光元件65，該有機發光元件65上面亦被鈍化層61b所保護之構成。In the active matrix type organic EL display device 6 of the present embodiment, the top gate type thin film transistor 1 shown in FIG. 3A is used as the driving transistor 1a and the switching transistor on the substrate 60 including the passivation layer 61a. Arranged as 1b, the transistors 1a and 1b are provided with an organic light-emitting element 65 composed of an organic light-emitting layer 64 sandwiched by a lower electrode 62 and an upper electrode 63, and the organic light-emitting element 65 is also provided with a passivation layer 61b. The composition of the protection.
又，如圖19所示，本實施形態的有機EL顯示裝置7係具備相互平行的複數條閘極配線66、及和該閘極配線66交叉之相互平行的資料配線67及驅動配線68。此處的閘極配線66和資料配線67、驅動配線68係電氣絕緣。開關用薄膜電晶體1b的閘極電極16a係連接於閘極配線66，開關用薄膜電晶體1b的源極電極13b係連接於資料配線67。又，開關用薄膜電晶體1b的汲極電極14b係連接於驅動用薄膜電晶體1a的閘極電極16a，同時藉由使用電容器69而將驅動用薄膜電晶體1a保持在導通狀態。驅動用薄膜電晶體1a的源極電極13a係連接於驅動配線68，汲極電極14a係連接於有機EL發光元件65。Further, as shown in FIG. 19, the organic EL display device 7 of the present embodiment includes a plurality of gate wirings 66 that are parallel to each other, and a data wiring 67 and a driving wiring 68 that are parallel to each other and intersect with the gate wiring 66. Here, the gate wiring 66, the data wiring 67, and the driving wiring 68 are electrically insulated. The gate electrode 16a of the thin film transistor 1b for switching is connected to the gate wiring 66, and the source electrode 13b of the thin film transistor 1b for switching is connected to the data wiring 67. Further, the gate electrode 14b of the switching thin film transistor 1b is connected to the gate electrode 16a of the driving thin film transistor 1a, and the driving thin film transistor 1a is maintained in an on state by using the capacitor 69. The source electrode 13a of the driving thin film transistor 1a is connected to the driving wiring 68, and the drain electrode 14a is connected to the organic EL light emitting element 65.
圖18所示之本實施形態的有機EL裝置中，雖作成具備頂閘極型的薄膜電晶體1a及1b者，但在本發明的顯示裝置即有機EL裝置中所用的薄膜電晶體不限為頂閘極型，亦可為底閘極型的薄膜電晶體。In the organic EL device of the present embodiment shown in FIG. 18, the thin film transistors 1a and 1b having the top gate type are formed, but the thin film transistor used in the organic EL device of the display device of the present invention is not limited to The top gate type can also be a bottom gate type thin film transistor.
本發明的薄膜電晶體由於具有高遷移率，故能進行低消耗電力且高品質的顯示。又，依據本發明，由於使用可在低溫(例如200℃以下)下成膜的非晶質IGZO膜作為半導體層能製造薄膜電晶體，故可使用樹脂基板(塑膠基板)作為基板。因此，依據本發明，可提供顯示品質優異的撓性有機EL顯示裝置。Since the thin film transistor of the present invention has high mobility, it can perform display with low power consumption and high quality. Further, according to the present invention, since a thin film transistor can be produced by using an amorphous IGZO film which can be formed at a low temperature (for example, 200 ° C or lower) as a semiconductor layer, a resin substrate (plastic substrate) can be used as the substrate. Therefore, according to the present invention, it is possible to provide a flexible organic EL display device excellent in display quality.
此外，在圖18所示的有機EL顯示裝置中，可將上部電極63設為透明電極作成頂部發光型，亦可藉由將下部電極62及TFT的各電極設為透明電極作成底部發光型。Further, in the organic EL display device shown in FIG. 18, the upper electrode 63 may be a transparent electrode to be a top emission type, and each of the lower electrode 62 and the TFT may be a transparent electrode to form a bottom emission type.
＜X射線感測器＞<X-ray sensor>
圖20係表示屬本發明的感測器的一實施形態之X射線感測器的一部分之概略剖面圖，圖21係表示其電氣配線的概略構成圖。Fig. 20 is a schematic cross-sectional view showing a part of an X-ray sensor according to an embodiment of the sensor of the present invention, and Fig. 21 is a schematic configuration view showing the electric wiring.
圖20係更具體地放大X射線感測器陣列的一部分之概略剖面圖。本實施形態的X射線感測器7係具備形成在基板上的薄膜電晶體1及電容器70、形成在電容器70上的電荷收集用電極71、X射線變換層72、及上部電極73所構成。在薄膜電晶體1上設有鈍化膜75。Figure 20 is a schematic cross-sectional view showing a portion of the X-ray sensor array more specifically enlarged. The X-ray sensor 7 of the present embodiment includes a thin film transistor 1 and a capacitor 70 formed on a substrate, a charge collection electrode 71 formed on the capacitor 70, an X-ray conversion layer 72, and an upper electrode 73. A passivation film 75 is provided on the thin film transistor 1.
電容器70係成為以電容器用下部電極76和電容器用上部電極77包夾絕緣膜78而成的構造。電容器用上部電極77係經由設置在絕緣膜78的接觸孔79而與薄膜電晶體1的源極電極13和汲極電極14當中任一方(圖20中為汲極電極14)連接。The capacitor 70 has a structure in which the insulating film 78 is sandwiched between the capacitor lower electrode 76 and the capacitor upper electrode 77. The capacitor upper electrode 77 is connected to one of the source electrode 13 and the drain electrode 14 of the thin film transistor 1 (the gate electrode 14 in FIG. 20) via a contact hole 79 provided in the insulating film 78.
電荷收集用電極71係設於電容器70中的電容器用上部電極77上，接觸電容器用上部電極77。X射線變換層72係由非晶質硒所構成的層，且以覆蓋薄膜電晶體1及電容器70的方式設置。上部電極73係設於X射線變換層72上，接觸X射線變換層72。The charge collection electrode 71 is provided on the capacitor upper electrode 77 in the capacitor 70, and is in contact with the capacitor upper electrode 77. The X-ray conversion layer 72 is a layer made of amorphous selenium and is provided to cover the thin film transistor 1 and the capacitor 70. The upper electrode 73 is provided on the X-ray conversion layer 72 and contacts the X-ray conversion layer 72.
如圖21所示，本實施形態的X射線感測器7係具備相互平行的複數條閘極配線81、及和閘極配線81交叉之相互平行的複數條資料配線82。此處的閘極配線81和資料配線82係電氣絕緣。在閘極配線81和資料配線82的交叉部附近備有薄膜電晶體1。As shown in FIG. 21, the X-ray sensor 7 of the present embodiment includes a plurality of gate wirings 81 that are parallel to each other, and a plurality of data wirings 82 that are parallel to each other and that intersect with the gate wiring 81. Here, the gate wiring 81 and the data wiring 82 are electrically insulated. A thin film transistor 1 is provided in the vicinity of the intersection of the gate wiring 81 and the data wiring 82.
薄膜電晶體1的閘極電極16係連接於閘極配線81，薄膜電晶體1的源極電極13係連接於資料配線82。又，薄膜電晶體1的汲極電極14係連接於電荷收集用電極71，而且該電荷收集用電極71係和被接地的對向電極76構成電容器70。The gate electrode 16 of the thin film transistor 1 is connected to the gate wiring 81, and the source electrode 13 of the thin film transistor 1 is connected to the data wiring 82. Further, the drain electrode 14 of the thin film transistor 1 is connected to the charge collection electrode 71, and the charge collection electrode 71 and the grounded counter electrode 76 constitute the capacitor 70.
在本構成的X射線感測器7中，X射線在圖21中從上部(上部電極73側)照射，在X射線變換層72生成電子-電洞對。事先經由上部電極73對此X射線變換層72施加高電場，使所生成的電荷蓄積在電容器70，藉由依序掃描薄膜電晶體1而讀出。In the X-ray sensor 7 of the present configuration, the X-rays are irradiated from the upper portion (the upper electrode 73 side) in FIG. 21, and an electron-hole pair is generated in the X-ray conversion layer 72. A high electric field is applied to the X-ray conversion layer 72 via the upper electrode 73 in advance, and the generated electric charge is accumulated in the capacitor 70, and is read by sequentially scanning the thin film transistor 1.
本發明的X射線感測器由於具備導通電流高、可靠性優異之薄膜電晶體1，故S/N高、感度特性優異，在使用於X射線數位攝影裝置的情況可獲得寬動態範圍的畫像。特別是，本發明的X射線數位攝影裝置並非僅能進行靜止畫像攝影者，適合於使用在能以1台進行動畫的透視和靜止畫像的攝影之X射線數位攝影裝置。再者，在薄膜電晶體中的活性層之IGZO是非晶質的情況，可獲得均一性優異的畫像。Since the X-ray sensor of the present invention has the thin film transistor 1 having high on-current and excellent reliability, it has high S/N and excellent sensitivity characteristics, and can be used in an X-ray digital imaging apparatus to obtain a wide dynamic range image. . In particular, the X-ray digital photographing apparatus of the present invention is not limited to a still portrait photographer, and is suitable for use in an X-ray digital photographing apparatus that can perform photography of a perspective and a still image that can be animated at one station. Further, in the case where the IGZO of the active layer in the thin film transistor is amorphous, an image excellent in uniformity can be obtained.
此外，在圖20所示之本實施形態的X射線感測器中雖設為具備頂閘極型的薄膜電晶體者，本發明的感測器中所用的薄膜電晶體不受限為頂閘極型，亦可為底閘極型的薄膜電晶體。Further, in the X-ray sensor of the present embodiment shown in FIG. 20, a thin film transistor having a top gate type is used, and the thin film transistor used in the sensor of the present invention is not limited to the top gate. The pole type can also be a bottom gate type thin film transistor.
[實施例1][Example 1]
針對底閘極型薄膜電晶體，製造了實施例1、2、3、比較例1、2並比較了遷移率。表4係呈現各電晶體的Ga/(In+Ga)及成膜時的氧分壓/氬分壓及遷移率之表。For the bottom gate type thin film transistor, Examples 1, 2, and 3, and Comparative Examples 1 and 2 were produced and the mobility was compared. Table 4 shows the Ga/(In+Ga) of each transistor and the oxygen partial pressure/argon partial pressure and mobility at the time of film formation.
＜實施例1＞<Example 1>
實施例1是製造底閘極、頂接觸型的薄膜電晶體。作成基板，係使用表面上形成有SiO2氧化膜100nm之高濃度摻雜的p型矽基板(三菱材料公司製品)。氧化物半導體層係設為IGZO所構成者，首先，係以濺鍍方式成膜5nm的Ga/(In+Ga)=0.25，Zn/(In+Ga)=0.5即InGaZnO膜作為第1領域A1，之後，以濺鍍方式成膜30nm的Ga/(In+Ga)=0.75，Zn/(In+Ga)=0.5的IGZO膜作為第2領域A2。氧化物半導體層係在各領域間以不曝露於大氣中的情況連續地進行成膜。各領域的濺鍍係以採用In2O3標靶、Ga2O3標靶、ZnO標靶的共濺鍍(co-sputter)來進行。各領域的膜厚調整係藉成膜時間的調整而進行。各領域的詳細濺鍍條件如下。Embodiment 1 is to manufacture a bottom gate, top contact type thin film transistor. As a substrate, a p-type ruthenium substrate (product of Mitsubishi Materials Co., Ltd.) doped with a high concentration of 100 nm of an SiO 2 oxide film formed on the surface thereof was used. The oxide semiconductor layer is made of IGZO. First, an InGaZnO film having 5 nm of Ga/(In+Ga)=0.25 and Zn/(In+Ga)=0.5 is formed as a first field A by sputtering. 1 . Thereafter, an IGZO film of 30 nm of Ga/(In+Ga)=0.75 and Zn/(In+Ga)=0.5 was formed by sputtering as the second field A 2 . The oxide semiconductor layer is continuously formed into a film between the fields without being exposed to the atmosphere. Sputtering in various fields was carried out by co-sputter using an In 2 O 3 target, a Ga 2 O 3 target, and a ZnO target. The film thickness adjustment in each field is carried out by adjusting the film formation time. Detailed sputtering conditions in various fields are as follows.
(第1領域A1的濺鍍條件)(Sputter condition of the first field A 1 )
到達真空度；6×10-6PaReaching vacuum; 6×10 -6 Pa
成膜壓力；4.4×10-1PaFilm formation pressure; 4.4×10 -1 Pa
成膜溫度；室溫Film formation temperature; room temperature
氧分壓/氬分壓；0.02Oxygen partial pressure / argon partial pressure; 0.02
In2O3、Ga2O3、ZnO標靶的投入電力比；43.0：38.0：19.0Input power ratio of In 2 O 3 , Ga 2 O 3 , ZnO target; 43.0:38.0:19.0
(第2領域A2的濺鍍條件)(Sputter condition of the second field A 2 )
到達真空度；6×10-6PaReaching vacuum; 6×10 -6 Pa
成膜壓力；4.4×10-1PaFilm formation pressure; 4.4×10 -1 Pa
成膜溫度；室溫Film formation temperature; room temperature
氧分壓/氬分壓；0.005Oxygen partial pressure / argon partial pressure; 0.005
In2O3、Ga2O3、ZnO標靶的投入電力比；14.7：67.8：17.5Input power ratio of In 2 O 3 , Ga 2 O 3 , ZnO target; 14.7: 67.8:17.5
在利用濺鍍方式積層氧化物半導體層之後，利用隔著有金屬罩的真空蒸鍍法，將Ti(10nm)/Au(40nm)所構成的歐姆接面形成於積層膜上。After the oxide semiconductor layer was laminated by sputtering, an ohmic junction formed of Ti (10 nm)/Au (40 nm) was formed on the laminated film by a vacuum deposition method with a metal cover.
按以上那様而獲得通道長180μm、通道寬1mm的底閘極型薄膜電晶體1之實施例1。According to the above, the first embodiment of the bottom gate type thin film transistor 1 having a channel length of 180 μm and a channel width of 1 mm was obtained.
＜實施例2＞<Example 2>
元件構成係和實施例1同樣，僅氧化物半導體層的組成不同。首先，係以濺鍍方式成膜5nm的Ga/(In+Ga)=0.375，Zn/(In+Ga)=0.5即IGZO膜作為第1領域A1，之後，以濺鍍方式成膜30nm的Ga/(In+Ga)=0.625，Zn/(In+Ga)=0.5的IGZO膜作為第2領域A2。氧化物半導體層係在各領域間以不曝露於大氣中的情況連續地進行成膜。各領域的濺鍍係以採用In2O3標靶、Ga2O3標靶、ZnO標靶的共濺鍍(co-sputter)來進行。各領域的膜厚調整係藉成膜時間的調整而進行。各領域的詳細濺鍍條件如下。The element configuration is the same as that of the first embodiment, and only the composition of the oxide semiconductor layer is different. First, a 5 nm Ga/(In+Ga)=0.375, Zn/(In+Ga)=0.5 IGZO film was used as the first field A 1 by sputtering, and then a 30 nm film was formed by sputtering. An IGZO film having Ga/(In+Ga)=0.625 and Zn/(In+Ga)=0.5 is the second field A 2 . The oxide semiconductor layer is continuously formed into a film between the fields without being exposed to the atmosphere. Sputtering in various fields was carried out by co-sputter using an In 2 O 3 target, a Ga 2 O 3 target, and a ZnO target. The film thickness adjustment in each field is carried out by adjusting the film formation time. Detailed sputtering conditions in various fields are as follows.
(第1領域A1的濺鍍條件)(Sputter condition of the first field A 1 )
到達真空度；6×10-6PaReaching vacuum; 6×10 -6 Pa
成膜壓力；4.4×10-1PaFilm formation pressure; 4.4×10 -1 Pa
成膜溫度；室溫Film formation temperature; room temperature
氧分壓/氬分壓；0.02Oxygen partial pressure / argon partial pressure; 0.02
In2O3、Ga2O3、ZnO標靶的投入電力比；39.5：50.0：18.0Input power ratio of In 2 O 3 , Ga 2 O 3 , ZnO target; 39.5: 50.0: 18.0
(第2領域A2的濺鍍條件)(Sputter condition of the second field A 2 )
到達真空度；6×10-6PaReaching vacuum; 6×10 -6 Pa
成膜壓力；4.4×10-1PaFilm formation pressure; 4.4×10 -1 Pa
成膜溫度；室溫Film formation temperature; room temperature
氧分壓/氬分壓；0.005Oxygen partial pressure / argon partial pressure; 0.005
In2O3、Ga2O3、ZnO標靶的投入電力比；20.5：61.0：17.0Input power ratio of In 2 O 3 , Ga 2 O 3 , ZnO target; 20.5:61.0:17.0
＜實施例3＞<Example 3>
元件構成係和實施例1同樣，而氧化物半導體層的組成及氧濃度不同。首先，係以濺鍍方式成膜5nm的Ga/(In+Ga)=0.0，Zn/(In+Ga)=0.5即IGZO膜作為第1領域A1，之後，以濺鍍方式成膜30nm的Ga/(In+Ga)=1.0，Zn/(In+Ga)=0.5的IGZO膜作為第2領域A2。氧化物半導體層係在各領域間以不曝露於大氣中的情況連續地進行成膜。各領域的濺鍍係以採用In2O3標靶、Ga2O3標靶、ZnO標靶的共濺鍍(co-sputter)來進行。各領域的膜厚調整係藉成膜時間的調整而進行。各領域的詳細濺鍍條件如下。The element configuration was the same as in Example 1, and the composition and oxygen concentration of the oxide semiconductor layer were different. First, a 5 nm Ga/(In+Ga)=0.0, Zn/(In+Ga)=0.5 IGZO film was formed as the first field A 1 by sputtering, and then a 30 nm film was formed by sputtering. An IGZO film having Ga/(In+Ga)=1.0 and Zn/(In+Ga)=0.5 is referred to as the second field A 2 . The oxide semiconductor layer is continuously formed into a film between the fields without being exposed to the atmosphere. Sputtering in various fields was carried out by co-sputter using an In 2 O 3 target, a Ga 2 O 3 target, and a ZnO target. The film thickness adjustment in each field is carried out by adjusting the film formation time. Detailed sputtering conditions in various fields are as follows.
(第1領域A1的濺鍍條件)(Sputter condition of the first field A 1 )
到達真空度；6×10-6PaReaching vacuum; 6×10 -6 Pa
成膜壓力；4.4×10-1PaFilm formation pressure; 4.4×10 -1 Pa
成膜溫度；室溫Film formation temperature; room temperature
氧分壓/氬分壓；0.067Oxygen partial pressure / argon partial pressure; 0.067
In2O3、Ga2O3、ZnO標靶的投入電力比；55.0：0.0：13.0Input power ratio of In 2 O 3 , Ga 2 O 3 , ZnO target; 55.0:0.0:13.0
(第2領域A1的濺鍍條件)(Sputter condition of the second field A 1 )
到達真空度；6×10-6PaReaching vacuum; 6×10 -6 Pa
成膜壓力；4.4×10-1PaFilm formation pressure; 4.4×10 -1 Pa
成膜溫度；室溫Film formation temperature; room temperature
氧分壓/氬分壓；0.005Oxygen partial pressure / argon partial pressure; 0.005
In2O3、Ga2O3、ZnO標靶的投入電力比；0.0：60.0：15.0Input power ratio of In 2 O 3 , Ga 2 O 3 , ZnO target; 0.0:60.0:15.0
＜比較例1＞<Comparative Example 1>
除了實施例1的氧化物半導體之成膜是不進行層厚方向的組成及氧調變，且在投入電力比設為31.5：61.0：20.0，氧分壓/氬分壓設為0.002的條件下，僅將IGZO膜成膜45nm以外，其餘係以和實施例1同樣的方法製造薄膜電晶體者，將其作為比較例1。此乃在活性層具有以往的In：Ga：Zn=1：1：1組成(Ga/(In+Ga)=0.5)的IGZO單膜之電晶體，且層厚方向未形成有方井位能(Square-well potential)構造之情況者。In the film formation of the oxide semiconductor of the first embodiment, the composition in the layer thickness direction and the oxygen modulation were not performed, and the input power ratio was set to 31.5:61.0:20.0, and the oxygen partial pressure/argon partial pressure was set to 0.002. A film transistor was produced in the same manner as in Example 1 except that the IGZO film was formed into a film of 45 nm, and this was designated as Comparative Example 1. This is an IGZO single film transistor having a conventional In:Ga:Zn=1:1:1 composition (Ga/(In+Ga)=0.5) in the active layer, and no square well potential is formed in the layer thickness direction. (Square-well potential) construction situation.
＜比較例2＞<Comparative Example 2>
除了實施例1的氧化物半導體層之成膜是成膜第1領域且不成膜第2領域以外，其餘是以和實施例1同樣的方法來製造薄膜電晶體，將其作為比較例2。比較例2係除了在層厚方向未形成有方井位能構造以外，成為載子供給層的第2領域未包含在構造中之情況者。A thin film transistor was produced in the same manner as in Example 1 except that the film formation of the oxide semiconductor layer of Example 1 was the first field of film formation and the second field of film formation, and Comparative Example 2 was used. In Comparative Example 2, the second field which is the carrier supply layer is not included in the structure except that the square well energy structure is not formed in the layer thickness direction.
針對上述實施例1、2、3及比較例1、2，使用半導體參數分析儀4156C(Agilent Technologies；安倫科技公司製品)，進行了電晶體特性(Vg-Id特性)及遷移率μ的測定。測定結果顯示於圖22。Vg-Id特性的測定為，將汲極電壓(Vd)固定成10V，使閘極電壓(Vg)在-15V～+15V的範圍內變化，測定各閘極電壓(Vg)中的汲極電流(Id)。With respect to the above-described Examples 1, 2, and 3 and Comparative Examples 1 and 2, the transistor characteristics (Vg-Id characteristics) and the mobility μ were measured using a semiconductor parameter analyzer 4156C (Agilent Technologies; manufactured by Allen Technology). . The measurement results are shown in Fig. 22. The Vg-Id characteristic is measured by fixing the gate voltage (Vd) to 10 V, changing the gate voltage (Vg) in the range of -15 V to +15 V, and measuring the drain current in each gate voltage (Vg). (Id).
如同表4所示，具有方井位能構造的實施例1、2、3中可獲得20cm2/Vs以上的遷移率，特別是實施例3中獲得了遷移率是57.4cm2/Vs的高值。另一方面，有關在層厚方向上組成‧氧濃度無調變的比較例1，獲得了是以往的IGZO單膜電晶體之平均值即11cm2/Vs左右的遷移率。又，有關未成膜第2領域的比較例2，雖為電晶體驅動者，但相較於積層TFT元件，遷移率是大幅減低成0.029cm2/Vs。此乃意味著由於第2領域是載子供給層，所以在没有載子供給層的比較例2中無法獲得足夠的載子濃度。As shown in Table 4, the mobility of 20 cm 2 /Vs or more was obtained in Examples 1, 2, and 3 having a square well energy structure, and in particular, the mobility obtained in Example 3 was 57.4 cm 2 /Vs. value. On the other hand, in Comparative Example 1 in which the composition of the ‧ oxygen concentration was not modulated in the layer thickness direction, a mobility of about 11 cm 2 /Vs which is an average value of the conventional IGZO single-crystal transistor was obtained. Further, in Comparative Example 2 in the second field of the unfilmed film, although the transistor driver was used, the mobility was drastically reduced to 0.029 cm 2 /Vs as compared with the laminated TFT device. This means that since the second field is the carrier supply layer, sufficient carrier concentration cannot be obtained in Comparative Example 2 in which the carrier supply layer is not provided.
圖23顯示實施例1、2、3、比較例1中之遷移率μ對位能深度Δχ依存性。此處Δχ為，除了b/(a+b)之調變以外，還算出基於氧濃度調變的電子親和力差是大約0.1eV。可知當使位能深度Δχ繼續增大時遷移率會有繼續增大的舉動。從該圖可知，藉由設成大概Δχ=0.17eV以上，可獲得IGZO單膜的遷移率大約兩倍即20cm2/Vs以上的遷移率，可提供低消耗電力且高品質的顯示裝置或高感度的X射線感測器等。因此本發明的電晶體中以第1、第2領域的電子親和力差是0.17eV以上者較佳。Fig. 23 shows the dependence of the mobility μ on the potential energy depth Δχ in Examples 1, 2, 3 and Comparative Example 1. Here, Δχ is calculated to be about 0.1 eV in addition to the modulation of b/(a+b), and the electron affinity difference based on the oxygen concentration modulation. It can be seen that the mobility will continue to increase as the bit depth Δχ continues to increase. As can be seen from the figure, by setting approximately Δχ = 0.17 eV or more, a mobility of about twice the mobility of the IGZO single film, that is, 20 cm 2 /Vs or more can be obtained, and a high-quality display device or a high-quality display device can be provided. Sensitive X-ray sensor, etc. Therefore, in the transistor of the present invention, the difference in electron affinity between the first and second domains is preferably 0.17 eV or more.
1、2、3、4．．．薄膜電晶體1, 2, 3, 4. . . Thin film transistor
11．．．基板11. . . Substrate
12．．．氧化物半導體層12. . . Oxide semiconductor layer
13．．．源極電極13. . . Source electrode
14．．．汲極電極14. . . Bipolar electrode
15．．．閘極絕緣膜15. . . Gate insulating film
16．．．閘極電極16. . . Gate electrode
A1．．．氧化物半導體層之第1領域A 1 . . . The first field of the oxide semiconductor layer
A2．．．氧化物半導體層之第2領域A 2 . . . The second field of the oxide semiconductor layer
圖1係用以說明半導體電子構造之參數的圖。Figure 1 is a diagram for explaining parameters of a semiconductor electronic structure.
圖2(A)係表示基於電子親和力差的位能構造之圖及(B)係表示帶隙能構造之圖。Fig. 2(A) is a view showing a potential energy structure based on a difference in electron affinity, and (B) is a view showing a band gap energy structure.
圖3係表示(A)頂閘極-頂接觸型，(B)頂閘極-底接觸型，(C)底閘極-頂接觸型，(D)底閘極-底接觸型的薄膜電晶體之構成的示意剖面圖。Figure 3 shows (A) top gate-top contact type, (B) top gate-bottom contact type, (C) bottom gate-top contact type, (D) bottom gate-bottom contact type thin film A schematic cross-sectional view of the structure of the crystal.
圖4係表示IGZO積層膜在(A)積層之後不久、(B)250℃退火處理後、及(C)500℃退火處理後之剖面STEM像。4 is a cross-sectional STEM image of the IGZO laminate film after (A) lamination, (B) annealing at 250 ° C, and (C) annealing at 500 ° C.
圖5係表示有關樣本1～5的Tauc plot之圖。Fig. 5 is a view showing the Tauc plot of the samples 1 to 5.
圖6係表示從圖5導出的帶隙能之組成比依存的圖。Fig. 6 is a view showing the composition ratio dependence of the band gap energy derived from Fig. 5.
圖7係表示有關樣本1～5的激發光能和規格化光電子產率之圖。Fig. 7 is a graph showing the excitation light energy and the normalized photoelectron yield of the samples 1 to 5.
圖8係表示從圖7所求得之離子化位能對組成依存性的圖。Fig. 8 is a graph showing the dependence of the ionization potential energy on the composition obtained from Fig. 7.
圖9係表示電子親和力對組成依存性之圖。Figure 9 is a graph showing the dependence of electron affinity on composition.
圖10(A)係表示有關樣本6，7、(B)係表示有關樣本8，9的Tauc plot之圖。Fig. 10(A) shows the related samples 6, 7, and (B) showing the Tauc plot of the samples 8, 9.
圖11係表示從圖10導出之帶隙能對氧分壓/氬分壓依存性之圖。Fig. 11 is a graph showing the dependence of the band gap energy on the oxygen partial pressure/argon partial pressure derived from Fig. 10.
圖12(A)係表示有關樣本6，7、(B)係表示有關樣本8，9的激發光能和規格化電子產率之圖。Fig. 12(A) shows that the relevant samples 6, 7, and (B) show the excitation light energy and the normalized electron yield of the samples 8, 9.
圖13係表示從圖12導出之離子化位能對氧分壓/氬分壓依存性之圖。Fig. 13 is a graph showing the dependence of ionization potential energy on oxygen partial pressure/argon partial pressure derived from Fig. 12.
圖14係表示電子親和力對氧分壓/氬分壓依存性之圖。Fig. 14 is a graph showing the dependence of electron affinity on oxygen partial pressure/argon partial pressure.
圖15(A)係表示比電阻、(B)係表示載子密度、及(C)係表示遷移率對Ga/(In+Ga)依存性之圖。Fig. 15(A) shows the specific resistance, (B) shows the carrier density, and (C) shows the mobility versus Ga/(In+Ga) dependency.
圖16係表示實施形態的液晶顯示裝置之一部分的概略剖面圖。Fig. 16 is a schematic cross-sectional view showing a part of a liquid crystal display device of the embodiment.
圖17係圖16的液晶顯示裝置之電氣配線的概略構成圖。Fig. 17 is a schematic configuration diagram of electric wiring of the liquid crystal display device of Fig. 16;
圖18係表示實施形態的有機EL顯示裝置之一部分的概略剖面圖。Fig. 18 is a schematic cross-sectional view showing a part of an organic EL display device of the embodiment.
圖19係圖18的有機EL顯示裝置之電氣配線的概略構成圖。19 is a schematic configuration diagram of electrical wiring of the organic EL display device of FIG. 18.
圖20係表示實施形態的X射線感測器陣列之一部分的概略剖面圖。Fig. 20 is a schematic cross-sectional view showing a part of an X-ray sensor array of the embodiment.
圖21係圖20的X射線感測器陣列之電氣配線的概略構成圖。21 is a schematic configuration diagram of electrical wiring of the X-ray sensor array of FIG. 20.
圖22係表示實施例及比較例的Vg-Id特性之圖。Fig. 22 is a view showing the Vg-Id characteristics of the examples and the comparative examples.
圖23係表示實施例1、2、3、比較例1中之遷移率μ對位能深度Δχ依存性之圖。Fig. 23 is a graph showing the dependence of the mobility μ on the bit depth Δχ in Examples 1, 2, 3 and Comparative Example 1.
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| JP5626978B2 (en) | 2014-11-19 |
| JP2012059860A (en) | 2012-03-22 |
| TW201222823A (en) | 2012-06-01 |
| KR20120026005A (en) | 2012-03-16 |
| CN102403361A (en) | 2012-04-04 |
| KR101905898B1 (en) | 2018-10-08 |
| CN102403361B (en) | 2015-09-23 |
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