CN103887345A - Oxide thin-film transistor and manufacturing method thereof - Google Patents
Oxide thin-film transistor and manufacturing method thereof Download PDFInfo
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- CN103887345A CN103887345A CN201410122981.7A CN201410122981A CN103887345A CN 103887345 A CN103887345 A CN 103887345A CN 201410122981 A CN201410122981 A CN 201410122981A CN 103887345 A CN103887345 A CN 103887345A
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- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 87
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000010408 film Substances 0.000 claims description 62
- 230000004888 barrier function Effects 0.000 claims description 20
- 239000012212 insulator Substances 0.000 claims description 20
- 238000005240 physical vapour deposition Methods 0.000 claims description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 13
- 239000001301 oxygen Substances 0.000 claims description 13
- 229910052760 oxygen Inorganic materials 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 239000012528 membrane Substances 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 claims description 2
- 230000001105 regulatory effect Effects 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 35
- 238000000151 deposition Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
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- 239000000463 material Substances 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 5
- 239000002356 single layer Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
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- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention discloses an oxide thin-film transistor and a manufacturing method thereof. The oxide thin-film transistor comprises a substrate, wherein a grid electrode, a gate insulation layer and a semiconductor active layer are sequentially arranged on the substrate, a source electrode and a drain electrode are arranged on the positions, located on the two sides of the grid electrode, of the semiconductor active layer respectively, a conducting channel is arranged between the source electrode and the drain electrode, the semiconductor active layer comprises a first oxide thin film with a resistance value of R1, a second oxide thin film with a resistance value of R2 and a third oxide thin film with a resistance value of R3, the gate insulation layer is covered by the first oxide thin film, the second oxide thin film and third oxide thin film in sequence, the resistance value at the positions of the source electrode and drain electrode of the third oxide thin film is R4 which is obtained after the resistance value at the positions of the source electrode and drain electrode of the third oxide thin film is reduced by means of a special technique, and both R1 and R3 are larger than R2; the parts, except the source electrode and drain electrode, of the semiconductor active layer are covered by a protective insulation layer, and the source electrode and drain electrode of the semiconductor active layer are covered by a metal layer. According to the oxide thin-film transistor and the manufacturing method thereof, fixed resistance of a traditional semiconductor oxide thin film is changed into gradually changed resistance, and then leak currents are reduced and device stability is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, specifically a kind of oxide thin film transistor and manufacture method thereof.
Background technology
In the time of nearly more than ten years, with silica-base film field-effect transistor (Thin Film Transistor, TFT) develop rapidly for the liquid crystal display device of driver element has obtained with series of advantages such as its volume are little, lightweight, quality is high, and become the Message Display Terminal of main flow.But because himself mobility is lower, and cannot realize the problems such as high-resolution demonstration, its in large scale flat panel display field gradually oxide TFT replace.
Oxide TFT has higher mobility, is applicable to being very much applied to following display.But compared with general silicon materials (below taking conductor oxidate IGZO as example), IGZO material itself has unsteadiness, this is owing to there being a large amount of oxygen rooms in traditional IGZO film, make TFT under grid voltage action condition, due to the variation of electric field, it is moving to there is migration in electric charge between film interface, produce new hot carrier electric charge and superfluous charge carrier, excess carrier can move between film interface, thereby cause the drift of the serious and threshold voltage of the boundary defect that contacts with IGZO in device, device electrical stability declines, therefore its popularization and application have directly been affected.This problem is to exist in semiconductor device always, particularly evident in oxide semiconductor TFT device.
This phenomenon is especially obvious in NBTS senile experiment process, along with the testing time increases, the leakage current of inspection IGZO-TFT device increases, IdVg current-voltage characteristic curve drifts about to the right, its reason is between IGZO oxide-semiconductor film and insulation film, to have produced new electric charge, and spreads between IGZO oxide-semiconductor film and insulation film interface.
The resistance of oxide semiconductor and oxygen defect density have direct relation, due to sull deposition process, the variation of partial pressure of oxygen can cause the ratio of sull oxygen defect, thus change film resistance, such as IGZO
xsquare resistance can change along with the variation of X, X=4 is compared with X=5, film resistor changes to 10E14 by 5E13, energy gap E
gbe 3.5 and 4.5, oxygen defect is less, the therefore deteriorated minimizing in interface.If but the energy gap of active layer is greater than 4.0, the threshold voltage of device is excessive.Industry, for a lot of research of doing of oxide transistor active layer, is improved thereby improve the stability that improves oxide device in sull interface.
The object of the invention is the stability in order to improve oxide semiconductor element.The resistance value of the active layer of existing oxide thin film transistor is evenly constant, the present invention proposes a kind of oxide semi conductor transistor with gradual change resistance channel layer, with respect to existing device architecture, adopt the deteriorated minimizing in interface between device architecture active layer of the present invention and insulating barrier, active layer interfacial characteristics reaches improvement, leakage current reduces, and the stability of device improves.Oxide semiconductor thin-film can be realized by PVD deposition process, can, in PVD deposition, realize gradual change resistance channel layer by changing oxygen content (partial pressure of oxygen), and the oxygen content of film coating environment is high, and resistance is large, otherwise resistance is relatively little.
Summary of the invention
The object of the invention is the defect existing for prior art, propose a kind of oxide thin film transistor with gradual change resistance channel layer, to reduce the deteriorated of active layer and interfacial dielectric layer, improve the stability of device.
The present invention adopts following technical scheme:
A kind of oxide thin film transistor, comprise underlay substrate, on underlay substrate, be provided with successively grid, gate insulator, semiconductor active layer, protection insulating barrier and metal level, wherein, the position that is positioned at grid both sides in semiconductor active layer is respectively equipped with source electrode and drain electrode, between source electrode and drain electrode, has conducting channel; Described semiconductor active layer cover gate insulating barrier; Protection insulating barrier covers on the semiconductor active layer except source electrode and drain locations; The upper covering metal layer of source electrode and drain electrode; Described semiconductor active layer comprises the first oxide semiconductor film that the resistance that covers successively on gate insulator is R1, the second oxide semiconductor film and the 3rd oxide semiconductor film that resistance is R2, the 3rd oxide semiconductor film is R4 in the resistance of source electrode and drain locations, other local resistances are R3, R4 is that the source electrode and the drain locations that act on the 3rd oxide semiconductor film by special process obtain, and the resistance of R4 is less than R3; The resistance of R2 is less than the resistance of R1, and the resistance of R2 is also less than the resistance of R3.
Described making step is as follows:
S1: form grid on underlay substrate;
S2: form gate insulator on grid;
S3: utilize different depositional environment conditions, cover semiconductor active layer at gate insulator, semiconductor active layer comprises the 3rd oxide semiconductor film that the first oxide semiconductor film that the resistance that covers successively on gate insulator is R1, the second oxide semiconductor film that resistance is R2 and resistance are R3, R2 resistance is less than the resistance of R1, and the resistance of R2 is also less than the resistance of R3;
S4: the position that is positioned at grid both sides in semiconductor active layer arranges respectively source electrode and drain electrode, between source electrode and drain electrode, it is conducting channel, covering protection insulating barrier on the 3rd oxide semiconductor film that is R3 to the resistance in step S3, and then remove the protection insulating barrier in source electrode and drain locations;
S5: the source electrode described in step S3 and drain locations metal-coated membrane are formed to metal level, and adopting process makes the resistance of active layer the 3rd oxide semiconductor film that source/drain position exposes become R4 by R3 before plated film, and the resistance of R4 is less than R3.
Described gate insulator and protection insulating barrier adopt metallo-organic compound chemical vapour deposition (CVD) (Metal-organic Chemical Vapor Deposition is called for short MOCVD) technique; Semiconductor active layer adopts physical vapour deposition (PVD) (Physical Vapor Deposition is called for short PVD) technique.
Described first, second, and third oxide semiconductor film is that the partial pressure of oxygen by regulating PVD technique realizes; The R2 Standard resistance range value of the second oxide semiconductor film is: 1E13--5E13 ohm, and its band gap is 3.0-3.8EV; First and the 3rd the R1 of oxide semiconductor film and the Standard resistance range of R3 be 1E14--5E14 ohm, band gap is 4.0-4.5EV.
Described source electrode and drain metallization film form before metal level, adopt the technique of plasma bombardment to make the resistance of active layer the 3rd oxide semiconductor film that source/drain position exposes become R4 by R3.
Beneficial effect of the present invention:
The present invention can reduce the interfacial characteristics of oxide thin film transistor, reduces leakage current, improves the stability of device.
Brief description of the drawings
Fig. 1 is the structural representation after completing of step S1 of the present invention and S2;
Fig. 2 and Fig. 3 are the structural representations after completing of step S3 of the present invention;
Fig. 4 and Fig. 5 are the structural representations after completing of step S4 of the present invention;
Fig. 6 and Fig. 7 are the structural representations after completing of step S5 of the present invention;
Fig. 8 is the existing conductor oxidate TFT partial schematic diagram distinguishing with Fig. 4 of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in detail.
As shown in Figure 7: a kind of oxide thin film transistor, comprise underlay substrate 1, on underlay substrate 1, be provided with successively grid 2, gate insulator 3, semiconductor active layer 10, protection insulating barrier 7 and metal level 11, wherein, the position that is positioned at grid 2 both sides in semiconductor active layer 10 is respectively equipped with source electrode 8 and drain electrode 9, between source electrode 8 and drain electrode 9, has conducting channel; Described semiconductor active layer 10 cover gate insulating barriers 3; Protection insulating barrier 7 covers on the semiconductor active layer 10 except source electrode 8 and drain electrode 8 positions; Covering metal layer 11 in source electrode 8 and drain electrode 9; Described semiconductor active layer 10 comprises the second oxide semiconductor film 5 and the 3rd oxide semiconductor film 6 that the first oxide semiconductor film 4, resistance that the resistance that covers successively on gate insulator is R1 are R2, the 3rd oxide semiconductor film 6 is R4 in the resistance of source electrode 8 and drain electrode 9 positions, other local resistances are R3, R4 is that the source electrode 8 and drain electrode 9 positions that act on the 3rd oxide semiconductor film 6 by special process obtain, and the resistance of R4 is less than R3; The resistance of R2 is less than the resistance of R1, and the resistance of R2 is also less than the resistance of R3.
The flow process of above-mentioned a kind of oxide thin film transistor device making method is as shown in Fig. 1-6, and preparation method is as follows:
S1: form on underlay substrate 1 and adopt grid 2; Grid 2 can be used the single layer structure of the alloys such as metal or AlNd, MoNb such as Cu, Al, Cr, also can use the metal laminated formation such as Al/Mo, Ti/Al/Ti.
S2: form gate insulator 3 on grid 2; Gate insulator 3 can be by SiO
2form Deng monolayer material, also can use SiN
x/ SiO
2lamination Deng megohmite insulant forms; Gate insulator 3 adopts CVD process deposits.
S3: cover active layer on gate insulator 3, utilize different depositional environment conditions, it is that R1 the first oxide semiconductor film 4, resistance are that the 3rd semiconductor active layer film 6 that R2 the second oxide semiconductor film 5 and resistance are R3 forms that active layer comprises resistance, and R2 resistance is less than R1 and R3; The deposition of active layer adopts PVD technique, realizes different resistances by the partial pressure of oxygen that regulates PVD technique; The R2 Standard resistance range value of the second oxide semiconductor film is: 1E13--5E13 ohm, and its band gap is 3.0-3.8EV; First and the 3rd the R1 of oxide semiconductor film and the Standard resistance range of R3 be 1E14--5E14 ohm, band gap is 4.0-4.5EV.
S4: source electrode 8 and drain electrode 9 are set respectively in the position that is positioned at grid both sides in semiconductor active layer; between source electrode 8 and drain electrode 9, it is conducting channel; covering protection insulating barrier 7 on the 3rd oxide semiconductor film 6 that is R3 to the resistance in step S3, and then remove source electrode 8 and drain electrode 9 locational protection insulating barrier 7 materials.
S5: the source electrode 8 described in step S4 and drain electrode 9 metal-coated membranes are formed to metal level 11, before plated film, adopt the technique of plasma bombardment to make the resistance of semiconductor active layer 10 the 3rd oxide semiconductor film 6 that source/drain position exposes become R4 by R3, the resistance of R4 is less than R3, and the resistance of other positions remains R3; The material of the metal film plating can be used the single layer structure of the alloys such as metal or AlNd, MoNb such as Cu, Al, Cr, also can use the metal laminated formation such as Al/Mo, Ti/Al/Ti.
Embodiment mono-:
As shown in Figure 1, on the underlay substrate 1 of first making at glass etc., form grid 2 by PVD method depositing Ti/Al/Ti, thickness is 350nm, and photoetching-development-etch gate patterns becomes grid 2; By CVD method deposition SiO
2 form gate insulator 3 and cover on grid 2, thickness is 300nm.
As shown in Figure 2, setting PVD deposition process environmental parameter is: Temp=300 DEG C, Ar
2=200sccm, O
2=40sccm, oxygen ratio is 16%, and deposition pressure is 0.35Pa, and obtaining resistance is the first oxide semiconductor film 4 of R1=10E14, and thickness is 10nm, covers on gate insulator 3.
As shown in Figure 3, setting PVD deposition process environmental parameter is: Temp=300 DEG C, Ar
2=210sccm, O
2=30sccm, oxygen ratio is 12.5%, deposition pressure is 0.35Pa, obtaining resistance is the second oxide semiconductor film 5 of R2=5E13, thickness is 30nm, cover on the first oxide semiconductor film 4, the 3rd oxide semiconductor film 6 and the first oxide semiconductor film 4 adopt same deposition process and sedimentary condition, and resistance is also 10E14.
As shown in Figure 4, adopt CVD method deposition SiO
2as protection insulating barrier 7, material is SiO
2, thickness is 100nm.
As shown in Figure 5, utilize photoetching-development-etching process, remove source electrode 8 and drain electrode 9 locational protection insulating barrier 7 materials.
As shown in Figures 6 and 7, under room temperature environment, first adopt Ar
2the drain surface 5 minutes of semiconductor active layer 10 the 3rd oxide semiconductor film 6 that 9 positions expose of plasma bombardment source electrode 8/, makes resistance R 3 become 10E3 from 10E14, and then source electrode 8 and drain electrode 9 metal-coated membranes is formed to metal levels 11.
Above embodiment only, for explanation technological thought of the present invention, can not limit protection scope of the present invention with this, every technological thought proposing according to the present invention, and any change of doing on technical scheme basis, within all falling into protection range of the present invention; The technology that the present invention does not relate to all can be realized by prior art.
Claims (5)
1. an oxide thin film transistor, comprise underlay substrate, on underlay substrate, be provided with successively grid, gate insulator, semiconductor active layer, protection insulating barrier and metal level, wherein, the position that is positioned at grid both sides in semiconductor active layer is respectively equipped with source electrode and drain electrode, between source electrode and drain electrode, there is conducting channel, it is characterized in that: described semiconductor active layer cover gate insulating barrier; Protection insulating barrier covers on the semiconductor active layer except source electrode and drain locations; The upper covering metal layer of source electrode and drain electrode; Described semiconductor active layer comprises the first oxide semiconductor film that the resistance that covers successively on gate insulator is R1, the second oxide semiconductor film and the 3rd oxide semiconductor film that resistance is R2, the 3rd oxide semiconductor film is R4 in the resistance of source electrode and drain locations, other local resistances are R3, R4 is that the source electrode and the drain locations that act on the 3rd oxide semiconductor film by special process obtain, and the resistance of R4 is less than R3; The resistance of R2 is less than the resistance of R1, and the resistance of R2 is also less than the resistance of R3.
2. a manufacture method for oxide thin film transistor as claimed in claim 1, is characterized in that described making step is as follows:
S1: form grid on underlay substrate;
S2: form gate insulator on grid;
S3: utilize different depositional environment conditions, cover semiconductor active layer at gate insulator, semiconductor active layer comprises the 3rd oxide semiconductor film that the first oxide semiconductor film that the resistance that covers successively on gate insulator is R1, the second oxide semiconductor film that resistance is R2 and resistance are R3, R2 resistance is less than the resistance of R1, and the resistance of R2 is also less than the resistance of R3;
S4: the position that is positioned at grid both sides in semiconductor active layer arranges respectively source electrode and drain electrode, between source electrode and drain electrode, it is conducting channel, covering protection insulating barrier on the 3rd oxide semiconductor film that is R3 to the resistance in step S3, and then remove the protection insulating barrier in source electrode and drain locations;
S5: the source electrode described in step S3 and drain locations metal-coated membrane are formed to metal level, and adopting process makes the resistance of the 3rd oxide semiconductor film that source/drain position exposes become R4 by R3 before plated film, and the resistance of R4 is less than R3.
3. a kind of oxide thin film transistor according to claim 1 and 2 and manufacture method thereof, it is characterized in that: described gate insulator and protection insulating barrier adopt metallo-organic compound chemical vapour deposition (CVD) (Metal-organic Chemical Vapor Deposition is called for short MOCVD) technique; Semiconductor active layer adopts physical vapour deposition (PVD) (Physical Vapor Deposition is called for short PVD) technique.
4. a kind of oxide thin film transistor according to claim 3 and manufacture method thereof, is characterized in that: described first, second, and third oxide semiconductor film is that the partial pressure of oxygen by regulating PVD technique realizes; The R2 Standard resistance range value of the second oxide semiconductor film is: 1E13--5E13 ohm, and its band gap is 3.0-3.8EV; First and the 3rd the R1 of oxide semiconductor film and the Standard resistance range of R3 be 1E14--5E14 nurse, band gap is 4.0-4.5EV.
5. a kind of oxide thin film transistor according to claim 3 and manufacture method thereof, it is characterized in that: described source electrode and drain metallization film form before metal level, adopt the technique of plasma bombardment to make the resistance of active layer the 3rd oxide semiconductor film that source/drain position exposes become R4 by R3.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105988253A (en) * | 2015-03-03 | 2016-10-05 | 群创光电股份有限公司 | Display panel and display device |
| CN108288603A (en) * | 2017-01-10 | 2018-07-17 | 昆山国显光电有限公司 | A kind of TFT substrate and its manufacturing method and display screen |
| CN108780818A (en) * | 2016-03-04 | 2018-11-09 | 株式会社半导体能源研究所 | Semiconductor device, the manufacturing method of the semiconductor device and the display device including the semiconductor device |
| CN114646675A (en) * | 2022-04-02 | 2022-06-21 | 西安电子科技大学杭州研究院 | Hydrogen sensor based on thin film transistor/preparation method and application thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105988253A (en) * | 2015-03-03 | 2016-10-05 | 群创光电股份有限公司 | Display panel and display device |
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| CN108780818A (en) * | 2016-03-04 | 2018-11-09 | 株式会社半导体能源研究所 | Semiconductor device, the manufacturing method of the semiconductor device and the display device including the semiconductor device |
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| CN108288603A (en) * | 2017-01-10 | 2018-07-17 | 昆山国显光电有限公司 | A kind of TFT substrate and its manufacturing method and display screen |
| CN114646675A (en) * | 2022-04-02 | 2022-06-21 | 西安电子科技大学杭州研究院 | Hydrogen sensor based on thin film transistor/preparation method and application thereof |
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