TWI557855B - 封裝載板及其製作方法 - Google Patents

封裝載板及其製作方法 Download PDF

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Publication number
TWI557855B
TWI557855B TW100149852A TW100149852A TWI557855B TW I557855 B TWI557855 B TW I557855B TW 100149852 A TW100149852 A TW 100149852A TW 100149852 A TW100149852 A TW 100149852A TW I557855 B TWI557855 B TW I557855B
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Taiwan
Prior art keywords
layer
wafer
insulating layer
patterned
conductive
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TW100149852A
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English (en)
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TW201327735A (zh
Inventor
孫世豪
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旭德科技股份有限公司
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Priority to TW100149852A priority Critical patent/TWI557855B/zh
Priority to CN201210089136.5A priority patent/CN103187314B/zh
Priority to US13/469,079 priority patent/US9330941B2/en
Priority to JP2012182830A priority patent/JP5671504B2/ja
Publication of TW201327735A publication Critical patent/TW201327735A/zh
Priority to US15/072,349 priority patent/US9510453B2/en
Application granted granted Critical
Publication of TWI557855B publication Critical patent/TWI557855B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
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Description

封裝載板及其製作方法
本發明是有關於一種封裝結構及其製作方法，且特別是有關於一種封裝載板及其製作方法。
晶片封裝的目的在於保護裸露的晶片、降低晶片接點的密度及提供晶片良好的散熱。常見的封裝方法是晶片透過打線接合(wire bonding)或覆晶接合(flip chip bonding)等方式而安裝至一封裝載板，以使晶片上的接點可電性連接至封裝載板。因此，晶片的接點分佈可藉由封裝載板重新配置，以符合下一層級的外部元件的接點分佈。
一般來說，封裝載板的製作通常是以核心(core)介電層作為蕊材，並利用全加成法(fully additive process)、半加成法(semi-additive process)、減成法(subtractive process)或其他方式，將圖案化線路層與圖案化介電層交錯堆疊於核心介電層上。如此一來，核心介電層在封裝載板的整體厚度上便會佔著相當大的比例。因此，若無法有效地縮減核心介電層的厚度，勢必會使封裝結構於厚度縮減上產生極大的障礙。
本發明提供一種封裝載板，適於承載至少一晶片。
本發明提供一種封裝載板的製作方法，用以製作上述之封裝載板。
本發明提出一種封裝載板的製作方法，其包括以下步驟。提供一支撐板。支撐板具有一上表面。形成一圖案化線路層於支撐板的上表面上，其中圖案化線路層暴露出部分上表面。壓合一絕緣層及一位於絕緣層之一第一表面上的導電層於圖案化線路層上，其中絕緣層覆蓋圖案化線路層與圖案化線路層所暴露出的部分上表面。形成多個導電連接結構於圖案化線路層上。圖案化上上述之導電層以定義出多個分別連接導電連接結構且暴露出絕緣層之部分第一表面的接墊。移除支撐板，以暴露出絕緣層相對於第一表面的一第二表面，其中絕緣層的第二表面與圖案化線路層的一接合表面齊平。
本發明還提出一種封裝載板，適於承載至少一晶片。封裝載板包括一絕緣層、一圖案化線路層、多個導電連接結構以及多個接墊。絕緣層具有彼此相對之一第一表面與一第二表面。圖案化線路層內埋於絕緣層的第二表面，且具有一接合表面。絕緣層的第二表面與圖案化線路層的接合表面齊平，且晶片配置於圖案化線路層上。導電連接結構內埋於絕緣層中，且連接圖案化線路層。接墊配置於絕緣層的第一表面上，且分別連接導電連接結構。
基於上述，由於本發明是先以支撐板做為一支撐結構，且將圖案化線路層、絕緣層、導電連接結構及接墊形成於支撐板上後，移除支撐板而完成封裝載板的製作。因此，相較於習知具有核心介電層的封裝結構而言，本發明之封裝載板可具有較薄的封裝厚度。再者，由於本發明之封裝載板的圖案化線路層是內埋於絕緣層，因此當晶片配置於圖案化線路層上而構成一封裝結構時，此封裝結構可具有較薄的封裝厚度。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1A至圖1E為本發明之一實施例之一種封裝載板的製作方法的剖面示意圖。請先參考圖1A，依照本實施例的封裝載板的製作方法，首先，提供一支撐板10，其中支撐板10具有一上表面12。接著，形成一圖案化線路層110於支撐板10的上表面12上，其中圖案化線路層110暴露出支撐板10的部分上表面12，且圖案化線路層110的線寬例如是介於15微米至35微米之間，而圖案化線路層110的線距至少大於15微米。意即，於此之圖案化線路層110可視為一種細線路。
需說明的是，在本實施例中，形成圖案化線路層110的方法是電鍍法(plating)，必須先形成一電鍍種子層(未繪示)於支撐板10上，之後再以此電鍍種子層為電極，電鍍形成此圖案化線路層110，因此支撐板10的材質可採用絕緣材料或金屬材料。
接著，請參考圖1B(a)，壓合一絕緣層120及一位於絕緣層120之一第一表面122上的導電層130a於圖案化線路層110上，其中絕緣層120覆蓋圖案化線路層110與圖案化線路層110所暴露出的支撐板10的部分上表面12。
接著，請參考圖1C(a)，對導電層130a照射一雷射光束(未繪示)，以形成多個從導電層130a延伸至圖案化線路層110的盲孔H。接著，並填入一導電材料142於盲孔H內，而形成導電連接結構140a，其中導電連接結構140a連接導電層130a與圖案化線路層110，且每一導電連接結構140a的一下表面144與導電層130a的一底表面132實質上齊平。
值得一提的是，本發明並不限定壓合絕緣層120及其上之導電層130a於圖案化線路層110上以及形成導電連接結構140a的順序，以及導電連接結構140a的結構形態。雖然此處所提及的步驟是先壓合絕緣層120及其上之導電層130a於圖案化線路層110上之後，再形成導電連接結構140a，且此導電連接結構140a具體化為一導電盲孔連接結構。然而，於其他實施例中，請參考圖1B(b)，亦可先形成導電連接結構140b於圖案化線路層110上之後，之後，請參考圖1C(b)，再壓合絕緣層120及其上之導電層130b於圖案化線路層110上。此時，導電連接結構140b會穿出絕緣層120且與導電層130b接觸，其中導電連接結構140b的一表面146與絕緣層120的第一表面122實質上切齊，且此導電連接結構140b具體化為一導電柱。此外，絕緣層120包覆導電連接結構140b，且導電連接結構140b位於導電層130b與圖案化線路層110之間。上述之步驟仍屬於本發明可採用的技術方案，不脫離本發明所欲保護的範圍。
之後，接續圖1C(a)之步驟後，請參考圖1D，圖案化上述之導電層130a，以定義出多個分別連接導電連接結構140a且暴露出絕緣層120之部分第一表面122的接墊150a。
最後，請同時參考圖1D與圖1E，移除支撐板10，以暴露出絕緣層120相對於第一表面122的一第二表面124，其中絕緣層120的第二表面124與圖案化線路層110的一接合表面112實質上齊平。至此，已完成封裝載板100a的製作。
在結構上，請再參考圖1E，本實施例之封裝載板100a包括圖案化線路層110、絕緣層120、導電連接結構140a以及接墊150a。絕緣層120具有彼此相對之第一表面122與第二表面124。圖案化線路層110內埋於絕緣層120的第二表面124且具有一接合表面112。絕緣層120的第二表面124與圖案化線路層110的接合表面112實質上齊平。導電連接結構140a內埋於絕緣層120中且連接圖案化線路層110。接墊150a配置於絕緣層120的第一表面122上且分別連接導電連接結構140a。
由於本實施例是先以支撐板10做為一支撐結構，且將圖案化線路層110、絕緣層120、導電連接結構140a及接墊150a形成於支撐板10上後，移除支撐板10而完成封裝載板100a的製作。因此，相較於習知具有核心介電層的封裝結構而言，本實施例之封裝載板100a無須支撐結構(即支撐板10或習知之核心介電層)的厚度，可具有較薄的封裝厚度。再者，由於本實施例之封裝載板100a的圖案化線路層110是內埋於絕緣層120，因此當將一晶片(未繪示)配置於封裝載板100a的圖案化線路層110上而構成一封裝結構時，此封裝結構可具有較薄的封裝厚度，以符合現今薄型化的趨勢。
值得一提的是，本發明並不限定絕緣層120、導電層130a(或130b)及導電連接結構140a(或140b)的層數，雖然與此所形成之絕緣層120、導電層130a(或130b)及導電連接結構140a(或140b)的層數實質上各為一層。但於其他未繪示的實施例中，本領域的技術人員當可參照前述實施例之圖1B(a)、1C(a)、1B(b)、1C(b)說明，依據實際需求，重複前述1B(a)、1C(a)、1B(b)、1C(b)的步驟，而形成具有多層導電層之封裝載板的結構，以達到所需的技術效果。
在此必須說明的是，下述實施例沿用前述實施例的元件標號與部分內容，其中採用相同的標號來表示相同或近似的元件，並且省略了相同技術內容的說明。關於省略部分的說明可參考前述實施例，下述實施例不再重複贅述。
圖1F為本發明之一實施例之一種封裝載板的剖面示意圖。請參考圖1F，本實施例之封裝載板100b與圖1E之封裝載板100a相似，惟二者主要差異之處在於：本實施例之封裝載板100b更包括一防銲層160，其中防銲層160配置於絕緣層120的第二表面124上，其中防銲層160暴露出圖案化線路層110的部分接合表面112。
在製程上，本實施例的封裝載板100b可以採用與前述實施例之封裝載板100a大致相同的製作方式，並且在圖1E的步驟後，即移除支撐板10之後，形成一防銲層160於絕緣層120的第二表面124上，其中防銲層160暴露出圖案化線路層110的部分接合表面112，用以可作為後續晶片(未繪示)與銲線(未繪示)的接合位置。此即可大致完成封裝載板100b的製作。
圖1G為本發明之另一實施例之一種封裝載板的剖面示意圖。請參考圖1G，本實施例之封裝載板100c與圖1F之封裝載板100b相似，惟二者主要差異之處在於：本實施例之封裝載板100c更包括一表面處理層170，其中表面處理層170配置於圖案化線路層110的接合表面112上，且表面處理層170的材質包括金、銀、鎳/金、鎳/鈀/金、鎳/銀或其他適當的金屬材質。
在製程上，本實施例的封裝載板100c可以採用與前述實施例之封裝載板100b大致相同的製作方式，並且在圖1F的步驟後，即形成防銲層160之後，形成一表面處理層170於未被防銲層160所覆蓋之圖案化線路層110的接合表面112上，用以避免圖案化線路層110產生氧化而影響後續晶片(未繪示)與銲線(未繪示)接合的可靠度。此即可大致完成封裝載板100c的製作。
圖1H為本發明之又一實施例之一種封裝載板的剖面示意圖。請參考圖1H，本實施例之封裝載板100d與圖1E之封裝載板100a相似，惟二者主要差異之處在於：本實施例之封裝載板100d更包括一表面處理層170，其中表面處理層170配置於圖案化線路層110的接合表面112上，且表面處理層170的材質包括金、銀、鎳/金、鎳/鈀/金、鎳/銀或其他適當的金屬材質。
在製程上，本實施例的封裝載板100d可以採用與前述實施例之封裝載板100a大致相同的製作方式，並且在圖1E的步驟後，即移除支撐板10之後，形成一表面處理層170於圖案化線路層110的接合表面112上，用以避免圖案化線路層110產生氧化而影響後續晶片(未繪示)與銲線(未繪示)接合的可靠度。此即可大致完成封裝載板100d的製作。
圖2A為為本發明之一實施例之一種封裝載板承載多個晶片的剖面示意圖。請參考圖2A，本實施例之封裝載板100c適於承載至少一晶片(圖2A中繪示兩個晶片200a、200b)，其中晶片200a、200b配置於圖案化線路層110上方之表面處理層170上，且晶片200a、200b例如是一積體電路晶片，其例如為一繪圖晶片、一記憶體晶片等單一晶片或是一晶片模組，或者是一光電晶片，其例如是一發光二極體(LED)晶片或一雷射二極體晶片，於此並不加以限制晶片200a、200b的種類與型態。
詳細來說，本實施例之圖案化線路層110包括至少一晶片接墊(圖2A中示意地繪示二個晶片接墊114a、114b)與多個接合接墊116(圖2A中示意地繪示二個)，其中晶片200a、200b分別配置於晶片接墊114a、114b上，且晶片200a、200b分別透過至少一銲線220而連接至接合接墊116上。於此，晶片200a、200b有部分區域是埋入於防銲層160與表面處理層170所構成的一空間中。再者，本實施例可藉由一封裝膠體210來包覆晶片200a、200b、銲線220以及部分封裝載板100c，用以保護晶片200a、200b、銲線220與封裝載板100c之間的電性連接關係。此外，本實施例亦可透過多個銲球230銲接至接墊150a上，來使封裝載板100c透過銲球230與外部電路(未繪示)電性連接。
值得一提的是，於其他實施例中，請參考圖2B，晶片200a、200b亦可配置於具有導電柱形態之導電連接結構140b的封裝載板100e上，其中接墊150b是對導電層130b(請參考圖1C(b))進行一圖案化的步驟所構成；或者是，請參考圖2C，晶片200a、200b亦可配置封裝載板100d上，其中圖案化線路層110具有三個接合接墊116；亦或是，請參考圖2D，晶片200a、200b亦可配置於封裝載板100f，且透過銲線220與接合接墊116電性連接，其中此封裝載板100f與圖1E之封裝載板100a相似，差異之處在於：封裝載板100f具有導電柱形態之導電連接結構140b以及配置於圖案化線路層110的接合表面112上的表面處理層170，其中接墊150b是對導電層130b(請參考圖1C(b))進行一圖案化的步驟所構成。
此外，於其他未繪示的實施例中，於亦可選用於如前述實施例所提及之封裝載板100a、100b本領域的技術人員當可參照前述實施例的說明，依據實際需求，將晶片200a、200b配置於所選用之前述構件上，以達到所需的技術效果。
綜上所述，由於本發明是先以支撐板做為一支撐結構，且將圖案化線路層、絕緣層、導電連接結構及接墊形成於支撐板上後，移除支撐板而完成封裝載板的製作。因此，相較於習知具有核心介電層的封裝結構而言，本發明之封裝載板可具有較薄的封裝厚度。再者，由於本發明之封裝載板的圖案化線路層是內埋於絕緣層，因此當晶片配置於圖案化線路層上而構成一封裝結構時，此封裝結構可具有較薄的封裝厚度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10．．．支撐板
12．．．上表面
100a、100b、100c、100d、100e、100f．．．封裝載板
110．．．圖案化線路層
112．．．接合表面
114a、114b．．．晶片接墊
116．．．接合接墊
120．．．絕緣層
122．．．第一表面
124．．．第二表面
130a、130b．．．導電層
132．．．底表面
140a、140b．．．導電連接結構
142．．．導電材料
144．．．下表面
146．．．表面
150a、150b．．．接墊
160．．．防銲層
170．．．表面處理層
200a、200b．．．晶片
210．．．封裝膠體
220．．．銲線
230．．．銲球
H．．．盲孔
圖1A至圖1E為本發明之一實施例之一種封裝載板的製作方法的剖面示意圖。
圖1F為本發明之一實施例之一種封裝載板的剖面示意圖。
圖1G為本發明之另一實施例之一種封裝載板的剖面示意圖。
圖1H為本發明之又一實施例之一種封裝載板的剖面示意圖。
圖2A為本發明之一實施例之一種封裝載板承載多個晶片的剖面示意圖。
圖2B為本發明另之一實施例之一種封裝載板承載多個晶片的剖面示意圖。
圖2C為本發明又之一實施例之一種封裝載板承載多個晶片的剖面示意圖。
圖2D為本發明再之一實施例之一種封裝載板承載多個晶片的剖面示意圖。
100a．．．封裝載板
110．．．圖案化線路層
112．．．接合表面
120．．．絕緣層
122．．．第一表面
124．．．第二表面
140a．．．導電連接結構
150a．．．接墊

Claims (7)

  1. 一種封裝載板的製作方法，包括：提供一支撐板，該支撐板具有一上表面；形成一圖案化線路層於該支撐板的該上表面上，其中該圖案化線路層暴露出部分該上表面，其中該圖案化線路層包括至少一晶片接墊；壓合一絕緣層及一位於該絕緣層之一第一表面上的導電層於該圖案化線路層上，其中該絕緣層覆蓋該圖案化線路層與該圖案化線路層所暴露出的部分該上表面；形成多個導電連接結構於該圖案化線路層上；圖案化該導電層，以定義出多個分別連接該些導電連接結構且暴露出該絕緣層之部分該第一表面的接墊；以及移除該支撐板，以暴露出該絕緣層相對於該第一表面的一第二表面，其中該絕緣層的該第二表面與該圖案化線路層的一接合表面齊平；於移除該支撐板之後，形成一表面處理層於該圖案化線路層的該接合表面上，且該表面處理層位在一晶片以及該晶片接墊之間；以及於移除該支撐板之後，形成一防銲層於該絕緣層的該第二表面上，其中該防銲層暴露出該圖案化線路層的部分該接合表面，且該晶片的一部分區域埋入於該防銲層與該表面處理層所構成的一空間中。
  2. 如申請專利範圍第1項所述之封裝載板的製作方法，其中形成該些導電連接結構於該圖案化線路層上的步 驟是在壓合該絕緣層及其上之該導電層於該圖案化線路層上之後，而形成該些導電連接結構於該圖案化線路層上的步驟包括：對該導電層照射一雷射光束，以形成多個從該導電層延伸至該圖案化線路層的盲孔；以及填入一導電材料於該些盲孔內，而形成該些導電連接結構，其中該些導電連接結構連接該導電層與該圖案化線路層，且各該導電連接結構的一下表面與該導電層的一底表面齊平。
  3. 如申請專利範圍第1項所述之封裝載板的製作方法，其中形成該些導電連接結構於該圖案化線路層上的步驟是在壓合該絕緣層及其上之該導電層於該圖案化線路層上之前，而壓合該絕緣層及其上之該導電層於該圖案化線路層上之後，該絕緣層包覆該些導電連接結構，且該些導電連接結構位於該導電層與該圖案化線路層之間。
  4. 一種封裝載板，適於承載至少一晶片，該封裝載板包括：一絕緣層，具有彼此相對之一第一表面與一第二表面；一圖案化線路層，內埋於該絕緣層的該第二表面，且具有一接合表面，其中該絕緣層的該第二表面與該圖案化線路層的該接合表面齊平，且該晶片配置於該圖案化線路層的該接合表面上，其中該圖案化線路層包括至少一晶片接墊，該晶片配置於該晶片接墊上；多個導電連接結構，內埋於該絕緣層中，且連接該圖 案化線路層；多個接墊，配置於該絕緣層的該第一表面上，且分別連接該些導電連接結構；一表面處理層，配置於該晶片以及該晶片接墊之間；以及一防銲層，配置於該絕緣層的該第二表面上，其中該防銲層暴露出該圖案化線路層的部分該接合表面，而該晶片的一部分區域埋入於該防銲層與該表面處理層所構成的一空間中，且該晶片的一下表面低於該防銲層的一上表面。
  5. 如申請專利範圍第4項所述之封裝載板，其中該圖案化線路層包括多個接合接墊，且該晶片透過至少一銲線連接至該些接合接墊之一上。
  6. 如申請專利範圍第4項所述之封裝載板，其中該圖案化線路層的線寬介於15微米至35微米之間，而該圖案化線路層的線距至少大於15微米。
  7. 一種封裝結構，包括：一晶片；一絕緣層，具有彼此相對之一第一表面與一第二表面；一圖案化線路層，內埋於該絕緣層的該第二表面，且具有一接合表面，其中該絕緣層的該第二表面與該圖案化線路層的該接合表面齊平，且該晶片配置於該圖案化線路層的該接合表面上，其中該圖案化線路層包括至少一晶片接墊，該晶片配置於該晶片接墊上； 多個導電連接結構，內埋於該絕緣層中，且連接該圖案化線路層；多個接墊，配置於該絕緣層的該第一表面上，且分別連接該些導電連接結構；一表面處理層，配置於該晶片以及該晶片接墊之間；以及一防銲層，配置於該絕緣層的該第二表面上，其中該防銲層暴露出該圖案化線路層的部分該接合表面，而該晶片的一部分區域埋入於該防銲層與該表面處理層所構成的一空間中，且該晶片的一下表面低於該防銲層的一上表面。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140097003A1 (en) * 2012-10-05 2014-04-10 Tyco Electronics Amp Gmbh Electrical components and methods and systems of manufacturing electrical components
TWM517410U (zh) * 2014-02-13 2016-02-11 群成科技股份有限公司 電子封裝件與封裝載板
TWI623251B (zh) * 2014-08-29 2018-05-01 恆勁科技股份有限公司 中介基板之製法
CN105491796B (zh) * 2014-10-08 2019-02-22 深圳市昶东鑫线路板有限公司 电路板的制作方法
CN105592639B (zh) * 2014-10-23 2019-01-25 碁鼎科技秦皇岛有限公司 电路板及其制作方法
KR101706470B1 (ko) * 2015-09-08 2017-02-14 앰코 테크놀로지 코리아 주식회사 표면 마감층을 갖는 반도체 디바이스 및 그 제조 방법
KR102506697B1 (ko) * 2016-05-18 2023-03-08 에스케이하이닉스 주식회사 관통 몰드 볼 커넥터를 포함하는 반도체 패키지
CN106941769B (zh) * 2016-11-16 2019-12-27 林进东 一种综合性能良好的散热结构件及其制备工艺
CN112151433B (zh) * 2019-06-27 2024-02-09 何崇文 基板结构、封装结构及其制作方法
CN113286440B (zh) * 2020-02-19 2022-09-02 何崇文 导线架及其制作方法
CN113113394A (zh) * 2021-03-22 2021-07-13 江西展耀微电子有限公司 透明灯膜及其制备方法、显示屏
CN113224224A (zh) * 2021-04-19 2021-08-06 江西展耀微电子有限公司 透明灯膜及其制备方法、显示屏
CN113464871B (zh) * 2021-06-30 2023-08-15 江西新菲新材料有限公司 灯膜及其制备方法、电子设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201108905A (en) * 2009-06-03 2011-03-01 Shinko Electric Ind Co Wiring substrate and method of manufacturing the same
TWI341002B (en) * 2007-02-09 2011-04-21 Unimicron Technology Corp Coreless flip-chip packing substrate and method for making coreless packing substrate
TW201142958A (en) * 2010-05-20 2011-12-01 Adl Engineering Inc Package method for quad flat no-lead package

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5072520A (en) * 1990-10-23 1991-12-17 Rogers Corporation Method of manufacturing an interconnect device having coplanar contact bumps
JP3241605B2 (ja) 1996-09-06 2001-12-25 松下電器産業株式会社 配線基板の製造方法並びに配線基板
JP2001352171A (ja) * 2000-06-09 2001-12-21 Matsushita Electric Ind Co Ltd 接着シート、接着シートを用いた回路基板及びその製造方法
US6753612B2 (en) * 2001-04-05 2004-06-22 International Business Machines Corporation Economical high density chip carrier
JP3946578B2 (ja) 2001-06-05 2007-07-18 大日本印刷株式会社 受動素子を備えた配線板の製造方法、受動素子を備えた配線板
JP2004221131A (ja) * 2003-01-09 2004-08-05 Yamaichi Electronics Co Ltd 両面プリント配線板の製造方法
JP2005044899A (ja) 2003-07-24 2005-02-17 Daiwa Kogyo:Kk 層間接続構造の形成方法及び多層配線基板
JP4890959B2 (ja) * 2005-06-17 2012-03-07 日本電気株式会社 配線基板及びその製造方法並びに半導体パッケージ
JP4839138B2 (ja) * 2006-06-20 2011-12-21 新光電気工業株式会社 配線基板の製造方法
JP5258045B2 (ja) 2006-06-30 2013-08-07 日本電気株式会社 配線基板、配線基板を用いた半導体装置、及びそれらの製造方法
JP4758869B2 (ja) * 2006-11-08 2011-08-31 新光電気工業株式会社 半導体装置の製造方法
TWI334202B (en) * 2006-12-14 2010-12-01 Ase Electronics Inc Carrier and manufacturing process thereof
CN101286454B (zh) * 2007-04-10 2011-03-30 上海美维科技有限公司 印制电路板的制作方法
JP5101169B2 (ja) * 2007-05-30 2012-12-19 新光電気工業株式会社 配線基板とその製造方法
KR100969326B1 (ko) * 2007-09-18 2010-07-09 삼성전기주식회사 다층 인쇄회로기판 및 그 제조방법
JP5025399B2 (ja) * 2007-09-27 2012-09-12 新光電気工業株式会社 配線基板及びその製造方法
JP4784586B2 (ja) * 2007-10-25 2011-10-05 パナソニック株式会社 部品内蔵プリント配線基板および部品内蔵プリント配線基板の製造方法
JP2009267274A (ja) 2008-04-30 2009-11-12 Ngk Spark Plug Co Ltd 発光素子実装用配線基板
TWI371830B (en) * 2008-05-29 2012-09-01 Advanced Semiconductor Eng Circuit board process
US8188380B2 (en) * 2008-12-29 2012-05-29 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
CN101989592B (zh) * 2009-07-30 2012-07-18 欣兴电子股份有限公司 封装基板与其制法
JP5361680B2 (ja) 2009-11-26 2013-12-04 京セラ株式会社 配線基板
US8530755B2 (en) * 2010-03-31 2013-09-10 Ibiden Co., Ltd. Wiring board and method for manufacturing the same
CN102870210A (zh) 2010-05-07 2013-01-09 旭硝子株式会社 元件搭载用基板及其制造方法
CN102299082B (zh) * 2010-08-31 2014-04-16 先进封装技术私人有限公司 半导体承载元件的制造方法及应用其的封装件的制造方法
TWI495051B (zh) * 2011-07-08 2015-08-01 Unimicron Technology Corp 無核心層之封裝基板及其製法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI341002B (en) * 2007-02-09 2011-04-21 Unimicron Technology Corp Coreless flip-chip packing substrate and method for making coreless packing substrate
TW201108905A (en) * 2009-06-03 2011-03-01 Shinko Electric Ind Co Wiring substrate and method of manufacturing the same
TW201142958A (en) * 2010-05-20 2011-12-01 Adl Engineering Inc Package method for quad flat no-lead package

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