TWI554883B - 用於在記憶體系統中分割資料結構之系統及方法 - Google Patents

用於在記憶體系統中分割資料結構之系統及方法 Download PDF

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TWI554883B
TWI554883B TW104117868A TW104117868A TWI554883B TW I554883 B TWI554883 B TW I554883B TW 104117868 A TW104117868 A TW 104117868A TW 104117868 A TW104117868 A TW 104117868A TW I554883 B TWI554883 B TW I554883B
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memory
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TW201614501A (en
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Ｊ 湯瑪斯 帕洛斯基
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美光科技公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0727—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a storage system, e.g. in a DASD or network based storage system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0617—Improving the reliability of storage systems in relation to availability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0661—Format or protocol conversion arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
    • G06F3/0688—Non-volatile semiconductor memory arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
    • H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
    • H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
    • H04L1/1867—Arrangements specially adapted for the transmitter end
    • H04L1/189—Transmission or retransmission of more than one copy of a message
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/12—Avoiding congestion; Recovering from congestion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/10—Flow control; Congestion control
    • H04L47/25—Flow control; Congestion control with rate being modified by the source upon detecting a change of network conditions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/52—Queue scheduling by attributing bandwidth to queues
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Security & Cryptography (AREA)
  • Communication Control (AREA)
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  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Description

用於在記憶體系統中分割資料結構之系統及方法 相關申請案之交叉參考
本申請案係主張2014年6月2日申請之標題為「Systems and Methods for a Scalable Memory System Protocol」之美國臨時專利申請案第62/006,668號之優先權的非臨時申請案，該美國臨時專利申請案以引用的方式併入本文中。
本揭示內容大致係關於一種用於改良可使用記憶體裝置執行資料操作(例如，讀取、寫入)之速率之記憶體系統。更具體地，本揭示內容係關於用於改良記憶體系統回應於存取記憶體系統之請求之速率之系統及技術。
本章節旨在向讀者介紹可能與本揭示內容之各種態樣相關之本技術之各種態樣，該等態樣在下文中描述及/或主張。據信此討論有助於為讀者提供背景資訊以促進更好地理解本揭示內容之各種態樣。因此，應瞭解，此等陳述在此意義上閱讀且並非作為先前技術之認可。
通常，低能力(例如，低請求速率)記憶體類型(諸如一動態隨機存取記憶體(DRAM)組件)與高能力(例如，高請求速率)記憶體(諸如一靜態隨機存取記憶體(SRAM)組件)相比可能相對廉價。因而，可基於 記憶體類型的各自能力在特定記憶體類型上執行特定資料操作(例如，讀取、寫入)。例如，對於涉及多個動作的大型複雜資料操作，使用SRAM組件來確保與在使用DRAM組件執行相同資料操作時相比，資料操作被更快速地執行可能係有利的。雖然SRAM組件可用於高效地執行所請求資料操作，但是SRAM組件通常歸因於成本考慮而在記憶體裝置上受限。因而，使用較小能力記憶體組件或其他記憶體類型來按類似於或高於高能力記憶體組件之速率執行操作可能係有利的。
10‧‧‧計算系統
12‧‧‧晶片上主機系統(SoC)
14‧‧‧記憶體裝置
16‧‧‧通道
22‧‧‧記憶體SoC
23‧‧‧緩衝器
24‧‧‧NAND記憶體
26‧‧‧減小延時動態隨機存取記憶體(RLDRAM)
27‧‧‧記憶體組件30之一部分
28‧‧‧雙倍資料速率***同步動態隨機存取記憶體(DDR4)
29‧‧‧通道
30‧‧‧三維堆疊記憶體組件
31‧‧‧鏈路
32‧‧‧記憶體層
33‧‧‧邏輯層
34‧‧‧室
35‧‧‧庫
36‧‧‧控制邏輯部分
40‧‧‧方法
42‧‧‧方塊
44‧‧‧方塊
46‧‧‧方塊
60‧‧‧資料結構
62‧‧‧記憶體位址
70‧‧‧分割資料結構
72‧‧‧虛擬庫
74‧‧‧虛擬庫
76‧‧‧虛擬庫
78‧‧‧虛擬庫
90‧‧‧方法
92‧‧‧方塊
94‧‧‧方塊
96‧‧‧方塊
98‧‧‧方塊
110‧‧‧對數圖
在閱讀下列詳細描述及在參考圖式時可更好地暸解本揭示內容之各種態樣，其中：圖1繪示根據一實施例之一計算系統之一實例之一方塊圖；圖2繪示根據一實施例之可作為圖1之計算系統之部分之一記憶體裝置之一實例之一方塊圖；圖3繪示根據一實施例之可包含若干記憶體層之一例示性三維堆疊記憶體組件之一俯視圖；圖4繪示根據一實施例之圖3之記憶體組件之實體層之一示意圖；圖5繪示根據一實施例之組成圖3之記憶體組件之一部分的實體層之例示性虛擬庫之一示意圖；圖6繪示根據一實施例之映射至虛擬庫之四個資料結構之一方塊圖；圖7繪示根據一實施例之用於判定將在圖3之記憶體裝置之一記憶體組件中形成之虛擬庫之數目之方法之一流程圖；圖8繪示根據一實施例之一記憶體組件之一例示性資料結構之一方塊圖； 圖9繪示根據一實施例之圖4之資料結構之一分割版本之一方塊圖；圖10繪示根據一實施例之用於基於一較佳佇列深度判定將在圖2之記憶體裝置之一記憶體組件中形成之虛擬庫之數目之一方法之一流程圖；及圖11繪示根據一實施例之相對於各種佇列深度的虛擬庫之數目的一對數圖。
下文將描述一或多個特定實施例。為了提供此等實施例之一簡潔描述，本說明書中未描述一實際實施方案之所有特徵。應暸解，如在任何工程或設計項目中，在任何此實際實施方案的研發中，需作出許多實施方案特定決策以達成可隨實施方案變化而變化之研發者的特定目標，諸如符合系統相關及業務相關的限制。此外，應暸解，此一研發工作可能係複雜且耗時的，但對於獲利於本揭示內容之一般技術者而言，該研發工作仍將係一例常設計、製作及製造任務。
大致上，不同的記憶體類型具有不同能力。即，不同的記憶體類型可比其他記憶體類型更高效地執行特定類型的功能。例如，DRAM記憶體類型可能無法像一SRAM記憶體一樣快地執行功能。在某些實施例中，一記憶體系統可將一DRAM之部分映射為虛擬庫，且使用虛擬庫同時執行多個操作。因而，可能已由SRAM個別地執行之操作現可使用DRAM執行。藉由在DRAM之虛擬庫中同時執行此多個操作，使用虛擬庫之一記憶體系統可提供在使用一較低請求速率記憶體(DRAM)的同時，使用一高請求速率記憶體(如SRAM)之一錯覺。因此，較高能力記憶體(如SRAM)可被保留用於執行其他程序。有關在各種記憶體類型中映射虛擬庫以執行更高效操作之額外細節將在下文更詳細描述。
使用可擴充協定的計算及記憶體系統
經由介紹，圖1繪示可包含記憶體裝置之一計算系統10之一方塊圖，該等記憶體裝置可根據本文中描述的技術在記憶體組件中映射虛擬庫。計算系統10可為多種計算裝置之任何者，諸如一電腦、傳呼機、蜂巢式電話、個人記事簿、控制電路等。計算系統10可包含一晶片上主機系統(SoC)12，該晶片上主機系統(SoC)12可耦合至若干記憶體裝置14。主機SoC 12可為一積體電路(IC)，其將一電腦或其他電子系統之所有組件整合至一單個晶片中。因而，主機SoC 12可包含一或多個處理器，諸如一微處理器，該一或多個處理器可控制計算系統10中之系統功能及請求的處理。如本文中使用，處理器可包含能夠在一相應電裝置上執行可執行指令的任何適當處理器。
如上所述，主機SoC 12可耦合至記憶體裝置14。在某些實施例中，主機SoC 12可經由通道16耦合至記憶體裝置14。通道16可包含匯流排、電佈線或類似者。
圖2描繪記憶體裝置14之一實施例之一方塊圖。記憶體裝置14可包含經設計以留存數位資料之任何電儲存裝置。記憶體裝置14可涵蓋各種各樣的記憶體組件，包含揮發性記憶體及非揮發性記憶體。揮發性記憶體可包含動態隨機存取記憶體(DRAM)及/或靜態隨機存取記憶體(SRAM)。此外，揮發性記憶體可包含若干記憶體模組，諸如單列直插記憶體模組(SIMM)或雙列直插記憶體模組(DIMM)。
非揮發性記憶體可包含將結合揮發性記憶體使用之一唯讀記憶體(ROM)，諸如一EPROM及/或快閃記憶體(例如，NAND)。此外，非揮發性記憶體可包含一高容量記憶體，諸如一磁帶或磁碟機記憶體。如將暸解，揮發性記憶體或非揮發性記憶體可被視為用於儲存程式碼(例如，指令)之一非暫態有形機器可讀媒體。
如圖2中所示，在某些實施例中，記憶體裝置14可包含一晶片上 系統(SoC)22，該晶片上系統(SoC)22可為一記憶體中處理器(PIM)或一電腦處理器(CPU)，其緊實地耦合至儲存在記憶體裝置14上的記憶體組件。通常，記憶體SoC 22可與記憶體裝置14之記憶體組件在相同矽晶片上。藉由將處理組件及記憶體組件合併至記憶體裝置14中，記憶體SoC 22可管理在記憶體組件與主機SoC 12之間傳送及接收資料請求及回應的方式。在某些實施例中，記憶體SoC 22可控制記憶體組件之間的訊務以減小延時及增大頻寬。如將暸解，在根據本文中描述之實施例控制記憶體組件與其他裝置之間的傳送時，主機SoC 12及記憶體SoC 22可採用一可擴充記憶體系統協定。因而，可擴充記憶體系統協定可在記憶體裝置14與主機SoC 12之間的通道16，以及在記憶體組件與記憶體SoC 22之間的通道29上操作。
在某些實施例中，記憶體裝置14亦包含一緩衝器23。緩衝器23可儲存由記憶體SoC 22所接收的一或多個封包。舉例而言，記憶體裝置14可包含諸如NAND記憶體24、減小延時動態隨機存取記憶體(RLDRAM)26、雙倍資料速率***同步動態隨機存取記憶體(DDR4)28及類似者之記憶體類型。
在某些實施例中，主機SoC 12及記憶體SoC 22可基於經由記憶體組件、暫存器及類似者提供之電腦可執行指令執行各種操作。記憶體組件或儲存器可為可充當用於儲存記憶體可執行碼、資料或類似者的媒體的任何適當製品。此等製品可代表電腦可讀媒體(即，任何適當形式的記憶體或儲存器)，該電腦可讀媒體可儲存由主機SoC 12或記憶體SoC 22使用來執行當前揭示技術的處理器可執行碼。記憶體及儲存器亦可用於儲存資料、資料分析及類似者。記憶體及儲存器可代表非暫態電腦可讀媒體(即，任何適當形式的記憶體或儲存器)，該非暫態電腦可讀媒體可儲存由主機SoC 12或記憶體SoC 22用於執行本文中描述的各種技術的處理器可執行碼。應注意，非暫態僅指示媒體係有 形的且並非一信號。
資料結構的高度分割
如上所述，可藉由利用特定類型的記憶體之能力以執行通常在其他類型的記憶體上執行的操作而更高效地使用記憶體裝置。例如，如DRAM之低能力記憶體類型與諸如SRAM之高能力記憶體相比可能相對廉價。雖然DRAM可能無法像一SRAM一樣快地執行功能，但是DRAM之可獨立操作區域(IOR)(諸如庫)可用於同時執行可能已由SRAM個別地執行的多個操作。因而，在某些實施例中，記憶體SoC 22可在記憶體裝置14內分割一或多個記憶體組件之資料結構。即，記憶體SoC 22可決定如何使用各記憶體組件之可用資料結構分佈資訊。應提及，如本文中討論，分割一資料結構大致涉及根據記憶體組件中已存在的庫將資料結構的部分映射至現有庫的虛擬庫中，及類似情況。如將暸解，鑑於庫在記憶體組件內的各自資料結構，庫可獨立於彼此操作。以相同方式，在各庫中映射的虛擬庫可取決於其中映射各各自虛擬庫之庫而獨立於彼此操作。在任何情況中，在判定記憶體組件中的可用資料結構後，記憶體SoC 22可將作為記憶體組件之部分之不同資料結構映射至記憶體組件之庫或虛擬庫中。因此，高度分割技術可允許具有高的庫計數的廉價記憶體，諸如DRAM(即，具有比一慣用DRAM多的庫及被分割以作為一慣用DRAM中不存在的虛擬庫操作之可能庫的DRAM)取代更昂貴且高能力的記憶體，諸如SRAM。
記住上述內容，記憶體裝置14之各記憶體組件可包含特定數目的資料結構，該等資料結構在記憶體組件最初製造時，作為該記憶體組件的部分。例如，一記憶體組件可為一堆疊裝置，該堆疊裝置包含可分佈至不同部分(諸如室(vault)或庫)之記憶體之若干層。圖3繪示一例示性三維堆疊記憶體組件30之一俯視圖，該三維堆疊記憶體組件30可包含可能在製造時形成的若干記憶體層。如圖3中所示，記憶體組 件30可包含耦合至其上之若干鏈路31。通常，上文討論的通道29可包含一或多個鏈路31，且可提供對記憶體組件30之存取。在所描繪之實施例中，各鏈路31可包含三個進入信道及兩個外出信道。
如上所述，記憶體組件30可包含若干記憶體層及一邏輯層。例如，圖4繪示記憶體組件30之一示意圖，該記憶體組件30具有八個記憶體層32(例如，DRAM層1至8)及一個邏輯層33(例如，邏輯層0)。各記憶體層32可包含可用於儲存資料之記憶體位元單元。邏輯層33可包含控制電路組件，該等控制電路組件可促進至記憶體層32之一者或多者及至一外部介面之存取。
如上文討論，記憶體組件30可在製造時分割以提供記憶體組件30之單獨區段或IOR。在一個實例中，各記憶體層32可被分為大片段(例如，室)，該等大片段可被進一步分割為較小片段(例如，庫)。根據本文中描述之技術，庫可被進一步分割為虛擬庫。圖5繪示上文討論之記憶體組件30之一部分27之一示意圖。如圖5中所示，記憶體組件30之部分27之各記憶體層32可被分割為兩個室34，且各室34可被分割為兩個庫35。
應注意，圖5繪示有關鏈路31之一者之邏輯及記憶體堆疊之一部分27。在一實施例中，對於整個記憶體組件30，可能存在64個此等部分(例如，切片)。由於各記憶體層32被分割成兩個室34，故邏輯層33可包含兩個控制邏輯部分38，該等控制邏輯部分38可控制至各各自室34的資料流量。在所描繪之實施例中，每一個外部鏈路31繪示兩個室34。此組態可提供DRAM技術之內部速度能力的最佳化及其如何匹配至邏輯層33之外部速度能力。但是，應注意，在某些實施例中，各室34可包含耦合至邏輯層之其自己的個別垂直匯流排(未展示)。在某些實施例中，各鏈路31可經由邏輯層33存取室34。因而，邏輯層33可提供對記憶體層32的任何者之存取。
記住這點，記憶體SoC 22或任何其他適當裝置可將庫35進一步分割成虛擬庫36，該等虛擬庫36可用於提供記憶體組件30之改良操作。即，在某些實施例中，記憶體SoC 22將記憶體層32之片段(例如，庫35)之不同部分分配為單獨的虛擬庫36，該等虛擬庫36可用於執行各種資料操作。
舉例而言，圖6繪示可作為記憶體組件30之部分之四個例示性資料結構37。如將暸解，使用本文中揭示之系統及技術，記憶體SoC 22可將資料結構37映射至跨庫35分佈之虛擬庫36中。即，記憶體組件30可包含已被分割為四個虛擬庫36(虛擬庫0至3)之六個庫36(庫0至5)。如圖6中所示，資料結構A及資料結構D係讀取-修改-寫入(RMW)結構，其被映射至數量為唯讀結構兩倍之實體庫中。即，與可各跨一個庫35映射的唯讀結構相比，RMW結構之暫存器可各跨兩個庫35映射。藉由將各結構映射至不同庫35，記憶體SoC 22可改良記憶體組件30處置多個請求的能力。例如，若一第一請求涉及存取資料結構A之暫存器A0且一第二請求涉及存取資料結構A之暫存器A5，則記憶體SoC 22可能不針對第二請求提供對資料結構A的存取，直至第一請求已被處理為止。但是，若資料結構37被映射至圖6中所示之虛擬庫36中，則由於暫存器A0及A5被映射至作為不同庫35之部分之不同虛擬庫36，故記憶體SoC 22可同時處理第一請求及第二請求，此係因為其等兩者存取不同庫35。
記住記憶體組件30之例示性分割結構，下文將使用一網路設備實例描述使用記憶體組件之高度分割之技術。但是，應注意，此相同方法亦可在不存在清晰的資料結構時工作。通常，如上所述，藉由將可獨立操作區域(IOR)(如DRAM庫(例如，庫35))放入一定址結構之低階位元中，與資料結構之分割相比，可達成相同系統操作效果。例如，若DRAM自然存取係128位元(16位元組)，則緊接在16B群組之前 的位址位元可引向下一IOR。因而，連續的隨機交易可能進入與前一交易不同的IOR。
查看一網路設備實例，在可支援網際網路訊務之一高速路由器中，當一封包被路由器接收時，可參照高達40個不同資料結構。若輸入資料之集合線速率係400Gb/s，則最小封包大小係512個位元，且圍繞封包之額外時間間隙導致封包持續時間為672個位元，且所有封包為相同大小，則封包速率係1.68ns或672個位元/400Gb/s。一些結構可簡單依每個封包被觸碰(例如，讀取或寫入)一次，而其他結構可被觸碰兩次(例如，讀取及寫入)。因而，為了支援此線速率，記憶體可支援2次觸碰之隨機存取速率1.68ns/2=0.84ns，其可能難以使任何記憶體支援此類型之隨機存取。此外，可能難以設計DRAM以允許0.84ns的列循環時間(tRC)或將其擴充至tRC的甚至更小值。如本文中所使用，一記憶體組件之tRC指記憶體組件之一記憶體列完成一完整循環(從列啟動至主動列之預充電)所花費的最小時間量(例如，時脈循環)。
為了促進此類型之隨機存取，由記憶體SoC 22利用的個別DRAM的庫計數的數目可增大以提供足夠數目的庫來涵蓋隨機具有0.84ns的針對2次觸碰之近似存取速率之一應用程式的需要。為了判定個別DRAM之庫計數的數目，記憶體SoC 22可判定一記憶體組件之資料結構可用於根據較佳隨機存取請求速率實現一成功系統操作之一程度或量。通常，分割使用的數量可依據記憶體組件之tRC對較佳隨機存取請求速率之一比率。
記住上述內容，圖7繪示用於判定記憶體SoC 22可選擇以在一記憶體組件(例如，DRAM)中使用之最小數目之片段的方法40。若記憶體組件包含小於此最小數目的片段，則記憶體組件之片段可開始接收隨機請求，該隨機請求將偶爾佔用各片段，同時到達且導致各種延 遲。因而，在實務中，在執行方法40後實施之片段的數目可包含除所計算的最小值以外的一或多個片段。如本文中使用，片段指代記憶體組件30中已存在的庫35。片段亦指代如上文描述藉由一處理器映射之虛擬庫36。在某些實施例中，記憶體SoC 22可在使用一各自記憶體組件之不同片段之前執行下文描述之方法40。但是，應暸解，方法40可由任何適當處理器執行。為討論目的，將參考虛擬庫36描述方法40之下列描述，但是應暸解，方法40亦可參考作為記憶體組件30之部分之庫35執行。
在方塊42處，記憶體SoC 22可接收預期被傳送至記憶體SoC 22之一預期隨機存取速率。重新參考上文提出之實例，若輸入資料之一集合線速率係400Gb/s，則最小封包大小係512個位元(包含封包間間隙之672位元等效物)，且所有封包為最小大小，則各所接收封包之預期隨機存取速率係大約1.68ns。假設各封包包含2次觸碰資料操作，則針對各所接收封包之預期隨機存取速率係大約0.84ns。
在方塊44處，記憶體SoC 22可接收一記憶體組件之一列循環時間(tRC)。如上文討論，一記憶體組件之tRC指記憶體組件之一記憶體列完成一完整循環(從列啟動至主動列之預充電)所花費的最小時間量(例如，時脈循環)。換言之，記憶體組件之tRC可指一記憶體組件中之一資料結構(例如，庫)在執行一個資料操作(例如，2次觸碰操作)時可使用的時間量。
在方塊46處，記憶體SoC 22可基於記憶體組件之tRC對各所接收封包之預期隨機存取速率之一比率判定各自記憶體組件中可使用的虛擬庫之最小數目。若在方塊44處接收之記憶體組件之tRC係8.4ns，則在上文實例中記憶體組件之tRC對各所接收封包之預期隨機存取速率的比率係8.4：0.84或10至1。記憶體組件之tRC與各所接收封包之預期隨機存取速率之間的所產生比率可對應於將在各自記憶體組件中使用 以適應各所接收封包之預期隨機存取速率之最小數目之虛擬庫。即，所產生的比率可識別各自記憶體組件中在不添加封包至一佇列的情況下繼續接收封包所需之虛擬庫之數目。
如上所述，記憶體組件30可在設計或製造記憶體組件30時，被大致分佈至不同結構(例如，室34、庫35)中。一分佈實例包含將記憶體組件30劃分為庫35，如上文討論。庫30可使用共用的獨立列及行解碼器、感測放大器及資料路徑存取。
記住這點，在一些實施例中，記憶體SoC 22可藉由將一庫35劃分為虛擬庫36而使用較少資源來存取記憶體層35。即，記憶體SoC 22可將一庫35之不同部分映射至若干虛擬庫36中以使不同庫35能獨立操作。因而，邏輯層33之單獨列解碼器可用於存取各虛擬庫36，但資源的一些共性仍可沿著各自資料路徑及經由邏輯層33之行解碼器存在。
與將不同庫35映射至不同室34或不同記憶體層32之部分中相比，藉由將一個庫35映射至虛擬庫34中，記憶體SoC 22可引致較少面積損失(例如，額外2至3%)。即，一新請求可進入具有若干虛擬庫36之此單個庫35，且使用共用資源(例如，行解碼器)存取虛擬庫之各者。因而，記憶體SoC 22可按~4ns之行至行延遲時間(tCCD)之一速率送達一請求，該延遲時間比整個庫35之列循環時間(tRC)(例如，~35ns)快。雖然在一些情況中，tCCD速率可比資料路徑能力(例如，可按1至2ns操作)慢，但是與習知系統相比，使用虛擬庫36仍可在存取記憶體組件30時提供改良的速率。
重新參考方塊46，在判定將在各自記憶體組件中使用之虛擬庫之最小數目後，記憶體SoC 22可開始將各自記憶體組件中之一或多個資料結構映射至一各自虛擬庫36。應注意，藉由將記憶體組件30設計為具有更多庫35，或將虛擬庫36添加至庫35，記憶體組件30可使用額外矽區域，其可關聯於更高成本及因此更高之每位元成本。因此，若 記憶體組件30的晶粒大小恆定，則較少位元在記憶體組件30中可用。但是，本文中描述之映射程序不會實際導致任何記憶體容量(例如，記憶體位元計數)損失減小。而是，本文中描述之映射技術可導致資料圍繞記憶體組件30散佈。因而，額外邏輯可用於保持追蹤使用中的記憶體及空閒的記憶體。
為了更好地繪示分割記憶體組件的好處，圖8繪示尚未被分割成虛擬庫36之一記憶體組件之一例示性資料結構60。如圖8中所示，資料結構60包含16個記憶體位址62。當一封包請求被具有資料結構60之各自記憶體組件接收時，封包請求之相應資料操作可能導致資料結構無法被記憶體組件30之tRC獲得。即，例如，若一第一封包請求包含針對資料結構60之元素3之一請求，且一第二封包請求包含針對元素16之一請求，則第二封包請求無法被執行，直至第一封包請求已被完成或直至記憶體組件之tRC已通過為止。若當第二請求封包正在試圖存取資料結構60時，記憶體組件之tRC尚未通過，則記憶體SoC 22可被放置在針對各自資料結構60之一佇列中。
圖9繪示具有虛擬庫72、74、76及78之一分割資料結構70。在一實施例中，資料結構70之各輸入項可基於虛擬庫36之數目按循環方式編號。例如，取代如圖8之資料結構60中所示按時間順序對各記憶體位址編號，將元素1映射至虛擬庫72、將元素2映射至虛擬庫74，將元素3映射至虛擬庫76、將元素4映射至虛擬庫78、將元素5映射至虛擬庫72等等。
記住上述內容，當將上文提出之實例應用至圖9之分割資料結構70時，分割資料結構70之值將變得明顯。即，若第一封包請求包含針對分割資料結構70之元素3之一請求，則記憶體SoC 22可提供對分割資料結構70之虛擬庫76之存取。由於各分割資料結構係相同記憶體組件之部分，故各虛擬庫之tRC對應於記憶體組件之tRC。但是，與資 料結構60不同，若第二封包請求包含針對元素16之一請求，則記憶體SoC 22可提供對虛擬庫78之存取，而不管第一封包請求是否已停止存取虛擬庫76。如將暸解，由於虛擬庫76及虛擬庫78係獨立於彼此，故即使當虛擬庫76忙於執行另一操作時，記憶體SoC 22仍可提供對虛擬庫78之存取。因而，與資料結構60相比，記憶體組件使用分割資料結構70高效執行資料操作的能力隨更多虛擬庫產生而增大。
雖然圖7之方法40可提供將在記憶體組件30中形成的最小數目之虛擬庫，但是在記憶體組件30中增加額外虛擬庫以補償各種錯誤、非預期延遲、在佇列中等待存取記憶體組件30之封包及類似者可能是有利的。例如，考慮針對1011個隨機請求循環之上文描述之網路系統之模擬及假設每1.68ns可接收一請求之一基線SRAM及無資料結構分割，佇列深度(即，一新請求在全管線化系統中等待一答案的時間)針對僅具有1次觸碰之操作可為1個封包。另一方面，針對具有2次觸碰的操作，佇列時間傾向於無限。即，當每個請求執行一觸碰兩次時，SRAM無法跟上。由於每1.68ns，記憶體組件可接收一兩次觸碰請求(即使其在該時間跨度內只能處理一次觸碰操作)，故佇列深度在各所接收封包後增大，且傾向於無限。因而，此模擬系統無法如設計般起作用。
現參考來自使用4向資料結構分割之上述實例之一模擬之一些資料點，具有相對tRC=2*請求速率之一裝置之最大佇列延遲被模擬為12。對於相對tRC=3x，最大佇列延遲被模擬為31。基於各自記憶體組件之各種性質，可能期望良好系統操作之一最大佇列延遲不大於大約15。因而，tRC=2x係每個封包1次觸碰結構之一合理解決方案。對於2次觸碰，tRC被有效翻番，此係因為需要2個操作，因此tRC=2x將表現為tRC=4x，其在此實例中將具有不可接受的長佇列時間。
在64向分割中且假設tRC=8.4ns(即，5x封包速率)，佇列深度可 被模擬為6，其對於每個封包1次觸碰而言係可接受的。但是，在模擬每個封包2次觸碰的tRC=10x，佇列深度可被模擬為9，其亦可能係可接受的。因此，藉由採用各自記憶體組件之64個庫(其等可依5x封包速率循環)，即使在每個輸入封包2次觸碰記憶體的情況下，記憶體系統仍可跟上全線速率。
在tRC=6x(即，在本實例中的10.08ns)之64向分割中，DRAM的相應種類可使用快速庫循環技術，同時仍使用習知1T-1C DRAM及習知感測放大器建立。在此，佇列針對1次觸碰可為7，且針對2次觸碰可為10，兩者再次係可接受的。舉例而言，若40個資料結構之一系統具有1次觸碰(即，唯讀)結構之14個結構，且具有2次觸碰(即，讀取-修改-寫入)結構之24個結構，則針對14個唯讀結構之各者之16向分割可能涉及總共224個庫。因而，在本實例中，佇列將為13。其餘26個結構可被賦予30向分割，藉此消耗780個庫35。在此，2次觸碰佇列可為14個。在本實例中涉及之庫35的總數目接著可為224+780=1,004。若可用的庫35的總數目係1,024，則20個庫35仍可用於其他功能。記住這點，若系統使用8個DRAM來達成期望記憶體容量及頻寬，則各DRAM可使用128個庫35，其等可能比一產業標準DRAM高，但按合理成本設計及建造仍可行。
雖然在此參考一網路路由器描述資料結構之分割，但是應暸解，本文中描述之技術亦可用於其他類型之系統中。因而，上述實例不旨在將當前揭示技術之範疇限制為網路化。
記住上述內容，圖10繪示用於基於一較佳佇列深度判定將在記憶體組件中形成之虛擬庫之數目之一方法90。如上文參考圖7所提及，為討論目的，將參考虛擬庫36描述方法90之下列描述，但是應暸解，方法90亦可參考作為記憶體組件30之部分之庫35執行。
在一實施例中，方法90可在根據方法40判定將在記憶體組件中 形成之虛擬庫36之數目後執行。即，方法40可用於判定將在記憶體組件30中映射之虛擬庫36之最小數目，且接著方法90可用於微調或識別將在記憶體組件30中映射之虛擬庫36之數目以高效執行各種資料請求。
如同方法40，方法90之下文描述將被描述為由記憶體組件SoC 22執行，但是應暸解，任何適當處理器可執行方法90。此外，雖然方法90按特定順序提出，但是應注意，方法90可按任何適當順序執行。
現參考圖10，在方塊92處，記憶體SoC 22可接收一較佳佇列深度。較佳佇列深度可基於在記憶體組件被分割後可用之記憶體量判定。通常，各佇列深度增量涉及在記憶體組件中使用額外暫存器或額外記憶體以儲存佇列化之相應資料。因而，較佳佇列深度可與記憶體組件中可用之記憶體量相關。
應注意，記憶體成本涉及增大記憶體組件30可支援之佇列深度之量。即增大記憶體組件30之可用佇列深度，涉及使用記憶體組件30之更多暫存器來增大佇列深度。但是，為了減小佇列深度，記憶體SoC 22可在記憶體組件30內映射虛擬庫36。但是，虛擬庫36的映射仍增大記憶體成本，且增加有關邏輯層33之邏輯成本以適應針對不同虛擬庫36之不同佇列。但是，與分割記憶體組件30相比之未分割記憶體組件30之相對較長佇列深度對應於與使用具有虛擬庫36所涉及的多個佇列相比之較低系統效能。
在方塊94處，記憶體SoC 22可基於針對記憶體組件30之虛擬庫36具有一定預期觸碰率之隨機訊務判定在達到較佳佇列深度前執行的循環數目。在某些實施例中，虛擬庫36之預期量可對應於方法40之結果。
使用針對使用方法40判定之最小數目的虛擬庫36具有預期觸碰率之隨機訊務，記憶體SoC 22可執行記憶體組件30接收特定數目之隨 機請求之一模擬。在一實施例中，記憶體SoC 22可執行模擬，直至已達到較佳佇列深度。
舉例而言，圖11繪示一對數圖110，其繪示關於記憶體組件30中存在的虛擬庫36之數目，各種佇列深度值在若干循環內發生時的情況。如對數圖110中所示，當記憶體組件30被分割為4個虛擬庫36時，在10,000個循環後達到2的最大佇列深度。記住這點，在方塊94處，記憶體SoC 22可使用一模擬來判定預期在達到較佳佇列深度之前執行之循環的數目。
再次參考圖10，在方塊96處，記憶體SoC 22可判定循環數目是否大於一定臨限。在一實施例中，臨限可與被模擬為訊務之封包之一預期封包錯誤率相關聯。即，雖然藉由上文描述之方法40判定之虛擬庫36之數目可提供足夠數目的虛擬庫36來執行與所接收封包相關聯之資料操作，但是所判定數目不考慮所接收封包之封包錯誤率。任何封包可具有反映在一錯誤可能發生之前執行之預期數目之循環之一封包錯誤率。例如，封包錯誤率可為每109個循環1個錯誤。當一封包發生一錯誤，封包被重新傳送且記憶體組件30之佇列(例如，佇列深度)可增大。
記住這點，且考慮作為模擬的部分之封包之隨機訊務，一請求封包可在先前請求封包完成處理前重複到達相同虛擬庫36。因而，請求封包可作為佇列的部分備份或儲存在一暫存器中。在某些實施例中，請求封包之積存可儲存在記憶體組件30前方之佇列中。但是，佇列的大小受限，此係因為用於在佇列中保存封包之各暫存器耗用記憶體空間。某時，記憶體空間將不再可用。若佇列資源被剔除的頻率歸因於封包錯誤而小於正常封包丟棄率，則記憶體組件30之操作中可能不存在任何可觀測的損失。例如，若封包在109次中丟棄1個，則記憶體組件30可被選擇包含足夠的暫存器來支援在1012個請求中丟棄1個 之一佇列或0.1%的正常封包丟棄率。因而，重新參考方塊96，在一些實施例中，臨限可比封包錯誤率大一定倍數。例如，若1010個封包之一個封包丟棄，則臨限可被設定為1012。
若記憶體SoC 22判定循環數目不大於臨限，則記憶體SoC 22可結束方法90，且用方塊94處使用的虛擬庫的數目繼續進行。但是，若記憶體SoC 22判定循環數目大於臨限，則記憶體SoC 22可增大在記憶體組件30中映射的虛擬庫36的量，且在方塊98處，重複方塊94至98，直至達到較佳佇列深度的循環數目小於臨限。
雖然上文描述之方法90被描述為由記憶體SoC 22執行，但是應注意，在某些實施例中，方法90可由獨立於記憶體裝置14操作之一處理器執行。即，與典型記憶體SoC相比，執行方法90之處理器可具有額外處理力，以判定虛擬庫36之量以更快地使用。但是，若方法90由記憶體SoC 22執行，則應注意，記憶體SoC 22可包含額外控制邏輯、計數器及隨機數目產生器以高效執行方法90。
雖然本文中描述之實施例可具有各種修改及替代形式，但是特定實施例已在圖式中藉由實例展示且已在本文中予以詳細描述。然而，應瞭解，本發明並不旨在限於所揭示之特定形式。而是，本發明涵蓋落於如藉由下列隨附申請專利範圍定義之本發明之精神及範疇內之所有修改、等效物及替代。
27‧‧‧記憶體組件30之一部分
31‧‧‧鏈路
32‧‧‧記憶體層
33‧‧‧邏輯層
34‧‧‧室
35‧‧‧庫
36‧‧‧控制邏輯部分

Claims (20)

  1. 一種記憶體裝置，其包括：一記憶體組件，其經組態以儲存資料；及一處理器，其經組態以基於與該記憶體組件相關聯之一或多個性質及該記憶體組件之一預期隨機存取速率而在該記憶體組件中映射一或多個庫或一或多個虛擬庫。
  2. 如請求項1之記憶體裝置，其中該記憶體組件包括一動態隨機存取記憶體或一NAND記憶體。
  3. 如請求項1之記憶體裝置，其中該處理器經組態以經由該等虛擬庫之兩個不同虛擬庫在該記憶體組件上執行至少兩個資料操作，其中該至少兩個資料操作之一部分被同時執行。
  4. 如請求項1之記憶體裝置，其中與該記憶體組件相關聯之該等性質包括該記憶體組件之一列循環時間。
  5. 如請求項1之記憶體裝置，其中該預期隨機存取速率係基於由該處理器接收之請求之一聚合線速率、該等請求之各請求之一最小大小及由該等請求之各請求執行之觸碰操作之一類型判定。
  6. 一種方法，其包括：經由一處理器，接收與存取一記憶體組件相關聯之一預期隨機存取速率；經由該處理器，接收與該記憶體組件相關聯之一列循環時間；經由該處理器，基於該預期隨機存取速率及該列循環時間判定將在該記憶體組件中產生之庫之一第一數目或虛擬庫之一第二數目；及經由該處理器，分別基於該第一數目之庫或該第二數目之虛 擬庫在該記憶體組件中映射一或多個庫或一或多個虛擬庫，其中該記憶體組件中之該一或多個虛擬庫之各虛擬庫可基於該記憶體組件中之該一或多個虛擬庫之位置獨立存取。
  7. 如請求項6之方法，其中該列循環時間包括該記憶體組件之一記憶體列完成一完整循環之一時間量。
  8. 如請求項6之方法，其中該預期隨機存取速率係基於與存取該記憶體組件之各請求相關聯之觸碰之一數目判定。
  9. 如請求項6之方法，其中判定將在該記憶體組件中產生之虛擬庫之該數目包括判定該列循環時間對該預期隨機存取速率之一比率。
  10. 如請求項6之方法，其包括經由該處理器存取該一或多個虛擬庫之一第一虛擬庫，同時該一或多個虛擬庫之一第二虛擬庫亦被存取。
  11. 如請求項6之方法，其包括經由該處理器將該等記憶體組件之複數個元素映射至該等記憶體組件之該一或多個庫或該一或多個虛擬庫中之一或多個元素。
  12. 如請求項6之方法，其包括經由該處理器，基於該記憶體組件之一較佳佇列深度判定將在該記憶體組件中產生之虛擬庫之該第二數目。
  13. 如請求項12之方法，其中經由該處理器，基於該較佳佇列深度判定將在該記憶體組件中產生之虛擬庫之該第二數目包括執行存取該記憶體組件之複數個隨機請求之一模擬及判定由該處理器執行以達到該較佳佇列深度之循環之一數目。
  14. 一種有形、非暫態、機器可讀媒體，其包括指令，該等指令經組態以：接收一記憶體組件之一較佳佇列深度，其中該較佳佇列深度 包括在一佇列中等待存取該記憶體組件之封包之一數目；基於將由該記憶體組件接收之複數個隨機封包之一預期觸碰速率及該記憶體組件中之庫之一第一數目或虛擬庫之一第二數目判定達到該較佳佇列深度之循環之一數目，其中該記憶體組件中之該第二數目之虛擬庫之各虛擬庫可基於該記憶體組件中之該第二數目之虛擬庫之各虛擬庫之一位置獨立存取；及基於循環之該數目判定該記憶體組件中之庫之一第三數目或虛擬庫之一第四數目。
  15. 如請求項14之有形、非暫態、機器可讀媒體，其中用於判定循環之該數目之該等指令包括以下指令：執行藉由該記憶體組件針對該第一數目之庫或該第二數目之虛擬庫接收該複數個隨機封包之一模擬；及基於該模擬判定循環之該數目。
  16. 如請求項14之有形、非暫態、機器可讀媒體，其中用於判定虛擬庫之該第四數目之該等指令包括以下指令：判定循環之該數目是否超過一臨限；及當循環之該數目超過該臨限時，增加虛擬庫之該第二數目。
  17. 如請求項16之有形、非暫態、機器可讀媒體，其中該臨限與一封包錯誤率相關聯。
  18. 如請求項17之有形、非暫態、機器可讀媒體，其中該封包錯誤率包括在由該記憶體組件接收該複數個隨機封包之一模擬期間在一錯誤發生前執行之一預期數目之循環。
  19. 如請求項16之有形、非暫態、機器可讀媒體，其中該臨限係一封包錯誤率之一倍數。
  20. 如請求項14之有形、非暫態、機器可讀媒體，其中該記憶體組件包括一動態隨機存取記憶體或一NAND記憶體。
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