TWI543314B - 半導體封裝物 - Google Patents

半導體封裝物 Download PDF

Info

Publication number
TWI543314B
TWI543314B TW102117835A TW102117835A TWI543314B TW I543314 B TWI543314 B TW I543314B TW 102117835 A TW102117835 A TW 102117835A TW 102117835 A TW102117835 A TW 102117835A TW I543314 B TWI543314 B TW I543314B
Authority
TW
Taiwan
Prior art keywords
circuit board
semiconductor package
semiconductor
semiconductor wafer
layer
Prior art date
Application number
TW102117835A
Other languages
English (en)
Other versions
TW201349412A (zh
Inventor
陳泰宇
李鐘發
許文松
林世欽
Original Assignee
聯發科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 聯發科技股份有限公司 filed Critical 聯發科技股份有限公司
Publication of TW201349412A publication Critical patent/TW201349412A/zh
Application granted granted Critical
Publication of TWI543314B publication Critical patent/TWI543314B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

半導體封裝物
本發明係關於積體電路裝置(IC devices)，且特別是關於具有較少翹曲問題(warpage problem)以及較佳熱效能(improved thermal enhancement)之一種半導體封裝物。
一般之球柵陣列(BGA)半導體封裝物包括了安裝於絕緣之印刷電路板(PCB)之上表面之半導體晶片。印刷電路板可由如FR4板、FR5板、或BT(雙馬來醯亞胺-三氮雜苯，bismaleimide-triazine)板之經玻璃纖維填充之有機堆疊物所製成，且具有位於其上方表面與下方表面上之內連導電線路圖案。於半導體晶片、基板上方表面上以及延伸於半導體晶片與基板上方表面上之導電圖案之間之如銲線之導電物之上則覆蓋有固化之包覆材料(encapsulating material)。於基板之下方表面之導電圖案上則形成有導電球狀物或其他之輸入/輸出端子。
為了符合封裝物的更小與更薄的趨勢，於如球柵陣列半導體封裝物所遭遇困難之一為起因於製程中的溫度循環以及如基板與包覆材料間的熱膨脹特性差異之不同封裝材料的熱膨脹特性的差異所造成之半導體封裝物的翹曲(warpage)情形。而於封裝基板翹曲處，位於基板之下方表面處之此些導電球狀物或其他輸入/輸出端子將為不平整的。如此 於安裝半導體封裝物至主機板時將形成困難。而隨著封裝物尺寸的增加，其翹曲程度隨之增加，且因此限制了封裝物的尺寸的上限。另一期望則為隨著先進晶圓製程節點的縮減與功率密度的增加時增進封裝物的熱表現。為了保持積體電路的功能與可靠度，積體電路的功率消耗需配合所使用封裝物之功率限制，而因此積體電路之功能複雜程度則將受限於此功率限制。
依據一實施例，本發明提供了一種半導體封裝物，包括：一電路板，具有相對之一第一表面與一第二表面；一半導體晶片，形成於該電路板之該第一表面之一中央部上，具有一第一剖面尺寸；一間隔物，形成於該半導體晶片之一中央部之上，具有少於該第一剖面尺寸之一第二剖面尺寸；一包覆層，形成於該電路板上，覆蓋該半導體晶片且環繞該間隔物；一散熱層，形成於該包覆層與該間隔物上；以及複數個錫球，形成於該電路板之該第二表面上。
依據另一實施例，本發明提供了一種半導體封裝物，包括：一電路板，具有相對之一第一表面與一第二表面；一半導體晶片，形成於該電路板之該第一表面之一中央部上；一加強板，形成於該電路板之該第一表面之一邊緣部上，環繞該半導體晶片；一包覆層，形成於該電路板上，覆蓋該半導體晶片且為該加強板所環繞；一散熱層，形成於該包覆層與該加強板上；以及複數個錫球，形成於該電路板之該第二表面上。
依據又一實施例，本發明提供了一種半導體封裝物，包括：一電路板，具有相對之一第一表面與一第二表面； 一半導體晶片，形成於該電路板之該第一表面之一中央部上；一包覆層，形成於該電路板上，覆蓋該半導體晶片；一類U形散熱層，形成於該電路板上，包括覆蓋該包覆層之一頂面之一第一部與埋設於該包覆層內之一第二部；以及複數個錫球，形成於該電路板之該第二表面之上。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
10‧‧‧半導體封裝物
12‧‧‧電路板
14‧‧‧第一表面
16‧‧‧第二表面
18‧‧‧第一黏著層
20‧‧‧半導體晶片
22‧‧‧第一表面
24‧‧‧第二表面
26‧‧‧第二黏著層
28‧‧‧間隔物
30‧‧‧包覆層
32‧‧‧散熱層
34‧‧‧導電連接物
36‧‧‧導電球狀物
40‧‧‧半導體封裝物
42‧‧‧熱中間層
50‧‧‧半導體封裝物
52‧‧‧加強板
60‧‧‧半導體封裝物
62‧‧‧類U形散熱層
62a‧‧‧第一部
62b‧‧‧第二部
64‧‧‧開口
68‧‧‧第三黏著層
70‧‧‧條狀電路板
72‧‧‧主要條狀物
74‧‧‧電路板
76‧‧‧孔洞
A‧‧‧輸入/輸出銲墊
B‧‧‧銲墊
W1‧‧‧寬度
W2‧‧‧寬度
第1圖為一剖面圖，顯示了依據本發明一實施例之一半導體封裝物。
第2圖為一上視示意圖，顯示了如第1圖所示之半導體封裝物。
第3圖為一剖面圖，顯示了依據本發明另一實施例之一半導體封裝物。
第4圖為一剖面圖，顯示了依據本發明又一實施例之一半導體封裝物。
第5圖為一上視示意圖，顯示了如第4圖所示之半導體封裝物。
第6圖為一剖面圖，顯示了依據本發明另一實施例之一半導體封裝物。
第7圖為一立體示意圖，顯示了如第6圖所示之半導體封裝物之一散熱層。
第8圖為一上視示意圖，顯示了如第6圖所示之半導體封裝物。
第9圖為一上視示意圖，顯示了適用於製作如第1、3、4、6等圖所示之半導體封裝物之一種條狀電路板。
第1圖顯示了依據本發明之一實施例之具有較少翹曲問題之一種半導體封裝物10，其包括一電路板12、一半導體晶片20、一間隔物(spacer)28、一包覆層30、一散熱層32、以及複數個導電球狀物36。
請參照第1圖，半導體晶片20係為如微處理器(microprocessor)晶片、記憶體(memory)晶片或其他功能晶片之一功能性晶片(functional chip)，且具有主動之一第一表面22與非主動之一第二表面24。半導體晶片20之第一表面22包括位於鄰近第一表面22之周邊區處之數個輸入/輸出銲墊(input/output pad)A。半導體晶片20則可藉由研磨第二表面24而經過薄化。於一實施例中，半導體晶片20可具有約為2*10-6 m/m-K-4*10-6m/m-K之熱膨脹係數(coefficient of thermal expansion，CTE)。
半導體晶片20係透過一第一黏著層18而安裝於電路板12之中央部。電路板12具有相對之第一表面14與第二表面16，而第一黏著層18與半導體晶片20係依序形成於電路板12之第一表面14的中央部上。電路板12主要由如BT板、FR4板、FR5板之樹脂層(未顯示)或其他之經玻璃纖維填充之有機(如環氧樹脂)層疊物類型之用於製造半導體封裝物之印刷電路板所製 成。此外，於電路板12內亦形成有數個導電線路與數個導電內連物(皆未顯示)，進而形成了於半導體晶片20與導電球狀物36之間的適當電性連結情形。於一實施例中，電路板12可具有約為4*10-6 m/m-K-25*10-6 m/m-K之一整體熱膨脹係數(overall CTE)。而第一黏著層18可包括如環氧樹脂(epoxy)之材料，且具有約為30*10-6 m/m-K-65*10-6 m/m-K之熱膨脹係數。
如第1圖所示，於電路板12之第一表面14上形成有數個銲墊B以及數個導電之電路圖案(未顯示)，而於電路板12之第二表面16上則形成有數個導電球狀物36。半導體晶片20之輸出/輸入銲墊A係藉由一導電連接物34而電性連結於銲墊B，此導電連接物34則延伸於半導體晶片20與銲墊B之間。如第1圖所示，導電連接物34可為由金或鋁所形成之一銲線(bond wire)。
此外，間隔物28係透過一第二黏著層26而安裝於半導體晶片20之第一表面22之一中央部上。間隔物28為由一空白半導體晶圓所形成之如長方形之一非功能性晶片，且可包括相同於半導體晶片20之半導體層(未顯示)之一半導體材料。間隔物28具有一剖面尺寸，例如一寬度W1，其少於半導體晶片20之剖面尺寸，例如一寬度W2，而上述第一剖面尺寸與第二剖面尺寸之間具有約1：2-1：6之比例關係。於一實施例中，間隔物28可具有約2*10-6 m/m-K-5*10-6 m/m-K之熱膨脹係數。包覆層30則覆蓋了半導體晶片20之第一表面22以及電路板12之第一表面14，且環繞了間隔物28但沒有覆蓋間隔物28之頂面。包覆層30可藉由模塑與固化樹脂(例如環氧樹脂)材料所形成， 或藉由澆注與固化一液態樹脂(例如環氧樹脂)材料所形成。散熱層(heat spreading layer)32則覆蓋了包覆層30之頂面以及間隔物(亦即第二半導體晶片)28之頂面。於一實施例中，包覆層30可具有約5*10-6m/m-K-20*10-6m/m-K之熱膨脹係數。而散熱層32可由如銅、鋁或其他金屬合金所形成，且具有約12*10-6m/m-K-30*10-6m/m-K之熱膨脹係數、約50-350微米之厚度以及約50-420W/m-k之熱導率(thermal conductivity)。
導電球狀物36可由如鉛錫銲錫(lead tin solder)或其他金屬所形成，並可作為半導體封裝物10之輸出/輸入端子(input/output terminals)之用。導電球狀物36係透過導電連接物34、形成於電路板12上之銲墊B以及形成於電路板12內之導電線路與導電內連物(兩者皆未顯示)而分別電性連結於半導體晶片20之輸入/輸出銲墊A。導電球狀物36使得半導體封裝物10可安裝於一主機板(未顯示)上。亦可使用導電球狀物36以外之其他形態的輸出/輸入端子。
於第1圖所示之半導體封裝物10中，藉由間隔物28以及散熱層32的形成，可避免或至少降低翹曲問題的發生。間隔物28以及散熱層32提供了直接接合於半導體晶片20之一堅固框架，且因而限制了來自於電路板12之可能翹曲情形。
第2圖顯示了如第1圖所示之半導體封裝物10之一上視示意圖，而第1圖顯示了沿第2圖內線段1-1之剖面示意圖。於此實施例中，散熱層32係整個覆蓋電路板12，且基於簡化圖式之目的，於圖式中僅採用虛線方式繪示出半導體晶片20與間隔物28。
第3圖顯示了依據本發明之另一實施例之具有較少翹曲問題之一種半導體封裝物40，而此半導體封裝物40係由修改如第1-2圖所示之半導體封裝物10所得到。且基於簡化目的，在此相同標號係代表相同構件，且於下文中僅討論此些半導體封裝物10與40之間的差異處。
如第3圖所示，於散熱層32與間隔物(亦即第二半導體晶片)28之間形成有一熱中間層(thermal interlayer)42。於一實施例中，熱中間層42可由如環氧樹脂之材料所形成，且可具有約30*10-6m/m-K-65*10-6m/m-K之熱膨脹係數以及約5-100微米之厚度。
於第3圖所示之半導體封裝物40中，藉由間隔物28、熱中間層42以及散熱層32的形成可避免或至少降低翹曲問題的發生。此些間隔物(亦即第二半導體晶片)28、熱中間層42、以及散熱層32提供了可釋放累積於電路板12內之可能造成翹曲之熱應力之一垂直散熱通道。
第4圖顯示了依據本發明之又一實施例之具有較少翹曲問題之一種半導體封裝物50，而此半導體封裝物50係由修改如第3圖所示半導體封裝物40所得到。基於簡化目的，相同標號係代表相同構件，且於下文中僅討論半導體封裝物40與50之間的差異處。
如第4圖所示，於半導體封裝物50內並未形成有間隔物28與第二黏著層26。取得代之的是，於電路板12之第一表面14之周圍部上形成有一加強板(stiffener)52，以環繞半導體晶片20，而形成於電路板12上之包覆層30則覆蓋了半導體晶片 20且為加強板52所環繞。散熱層32係形成於包覆層30與加強板52之上，且熱中間層42係形成於散熱層32、包覆層30與加強板52之間。於一實施例中，加強板52可由如銅、鋁、或其他金屬合金所形成，且可具有約50*10-6m/m-K-420*10-6m/m-K之熱膨脹係數。
於第4圖所示之半導體封裝物50中，藉由加強板52、熱中間層42以及散熱層32的提供可避免或至少降低翹曲問題的發生。此些加強板52、熱中間層42、以及散熱層32的形成提供了直接接合於半導體晶片20之一堅固框架，且因而限制了來自於電路板12之可能翹曲情形。
第5圖為一上視示意圖，顯示了第4圖內所示之半導體封裝物50，而第4圖顯示了沿第5圖內線段4-4之剖面示意圖。於此實施例中，散熱層32係整個覆蓋了電路板12。同時，基於簡化之目的，於圖式中僅採用虛線繪示了第一半導體晶片20與加強板52。
第6圖顯示了依據本發明之另一實施例之具有較少翹曲問題之一種半導體封裝物60，而此半導體封裝物60係由修改如第1圖所示之半導體封裝物10所得到。基於簡化目的，在此相同標號係代表相同構件，且於下文中僅討論半導體封裝物10與60之間的差異處。
如第6圖所示，於半導體封裝物60內並未形成有間隔物28、第二黏著層26以及散熱層32。取得代之的是，於電路板12上形成了一類U形散熱層(U-like shaped heat spreading layer)62，其包括了形成於包覆層30之頂面上之一第一部62a以 及埋設於包覆層62之內之一第二部62b。類U形散熱層62之第二部62b係透過一第三黏著層68而安裝於半導體晶片20之上。於類U形散熱層62之第二部62b之內則形成有數個開口64，以使得形成包覆層30之材料可於其形成時流動並通過此些開口64。
於一實施例中，類U形散熱片62可由如銅、鋁、或其他金屬合金之材料所形成，且具有約50*10-6m/m-K-420*10-6m/m-K之熱膨脹係數。第三黏著層68可由如環氧樹脂(epoxy)之材料所形成，且具有約30*10-6m/m-K-65*10-6m/m-K之熱膨脹係數。第7圖為一立體圖，顯示了於第6圖所示之半導體封裝物60內所應用之類U形散熱片62。
於第6圖所示之半導體封裝物60中，藉由類U形散熱層62的形成，可避免或至少降低翹曲問題的發生。此類U形散熱層62提供了直接接合於半導體晶片20之一堅固框架，且因而限制了來自於電路板12之可能翹曲情形。
第8圖為一上視示意圖，顯示了如第6圖內之半導體封裝物60，而第6圖顯示了沿第8圖內線段6-6之半導體封裝物60的剖面圖。於此實施例中，類U形散熱層62完全覆蓋了電路板12，而基於簡化圖示目的，在此僅繪示了類U形散熱層62、形成於其內之開口64以及半導體晶片20。
前述之可具有較少翹曲問題之半導體封裝物10、40、50、60之可藉由一切割型打線接合球柵陣列封裝(sawing-type wire-bond BGA)製程所製成。而半導體封裝物10、40、50、60之構件可由一條狀電路板(circuit board strip)所製成。第9圖為一上視示意圖，顯示了依據本發明之一實施 例之一種條狀電路板70，其適用於製作上述之半導體封裝物10、40、50、60。此條狀電路板70包括由五個電路板74所形成之一主要條狀物72。主要條狀物72之周邊區之相對之列方向上形成有穿透之數個孔洞76。此些孔洞76可使得條狀電路板70於自動製程機台中的對準與前進。於此些半導體封裝物10、40、50、60之多個構件中則可自動地製作且形成於五個電路板74之內，並接著藉由一切割製程(未顯示)而分割形成單一之半導體封裝物10、40、50或60。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧半導體封裝物
12‧‧‧電路板
14‧‧‧第一表面
16‧‧‧第二表面
18‧‧‧第一黏著層
20‧‧‧半導體晶片
22‧‧‧第一表面
24‧‧‧第二表面
26‧‧‧第二黏著層
28‧‧‧間隔物
30‧‧‧包覆層
32‧‧‧散熱層
34‧‧‧導電連接物
36‧‧‧導電球狀物
A‧‧‧輸入/輸出銲墊
B‧‧‧銲墊
W1‧‧‧寬度
W2‧‧‧寬度

Claims (10)

  1. 一種半導體封裝物，包括：一電路板，具有相對之一第一表面與一第二表面；一半導體晶片，形成於該電路板之該第一表面之一中央部上；一加強板，形成於該電路板之該第一表面之一邊緣部上，環繞該半導體晶片；一包覆層，形成於該電路板上，覆蓋該半導體晶片且為該加強板所環繞；一散熱層，形成於該包覆層與該加強板上；以及複數個錫球，形成於該電路板之該第二表面上；其中於該電路板之該第一表面上形成有數個銲墊，該半導體晶片之輸出/輸入銲墊係藉由一銲線而電性連接於該第一表面上之該數個銲墊。
  2. 如申請專利範圍第1項所述之半導體封裝物，更包括一熱中間層，設置於該散熱層與該包覆層之間。
  3. 如申請專利範圍第1項所述之半導體封裝物，更包括一第一黏著層，設置於該電路板之該第一表面與該半導體晶片之間。
  4. 如申請專利範圍第1項所述之半導體封裝物，其中該散熱層包括銅或鋁。
  5. 如申請專利範圍第2項所述之半導體封裝物，其中該熱中間層包括環氧樹脂。
  6. 一種半導體封裝物，包括： 一電路板，具有相對之一第一表面與一第二表面；一半導體晶片，形成於該電路板之該第一表面之一中央部上；一包覆層，形成於該電路板上，覆蓋該半導體晶片；一類U形散熱層，形成於該電路板上，包括覆蓋該包覆層之一頂面之一第一部與埋設於該包覆層內之一第二部；以及複數個錫球，形成於該電路板之該第二表面之上；其中，所述半導體封裝物更包括複數個開口，形成於該類U形散熱層之該第二部內。
  7. 如申請專利範圍第6項所述之半導體封裝物，其中該類U形散熱層之該第二部係形成於該半導體晶片上。
  8. 如申請專利範圍第6項所述之半導體封裝物，更包括一第一黏著層，形成於該電路板之該第一表面與該半導體晶片之間。
  9. 如申請專利範圍第8項所述之半導體封裝物，更包括一第二黏著層，形成於該類U形散熱層之該第二部與該半導體晶片之間。
  10. 如申請專利範圍第6項所述之半導體封裝物，其中該散熱層包括銅或鋁。
TW102117835A 2012-05-24 2013-05-21 半導體封裝物 TWI543314B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201261651496P 2012-05-24 2012-05-24
US13/896,616 US9000581B2 (en) 2012-05-24 2013-05-17 Semiconductor package

Publications (2)

Publication Number Publication Date
TW201349412A TW201349412A (zh) 2013-12-01
TWI543314B true TWI543314B (zh) 2016-07-21

Family

ID=49620956

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102117835A TWI543314B (zh) 2012-05-24 2013-05-21 半導體封裝物

Country Status (3)

Country Link
US (2) US9000581B2 (zh)
CN (1) CN103426839B (zh)
TW (1) TWI543314B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9000581B2 (en) * 2012-05-24 2015-04-07 Mediatek Inc. Semiconductor package
US9252068B2 (en) 2012-05-24 2016-02-02 Mediatek Inc. Semiconductor package
US8836110B2 (en) * 2012-08-31 2014-09-16 Freescale Semiconductor, Inc. Heat spreader for use within a packaged semiconductor device
US20150371884A1 (en) * 2014-06-19 2015-12-24 Avago Technologies General Ip (Singapore) Pte. Ltd Concentric Stiffener Providing Warpage Control To An Electronic Package
US9627311B2 (en) 2015-01-22 2017-04-18 Mediatek Inc. Chip package, package substrate and manufacturing method thereof
KR102487563B1 (ko) * 2015-12-31 2023-01-13 삼성전자주식회사 반도체 패키지 및 그 제조방법
US9953904B1 (en) * 2016-10-25 2018-04-24 Nxp Usa, Inc. Electronic component package with heatsink and multiple electronic components
CN107301993A (zh) * 2017-06-08 2017-10-27 太极半导体（苏州）有限公司 一种增加非功能性芯片的封装结构及其制作工艺
US11404276B2 (en) * 2017-08-17 2022-08-02 Semiconductor Components Industries, Llc Semiconductor packages with thin die and related methods
WO2019066993A1 (en) * 2017-09-30 2019-04-04 Intel Corporation LOWERING MITIGATION STRUCTURES CREATED ON A SUBSTRATE USING HIGH-PERFORMANCE ADDITIVE MANUFACTURE
US11948855B1 (en) 2019-09-27 2024-04-02 Rockwell Collins, Inc. Integrated circuit (IC) package with cantilever multi-chip module (MCM) heat spreader
US11945714B2 (en) * 2020-07-30 2024-04-02 Stmicroelectronics S.R.L. Electronic device and corresponding method
TWI798952B (zh) * 2021-11-22 2023-04-11 矽品精密工業股份有限公司 電子封裝件及其製法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610442A (en) * 1995-03-27 1997-03-11 Lsi Logic Corporation Semiconductor device package fabrication method and apparatus
US5736785A (en) 1996-12-20 1998-04-07 Industrial Technology Research Institute Semiconductor package for improving the capability of spreading heat
US5904497A (en) * 1997-08-22 1999-05-18 Micron Technology, Inc. Method and apparatus for semiconductor assembly which includes testing of chips and replacement of bad chips prior to final assembly
TW454321B (en) 2000-09-13 2001-09-11 Siliconware Precision Industries Co Ltd Semiconductor package with heat dissipation structure
US6734552B2 (en) * 2001-07-11 2004-05-11 Asat Limited Enhanced thermal dissipation integrated circuit package
US7361995B2 (en) 2003-02-03 2008-04-22 Xilinx, Inc. Molded high density electronic packaging structure for high performance applications
TW200636954A (en) 2005-04-15 2006-10-16 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package and fabrication method thereof
US7332823B2 (en) 2005-12-15 2008-02-19 Intel Corporation Providing a metal layer in a semiconductor package
CN101101881A (zh) * 2006-07-03 2008-01-09 矽品精密工业股份有限公司 散热型封装结构及其制法
US9000581B2 (en) * 2012-05-24 2015-04-07 Mediatek Inc. Semiconductor package

Also Published As

Publication number Publication date
US9184107B2 (en) 2015-11-10
US9000581B2 (en) 2015-04-07
US20130313698A1 (en) 2013-11-28
TW201349412A (zh) 2013-12-01
US20150115429A1 (en) 2015-04-30
CN103426839B (zh) 2016-01-27
CN103426839A (zh) 2013-12-04

Similar Documents

Publication Publication Date Title
TWI543314B (zh) 半導體封裝物
TWI529878B (zh) 集成電路封裝件及其裝配方法
JP5579402B2 (ja) 半導体装置及びその製造方法並びに電子装置
US7656015B2 (en) Packaging substrate having heat-dissipating structure
US7719104B2 (en) Circuit board structure with embedded semiconductor chip and method for fabricating the same
KR102404058B1 (ko) 반도체 패키지
TWI671861B (zh) 半導體封裝結構及其製作方法
US20060249852A1 (en) Flip-chip semiconductor device
TWI646642B (zh) 晶片封裝結構及其製造方法
TWI506743B (zh) 半導體裝置的熱能管理結構及其製造方法
TWI419291B (zh) 引線框架結構、使用引線框架結構之進階四方扁平無引線封裝結構，以及其製造方法
JP6605382B2 (ja) 半導体装置及び半導体装置の製造方法
JP4110189B2 (ja) 半導体パッケージ
US9666506B2 (en) Heat spreader with wiring substrate for reduced thickness
US9252068B2 (en) Semiconductor package
TW201537719A (zh) 堆疊型半導體封裝
JP4494240B2 (ja) 樹脂封止型半導体装置
JP2012094592A (ja) 半導体装置及びその製造方法
JP5667381B2 (ja) 半導体装置及びその製造方法
TWI536515B (zh) 具有散熱結構之半導體封裝元件及其封裝方法
US8050049B2 (en) Semiconductor device
JP4647673B2 (ja) 放熱型多穿孔半導体パッケージ
JP2011061055A (ja) 半導体装置の製造方法
TWI297538B (en) Thermally and electrically enhanced stacked semiconductor package and fabrication method thereof
KR20140039563A (ko) 연성 기재의 패킹 제조 공정 및 그 구조