TWI543310B - 封裝裝置及其製造方法 - Google Patents

封裝裝置及其製造方法 Download PDF

Info

Publication number
TWI543310B
TWI543310B TW102136459A TW102136459A TWI543310B TW I543310 B TWI543310 B TW I543310B TW 102136459 A TW102136459 A TW 102136459A TW 102136459 A TW102136459 A TW 102136459A TW I543310 B TWI543310 B TW I543310B
Authority
TW
Taiwan
Prior art keywords
package
device wafer
molding material
wafer
molding
Prior art date
Application number
TW102136459A
Other languages
English (en)
Other versions
TW201415586A (zh
Inventor
陳旭賢
陳志華
葉恩祥
呂孟昇
陳承先
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201415586A publication Critical patent/TW201415586A/zh
Application granted granted Critical
Publication of TWI543310B publication Critical patent/TWI543310B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

封裝裝置及其製造方法
本發明係關於半導體封裝裝置，且特別關於封裝體層疊結構及其製造方法。
在積體電路的應用中，係需將越來越多的功能整合至產品中。例如，可能需將如3G影像元件、WiFi元件、藍芽元件及聲音/影像元件等不同功能的元件整合在一起以形成應用。
在傳統的整合方式中，不同元件皆接合至一中介層，且此中介層再與封裝基材接合。例如，在手機應用中，功率管理積體電路晶片、收發器(transceiver)晶片及多層陶瓷晶片電容(multi-layer ceramic capacitor)可使用此方式作接合。所形成的封裝體通常非常的厚及具有大面積。此外，既然各種與中介層連接之元件是透多個電連接器過與中介層連接，中介層的電連接器彼此之間的間距需非常小，且有時需小至約40nm至50nm。中介層需使用微凸塊以具有如此小的間距，但微凸塊在製造上仍面臨技術挑戰。
本揭露實施例係提供一種封裝裝置，包含：一底封裝體，包含：一塑膜材料；一第一裝置晶片模塑於此塑模材料中； 一穿組件通孔，穿透此塑模材料；及一第一重分佈線於此塑模材料上；以及一頂封裝體，包含一分離的被動裝置封裝於其中，其中此頂封裝體位於此底封裝體上並與其接合，且其中此分離的被動裝置與此第一重分佈線電性連接。
本揭露實施例亦提供一種封裝裝置，包含：一底封裝體，包含：一塑膜材料；一第一裝置晶片模塑於此塑模材料中；一第二裝置晶片模塑於此塑模材料中，其中此第一裝置晶片及此第二裝置晶片之電連接器包含與此塑模材料之一表面等高之終端；複數個穿組件通孔，穿透此塑模材料，其中此第一裝置晶片及此第二裝置晶片之電連接器之終端與這些穿組件通孔等高；第一重分佈層於此塑模材料之一第一側上，其中此第一重分佈線包含複數個第一重分佈線；及一第二重分佈層於此塑模材料之相對於此第一側之一第二側上，其中此第二重分佈層包含複數個第二重分佈線；以及一頂封裝體，位於此底封裝體上，其中此頂封裝體包含一分離的電容封裝於其中，且其中此分離的電容係與此底封裝體接合。
本揭露實施例更提供一種封裝裝置之製造方法，包含：形成一底封裝體，其包含：放置一第一裝置晶片及一第二裝置晶片於一載材上；形成複數個穿組件通孔於此載材上；模塑一第一裝置晶片、一第二裝置晶片及這些穿組件通孔於一塑膜材料中；薄化此塑模材料，其中在經過此薄化步驟之後，此塑模材料係暴露出這些穿組件通孔之頂端及此第一裝置晶片及此第二裝置晶片之電連接器之頂端；及形成複數個第一重分佈線於此塑模材料之一第一側上，其中這些第一重分佈線係與 這些穿組件通孔電性連接；以及形成一頂封裝體，其包含：接合一分離的被動裝置至此封裝體。
20‧‧‧載材
22‧‧‧黏著層
24‧‧‧裝置晶片
24A‧‧‧裝置晶片之表面
25‧‧‧裝置晶片
25A‧‧‧裝置晶片之表面
26‧‧‧導電柱
26A‧‧‧導電柱之頂端
27‧‧‧介電層
28‧‧‧穿組件通孔
28A‧‧‧穿組件通孔之頂端
28B‧‧‧穿組件通孔之背端
40‧‧‧塑模材料
40A‧‧‧塑模材料之表面
40B‧‧‧塑模材料之表面
42‧‧‧重分佈線
44‧‧‧介電層
46‧‧‧電連接器
48‧‧‧封裝體
49‧‧‧載材
50‧‧‧黏著劑
52‧‧‧介電層
54‧‧‧重分佈線
58‧‧‧封裝元件
60‧‧‧封裝元件
62‧‧‧連接器
64‧‧‧塑模材料
66‧‧‧頂封裝體
68‧‧‧封裝體層疊結構
第1至10圖顯示依照某些實施例製造之封裝體層疊結構於中間製造階段之剖面圖，其中裝置晶片內嵌於封裝體層疊結構中。
以下將詳述本揭露實施例之製造及使用。然而，可知的是，這些實施例係提供本發明之概念實施於各種特定內容中。在此所述的這些實施例係僅用以舉例，但並非用以限定本揭露。
本揭露係提供供封裝體層疊(Package On Package，POP)結構及其製造方法之實施例，並詳述封裝體層疊結構之中間製造階段及這些實施例之變化。在本揭露所述之各圖式及實施例中，相似之參考標號係用以指定相似元件。
第1至10圖顯示依照某些實施例製造封裝體層疊結構(PoP structure)於各中間階段之剖面圖。第1圖顯示載材20及載材20上的黏著層22。載板20可為玻璃載材、陶瓷載材或其類似物。黏著層22可由黏著材料形成，例如UV膠。
第2圖顯示裝置晶片24、25的放置，及導電柱28的形成。裝置晶片24、25可透過黏著層22置於載材20上，且彼此相互等高。裝置晶片24、25可為包含邏輯電晶體於其中之邏輯裝置晶片。在某些實施例中，裝置晶片24、25係設 計為手機應用，且可包含功率管理積體電路(PMIC)晶片、收發器晶片。雖然圖中僅顯示兩晶片24、25，然亦可設置更多彼此等高的的晶片於載材20上。
在本說明書中，導電柱28亦可稱為穿組件通孔(through assembly vias，TAVs)28。在某些實施例中，穿組件通孔28可先預形成，並接著放置於黏著層22上。在其他實施例中，穿組件通孔28可由電鍍形成。穿組件通孔28之電鍍可在放置晶片24、25之前進行，其可包含：形成晶種層(未顯示)於載材20上、形成光阻並將其圖案化、及於晶種層之未被光阻所覆蓋的暴露部分上電鍍穿組件通孔28。接著，移除光阻及晶種層之被光阻層所覆蓋的部分。裝置晶片24、25可接著放置於載材20上。穿組件通孔28之材料可包含銅、鋁或其類似物。在第2圖所示之結構中，穿組件通孔28之底端係與裝置晶片24、25之底面實質上等高。
在某些實施例中，金屬柱26(例如銅柱)形成於裝置晶片24、25之頂部部分上，並與裝置晶片24、25中的裝置電性連接。在某些實施例中，介電層27形成於裝置晶片24、25之頂面，且金屬柱26具有至少下部部分位於介電層27中。介電層27之頂面亦可與金屬柱26之頂端實質上等高。或者，可不形成介電層27，則金屬柱26突出超過裝置晶片24、25之剩餘部分。
參見第3圖，塑模材料40係模塑於裝置晶片24、25及穿組件通孔28上。塑模材料40填入至裝置晶片24、25及穿組件通孔28之間的間隙中，並與黏著層22相接觸。此外， 塑模材料40可填入金屬柱26與金屬柱26之間的間隙中。塑模材料40可包含塑模化合物、塑模底部填充物(molding underfill)、環氧樹脂或樹脂。塑模材料40之頂面高於金屬柱26及穿組件通孔28之頂端。接著，進行一薄化步驟以薄化塑模材料40，直至暴露出金屬柱26及穿組件通孔28，形成如第4圖所示之結構。此薄化步驟可為研磨步驟。由於此薄化步驟，穿組件通孔28之頂端28A與金屬柱26之頂端26A係實質上等高，且與塑模材料40之頂面40A實質上等高。
接著，參見第5圖，形成重分佈線42於塑模材料40上，以連接金屬柱26及穿組件通孔28。重分佈線42亦可內連接金屬柱26及穿組件通孔28。重分佈線42形成於介電層44中。在某些實施例中，重分佈線42之形成包含：沉積金屬層、圖案化金屬層及填入介電層44於重分佈線42之間的間隙中。重分佈線42可包含金屬或金屬合金，例如包含鋁、銅、鎢及或前述之合金。
第5圖亦顯示依照本揭露某些實施例之形成電連接器46。連接器46之形成可包含：放置焊球於重分佈線42之暴露部分上，並接著回焊焊球。在其他實施例中，連接器46之形成包含：進行電鍍步驟以形成焊接區域於重分佈層42上，並接著回焊此焊接區。連接器46亦可包含金屬柱(metal pillar)，或金屬柱(metal pillar)及焊蓋(solder caps)，且其亦可透過電鍍形成。在本說明書中，裝置晶片24及25、穿組件通孔28、塑模材料40及上方的重分佈線42及介電層44係以一併結合稱為封裝體48，且此封裝體48在此步驟中可為晶圓形 式。在其他實施例中，電連接器46係未在此製造階段形成，而是在接合封裝元件58及60後形成，所述接合步驟係顯示於第9圖。
參見第6圖，進行載材之替換。在載材替換製程中，先將載材49與封裝體48接合，其中載材20及49係各自位於封裝體48之兩相對側。載材49可透過黏著劑50與封裝體48接合，例如透過UV膠、膠帶或其類似物。接著，藉著使黏著層22失去黏性，可將載材20自封裝體48卸除。接著，再移除黏著層22。例如，當黏著層22由UV膠形成時，可將黏著層22暴露於UV光下，以使黏著層22失去黏性，並因此可將載材20及黏著層22由封裝體48卸除。
參見第7圖，在替換載材後，即暴露出穿組件通孔28之背端28B。在所示之結構中，穿組件通孔28之背端28B與裝置晶片24之背端24A及裝置晶片25之背端25A實質上等高。穿組件通孔28之背端28B亦可與塑模材料40之表面40B實質上等高。在某些實施例中，可進行研磨，以輕度地研磨裝置晶片24、25及穿組件通孔28之背面。由於進行了研磨，穿組件通孔28可稍突超過出置晶片24、25之背面，或與背端28B與表面40B、24A及25A等高。或者，亦可不進行此研磨步驟。
如第8圖所示，形成介電層52及重分佈線54。在某些實施例中，介電材料52可由一或多層之氧化物、氮化物、碳化物、氮化碳或前述之組成形成。某些重分佈線54可延伸至裝置晶片24、25上並與其對齊。因此，重分佈線54具有扇 入(fan-in)結構。在某些實施例中，重分佈線54之位於裝置晶片24、25上並與其對齊的部分係可與重分佈線54之位於穿組件通孔28上並與其對齊的部分相連接。
第9圖顯示接合封裝元件58及60至封裝體48。封裝元件58及60可為封裝體、裝置晶片、被動晶片及/或其類似物。在某些實施例中，封裝元件58為裝置晶片，且封裝元件60為分離的被動裝置，其未與如電晶體之主動裝置整合至相同晶片中。例如，當對應的封裝體是應用於手機時，封裝元件58可為基頻晶片，且封裝元件60可為多層陶瓷電容。上述之接合可為透過連接器62，以覆晶接合方式作接合。連接器62可包含焊料。可知的是，在不同的實施例中，裝置晶片24、25及58亦可與本實施例具有不同的排列方式。例如，功率管理積體電路晶片或收發器晶片可為裝置晶片58，且基頻晶片可為裝置晶片24及25之其中一者。
在接合封裝元件58、60之後，模塑封裝元件58及60於塑模材料64中。塑模材料64可與底封裝體48相接觸。因此，封裝元件58、60及塑模化合物64形成頂封裝體66，接合於底封裝體48下方。如此，即形成封裝體層疊結構。接著，將頂封裝體66及底封裝體48係自載材49卸除，形成如第10圖所示之結構。接著，晶圓級封裝體48可被切割為複數封裝體層疊結構68，其中每一封裝體層疊結構68包含一個頂封裝體66與一個底封裝體48相接合。
在某些實施例中，複數裝置晶片與穿組件通孔28一併嵌於底封裝體48中。此嵌有裝置晶片之底封裝體48的厚 度小於一般封裝基材的厚度，且小於中介層與封裝基材加起來的總厚度。因此，所形成之封裝體層疊結構68相較於傳統結構(裝置晶片及封裝元件與中介層接合)係具有經過縮減的厚度，傳統結構更接合於封裝基材上。此外，裝置晶片24、25及封裝元件58、60(第10圖)係為堆疊，而非在同相同的中介層上打線(在傳統結構中)。因此，相較於傳統結構，裝置晶片24、25及封裝元件58、60所佔的總面積可更為縮減。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍應以較寬廣的範圍或意義來解讀。
24‧‧‧裝置晶片
25‧‧‧裝置晶片
26‧‧‧導電柱
28‧‧‧穿組件通孔
40‧‧‧塑模材料
42‧‧‧重分佈線
44‧‧‧介電層
46‧‧‧電連接器
48‧‧‧封裝體
52‧‧‧介電層
54‧‧‧重分佈線
58‧‧‧封裝元件
60‧‧‧封裝元件
62‧‧‧連接器
64‧‧‧塑模材料
66‧‧‧頂封裝體

Claims (10)

  1. 一種封裝裝置，包含：一底封裝體，包含：一塑膜材料；一第一裝置晶片模塑於該塑模材料中，其中該第一裝置晶片包含複數個金屬柱，且該塑模材料填入該些金屬柱之間的間隙中；一穿組件通孔，穿透該塑模材料；及一第一重分佈線於該塑模材料上；以及一頂封裝體，包含一分離的被動裝置封裝於其中，其中該頂封裝體位於該底封裝體上並與其接合，且其中該分離的被動裝置與該第一重分佈線電性連接。
  2. 如申請專利範圍第1項所述之封裝裝置，更包含一第二裝置晶片模塑於該塑模材料中，其中該第一裝置晶片及該第二裝置晶片等高，其中該第一裝置晶片包含複數個第一電連接器，該第二裝置晶片包含複數個第二電連接器，其中該些第一電連接器之終端及該些第二電連接器之終端與該塑模材料之一表面等高。
  3. 如申請專利範圍第1項所述之封裝裝置，更包含一第二重分佈線於該塑模材料之相對於該第一重分佈線之相反側，其中該第二重分佈線係透過該穿組件通孔與該第一重分佈線電性連接。
  4. 一種封裝裝置，包含：一底封裝體，包含： 一塑膜材料；一第一裝置晶片模塑於該塑模材料中，其中該第一裝置晶片包含複數個金屬柱，且該塑模材料填入該些金屬柱之間的間隙中；一第二裝置晶片模塑於該塑模材料中，其中該第一裝置晶片及該第二裝置晶片之電連接器包含與該塑模材料之一表面等高之終端；複數個穿組件通孔，穿透該塑模材料，其中該第一裝置晶片及該第二裝置晶片之電連接器之終端與該些穿組件通孔等高；第一重分佈層於該塑模材料之一第一側上，其中該第一重分佈線包含複數個第一重分佈線；及一第二重分佈層於該塑模材料之相對於該第一側之一第二側上，其中該第二重分佈層包含複數個第二重分佈線；以及一頂封裝體，位於該底封裝體上，其中該頂封裝體包含一分離的電容封裝於其中，且其中該分離的電容係與該底封裝體接合。
  5. 如申請專利範圍第4項所述之封裝裝置，其中該頂封裝體更包含一第三裝置晶片與該底封裝體接合。
  6. 如申請專利範圍第4項所述之封裝裝置，其中該頂封裝體更包含一額外的塑模材料，且該分離的電容係模塑於該額外的塑模材料中，其中該額外的塑模材料係與該底封裝體相接觸。
  7. 如申請專利範圍第4項所述之封裝裝置，其中該第一裝置 晶片及該第二裝置晶片之電連接器之終端係與該塑模材料之一底面等高。
  8. 一種封裝裝置之製造方法，包含：形成一底封裝體，其包含：放置一第一裝置晶片及一第二裝置晶片於一載材上，其中該第一裝置晶片包含複數個金屬柱；形成複數個穿組件通孔於該載材上；模塑一第一裝置晶片、一第二裝置晶片及該些穿組件通孔於一塑膜材料中，其中該塑模材料填入該些金屬柱之間的間隙中；薄化該塑模材料，其中在經過該薄化步驟之後，該塑模材料係暴露出該些穿組件通孔之頂端及該第一裝置晶片及該第二裝置晶片之電連接器之頂端；及形成複數個第一重分佈線於該塑模材料之一第一側上，其中該些第一重分佈線係與該些穿組件通孔電性連接；以及形成一頂封裝體，其包含：接合一分離的被動裝置至該底封裝體。
  9. 如申請專利範圍第8項所述之封裝裝置之製造方法，其該形成該頂封裝體之步驟包含接合一第三裝置晶片至該底封裝體及模塑該分離的被動裝置於該塑模材料中，其中該塑模該分離的被動裝置之步驟係在接合該分離的被動裝置至該底封裝體之後進行。
  10. 如申請專利範圍第8項所述之封裝裝置之製造方法，更包含進行一晶片切割，以使該頂封裝體及該底封裝體與其他 封裝體分離。
TW102136459A 2012-10-11 2013-10-09 封裝裝置及其製造方法 TWI543310B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/649,941 US8975726B2 (en) 2012-10-11 2012-10-11 POP structures and methods of forming the same

Publications (2)

Publication Number Publication Date
TW201415586A TW201415586A (zh) 2014-04-16
TWI543310B true TWI543310B (zh) 2016-07-21

Family

ID=50454452

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102136459A TWI543310B (zh) 2012-10-11 2013-10-09 封裝裝置及其製造方法

Country Status (3)

Country Link
US (2) US8975726B2 (zh)
CN (2) CN103730434A (zh)
TW (1) TWI543310B (zh)

Families Citing this family (159)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
US8836136B2 (en) 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
US8975741B2 (en) * 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package
US9496195B2 (en) 2012-10-02 2016-11-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of depositing encapsulant along sides and surface edge of semiconductor die in embedded WLCSP
US9620413B2 (en) 2012-10-02 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier in semiconductor packaging
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US9721862B2 (en) 2013-01-03 2017-08-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of using a standardized carrier to form embedded wafer level chip scale packages
US9704824B2 (en) * 2013-01-03 2017-07-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded wafer level chip scale packages
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9941229B2 (en) 2013-10-31 2018-04-10 Infineon Technologies Ag Device including semiconductor chips and method for producing such device
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) * 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
KR20150091932A (ko) * 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
TWI517343B (zh) * 2014-03-25 2016-01-11 恆勁科技股份有限公司 覆晶堆疊封裝結構及其製作方法
US9754918B2 (en) 2014-05-09 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US9331021B2 (en) 2014-04-30 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-wafer package and method of forming same
US9666520B2 (en) 2014-04-30 2017-05-30 Taiwan Semiconductor Manufactuing Company, Ltd. 3D stacked-chip package
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US10177032B2 (en) * 2014-06-18 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaging devices, and methods of packaging semiconductor devices
US9385110B2 (en) 2014-06-18 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US9831214B2 (en) 2014-06-18 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packages, packaging methods, and packaged semiconductor devices
US9691726B2 (en) * 2014-07-08 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming fan-out package structure
US9847317B2 (en) 2014-07-08 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of packaging semiconductor devices and packaged semiconductor devices
CN104157619B (zh) * 2014-08-22 2016-09-28 山东华芯半导体有限公司 一种新型PoP堆叠封装结构及其制造方法
US20160095221A1 (en) * 2014-09-27 2016-03-31 Qualcomm Incorporated Integration of electronic elements on the backside of a semiconductor die
US9190367B1 (en) * 2014-10-22 2015-11-17 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US9420695B2 (en) * 2014-11-19 2016-08-16 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US20160172274A1 (en) * 2014-12-16 2016-06-16 Qualcomm Incorporated System, apparatus, and method for semiconductor package grounds
TWI559488B (zh) * 2014-12-27 2016-11-21 矽品精密工業股份有限公司 封裝結構及其製法
US20160240457A1 (en) * 2015-02-18 2016-08-18 Altera Corporation Integrated circuit packages with dual-sided stacking structure
US9583472B2 (en) * 2015-03-03 2017-02-28 Apple Inc. Fan out system in package and method for forming the same
US9633974B2 (en) * 2015-03-04 2017-04-25 Apple Inc. System in package fan out stacking architecture and process flow
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9978729B2 (en) * 2015-03-06 2018-05-22 Mediatek Inc. Semiconductor package assembly
US10368442B2 (en) * 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
US9659907B2 (en) * 2015-04-07 2017-05-23 Apple Inc. Double side mounting memory integration in thin low warpage fanout package
CN106057786B (zh) * 2015-04-13 2018-11-30 台湾积体电路制造股份有限公司 3d堆叠式芯片封装件
US9553001B2 (en) * 2015-04-28 2017-01-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a molding layer for semiconductor package
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US20170040266A1 (en) 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9627288B2 (en) * 2015-05-29 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures and methods of forming the same
US9520385B1 (en) 2015-06-29 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method for forming same
WO2017034589A1 (en) * 2015-08-27 2017-03-02 Intel Corporation Multi-die package
US9881850B2 (en) * 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US10049953B2 (en) * 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US10636773B2 (en) 2015-09-23 2020-04-28 Mediatek Inc. Semiconductor package structure and method for forming the same
US9704825B2 (en) * 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
CN105261611B (zh) * 2015-10-15 2018-06-26 矽力杰半导体技术(杭州)有限公司 芯片的叠层封装结构及叠层封装方法
US9837378B2 (en) * 2015-10-23 2017-12-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Fan-out 3D IC integration structure without substrate and method of making the same
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10483250B2 (en) 2015-11-04 2019-11-19 Intel Corporation Three-dimensional small form factor system in package architecture
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
CN106876358A (zh) * 2015-12-11 2017-06-20 安世有限公司 电子元件及其制造方法
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9589941B1 (en) * 2016-01-15 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip package system and methods of forming the same
US10665579B2 (en) * 2016-02-16 2020-05-26 Xilinx, Inc. Chip package assembly with power management integrated circuit and integrated circuit die
CN107154385A (zh) * 2016-03-04 2017-09-12 讯芯电子科技（中山）有限公司 堆叠封装结构及其制造方法
US10276402B2 (en) * 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
WO2017164905A1 (en) * 2016-03-25 2017-09-28 Intel Corporation Substrate-free system in package design
DE102016110862B4 (de) * 2016-06-14 2022-06-30 Snaptrack, Inc. Modul und Verfahren zur Herstellung einer Vielzahl von Modulen
US10109617B2 (en) 2016-07-21 2018-10-23 Samsung Electronics Co., Ltd. Solid state drive package
US9997471B2 (en) * 2016-07-25 2018-06-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10535632B2 (en) * 2016-09-02 2020-01-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and method of manufacturing the same
US20180076179A1 (en) * 2016-09-09 2018-03-15 Powertech Technology Inc. Stacked type chip package structure and manufacturing method thereof
US10276548B2 (en) 2016-09-14 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages having dummy connectors and methods of forming same
US9859245B1 (en) 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US11101222B2 (en) * 2016-09-29 2021-08-24 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers
US20180102298A1 (en) * 2016-10-06 2018-04-12 Mediatek Inc. Semiconductor device
US10529666B2 (en) * 2016-11-29 2020-01-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10002852B1 (en) 2016-12-15 2018-06-19 Dyi-chung Hu Package on package configuration
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US9978731B1 (en) 2016-12-28 2018-05-22 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package module
US11430751B2 (en) * 2016-12-30 2022-08-30 Intel Corporation Microelectronic devices designed with 3D stacked ultra thin package modules for high frequency communications
TWI643305B (zh) * 2017-01-16 2018-12-01 力成科技股份有限公司 封裝結構及其製造方法
US10319683B2 (en) 2017-02-08 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stacked package-on-package structures
TWI653725B (zh) * 2017-02-08 2019-03-11 南茂科技股份有限公司 指紋辨識封裝結構
US10784220B2 (en) * 2017-03-30 2020-09-22 Taiwan Semiconductor Manufacturing Co., Ltd. Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer
US10475718B2 (en) * 2017-05-18 2019-11-12 Advanced Semiconductor Engineering, Inc. Semiconductor device package comprising a dielectric layer with built-in inductor
US20180350708A1 (en) * 2017-06-06 2018-12-06 Powertech Technology Inc. Package structure and manufacturing method thereof
US10943869B2 (en) * 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US10541228B2 (en) * 2017-06-15 2020-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Packages formed using RDL-last process
US10217720B2 (en) * 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US11101209B2 (en) * 2017-09-29 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures in semiconductor packages and methods of forming same
US10886263B2 (en) * 2017-09-29 2021-01-05 Advanced Semiconductor Engineering, Inc. Stacked semiconductor package assemblies including double sided redistribution layers
US10763239B2 (en) * 2017-10-27 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-chip wafer level packages and methods of forming the same
CN108063095A (zh) * 2017-12-15 2018-05-22 路军 一种智能融合传感器芯片的封装方法
CN111095549A (zh) * 2017-12-29 2020-05-01 英特尔公司 容纳具有不同厚度的嵌入式管芯的贴片
WO2019133008A1 (en) * 2017-12-30 2019-07-04 Intel Corporation Ultra-thin, hyper-density semiconductor packages
US10388631B1 (en) * 2018-01-29 2019-08-20 Globalfoundries Inc. 3D IC package with RDL interposer and related method
US10510650B2 (en) * 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
KR102491103B1 (ko) 2018-02-06 2023-01-20 삼성전자주식회사 반도체 패키지 및 그 제조방법
KR102395199B1 (ko) 2018-02-22 2022-05-06 삼성전자주식회사 반도체 패키지
US10699980B2 (en) * 2018-03-28 2020-06-30 Intel IP Corporation Fan out package with integrated peripheral devices and methods
US11735570B2 (en) * 2018-04-04 2023-08-22 Intel Corporation Fan out packaging pop mechanical attach method
US10515929B2 (en) 2018-04-09 2019-12-24 International Business Machines Corporation Carrier and integrated memory
US10431563B1 (en) 2018-04-09 2019-10-01 International Business Machines Corporation Carrier and integrated memory
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
CN109300863A (zh) * 2018-09-28 2019-02-01 中国科学院微电子研究所 半导体封装结构以及半导体封装方法
KR102513085B1 (ko) * 2018-11-20 2023-03-23 삼성전자주식회사 팬-아웃 반도체 패키지
US20200161206A1 (en) * 2018-11-20 2020-05-21 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor manufacturing process
TWI728561B (zh) * 2018-11-29 2021-05-21 台灣積體電路製造股份有限公司 半導體封裝件以及其製造方法
US11282761B2 (en) 2018-11-29 2022-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of manufacturing the same
US20200211968A1 (en) * 2018-12-27 2020-07-02 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
CN109786271A (zh) * 2018-12-29 2019-05-21 华进半导体封装先导技术研发中心有限公司 一种三维堆叠封装方法及结构
CN111415909B (zh) * 2019-01-07 2022-08-05 台达电子企业管理（上海）有限公司 多芯片封装功率模块
US11063525B2 (en) 2019-01-07 2021-07-13 Delta Electronics (Shanghai) Co., Ltd. Power supply module and manufacture method for same
US11676756B2 (en) 2019-01-07 2023-06-13 Delta Electronics (Shanghai) Co., Ltd. Coupled inductor and power supply module
CN111415908B (zh) 2019-01-07 2022-02-22 台达电子企业管理（上海）有限公司 电源模块、芯片嵌入式封装模块及制备方法
TWI736859B (zh) * 2019-03-18 2021-08-21 矽品精密工業股份有限公司 電子封裝件及其製法
CN110600440B (zh) * 2019-05-13 2021-12-14 华为技术有限公司 一种埋入式封装结构及其制备方法、终端
US11380620B2 (en) * 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11417619B2 (en) * 2019-08-22 2022-08-16 Taiwan Semiconductor Manufacturing Company Ltd. Package and manufacturing method thereof
CN114450786A (zh) * 2019-10-30 2022-05-06 华为技术有限公司 芯片堆叠封装结构及其封装方法、电子设备
US11362036B2 (en) * 2020-01-06 2022-06-14 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
CN113098234B (zh) 2020-01-08 2022-11-01 台达电子企业管理（上海）有限公司 供电***
US11812545B2 (en) 2020-01-08 2023-11-07 Delta Electronics (Shanghai) Co., Ltd Power supply system and electronic device
CN113097190A (zh) 2020-01-08 2021-07-09 台达电子企业管理（上海）有限公司 电源模块及电子装置
US11342316B2 (en) 2020-01-16 2022-05-24 Mediatek Inc. Semiconductor package
US11462418B2 (en) 2020-01-17 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
KR20210109179A (ko) 2020-02-27 2021-09-06 삼성전자주식회사 반도체 패키지
US11948877B2 (en) * 2020-03-31 2024-04-02 Qualcomm Incorporated Hybrid package apparatus and method of fabricating
TWI771974B (zh) * 2020-04-03 2022-07-21 韓商Ｎｅｐｅｓ股份有限公司 半導體封裝件
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US20220262766A1 (en) * 2021-02-12 2022-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. Through-Dielectric Vias for Direct Connection and Method Forming Same
KR20220117032A (ko) 2021-02-16 2022-08-23 삼성전자주식회사 반도체 패키지
CN115148712A (zh) * 2021-03-29 2022-10-04 矽磐微电子(重庆)有限公司 半导体封装方法及半导体封装结构
US20220352082A1 (en) * 2021-04-28 2022-11-03 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor Package and Method
CN112992956B (zh) * 2021-05-17 2022-02-01 甬矽电子(宁波)股份有限公司 芯片封装结构、芯片封装方法和电子设备
US11854928B2 (en) * 2021-08-27 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and manufacturing method thereof
CN114496988A (zh) * 2022-04-19 2022-05-13 宁波德葳智能科技有限公司 脑电波处理***的再布线封装结构及其制作方法
CN117410261A (zh) * 2022-07-08 2024-01-16 长鑫存储技术有限公司 半导体封装结构及制备方法
CN115632034A (zh) * 2022-12-20 2023-01-20 珠海妙存科技有限公司 eMMC模组封装结构及其制作方法
CN117316907A (zh) * 2023-11-29 2023-12-29 浙江禾芯集成电路有限公司 一种晶圆级非tsv 3d堆叠封装结构及方法

Family Cites Families (81)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998025304A1 (fr) 1996-12-04 1998-06-11 Hitachi, Ltd. Dispositif a semi-conducteur
US6281046B1 (en) 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level
TW511405B (en) 2000-12-27 2002-11-21 Matsushita Electric Ind Co Ltd Device built-in module and manufacturing method thereof
US8158508B2 (en) 2001-03-05 2012-04-17 Megica Corporation Structure and manufacturing method of a chip scale package
US7573136B2 (en) 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US20040187297A1 (en) 2003-03-27 2004-09-30 E Touch Corporation Method of fabricating a polymer resistor in an interconnection via
US7164197B2 (en) 2003-06-19 2007-01-16 3M Innovative Properties Company Dielectric composite material
TWI260079B (en) 2004-09-01 2006-08-11 Phoenix Prec Technology Corp Micro-electronic package structure and method for fabricating the same
JPWO2006035528A1 (ja) 2004-09-29 2008-05-15 株式会社村田製作所 スタックモジュール及びその製造方法
US7105920B2 (en) 2004-11-12 2006-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design to improve chip package reliability
US7515434B2 (en) 2004-12-20 2009-04-07 Nortel Networks Limited Technique for enhancing circuit density and performance
US7394148B2 (en) * 2005-06-20 2008-07-01 Stats Chippac Ltd. Module having stacked chip scale semiconductor packages
US20080006936A1 (en) 2006-07-10 2008-01-10 Shih-Ping Hsu Superfine-circuit semiconductor package structure
US20080017407A1 (en) 2006-07-24 2008-01-24 Ibiden Co., Ltd. Interposer and electronic device using the same
CN200976345Y (zh) * 2006-11-24 2007-11-14 威盛电子股份有限公司 芯片封装结构
US8421244B2 (en) 2007-05-08 2013-04-16 Samsung Electronics Co., Ltd. Semiconductor package and method of forming the same
KR100923562B1 (ko) 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US7514797B2 (en) 2007-05-31 2009-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-die wafer level packaging
US7659609B2 (en) 2007-08-31 2010-02-09 Stats Chippac Ltd. Integrated circuit package-in-package system with carrier interposer
US8476769B2 (en) 2007-10-17 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Through-silicon vias and methods for forming the same
US8637341B2 (en) * 2008-03-12 2014-01-28 Infineon Technologies Ag Semiconductor module
US8093722B2 (en) * 2008-05-27 2012-01-10 Mediatek Inc. System-in-package with fan-out WLCSP
US7704796B2 (en) 2008-06-04 2010-04-27 Stats Chippac, Ltd. Semiconductor device and method of forming recessed conductive vias in saw streets
US7741151B2 (en) 2008-11-06 2010-06-22 Freescale Semiconductor, Inc. Integrated circuit package formation
US8344503B2 (en) 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
US7838337B2 (en) 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias
US7858441B2 (en) * 2008-12-08 2010-12-28 Stats Chippac, Ltd. Semiconductor package with semiconductor core structure and method of forming same
JP5147678B2 (ja) 2008-12-24 2013-02-20 新光電気工業株式会社 微細配線パッケージの製造方法
US7863100B2 (en) 2009-03-20 2011-01-04 Stats Chippac Ltd. Integrated circuit packaging system with layered packaging and method of manufacture thereof
JP4883203B2 (ja) * 2009-07-01 2012-02-22 株式会社テラミクロス 半導体装置の製造方法
CN102473684B (zh) 2009-07-30 2014-09-17 高通股份有限公司 ***级封装
US9230898B2 (en) 2009-08-17 2016-01-05 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US8803332B2 (en) 2009-09-11 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Delamination resistance of stacked dies in die saw
US8143097B2 (en) 2009-09-23 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of forming open cavity in TSV interposer to contain semiconductor die in WLCSMP
US8102599B2 (en) 2009-10-21 2012-01-24 International Business Machines Corporation Fabrication of optical filters integrated with injection molded microlenses
KR101099578B1 (ko) 2009-11-03 2011-12-28 앰코 테크놀로지 코리아 주식회사 재배선 및 ｔｓｖ를 이용한 적층 칩 패키지
US8901724B2 (en) 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
TWI436463B (zh) 2009-12-31 2014-05-01 Advanced Semiconductor Eng 半導體封裝結構及其製造方法
US8115260B2 (en) 2010-01-06 2012-02-14 Fairchild Semiconductor Corporation Wafer level stack die package
US8138014B2 (en) * 2010-01-29 2012-03-20 Stats Chippac, Ltd. Method of forming thin profile WLCSP with vertical interconnect over package footprint
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
JP5423874B2 (ja) 2010-03-18 2014-02-19 日本電気株式会社 半導体素子内蔵基板およびその製造方法
US8618654B2 (en) 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
KR101667656B1 (ko) 2010-03-24 2016-10-20 삼성전자주식회사 패키지-온-패키지 형성방법
US8183696B2 (en) * 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
JP2011233854A (ja) * 2010-04-26 2011-11-17 Nepes Corp ウェハレベル半導体パッケージ及びその製造方法
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8343810B2 (en) 2010-08-16 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming Fo-WLCSP having conductive layers and conductive vias separated by polymer layers
US8823166B2 (en) 2010-08-30 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Pillar bumps and process for making same
US8435835B2 (en) 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
US8518746B2 (en) 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
KR101695353B1 (ko) 2010-10-06 2017-01-11 삼성전자 주식회사 반도체 패키지 및 반도체 패키지 모듈
US8105875B1 (en) 2010-10-14 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Approach for bonding dies onto interposers
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
GB2485830A (en) * 2010-11-26 2012-05-30 Cambridge Silicon Radio Ltd Stacked multi-chip package using encapsulated electroplated pillar conductors; also able to include MEMS elements
US8619431B2 (en) * 2010-12-22 2013-12-31 ADL Engineering Inc. Three-dimensional system-in-package package-on-package structure
KR101215271B1 (ko) 2010-12-29 2012-12-26 앰코 테크놀로지 코리아 주식회사 반도체 패키지 구조물 및 반도체 패키지 구조물의 제조 방법
KR101236798B1 (ko) 2011-02-16 2013-02-25 앰코 테크놀로지 코리아 주식회사 웨이퍼 레벨 적층형 반도체 패키지 제조 방법
US8508045B2 (en) 2011-03-03 2013-08-13 Broadcom Corporation Package 3D interconnection and method of making same
US8883561B2 (en) 2011-04-30 2014-11-11 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within encapsulant with TMV for vertical interconnect in POP
US20120319295A1 (en) 2011-06-17 2012-12-20 Chi Heejo Integrated circuit packaging system with pads and method of manufacture thereof
US8710668B2 (en) 2011-06-17 2014-04-29 Stats Chippac Ltd. Integrated circuit packaging system with laser hole and method of manufacture thereof
US8541884B2 (en) 2011-07-06 2013-09-24 Research Triangle Institute Through-substrate via having a strip-shaped through-hole signal conductor
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US8975741B2 (en) 2011-10-17 2015-03-10 Taiwan Semiconductor Manufacturing Company, Ltd. Process for forming package-on-package structures
US8634221B2 (en) 2011-11-01 2014-01-21 Avago Technologies General Ip (Singapore) Pte. Ltd. Memory system that utilizes a wide input/output (I/O) interface to interface memory storage with an interposer and that utilizes a SerDes interface to interface a memory controller with an integrated circuit, and a method
US8916481B2 (en) 2011-11-02 2014-12-23 Stmicroelectronics Pte Ltd. Embedded wafer level package for 3D and package-on-package applications, and method of manufacture
US8928114B2 (en) 2012-01-17 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Through-assembly via modules and methods for forming the same
US9258922B2 (en) 2012-01-18 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. PoP structures including through-assembly via modules
US9881894B2 (en) 2012-03-08 2018-01-30 STATS ChipPAC Pte. Ltd. Thin 3D fan-out embedded wafer level package (EWLB) for application processor and memory integration
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US8723309B2 (en) 2012-06-14 2014-05-13 Stats Chippac Ltd. Integrated circuit packaging system with through silicon via and method of manufacture thereof
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US8791016B2 (en) 2012-09-25 2014-07-29 International Business Machines Corporation Through silicon via wafer, contacts and design structures
US9209156B2 (en) 2012-09-28 2015-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuits stacking approach
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
US8957525B2 (en) 2012-12-06 2015-02-17 Texas Instruments Incorporated 3D semiconductor interposer for heterogeneous integration of standard memory and split-architecture processor
US9087765B2 (en) 2013-03-15 2015-07-21 Qualcomm Incorporated System-in-package with interposer pitch adapter
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9679839B2 (en) 2013-10-30 2017-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method

Also Published As

Publication number Publication date
CN108962876B (zh) 2022-05-17
US8975726B2 (en) 2015-03-10
US9490167B2 (en) 2016-11-08
TW201415586A (zh) 2014-04-16
US20140103488A1 (en) 2014-04-17
CN103730434A (zh) 2014-04-16
CN108962876A (zh) 2018-12-07
US20150155203A1 (en) 2015-06-04

Similar Documents

Publication Publication Date Title
TWI543310B (zh) 封裝裝置及其製造方法
US10854577B2 (en) 3D die stacking structure with fine pitches
US20210287966A1 (en) Semiconductor package and method of making
US11069656B2 (en) Three-layer package-on-package structure and method forming same
US8803306B1 (en) Fan-out package structure and methods for forming the same
US10867897B2 (en) PoP device
CN111883481B (zh) 3d封装件结构及其形成方法
US9184128B2 (en) 3DIC package and methods of forming the same
US10199320B2 (en) Method of fabricating electronic package
US20180342414A1 (en) Wafer Level Chip Scale Packaging Intermediate Structure Apparatus and Method
TW201826461A (zh) 堆疊型晶片封裝結構
US10109618B2 (en) Bonding structure between semiconductor device package
CN103681613A (zh) 具有离散块的半导体器件
TWI614848B (zh) 電子封裝結構及其製法
TW201624641A (zh) 半導體封裝體
US8952268B2 (en) Interposed substrate and manufacturing method thereof
US20160329267A1 (en) Electronic package and fabrication method thereof
US20170186711A1 (en) Structure and method of fan-out stacked packages
TWI731888B (zh) 堆疊式半導體元件的製造方法
CN107123631B (zh) 电子封装件及其半导体基板与制法
US20130256915A1 (en) Packaging substrate, semiconductor package and fabrication method thereof
TWI723414B (zh) 電子封裝件及其製法
TW202123348A (zh) 電子封裝件之製法
TWI512921B (zh) 載板結構與晶片封裝結構及其製作方法
TWI627694B (zh) 模封互連基板之面板組合構造及其製造方法