TWI559488B - 封裝結構及其製法 - Google Patents

封裝結構及其製法 Download PDF

Info

Publication number
TWI559488B
TWI559488B TW103145895A TW103145895A TWI559488B TW I559488 B TWI559488 B TW I559488B TW 103145895 A TW103145895 A TW 103145895A TW 103145895 A TW103145895 A TW 103145895A TW I559488 B TWI559488 B TW I559488B
Authority
TW
Taiwan
Prior art keywords
layer
package structure
electronic component
conductive
dielectric layer
Prior art date
Application number
TW103145895A
Other languages
English (en)
Other versions
TW201624661A (zh
Inventor
劉亦瑋
陳彥亨
葉懋華
劉鴻汶
賴顗喆
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103145895A priority Critical patent/TWI559488B/zh
Priority to CN201510027102.7A priority patent/CN105870023A/zh
Priority to US14/956,758 priority patent/US9666536B2/en
Publication of TW201624661A publication Critical patent/TW201624661A/zh
Application granted granted Critical
Publication of TWI559488B publication Critical patent/TWI559488B/zh
Priority to US15/581,799 priority patent/US20170236783A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076—Shape of the containers
    • H01L2225/1088—Arrangements to limit the height of the assembly
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

封裝結構及其製法
本發明係有關一種封裝結構及其製法，尤指一種嵌埋電子元件之封裝結構及其製法。
隨著半導體技術的演進，半導體產品已開發出不同封裝產品型態，而為追求半導體封裝件之輕薄短小，因而發展出一種晶片級封裝件(chip scale package,CSP)，其特徵在於此種晶片級封裝件僅具有與晶片尺寸相等或略大的尺寸。
請參閱第1A至1F圖，係為習知半導體封裝件1之製法的剖面示意圖。
如第1A圖所示，提供具有第一黏著層100a之第一承載件10a，且設置至少一半導體元件11於該第一黏著層100a上，並形成一包覆層12以包覆該半導體元件11。該半導體元件11具有相對之主動面11a與非主動面11b，該主動面11a結合於該第一黏著層100a，並於該主動面11a上具有複數電極墊110。
如第1B圖所示，以研磨方式去除部份該包覆層12， 以令該半導體元件11之非主動面11b外露於該包覆層12之第二表面12b。接著，移除該第一承載件10a及第一黏著層100a，並於該包覆層12之第二表面12b上接置具有第二黏著層100b之第二承載件10b。
如第1C圖所示，形成一第一線路重佈層(redistribution layer，簡稱RDL)13於該包覆層12之第一表面12a與該半導體元件11之主動面11a上，且該第一線路重佈層13電性連接該半導體元件11之電極墊110。
如第1D圖所示，設置具有第三黏著層100c之第三承載件10c於該第一線路重佈層13上，再移除該第二承載件10b及該第二黏著層100b。之後以雷射方式形成複數貫穿該包覆層12之通孔121，以外露出該第一線路重佈層13。
如第1E圖所示，形成第二線路重佈層14於該包覆層12之第二表面12b上及通孔121中，以電性連接該第一線路重佈層13。
如第1F圖所示，移除該第三黏著層100c及該第三承載件10c，再進行切單製程，並形成複數如銲球之導電元件15於該第一線路重佈層13上，以令該導電元件15電性連接該第一線路重佈層13及該第二線路重佈層14。
然而，於該半導體封裝件1之製法中，以雷射方式形成通孔121，不僅速度慢(特別是孔數較多時)而耗時，且於形成該通孔121之過程中所產生之殘留物(如該包覆層12之殘膠等)極易堆積於該通孔121之底部，以致於後續製程中需先清洗該通孔121內部，才能將導電材料填入 該通孔121中以形成該第二線路重佈層14，導致製程步驟繁多。
其次，雷射開孔方式會造成該通孔121之壁面呈現凹凸不平，造成後續電鍍之導電材料無法有效附著於該通孔121之壁面上而發生脫落(peeling)現象，導致該半導體封裝件1之可靠度不佳。
再者，雷射鑽孔製程需由該包覆層12之第二表面12b上進行鑽孔，但受限於該包覆層12不透光，故雷射鑽孔設備無法偵測該包覆層12下之第一線路重佈層13，因而需以特殊製程及設備進行對位鑽孔，致使製程步驟增多及提高製作成本。
此外，雷射鑽孔製程之雷射光束會產生熱影響區(Heat Affact Zone)之問題，亦即當該通孔121之位置需靠近該半導體元件11時，雷射光束之高熱會破壞半導體元件11，故該通孔121之位置需與該半導體元件11保持一定距離，因而無法縮小該半導體封裝件1之尺寸，致使產品難以符合微小化之需求。
另一方面，於該半導體封裝件1之製法中，需多次(至少三次)進行結合/移除承載件(即該第一至第三承載件10a-10c)之步驟，致使製程步驟繁多，不僅耗時，且需消耗承載件及黏著層之料數，而增加產品之製作成本。
因此，如何克服習知技術之種種問題，實為一重要課題。
鑒於上述習知技術之缺失，本發明係提供一種封裝結構之製法，包括：提供具有金屬層之第一承載件；於該金屬層上形成圖案化之介電層，並於該介電層形成具有複數外露該金屬層之開口；於該複數開口中形成複數具有相對之第一端及第二端之導電柱，其中，各該複數導電柱以其第一端電性連接該金屬層，且各該複數導電柱之第二端凸出於該介電層之表面；設置至少一第一電子元件於該介電層上；形成包覆層於該介電層上，以令該包覆層包覆該複數導電柱、該第一電子元件及該介電層；移除部份該包覆層，以外露各該複數導電柱之第二端；以及移除該第一承載件。
本發明復提供一種封裝結構，包括：介電層；包覆層，形成於該介電層上，供該介電層與包覆層構成一具有相對之第一表面和第二表面之封裝體，其中，該第一表面係該介電層之外側面，該第二表面係該包覆層之外側面；至少一第一電子元件，係設於該介電層上，並嵌埋於該包覆層中；以及複數導電柱，係豎埋於該包覆層及該介電層中，各該複數導電柱具有相對之第一端及第二端，且該第一端外露於該第一表面，該第二端外露於該第二表面。
由上可知，本發明之封裝結構及其製法，主要藉由先形成導電柱於該介電層中，再形成該包覆層，故無須進行開孔製程，因而不僅可減少製程步驟而省時、降低製作成本，且能提昇封裝結構之可靠度、並能縮小該封裝結構之尺寸。此外，因無須進行開孔製程，故能減少進行結合/ 移除承載件之步驟次數；亦不須額外雷射製程，故能避免雷射所產生之熱影響區、需額外增加雷射對位設備、導電柱脫落(peeling)之問題，具備簡化製程及同時降低製作成本之功效。
1‧‧‧半導體封裝件
10a、20a‧‧‧第一承載件
100a、202a‧‧‧第一黏著層
10b、20b‧‧‧第二承載件
100b、202b‧‧‧第二黏著層
10c‧‧‧第三承載件
100c‧‧‧第三黏著層
11‧‧‧半導體元件
11a、24a‧‧‧主動面
11b、24b‧‧‧非主動面
110、240‧‧‧電極墊
12、25‧‧‧包覆層
12a‧‧‧第一表面
12b‧‧‧第二表面
121‧‧‧通孔
13‧‧‧第一線路重佈層
14‧‧‧第二線路重佈層
15、28、33‧‧‧導電元件
2、2’‧‧‧封裝結構
200a‧‧‧第一板體
201a‧‧‧第一離型層
200b‧‧‧第二板體
201b‧‧‧第二離型層
21‧‧‧金屬層
22‧‧‧介電層
221、271‧‧‧開口
222‧‧‧導電盲孔
23‧‧‧導電柱
231‧‧‧第一端
232‧‧‧第二端
24、32‧‧‧電子元件
26、31‧‧‧線路重佈層
27‧‧‧拒銲層
30‧‧‧封裝體
301‧‧‧第一表面
302‧‧‧第二表面
第1A至1F圖係為習知半導體封裝件之製法的剖面示意圖；第2A至2I圖係為本發明封裝結構之製法的剖面示意圖；其中，第2D’圖係為第2D圖之其他態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「第一」、「第二」及「表面」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2G圖係為本發明封裝結構2之製法的剖面示意圖。
如第2A圖所示，提供一第一承載件20a，該第一承載件20a具有係包括第一板體200a、第一離型層201a及第一黏著層202a。該第一板體200a可為半導體材、介電材、陶瓷材、玻璃或金屬材，但不限於此。
該第一離型層201a可為離型模，該第一黏著層202a可為膠材，且該第一離型層201a及該第一黏著層202a以塗佈或貼合方式分別依序形成於該第一板體200a上。
於該第一承載件20a之第一黏著層202a上形成金屬層21。該金屬層21可為銅，且以壓合(lamination)方式形成，以作為後續電鍍製程的導電路徑。
接著，於該金屬層21上形成圖案化之介電層22，該介電層22具有複數外露該金屬層21之開口221。該圖案化之介電層22係以曝光顯影方式形成，且該介電層22之材質可為感光型之聚苯噁唑(polybenzoxazole，PBO)。
如第2B圖所示，於該金屬層21之複數開口221中形成複數導電柱23，各該複數導電柱23具有相對之第一端231及第二端232。各該複數導電柱23可於圖案化之介電層22上以形成圖案化阻層(未圖式)及晶種層(未圖示)的電鍍製程來形成。
於本實施例中，各該複數導電柱23之第一端231係電性連接該金屬層21，而各該複數導電柱23之第二端232係凸出於該介電層22之表面，即各該複數導電柱23係立 設於該金屬層21上。
如第2C圖所示，設置至少一電子元件24於該介電層22上。該電子元件24具有相對之主動面24a及非主動面24b，該主動面24a結合於該介電層22，且該主動面24a上具有複數電極墊240。
接著，於介電層22上形成包覆層25，該包覆層25係包覆各該複數導電柱23、該電子元件24及該介電層22。該包覆層25可為封裝膠材，且其製程可選擇液態封膠(liquid compound)、噴塗(injection)、壓合(lamination)或模壓(compression molding)。
再者，該包覆層23係覆蓋該電子元件24之非主動面24b，及覆蓋各該複數導電柱23之第二端232。
如第2D圖所示，以如化學機械研磨(CMP)之研磨製程來移除部份該包覆層25，直到外露各該複數導電柱23之第二端232。於本實施例中，該電子元件24之非主動面24b上仍覆蓋有該包覆層25。
於另一實施例中，請參閱第2D’圖，可以研磨製程來移除部份該包覆層25，直到同時外露各該複數導電柱23之第二端232及該電子元件24之非主動面24b。
以下以接續第2D圖之製法繼續說明。接著，先設置第二承載件20b於該包覆層25上及結合各該複數導電柱23之第二端232後，再移除該第一承載件20a，如第2E圖所示。
於本實施例中，該第二承載件20b係包括第二板體 200b、第二離型層201b及第二黏著層202b。該第二板體200b、第二離型層201b及第二黏著層202b相同於前述第一板體200a、第一離型層201a及第一黏著層202a，於此不再贅述。
如第2F圖所示，形成線路重佈層26於該介電層22上。於一實施例中，係先移除該金屬層21後，以曝光顯影方式於該介電層22形成導電盲孔222，並以電鍍製程於該導電盲孔222及該介電層22上製作該線路重佈層26，並於介電層22上形成如綠漆之拒銲層27。
於另一實施例中，可先不移除該金屬層21，而形成該線路重佈層26的方式，則是於該金屬層21上先形成圖案化阻層(未圖示)後，再以蝕刻該金屬層21之方式來進行製作。接著，於該介電層22上形成如綠漆之拒銲層27。
上述之該拒銲層27形成有外露該線路重佈層26之開口271，以供植設如銲球之導電元件28。而該線路重佈層26係電性連接各該複數導電柱23之第一端231及該電子元件24之電極墊240。
如第2G圖所示，移除該第二承載件20b，並進行切單製程，以取得本發明之封裝結構2。
本發明之製法中，藉由先形成導電柱23於該介電層22之開口221中，再形成該包覆層25，使該導電柱23同時貫穿該介電層22及該包覆層25之上、下表面，故無需以雷射方式形成通孔之開孔製程，更不需進行雷射鑽孔對位、習知清洗通孔、於通孔中電鍍導電材等製程。因此， 本發明之製法不僅可減少製程步驟及降低製作成本，且能省略特殊製程及設備(如雷射對位之設備)，避免因通孔壁面凹凸不平所導致之導電柱脫落(peeling)之問題，故能提昇該封裝結構2之可靠度。
其次，因無須進行雷射鑽孔製程，故不會產生熱影響區(Heat Affact Zone)之問題，可避免電子元件24因雷射鑽孔所產生的高熱而被破壞。此外，更可依需求設計該導電柱23之位置，使該導電柱23與該電子元件24之距離可依需求縮短，而能縮小該封裝結構2之尺寸，達到產品符合微小化之需求。
再者，因無須進行開孔製程，因此只須二次進行結合/移除承載件(即該第一及第二承載件20a、20b)之步驟。本發明相較於習知技術，能有效減少結合/移除承載件知步驟次數，因而具備簡化製程及降低製作成本之功效。
本發明提供一種封裝結構2，係包括：介電層22、包覆層25、複數導電柱23、至少一電子元件24以及線路重佈層26。
該包覆層25係形成於該介電層22上，且該介電層22與該包覆層25構成一具有相對之第一表面301及第二表面302之封裝體30，其中，該第一表面301係該介電層22的外側面，該第二表面302係該包覆層25的外側面。
該複數導電柱23則豎埋於該包覆層25及該介電層22中。該複數導電柱23各具有相對之第一端231及第二端232，該第一端231係外露於該第一表面301，該第二端係 外露於該第二表面302。換言之，係以該第一端231及該第二端232分別貫穿該介電層22及該包覆層25之外側面。
該電子元件24係設於該介電層22上，並嵌埋於該包覆層25中，且該電子元件24具有相對之主動面24a及非主動面24b，並以該主動面24a結合於該介電層22，且該主動面24a上具有複數電極墊240。
於一實施例中，各該複數導電柱23之第一端231係齊平於該第一表面301，各該複數導電柱23之第二端232係齊平於該第二表面302。
該介電層22具有導電盲孔222，該線路重佈層26係形成於該封裝體30的第一表面301上及該導電盲孔222中，以電性連接各該複數導電柱23之第一端231及該電子元件24之主動面24a上的電極墊240。
於一實施例中，該封裝結構2復包括如綠漆之拒銲層27，係形成於該封裝體30的第一表面301上，並具有複數個外露該線路重佈層26之開口271，以供植設複數個如銲球之導電元件28，該複數導電元件28透過該線路重佈層26電性連接各該複數導電柱23及該電子元件24。
於本實施例中，該電子元件24之非主動面24b仍被包覆層25所覆蓋而未外露於該第二表面302。
於另一實施例中，該電子元件24之非主動面24b則外露於該第二表面302，以形成另一種態樣的封裝結構。
再於一實施例中，接續第2G圖，如第2H圖所示，取得本發明之封裝結構2後，可於封裝體30之第二表面302 上形成線路重佈層(redistribution layer，簡稱RDL)31，且該線路重佈層31係電性連接各該複數導電柱23之第二端232。接著，堆疊一電子元件32於該封裝體30之第二表面302上，並透過如銲錫凸塊、銅凸塊之導電元件33電性連接該線路重佈層31。其中，該電子元件32係為封裝體、晶片或基板等，並無特別限制。
再於另一實施例中，接續第2G圖，如第2I圖所示，取得本發明之封裝結構2後，可直接堆疊一電子元件32於該封裝體30之第二表面302上，並透過如銲錫凸塊、銅凸塊之導電元件33電性連接各該複數導電柱23之第二端232。
綜上所述，本發明之封裝結構及其製法，主要藉由先形成導電柱於該介電層中，再形成該包覆層，故無須進行開孔製程，因而不僅可減少製程步驟而省時、降低製作成本，且能提昇封裝結構之可靠度、並能縮小該封裝結構之尺寸。且因導電柱直接形成在介電層中，能夠有效降低應力，使本發明之封裝結構具備較佳的信賴性。
再者，因無須進行開孔製程，故能減少進行結合/移除承載件之步驟次數；亦不須額外雷射製程，故能避免雷射所產生之熱影響區、需額外增加雷射對位設備、導電柱脫落(peeling)之問題，具備簡化製程及同時降低製作成本之功效。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝結構
24‧‧‧電子元件
22‧‧‧介電層
25‧‧‧包覆層
23‧‧‧導電柱
26‧‧‧線路重佈層
231‧‧‧第一端
27‧‧‧拒銲層
232‧‧‧第二端
28‧‧‧導電元件
222‧‧‧導電盲孔
271‧‧‧開口
30‧‧‧封裝體
301‧‧‧第一表面
302‧‧‧第二表面

Claims (22)

  1. 一種封裝結構之製法，包括：提供具有金屬層之第一承載件；於該金屬層上形成圖案化之介電層，並於該介電層形成具有複數外露該金屬層之開口；於該複數開口中形成複數具有相對之第一端及第二端之導電柱，其中，各該複數導電柱以其第一端電性連接該金屬層，且各該複數導電柱之第二端凸出於該介電層之表面；設置至少一第一電子元件於該介電層上；形成包覆層於該介電層上，以令該包覆層包覆該複數導電柱、該第一電子元件及該介電層；移除部份該包覆層，以外露各該複數導電柱之第二端；以及移除該第一承載件。
  2. 如申請專利範圍第1項所述之封裝結構之製法，復包括於移除該第一承載件前，先設置第二承載件於該包覆層上，再移除該第一承載件。
  3. 如申請專利範圍第2項所述之封裝結構之製法，復包括移除該第一承載件後，先移除該金屬層，並形成第一線路重佈層於該介電層上，且該第一線路重佈層係電性連接各該複數導電柱之第一端及該第一電子元件。
  4. 如申請專利範圍第3項所述之封裝結構之製法，復包 括形成該第一線路重佈層後，移除該第二承載件。
  5. 如申請專利範圍第4項所述之封裝結構之製法，復包括移除該第二承載件後，形成第二線路重佈層於該包覆層上，該第二線路重佈層係電性連接各該複數導電柱之第二端。
  6. 如申請專利範圍第5項所述之封裝結構之製法，復包括堆疊一第二電子元件於該第二線路重佈層上，且該第二電子元件係電性連接該第二線路重佈層。
  7. 如申請專利範圍第4項所述之封裝結構之製法，復包括移除該第二承載件後，堆疊一第二電子元件於該包覆層上，該第二電子元件係電性連接各該複數導電柱之第二端。
  8. 如申請專利範圍第2項所述之封裝結構之製法，復包括移除該第一承載件後，對該金屬層以蝕刻方式製作線路重佈層，且該線路重佈層係電性連接各該複數導電柱之第一端及該電子元件。
  9. 如申請專利範圍第1項所述之封裝結構之製法，復包括於移除該第二承載件後進行切單製程。
  10. 如申請專利範圍第1項所述之封裝結構之製法，係以研磨方式移除部份該包覆層。
  11. 如申請專利範圍第1項所述之封裝結構之製法，其中，移除部份該包覆層之步驟並未使該電子元件外露於該包覆層。
  12. 如申請專利範圍第1項所述之封裝結構之製法，其中， 移除部份該包覆層之步驟除外露各該複數導電柱之第二端外，更外露該電子元件。
  13. 一種封裝結構，包括：介電層；包覆層，形成於該介電層上，供該介電層與包覆層構成一具有相對之第一表面和第二表面之封裝體，其中，該第一表面係該介電層之外側面，該第二表面係該包覆層之外側面；至少一第一電子元件，具有相對之主動面及非主動面，該第一電子元件係以該主動面設於該介電層上，並嵌埋於該包覆層中，以使該包覆層覆蓋該非主動面；以及複數導電柱，係豎埋於該包覆層及該介電層中，各該複數導電柱具有相對之第一端及第二端，且該第一端外露於該第一表面，該第二端外露於該第二表面。
  14. 如申請專利範圍第13項所述之封裝結構，其中，各該複數導電柱之第一端係齊平於該第一表面。
  15. 如申請專利範圍第13項所述之封裝結構，其中，各該複數導電柱之第二端係齊平於該第二表面。
  16. 如申請專利範圍第13項所述之封裝結構，復包括線路重佈層，係形成於該封裝體的第一表面上，並電性連接各該複數導電柱之第一端及該第一電子元件。
  17. 如申請專利範圍第16項所述之封裝結構，復包括複數導電元件，係形成於該線路重佈層上。
  18. 如申請專利範圍第13項所述之封裝結構，復包括線路重佈層，係形成於該封裝體的第二表面上，並電性連接各該複數導電柱之第二端。
  19. 如申請專利範圍第18項所述之封裝結構，復包括第二電子元件，係設於該線路重佈層上，且該第二電子元件係電性連接該線路重佈層。
  20. 如申請專利範圍第19項所述之封裝結構，其中，該第二電子元件係透過複數導電元件電性連接該線路重佈層。
  21. 如申請專利範圍第13項所述之封裝結構，復包括第二電子元件，係設於該包覆層上，且該第二電子元件係電性連接各該複數導電柱之第二端。
  22. 如申請專利範圍第21項所述之封裝結構，其中，該第二電子元件係透過複數導電元件電性連接各該複數導電柱之第二端。
TW103145895A 2014-12-27 2014-12-27 封裝結構及其製法 TWI559488B (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW103145895A TWI559488B (zh) 2014-12-27 2014-12-27 封裝結構及其製法
CN201510027102.7A CN105870023A (zh) 2014-12-27 2015-01-20 封装结构及其制法
US14/956,758 US9666536B2 (en) 2014-12-27 2015-12-02 Package structure and fabrication method thereof
US15/581,799 US20170236783A1 (en) 2014-12-27 2017-04-28 Package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103145895A TWI559488B (zh) 2014-12-27 2014-12-27 封裝結構及其製法

Publications (2)

Publication Number Publication Date
TW201624661A TW201624661A (zh) 2016-07-01
TWI559488B true TWI559488B (zh) 2016-11-21

Family

ID=56165105

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103145895A TWI559488B (zh) 2014-12-27 2014-12-27 封裝結構及其製法

Country Status (3)

Country Link
US (2) US9666536B2 (zh)
CN (1) CN105870023A (zh)
TW (1) TWI559488B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8884427B2 (en) * 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
TWI584430B (zh) * 2014-09-10 2017-05-21 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI552282B (zh) * 2014-11-03 2016-10-01 矽品精密工業股份有限公司 封裝結構及其製法
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
TWI612635B (zh) * 2016-08-22 2018-01-21 內埋式線路封裝之方法
US10325868B2 (en) * 2017-04-24 2019-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
KR102179165B1 (ko) * 2017-11-28 2020-11-16 삼성전자주식회사 캐리어 기판 및 상기 캐리어 기판을 이용한 반도체 패키지의 제조방법
CN109979890A (zh) * 2017-12-28 2019-07-05 凤凰先驱股份有限公司 电子封装件及其制法
CN108417982B (zh) * 2018-05-09 2024-03-08 盛合晶微半导体(江阴)有限公司 天线的封装结构及封装方法
TWI711095B (zh) * 2019-08-21 2020-11-21 欣興電子股份有限公司 封裝結構及其製備方法
CN111146093B (zh) * 2020-01-06 2021-08-24 亿芯微半导体科技(深圳)有限公司 一种半导体堆叠封装结构及其制备方法
CN111192863B (zh) * 2020-01-10 2021-07-13 广东汉岂工业技术研发有限公司 一种芯片堆叠封装结构及其制备方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201415586A (zh) * 2012-10-11 2014-04-16 Taiwan Semiconductor Mfg Co Ltd 封裝裝置及其製造方法
TW201419485A (zh) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg 半導體晶粒封裝與其形成方法
TW201426965A (zh) * 2012-12-28 2014-07-01 Taiwan Semiconductor Mfg 半導體晶粒封裝與封裝上封裝裝置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194436A (ja) * 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
SG149710A1 (en) * 2007-07-12 2009-02-27 Micron Technology Inc Interconnects for packaged semiconductor devices and methods for manufacturing such devices
US8039303B2 (en) * 2008-06-11 2011-10-18 Stats Chippac, Ltd. Method of forming stress relief layer between die and interconnect structure
US7993941B2 (en) * 2008-12-05 2011-08-09 Stats Chippac, Ltd. Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
US8937381B1 (en) * 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
TWI411075B (zh) * 2010-03-22 2013-10-01 Advanced Semiconductor Eng 半導體封裝件及其製造方法
CN102386104B (zh) * 2010-09-01 2014-11-12 群成科技股份有限公司 四边扁平无接脚封装方法
KR101711045B1 (ko) * 2010-12-02 2017-03-02 삼성전자 주식회사 적층 패키지 구조물
KR20150091932A (ko) * 2014-02-04 2015-08-12 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201415586A (zh) * 2012-10-11 2014-04-16 Taiwan Semiconductor Mfg Co Ltd 封裝裝置及其製造方法
TW201419485A (zh) * 2012-11-14 2014-05-16 Taiwan Semiconductor Mfg 半導體晶粒封裝與其形成方法
TW201426965A (zh) * 2012-12-28 2014-07-01 Taiwan Semiconductor Mfg 半導體晶粒封裝與封裝上封裝裝置

Also Published As

Publication number Publication date
US20160190099A1 (en) 2016-06-30
US9666536B2 (en) 2017-05-30
US20170236783A1 (en) 2017-08-17
CN105870023A (zh) 2016-08-17
TW201624661A (zh) 2016-07-01

Similar Documents

Publication Publication Date Title
TWI559488B (zh) 封裝結構及其製法
TWI656613B (zh) 晶片封裝結構及其製造方法
TWI548043B (zh) 封裝結構及其製法
US8766456B2 (en) Method of fabricating a semiconductor package
US9024422B2 (en) Package structure having embedded semiconductor component and fabrication method thereof
KR20130140643A (ko) 중합체성 충전재 트렌치를 갖는 반도체 칩 디바이스
US10522438B2 (en) Package structure having under ball release layer and manufacturing method thereof
TWI637467B (zh) 中介基材及其製作方法
US10109572B2 (en) Method for fabricating package structure
JP6418757B2 (ja) 配線基板及びその製造方法と半導体装置
US10129980B2 (en) Circuit board and electronic component device
TWI768874B (zh) 封裝結構及其製作方法
TWI662676B (zh) 具有內埋基板的線路載板及其製作方法與晶片封裝結構
TW202243148A (zh) 封裝結構及其製作方法
JP2008270443A (ja) 積層配線基板及びその製造方法
TWI548049B (zh) 半導體結構及其製法
TWI623984B (zh) 封裝結構及其製法
TW202029454A (zh) 封裝體及其封裝方法
TWI520238B (zh) 半導體封裝件及其製法
TWI776678B (zh) 半導體封裝件及其製造方法
KR100842916B1 (ko) 스택 패키지의 제조방법
TWI607676B (zh) 封裝基板及其電子封裝件與製法
TWI544846B (zh) 封裝載板及其製作方法
TW202324649A (zh) 電子封裝件及其製法
TW202414701A (zh) 封裝基板及其製法