TWI538070B - 半導體裝置及形成具有由聚合物層隔開的導電層和導電通路之扇出式晶圓級晶片尺寸封裝的方法 - Google Patents

半導體裝置及形成具有由聚合物層隔開的導電層和導電通路之扇出式晶圓級晶片尺寸封裝的方法 Download PDF

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TWI538070B
TWI538070B TW100127179A TW100127179A TWI538070B TW I538070 B TWI538070 B TW I538070B TW 100127179 A TW100127179 A TW 100127179A TW 100127179 A TW100127179 A TW 100127179A TW I538070 B TWI538070 B TW I538070B
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polymer layer
conductive
layer
semiconductor
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TW100127179A
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TW201216390A (en
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吳知勳
李植在
金振寬
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史達晶片有限公司
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Description

半導體裝置及形成具有由聚合物層隔開的導電層和導電通路之扇出式晶圓級晶片尺寸封裝的方法
本發明基本上係有關於半導體裝置，特別是關於一種半導體裝置以及形成具有由聚合物層(polymer layer)隔開的導電層和導電通路(conductive via)之扇出式晶圓級晶片尺寸封裝(fan-out wafer level chip scale package；Fo-WLCSP)的方法。
半導體裝置普遍存在於現代的電子產品之中。半導體裝置在電氣組件的數目及密度上有所不同。離散式半導體裝置一般而言包含一種電氣組件，例如，發光二極體(light emitting diode；LED)、小信號電晶體、電阻、電容、電感以及功率金氧半導體場效電晶體(MOSFET)。整合式半導體裝置則通常包含數百到數百萬個電氣組件。整合式半導體裝置之實例包含微控制器(microcontroller)、微處理器(microprocessor)、電荷耦合元件(charged-coupled device；CCD)、太陽能電池以及數位微型反射鏡元件(digital micro-mirror device；DMD)。
半導體裝置執行的功能範圍寬廣，諸如信號處理、高速計算、傳送及接收電磁信號、控制電子元件、將陽光轉換成電能、以及產生用於電視顯示的視覺投射。半導體裝置存在於娛樂、通信、電力轉換、網路、電腦、以及消費性產品等領域。半導體裝置亦存在於軍事應用、航空、汽車、工業控制、以及辦公室設備。
半導體裝置係利用半導體材料的電氣特性。半導體材料的原子結構使其可以藉由一電場或基極電流之施加或是透過摻雜處理而操縱其導電性。摻雜動作將雜質引入半導體材料以操縱及控制半導體裝置之導電性。
一半導體裝置包含主動式及被動式電氣結構。主動式結構，包含雙載子及場效電晶體，控制電流的流動。藉由改變摻雜以及電場或基極電流施用的程度，電晶體增進或限制其電流之流動。被動式結構，包含電阻、電容、及電感，在電壓及電流之間建立一執行各種電氣功能所需要的關係。被動式及主動式結構電性相連以形成電路，此使得半導體裝置能夠執行高速計算以及其他有用的功能。
半導體裝置的製造一般而言係採用二種複雜的製造程序，意即前端製造(front-end manufacturing)和後端製造(back-end manufacturing)，其各自均可能包含數百個步驟。前端製造包含在一半導體晶圓的表面上形成複數個晶粒。每一晶粒基本上均完全相同且包含由電性連接的主動及被動元件構成之電路。後端製造包含自完成的晶圓單一化(singulating)個別晶粒並封裝晶粒以提供結構上的支承以及環境隔離。
半導體產製的目的之一係產生較小型的半導體裝置。較小型的裝置基本上耗用較少之電力、具有較高之效能、且其生產更具效率性。此外，較小型的半導體裝置具有較小的佔用面積(footprint)，故能適合較小型之終端產品。一個較小的晶粒尺寸可以藉由改善前端製程而達成，以產生具有較小型、較高密度主動及被動元件之晶粒。後端製程可以藉由改善電性互連和封裝材料而產生具有較小佔用面積的半導體裝置封裝件。
圖1顯示一傳統型層疊封裝(package-on-package；PoP)式Fo-WLCSP 10，其具有半導體晶粒12疊置於半導體晶粒14之上並由封裝劑(encapsulant)16密封。一增生互連結構(interconnect structure)18形成於疊置的半導體晶粒12-14以及封裝劑16之上。半導體晶粒12及14利用接線20和22電性連接至互連結構18。半導體晶粒24被封裝劑26密封。一增生互連結構28形成於半導體晶粒24及封裝劑26之上。半導體晶粒24利用接線30電性連接至互連結構28。增生互連結構18利用形成於環繞半導體晶粒24及封裝劑26的一周圍上之凸塊32電性連接至增生互連結構28。
Fo-WLCSP 10的互連能力受限於形成於半導體晶粒24周圍的封裝劑26之高度需求。換言之，凸塊32必須形成充分之尺寸以延伸介於增生互連結構18與28之間的間隙。該間隙取決於封裝劑26之高度。因此，封裝劑26之高度限定凸塊配置選擇、凸塊間距、凸塊尺寸、以及輸入/輸出(I/O)數目。
其有必要提出一種在半導體晶粒周圍不使用封裝劑之Fo-WLCSP以減少凸塊間距及凸塊尺寸，並增加凸塊配置選擇及I/O數目。因此，在一實施例之中，本發明係一種製造一WLCSP的方法，其步驟包含提供一第一聚合物層，其包含形成於該第一聚合物層之內的複數個接觸墊、將該第一聚合物層接附至一載體、將一半導體晶粒配置至該第一聚合物層、形成一第二聚合物層於該半導體晶粒及第一聚合物層之上、形成穿過該第一及第二聚合物層的複數個第一導電通路、以及形成一第一導電層於該第二聚合物層之上。該第一導電層電性連接至該第一導電通路及半導體晶粒。該第一導電通路電性連接至該等接觸墊。該方法之步驟另外包含形成一第三聚合物層於該第二聚合物層及第一導電層之上、形成穿過該第三聚合物層之複數個第二導電通路、形成一第二導電層於該第三聚合物層之上、以及形成一第一互連結構於該第三聚合物層及第二導電層之上。該第二導電通路電性連接至該第一導電層。該第二導電層電性連接至該第二導電通路。
在另一實施例之中，本發明係一種製造一WLCSP的方法，其步驟包含提供一第一聚合物層，其包含形成於該第一聚合物層之內的複數個接觸墊、將該第一聚合物層接附至一載體、形成穿過該第一聚合物層的複數個第一導電通路、以及形成一第一導電層於該第一聚合物層之上。該第一導電通路電性連接至該接觸墊。該第一導電層電性連接至該第一導電通路。該方法之步驟另外包含形成一第二聚合物層於該第一聚合物層之上、將一半導體晶粒配置至該第二聚合物層、形成一第三聚合物層於該半導體晶粒及第二聚合物層之上、形成穿過該第二及第三聚合物層之複數個第二導電通路、以及形成一第二導電層於該第三聚合物層之上。該第二導電通路電性連接至該第一導電層。該第二導電層電性連接至該第二導電通路及半導體晶粒。該方法之步驟另外包含形成一第四聚合物層於該第三聚合物層及第二導電層之上、形成穿過該第四聚合物層之複數個第三導電通路、形成一第三導電層於該第四聚合物層之上、以及形成一第一互連結構於該第四聚合物層及第三導電層之上。該第三導電通路電性連接至該第二導電層。該第三導電層電性連接至該第三導電通路。
在另一實施例之中，本發明係一種製造一WLCSP的方法，其步驟包含提供一半導體晶粒、形成一第一聚合物層於該半導體晶粒周圍、形成穿過該第一聚合物層的複數個第一導電通路、形成一第一互連結構於電性連接至該第一導電通路之該第一聚合物層之一第一表面上、以及形成一第二互連結構於該第一聚合物層的該第一表面對面之一第二表面上。該第二互連結構電性連接至該第一導電通路。
在另一實施例之中，本發明係一種WLCSP，包含一半導體晶粒以及形成於該半導體晶粒周圍之第一聚合物層以及第二聚合物層。複數個第一導電通路穿過該第一聚合物層而形成。一第一互連結構形成於電性連接至該第一導電通路之該第一聚合物層之一第一表面上。一第二互連結構形成於該第一聚合物層的該第一表面對面之一第二表面上。該第二互連結構電性連接至該第一導電通路。
以下參照圖式之說明描述本發明於一或多個實施例之中，其中類似的編號代表相同或類似的構件。雖然其透過達成本發明目的之最佳模式進行本發明之說明，但熟習相關技術者應能了解，本發明涵蓋界定於所附申請專利範圍中的發明之精神和範疇所包含的替代、修改、以及等效結構，以及以下揭示及圖式所支持的等效結構。
一般而言其使用二種複雜的製造程序製造半導體裝置：前端製造和後端製造。前端製造包含在一半導體晶圓的表面上形成複數個晶粒。晶圓上的每一晶粒均包含主動及被動電氣元件，彼此電性連接以形成功能性的電路。諸如電晶體和二極體的主動電氣元件具有控制電流流動之能力。諸如電容、電感、電阻、及變壓器的被動電氣元件在電壓及電流之間建立一執行電路之功能所需要的關係。
藉由一系列製程步驟，包括摻雜、沉積、光學微影術(photolithography)、蝕刻、以及平整化(planarization)，被動及主動元件形成於半導體晶圓的表面上。摻雜係藉由諸如離子植入(ion implantation)或熱擴散(thermal diffusion)之技術將雜質引入半導體材料之中。摻雜製程修改主動元件中半導體材料之導電性，將半導體材料轉變成一絕緣體或導體，或是依據一電場或基極電流動態地改變半導體材料之導電性。電晶體包含依據需要配置的不同種類及摻雜程度之區域，使得電晶體能夠隨電場或基極電流之施加而增進或限制電流的流動。
主動及被動元件係由具有不同電氣特性的材料疊層所形成。該等疊層可以藉由各種沉積技術形成，該等沉積技術在某種程度上係隨著被沉積的材料種類而決定。舉例而言，薄膜沉積可以包含化學氣相沉積(chemical vapor deposition；CVD)、物理氣相沉積(physical vapor deposition；PVD)、電解式電鍍(electrolytic plating)、以及無電式電鍍(electroless plating)製程。每一疊層通常被圖案化以形成主動元件、被動元件、或介於元件間的電性連接的部分。
其可以利用光學微影術圖案化該等疊層，光學微影術包含將諸如光阻(photoresist)之感光材料沉積於待圖案化的疊層之上。其利用光將圖案自一光罩(photomask)轉移至光阻。受光的光阻圖案的部分被以一溶劑移除，而暴露出下層待圖案化的部分。殘餘的光阻被移除，而留下一圖案化之疊層。或者，某些種類材料之圖案化係藉由直接將材料沉積至一利用諸如無電式或電解式電鍍技術之先前沉積/蝕刻製程所形成的區域或空位之中。
沉積一材料之薄膜於一現有圖案之上可以擴大其下的圖案而產生一不均勻的平坦表面。其需要均勻的平坦表面以產生更小型且更密集的主動及被動元件。其可以使用平整化動作以自晶圓之表面移除材料而產生一均勻的平坦表面。平整化包含以一拋光墊磨光晶圓之表面。拋光期間一磨蝕材料及腐蝕性化學藥品被加至晶圓之表面。磨蝕的機械動作與化學藥品的腐蝕作用之結合移除任何不規則的表面形態，從而產生一均勻的平坦表面。
後端製造係指將完成的晶圓切割或單一化成個別的晶粒，而後封裝晶粒以得到結構上的支承以及環境隔離。針對晶粒之單一化，晶圓被沿著晶圓上稱為鋸割分隔道(saw street)或劃線區的非功能性區域刻線並分割。其利用一雷射切割工具或鋸片單一化晶圓。單一化之後，個別的晶粒被配置至一封裝基板，其包含接腳或接觸墊以連接其他系統組件。形成於半導體晶粒上的接觸墊接著被連接至封裝內的接觸墊。電性連接可以是由銲錫凸塊、凸柱凸塊(stud bump)、導電膠(conductive paste)、或打線接合(wirebond)製成。一封裝劑或其他模封材料沉積於封裝之上以提供實體支承以及電性絕緣。完成之封裝而後被***一電氣系統，而該半導體裝置之功能即提供給其他系統組件。
圖2例示電子裝置50，具有一晶片載體基板或印刷電路板(PCB)52，複數個半導體封裝件安置其表面之上。電子裝置50可以具有一種半導體封裝件，或者多種半導體封裝件，取決於應用。不同種類的半導體封裝件顯示於圖2之中以供例示之用。
電子裝置50可以是一使用半導體封裝件以執行一或多個電氣功能的獨立系統。或者，電子裝置50可以是一更大系統中之一子組件。舉例而言，電子裝置50可以是一行動電話、個人數位助理(PDA)、數位視訊攝影機(DVC)、或其他電子通信裝置的一部分。或者，電子裝置50可以是一繪圖卡、網路介面卡、或其他可以***一電腦中的信號處理卡。半導體封裝件可以包含微處理器、記憶體、特定用途積體電路(ASIC)、邏輯電路、類比電路、RF電路、離散元件、或其他半導體晶粒或電氣組件。微型化及重量縮減係此等產品被市場接受的關鍵。半導體元件之間的距離必須減少以達成更高之密度。
在圖2之中，PCB 52針對安置於PCB上的半導體封裝件的結構支承及電性互連提供一公共基板。導電信號走線54利用蒸鍍(evaporation)、電解式電鍍、無電式電鍍、網印(screen printing)、或其他適當之金屬沉積製程形成於PCB 52的一表面上或疊層內部。信號走線54提供每一半導體封裝件、載置組件、及其他外部系統組件之間的電性通連。走線54同時亦提供電源及接地連接給每一半導體封裝件。
在一些實施例之中，一半導體裝置具有二種封裝層級。第一層級封裝係一種用以將半導體晶粒機械式地且電氣式地接附至一中介載體的技術。第二層級封裝包含將中介載體機械式及電氣式地接附至PCB。在其他的實施例之中，一半導體裝置可以僅具有第一層級封裝，其中晶粒直接機械式及電氣式地安置至PCB。
基於例示之目的，PCB 52上顯示數種第一層級封裝，包含焊線封裝(bond wire package)56以及覆晶(flipchip)58。此外，其顯示PCB 52上亦安置數種第二層級封裝，包含球柵陣列(ball grid array；BGA)60、凸塊晶片載體(bump chip carrier；BCC)62、雙排型封裝(dual in-line package；DIP)64、基板柵格陣列(land grid array；LGA)66、多晶片模組(multi-chip module；MCM)68、四側無引腳扁平封裝(quad flat non-leaded package；QFN)70、以及四面扁平封裝(quad flat package)72。取決於系統需求，半導體封裝的任何組合，配合第一及第二層級封裝型式的任何組合，以及其他電子組件，均可以連接至PCB 52。在一些實施例之中，電子裝置50包含一單一安裝半導體封裝件，而其他實施例則需要多個互連之封裝件。藉由結合一或多個半導體封裝件於單一基板上，製造商可以將預製組件納入電子裝置及系統之中。由於半導體封裝件包含複雜的功能，故其可以利用較便宜的組件以及一效率化製造流程生產電子裝置。產生之裝置較不易故障且製造費用較低，而對消費者提供一較低之成本。
圖3a至3c顯示示範性半導體封裝。圖3a例示安置於PCB 52上的DIP 64的進一步細節。半導體晶粒74包含一作用區，包含實施成主動元件、被動元件、導電層、以及介電層的類比或數位電路，形成於晶粒之內並依據晶粒的電氣設計電性互連。舉例而言，該電路可以包含一或多個電晶體、二極體、電感、電容、電阻、以及其他電路構件形成於半導體晶粒74的作用區之內。接觸墊76係一或多層導電材料，諸如鋁(Al)、銅(Cu)、錫(Sn)、鎳(Ni)、金(Au)、或銀(Ag)，且電性連接至形成於半導體晶粒74內的電路構件。在DIP 64的組裝期間，其利用一金矽共熔層或諸如熱環氧樹脂(thermal epoxy)或環氧樹脂(epoxy resin)之黏著材料將半導體晶粒74配置至一中介載體78。封裝件主體包含一諸如聚合物或陶瓷之絕緣封裝材料。導線80及接線82提供介於半導體晶粒74與PCB 52之間的電性互連。針對環境之防護，封裝劑84沉積於封裝上以防止溼氣及微粒進入封裝之內汙染半導體晶粒74或接線82。
圖3b例示安置於PCB 52上的BCC 62的進一步細節。半導體晶粒88利用一底部填充或環氧樹脂黏著材料92配置於載體90之上。接線94提供介於接觸墊96與98之間的第一層級封裝互連。模封材料或封裝劑100沉積於半導體晶粒88和接線94之上以提供裝置的實體支承及電性絕緣。接觸墊102利用諸如電解式電鍍或無電式電鍍之一適當之金屬沉積製程形成於PCB 52之一表面上以防止氧化。接觸墊102電性連接至PCB 52中的一或多條導電信號走線54。凸塊104形成於BCC 62的接觸墊98與PCB 52的接觸墊102之間。
在圖3c之中，半導體晶粒58以一覆晶形式第一層級封裝面朝下地配置至中介載體106。半導體晶粒58之作用區108包含依據晶粒的電氣設計形成而實施成主動元件、被動元件、導電層、以及介電層的類比或數位電路。例如，該電路可以包含一或多個電晶體、二極體、電感、電容、電阻、以及作用區108內的其他電路構件。半導體晶粒58透過凸塊110電性且機械性地連接至載體106。
BGA 60利用凸塊112以一BGA型態第二層級封裝電性且機械性地連接至PCB 52。半導體晶粒58透過凸塊 110、信號線114、及凸塊112電性連接至PCB 52中的導電信號走線54。一模封材料或封裝劑116沉積於半導體晶粒58和載體106之上以提供裝置的實體支承及電性絕緣。該覆晶式半導體裝置提供一條短短的導電路徑，從半導體晶粒58上的主動元件到PCB 52上的導電軌線，以縮減信號傳播距離、降低電容、並增進整體電路效能。在另一實施例之中，半導體晶粒58可以利用覆晶型態之第一層級封裝不藉由中介載體106而機械性及電性地直接連接至PCB 52。
圖4a顯示一半導體晶圓120，其具有一用於結構支承的基座基板材料122，諸如矽、鍺、砷化鎵、磷化銦、或碳化矽。複數個半導體晶粒或元件124形成於晶圓120之上，被如前所述的鋸割分隔道126隔開。
圖4b顯示一部分半導體晶圓120之一剖面視圖。每一半導體晶粒124均具有一作用表面130，包含實施成主動元件、被動元件、導電層、以及介電層的類比或數位電路，形成於晶粒之內並依據晶粒的電氣設計和功能電性互連。例如，該電路可以包含一或多個電晶體、二極體、以及形成於作用表面130內的其他電路構件以實施類比電路或數位電路，諸如數位信號處理器(DSP)、ASIC、記憶體、或其他信號處理電路。半導體晶粒124同時亦可以包含用於RF信號處理的整合式被動元件(IPD)，諸如電感、電容、和電阻。在一實施例之中，半導體晶粒124係一覆晶型態之半導體晶粒。
一導電層132利用PVD、CVD、電解式電鍍、無電式 電鍍製程、或其他適當之金屬沉積製程形成於作用表面130之上。導電層132可以是一或多層鋁、銅、錫、鎳、金、銀、或其他適當之導電材料。導電層132係做為電性連接至作用表面130上之電路的接觸墊。
在圖4c之中，其利用一鋸片或雷射切割工具136穿透鋸割分隔道126將半導體晶圓120單一化成個別的半導體晶粒124。
與圖2及圖3a至3c相關，圖5a至圖5m例示一形成具有由聚合物層隔開的導電層和導電通路之一Fo-WLCSP的製程。在圖5a之中，一基板或載體140包含暫時或犧牲基座材料，諸如矽、聚合物、氧化鈹(beryllium oxide)、或其他用於結構支承的適當的低成本、堅硬材料。在一實施例之中，載體140係一膠帶(tape)。
一聚合物層142形成於載體140之上。聚合物層142可以是一種氧化物、氮化物、或玻璃材料。一電性傳導層144利用一諸如PVD、CVD、濺鍍(sputtering)、電解式電鍍、以及無電式電鍍的圖案化及金屬沉積製程形成於聚合物層142之內。導電層144可以是一或多層鋁、銅、錫、鎳、金、銀、或其他適當之導電材料。
一暫時性基板或載體146包含犧牲基座材料，諸如矽、聚合物、聚合物複合材料、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、或其他用於結構支承的適當的低成本、堅硬材料。一介面層或雙面膠帶148形成於載體146之上，做為一暫時黏著接合膜或蝕刻終止層(etch-stop layer)。
在圖5b之中，透過聚合物層142及接觸墊144，載體140配置至載體146上的介面層148。在一實施例之中，聚合物層142被壓合至介面層148。導電層144係做為一接觸墊之陣列，形成於環繞晶粒附著區域149之一周圍上。聚合物層142及接觸墊144構成一互連結構。
在圖5c之中，其藉由在箭頭150方向上之機械式削除，將載體140自聚合物層142移除。聚合物層142及接觸墊144維持貼附至介面層148及載體146。或者，載體140之移除可以是藉由化學蝕刻、CMP、機械式研磨、熱烘烤、紫外光、雷射掃描、或濕式剝除，以暴露出聚合物層142。
在圖5d之中，其將圖4a至4c的半導體晶粒124配置至聚合物層142，利用一取放(pick and place)動作使得作用表面130面朝遠離聚合物層之方向。半導體晶粒124被放置於接觸墊144之陣列內的晶粒附著區域149之上。
在圖5e之中，一聚合物層154形成於半導體晶粒124和聚合物層142之上。聚合物層154可以是一種氧化物、氮化物、或玻璃材料。其可以藉由一蝕刻製程移除一部分聚合物層154而暴露作為接觸墊的導電層132以供後續之電性互連。
在圖5f之中，其利用機械式鑽孔、雷射鑽孔、或深反應離子蝕刻(deep reactive ion etching；DRIE)穿過聚合物層154及142而形成複數個通路156向下延伸至接觸墊144。在圖5g之中，通路156利用電解式電鍍、無電式電鍍製程或其他適當之金屬沉積製程被填充以鋁、銅、錫、鎳、金、 銀、鈦、鎢(W)、多晶矽(poly-silicon)或其他適當之導電材料，以形成z方向導電柱或通路158。導電通路158電性連接至接觸墊144。
圖5h顯示沿圖5g之線條5h-5h所取之導電通路158之一上視圖，其穿過聚合物層154形成於環繞半導體晶粒124之一周圍處。
一電性傳導層或重分佈層(redistribution layer；RDL)160利用一諸如印刷、PVD、CVD、濺鍍、電解式電鍍及無電式電鍍之圖案化和金屬沉積製程形成於聚合物層154及導電通路158之上。導電層160可以是一或多層鋁、銅、錫、鎳、金、銀或其他適當之導電材料。一部分導電層160電性連接至作為接觸墊的導電層132及至導電通路158。其他部分之導電層160可以是電性相通或電性絕緣，取決於半導體晶粒124之設計及功能。
在圖5i之中，一聚合物層162形成於聚合物層154和導電層160之上。聚合物層162可以是一種氧化物、氮化物、或玻璃材料。其利用機械式鑽孔、雷射鑽孔或DRIE穿過聚合物層162形成複數個通路164向下延伸至導電層160，如圖5j所示。在圖5k之中，通路164利用電解式電鍍、無電式電鍍製程、或其他適當之金屬沉積製程被填充以鋁、銅、錫、鎳、金、銀、鈦、鎢、多晶矽或其他適當之導電材料，以形成z方向導電柱或通路166。導電通路166電性連接至導電層160。
一電性傳導層或RDL 168利用一諸如印刷、PVD、 CVD、濺鍍、電解式電鍍、及無電式電鍍之圖案化和金屬沉積製程形成於聚合物層162及導電通路166之上。導電層168可以是一或多層鋁、銅、錫、鎳、金、銀、或其他適當之導電材料。一部分導電層168電性連接至導電通路166。其他部分之導電層168可以是電性相通或電性絕緣，取決於半導體晶粒124之設計及功能。
在圖51之中，一選擇性凸塊底層金屬(under bump metallization；UBM)177形成於導電層168之上。一阻焊層(solder resist layer)170形成於聚合物層162、導電層168、及UBM 177之上。其藉由一蝕刻製程移除一部分阻焊層170以暴露導電層168或UBM 177以供凸塊形成或額外的封裝互連。或者，一絕緣或鈍化層(passivation layer)利用PVD、CVD、印刷、旋轉塗佈(spin coating)、噴霧塗佈(spray coating)、燒結(sintering)或熱氧化(thermal oxidation)形成於聚合物層162、導電層168和UBM 177之上。該絕緣層包含一或多層二氧化矽(SiO2)、氮化矽(Si3N4)、氮氧化矽(SiON)、五氧化鉭(Ta2O5)、氧化鋁(Al2O3)、或是具有類似絕緣及結構特性的其他材料。聚合物層162、導電通路166、導電層168、UBM 177以及光阻層170構成一互連結構。
在圖5m之中，半導體晶粒124利用鋸片或雷射切割工具174被單一化成個別的Fo-WLCSP 172。圖6a顯示單一化之後的Fo-WLCSP 172之一剖面視圖。其藉由化學蝕刻、機械式削除、CMP、機械式研磨、熱烘烤、紫外光、雷射掃描、或濕式剝除，移除暫時載體146和介面層148，以 暴露出接觸墊144。
一電性導電凸塊材料利用一蒸鍍、電解式電鍍、無電式電鍍、球滴法(ball drop)、或網印製程沉積於UBM 177之上。該凸塊材料可以是鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫、及其組合，並具有一選擇性的助焊劑。舉例而言，該凸塊材料可以是共熔錫/鉛、高鉛焊錫、或無鉛焊錫。該凸塊材料利用一適當之接附方式或黏合製程接合至UBM 177。在一實施例之中，該凸塊材料藉由將材料加熱至其熔點以上以形成球塊或凸塊176而被回流。在一些應用之中，凸塊176被回流第二次以增進對UBM 177的電性接觸。該等凸塊亦可以被壓接(compression bonded)至UBM 177。凸塊176代表一種可以形成於UBM 177之上的互連結構。
在Fo-WLCSP 172之中，半導體晶粒124透過導電層160及168以及導電通路158和166電性連接至凸塊176和接觸墊144以供外部電性互連。接觸墊144及凸塊176之陣列係形成於環繞半導體晶粒124之一周圍上。圖6b顯示具有接觸墊144之陣列的Fo-WLCSP 172之一上視圖。Fo-WLCSP 172之形成並未透過封裝劑或模封材料，如圖1所述。而是聚合物層142、154、及162形成於半導體晶粒124、導電層160及168、導電通路158及166、以及接觸墊144周圍，以提供電性絕緣及結構上的支承。其可以是以比先前技術中之封裝劑更低之高度形成聚合物層142、154、及162。因此，聚合物層142、154、及162提供彈性的凸塊配置選擇、縮減之凸塊間距、增加之I/O數目、以及 降低Fo-WLCSP 172之高度。
Fo-WLCSP 172適用於層疊封裝(PoP)之應用，諸如圖7所示，其中Fo-WLCSP 178疊置於Fo-WLCSP 172之上。Fo-WLCSP 178之組構類似Fo-WLCSP 172。Fo-WLCSP 172與Fo-WLCSP 178之間的電氣信號繞接穿過形成於環繞半導體晶粒124周圍之凸塊176之陣列。由於並無使用金質接線以供Fo-WLCSP之間的信號傳輸，故其互連電感及電容得以縮減且信號正確性得以增進。其可以藉由匹配介於半導體晶粒124與導電層160及168、導電通路158及166、和形成於聚合物層142、154、及162中的接觸墊144之間的阻抗，而降低反射雜訊及干擾。
與圖2及圖3a至3c相關，圖8a至圖8r例示形成具有由聚合物層隔開的導電層和導電通路之一Fo-WLCSP的另一製程。在圖8a之中，一基板或載體180包含暫時或犧牲基座材料，諸如矽、聚合物、氧化鈹、或其他用於結構支承的適當的低成本、堅硬材料。在一實施例之中，載體180係一膠帶。
一聚合物層182形成於載體180之上。聚合物層182可以是一種氧化物、氮化物、或玻璃材料。一電性傳導層184利用一諸如濺鍍、電解式電鍍以及無電式電鍍的圖案化及金屬沉積製程形成於聚合物層182之內。導電層184可以是一或多層鋁、銅、錫、鎳、金、銀或其他適當之導電材料。
一暫時性基板或載體186包含犧牲基座材料，諸如矽、 聚合物、聚合物複合材料、金屬、陶瓷、玻璃、玻璃環氧樹脂、氧化鈹、或其他用於結構支承的適當的低成本、堅硬材料。一介面層或雙面膠帶188形成於載體186之上，做為一暫時黏著接合膜或蝕刻終止層。
在圖8b之中，透過聚合物層182及接觸墊184，載體180被配置至載體186上的介面層188。在一實施例之中，聚合物層182被壓合至介面層188。導電層184係做為一接觸墊之陣列，均勻配置於聚合物層182之大致一整個表面區域之上。
在圖8c之中，其藉由在箭頭190方向上之機械式削除，將載體180自聚合物層182移除。聚合物層182及接觸墊184維持貼附至介面層188及載體186。或者，載體180之移除可以是藉由化學蝕刻、CMP、機械式研磨、熱烘烤、紫外光、雷射掃描、或濕式剝除，以暴露出聚合物層182。
圖8d顯示載體180移除之後的聚合物層182。其利用機械式鑽孔、雷射鑽孔、或DRIE穿過聚合物層182形成複數個通路196向下延伸至接觸墊184，如圖8e所示。在圖8f之中，通路196利用電解式電鍍、無電式電鍍製程、或其他適當之金屬沉積製程被填充以鋁、銅、錫、鎳、金、銀、鈦、鎢、多晶矽、或其他適當之導電材料，而形成z方向導電柱或通路198。導電通路198電性連接至接觸墊184。圖8g顯示沿圖8f之線條8g-8g所取之形成於接觸墊184之上的導電通路198之一上視圖。
一電性傳導層或RDL 200利用一諸如印刷、PVD、 CVD、濺鍍、電解式電鍍、及無電式電鍍之圖案化和金屬沉積製程形成於聚合物層182及導電通路198之上。導電層200可以是一或多層鋁、銅、錫、鎳、金、銀、或其他適當之導電材料。一部分導電層200電性連接至導電通路198。其他部分之導電層200可以是電性相通或電性絕緣，取決於半導體晶粒124之設計及功能。
在圖8h之中，一聚合物層202形成於聚合物層182和導電層200之上。聚合物層202可以是一種氧化物、氮化物、或玻璃材料。聚合物層182及202、導電通路198、以及導電層200構成一互連結構。
在圖8i之中，其將圖4a至4c的半導體晶粒124配置至聚合物層202，利用一取放動作使得作用表面130面朝遠離聚合物層之方向。
在圖8j之中，一聚合物層204形成於半導體晶粒124和聚合物層202之上。聚合物層204可以是一種氧化物、氮化物、或玻璃材料。其可以藉由一蝕刻製程移除一部分聚合物層204而暴露半導體晶粒124之作為接觸墊的導電層132以供後續之電性互連。
在圖8k之中，其利用機械式鑽孔、雷射鑽孔、或DRIE穿過聚合物層204及202形成複數個通路206向下延伸至導電層200。通路206係形成於環繞半導體晶粒124之一周圍上。在圖81之中，通路206利用電解式電鍍、無電式電鍍製程、或其他適當之金屬沉積製程被填充以鋁、銅、錫、鎳、金、銀、鈦、鎢、多晶矽、或其他適當之導電材料， 以形成z方向導電柱或通路208。導電通路208電性連接至導電層200。
圖8m顯示沿圖81之線條8m-8m所取之形成於半導體晶粒124周圍的導電通路208之一上視圖。
一電性傳導層或重分佈層(RDL)210利用一諸如印刷、PVD、CVD、濺鍍、電解式電鍍、及無電式電鍍之圖案化和金屬沉積製程形成於聚合物層204及導電通路208之上。導電層210可以是一或多層鋁、銅、錫、鎳、金、銀、或其他適當之導電材料。一部分導電層210電性連接至作為接觸墊的導電層132及至導電通路208。其他部分之導電層210可以是電性相通或電性絕緣，取決於半導體晶粒124之設計及功能。
在圖8n之中，一聚合物層212形成於聚合物層204和導電層210之上。聚合物層212可以是一種氧化物、氮化物、或玻璃材料。其利用機械式鑽孔、雷射鑽孔、或DRIE穿過聚合物層212形成複數個通路214向下延伸至導電層210，如圖8o所示。
在圖8p之中，通路214利用電解式電鍍、無電式電鍍製程、或其他適當之金屬沉積製程被填充以鋁、銅、錫、鎳、金、銀、鈦、鎢、多晶矽、或其他適當之導電材料，以形成z方向導電柱或通路216。導電通路216電性連接至導電層210。
一電性傳導層或RDL 218利用一諸如印刷、PVD、CVD、濺鍍、電解式電鍍、及無電式電鍍之圖案化和金屬 沉積製程形成於聚合物層212及導電通路216之上。導電層218可以是一或多層鋁、銅、錫、鎳、金、銀、或其他適當之導電材料。一部分導電層218電性連接至導電通路216。其他部分之導電層218可以是電性相通或電性絕緣，取決於半導體晶粒124之設計及功能。
在圖8q之中，一選擇性UBM 228形成於導電層218之上。一阻焊層220形成於聚合物層212、導電層218、及UBM 228之上。其藉由一蝕刻製程移除一部分阻焊層220以暴露導電層218或UBM 228以供凸塊形成或額外的封裝互連。或者，一絕緣或鈍化層利用PVD、CVD、印刷、旋轉塗佈、噴霧塗佈、燒結或熱氧化形成於聚合物層212、導電層218、和UBM228之上。該絕緣層包含一或多層SiO2、Si3N4、SiON、Ta2O5、Al2O3、或是具有類似絕緣及結構特性的其他材料。聚合物層212、導電通路216、導電層218、UBM 228、以及光阻層220構成一互連結構。
在圖8r之中，半導體晶粒124利用鋸片或雷射切割工具224被單一化成個別的Fo-WLCSP 222。圖9顯示單一化之後的Fo-WLCSP 222之一剖面視圖。其藉由化學蝕刻、機械式削除、CMP、機械式研磨、熱烘烤、紫外光、雷射掃描、或濕式剝除，移除暫時載體186和介面層188，以暴露出接觸墊184。
一電性導電凸塊材料利用一蒸鍍、電解式電鍍、無電式電鍍、球滴法、或網印製程沉積於UBM 228之上。該凸塊材料可以是鋁、錫、鎳、金、銀、鉛、鉍、銅、焊錫、 及其組合，並具有一選擇性的助焊劑。舉例而言，該凸塊材料可以是共熔錫/鉛、高鉛焊錫、或無鉛焊錫。該凸塊材料利用一適當之接附方式或黏合製程接合至UBM 228。在一實施例之中，該凸塊材料藉由將材料加熱至其熔點以上以形成球塊或凸塊226而被回流。在一些應用之中，凸塊226被回流第二次以增進對UBM 228的電性接觸。該等凸塊亦可以被壓接至UBM 228。凸塊226代表一種可以形成於UBM 228之上的互連結構。
在Fo-WLCSP 222之中，半導體晶粒124透過導電層200、210及218以及導電通路198、208、及216電性連接至凸塊226和接觸墊184以供外部電性互連。接觸墊184及凸塊226之陣列係形成於Fo-WLCSP 222的整個表面區域上。Fo-WLCSP 222之形成並未透過封裝劑或模封材料，如圖1所述。而是聚合物層182、202、204、及212形成於半導體晶粒124、導電層200、210、及218、導電通路198、208、及216、以及接觸墊184周圍，以提供電性絕緣及結構上的支承。其可以是以比先前技術中之封裝劑更低之高度形成聚合物層182、202、204、及212。因此，聚合物層182、202、204、及212提供彈性的凸塊配置選擇、縮減之凸塊間距、增加之I/O數目、以及降低Fo-WLCSP 222之高度。
Fo-WLCSP 222適用於PoP之應用，如圖10a所示，其中Fo-WLCSP 230疊置於Fo-WLCSP 222之上。在Fo-WLCSP 230之中，半導體晶粒231利用晶粒接附黏著劑234被配置 至半導體晶粒232。半導體晶粒231及232各自均具有一作用表面，包含實施成主動元件、被動元件、導電層、以及介電層的類比或數位電路，形成於晶粒之內並依據晶粒的電氣設計和功能電性互連。例如，該電路可以包含一或多個電晶體、二極體、以及形成於作用表面內的其他電路構件以實施類比電路或數位電路，諸如DSP、ASIC、記憶體、或其他信號處理電路。半導體晶粒231及232同時亦可以包含用於RF信號處理的IPD，諸如電感、電容、和電阻。接線236及238分別電性連接至半導體晶粒231及232上的接觸墊。一封裝劑240沉積於半導體晶粒231和232以及接線236和238之上。一增生互連結構242形成於半導體晶粒232及封裝劑240之上。半導體晶粒232以晶粒接附黏著劑235接合至互連結構242。接線236及238透過互連結構242電性連接至凸塊244，其又電性連接至Fo-WLCSP 222之接觸墊184。半導體晶粒231及232、封裝劑240、以及互連結構242構成一半導體封裝。圖10b顯示取自圖10a線條中之10b-10b的接觸墊184和聚合物層182之一剖面視圖。
Fo-WLCSP 222與Fo-WLCSP 230之間的電氣信號繞接穿過接觸墊184及凸塊244之陣列。由於並無使用金質接線以供Fo-WLCSP之間的信號傳輸，故其互連電感及電容得以縮減且信號正確性得以增進。其可以藉由匹配介於半導體晶粒124與導電層200、210、及218、導電通路198、208、及216、和形成於聚合物層182、202、204、及212 中的接觸墊184之間的阻抗，而降低反射雜訊及干擾。
圖11a顯示具有Fo-WLCSP 248疊置於Fo-WLCSP 250上的另一PoP組態，類似圖6a。在Fo-WLCSP 248之中，半導體晶粒252利用晶粒接附黏著劑256被配置至半導體晶粒254。半導體晶粒252及254各自均具有一作用表面，包含實施成主動元件、被動元件、導電層、以及介電層的類比或數位電路，形成於晶粒之內並依據晶粒的電氣設計和功能電性互連。例如，該電路可以包含一或多個電晶體、二極體、以及形成於作用表面內的其他電路構件以實施類比電路或數位電路，諸如DSP、ASIC、記憶體、或其他信號處理電路。半導體晶粒252及254同時亦可以包含用於RF信號處理的IPD，諸如電感、電容、和電阻。接線260及262分別電性連接至半導體晶粒252及254上的接觸墊。一封裝劑264沉積於半導體晶粒252和254以及接線260和262之上。一增生互連結構266形成於半導體晶粒252及254以及封裝劑264之上。半導體晶粒254以晶粒接附黏著劑258接合至互連結構266。接線260及262透過互連結構266電性連接至凸塊268，其又電性連接至Fo-WLCSP 250之接觸墊144。半導體晶粒252及254、封裝劑264、以及互連結構266構成一半導體封裝件。圖11b顯示取自圖11a中之線條11b-11b的接觸墊144和聚合物層142之一剖面視圖。
Fo-WLCSP 248與Fo-WLCSP 250之間的電氣信號繞接穿過接觸墊144及凸塊268之陣列。由於並無使用金質接 線以供Fo-WLCSP之間的信號傳輸，故其互連電感及電容得以縮減且信號正確性得以增進。其可以藉由匹配介於半導體晶粒124與導電層160及168、導電通路158及166、和形成於聚合物層142、154、及162中的接觸墊144之間的阻抗，而降低反射雜訊及干擾。
雖然以上已詳細例示一或多個本發明之實施例，但熟習相關技術者應能理解，其可以在未脫離申請專利範圍所界定的本發明之範疇下對該等實施例進行修改及調整。
10‧‧‧傳統型層疊封裝式Fo-WLCSP
12‧‧‧半導體晶粒
14‧‧‧半導體晶粒
16‧‧‧封裝劑
18‧‧‧增生互連結構
20‧‧‧接線
22‧‧‧接線
24‧‧‧半導體晶粒
26‧‧‧封裝劑
28‧‧‧增生互連結構
30‧‧‧接線
32‧‧‧凸塊
50‧‧‧電子裝置
52‧‧‧晶片載體基板/印刷電路板
54‧‧‧導電信號走線
56‧‧‧焊線封裝
58‧‧‧覆晶
60‧‧‧球柵陣列/BGA
62‧‧‧凸塊晶片載體/BCC
64‧‧‧雙排型封裝/DIP
66‧‧‧基板柵格陣列/LGA
68‧‧‧多晶片模組/MCM
70‧‧‧四側無引腳扁平封裝/QFN
72‧‧‧四面扁平封裝
74‧‧‧半導體晶粒
76‧‧‧接觸墊
78‧‧‧中介載體
80‧‧‧導線
82‧‧‧接線
84‧‧‧封裝劑
88‧‧‧半導體晶粒
90‧‧‧載體
92‧‧‧黏著材料
94‧‧‧接線
96‧‧‧接觸墊
98‧‧‧接觸墊
100‧‧‧模封材料/封裝劑
102‧‧‧接觸墊
104‧‧‧凸塊
106‧‧‧中介載體
108‧‧‧晶粒作用區
110‧‧‧凸塊
112‧‧‧凸塊
114‧‧‧信號線
116‧‧‧模封材料/封裝劑
120‧‧‧半導體晶圓
122‧‧‧基座基板材料
124‧‧‧半導體晶粒
126‧‧‧鋸割分隔道
130‧‧‧晶粒作用表面
132‧‧‧導電層
136‧‧‧鋸片/雷射切割工具
140‧‧‧基板/載體
142‧‧‧聚合物層
144‧‧‧導電層
146‧‧‧暫時性基板/載體
148‧‧‧介面層/雙面膠帶
149‧‧‧晶粒附著區域
150‧‧‧指示方向之箭頭
154‧‧‧聚合物層
156‧‧‧通路
158‧‧‧導電柱/導電通路
160‧‧‧導電層/重分佈層
162‧‧‧聚合物層
164‧‧‧通路
166‧‧‧導電柱/導電通路
168‧‧‧導電層/重分佈層
170‧‧‧阻焊層
172‧‧‧Fo-WLCSP
174‧‧‧鋸片/雷射切割工具
176‧‧‧凸塊
177‧‧‧凸塊底層金屬/UBM
178‧‧‧Fo-WLCSP
180‧‧‧基板/載體
182‧‧‧聚合物層
184‧‧‧導電層
186‧‧‧暫時性基板/載體
188‧‧‧介面層/雙面膠帶
190‧‧‧指示方向之箭頭
196‧‧‧通路
198‧‧‧導電柱/導電通路
200‧‧‧導電層/重分佈層
202‧‧‧聚合物層
204‧‧‧聚合物層
206‧‧‧通路
208‧‧‧導電柱/導電通路
210‧‧‧導電層/重分佈層
212‧‧‧聚合物層
214‧‧‧通路
216‧‧‧導電柱/導電通路
218‧‧‧導電層/重分佈層
220‧‧‧阻焊層
222‧‧‧Fo-WLCSP
224‧‧‧鋸片/雷射切割工具
226‧‧‧球塊/凸塊
228‧‧‧凸塊底層金屬/UBM
230‧‧‧Fo-WLCSP
231‧‧‧半導體晶粒
232‧‧‧半導體晶粒
234‧‧‧晶粒接附黏著劑
236‧‧‧接線
238‧‧‧接線
240‧‧‧封裝劑
242‧‧‧增生互連結構
244‧‧‧凸塊
248‧‧‧Fo-WLCSP
250‧‧‧Fo-WLCSP
252‧‧‧半導體晶粒
254‧‧‧半導體晶粒
256‧‧‧晶粒接附黏著劑
258‧‧‧晶粒接附黏著劑
260‧‧‧互連結構
262‧‧‧接線
264‧‧‧接線
266‧‧‧互連結構
268‧‧‧凸塊
圖1例示一傳統型PoP式Fo-WLCSP，其具有被封裝劑密封的半導體晶粒；圖2例示具有不同種類之封裝件安置於其表面之一PCB；圖3a至圖3c例示安置於該PCB之代表性半導體封裝件之進一步細節；圖4a至圖4c例示一包含複數個半導體晶粒之半導體晶圓；圖5a至圖5m例示一形成具有由聚合物層隔開的導電層和導電通路之一Fo-WLCSP的製程；圖6a至圖6b例示該具有由聚合物層隔開的導電層和導電通路之Fo-WLCSP；圖7例示一具有由聚合物層隔開的導電層和導電通路之疊置Fo-WLCSP之PoP配置； 圖8a至圖8r例示形成具有由聚合物層隔開的導電層和導電通路之一Fo-WLCSP的另一製程；圖9例示該具有由聚合物層隔開的導電層和導電通路之Fo-WLCSP；圖10a至圖10b例示依據圖9形成之一PoP式Fo-WLCSP；而圖11a至圖11b例示依據圖6a至圖6b形成之一PoP式Fo-WLCSP。
124．．．半導體晶粒
130．．．晶粒作用表面
132．．．導電層
140．．．基板/載體
142．．．聚合物層
144．．．導電層
146．．．暫時性基板/載體
148．．．介面層/雙面膠帶
149．．．晶粒附著區域
150．．．指示方向之箭頭
154．．．聚合物層
156．．．通路
158．．．導電柱/通路
160．．．導電層/重分佈層
162．．．聚合物層
164．．．通路
166．．．導電柱/通路
168．．．導電層/重分佈層
170．．．阻焊層
172．．．Fo-WLCSP
174．．．鋸片/雷射切割工具
177．．．凸塊底層金屬/UBM

Claims (21)

  1. 一種製造晶圓級晶片尺寸封裝(WLCSP)的方法，包含：提供一第一聚合物層，其包括形成於該第一聚合物層之內的一接觸墊；提供一半導體晶粒於該第一聚合物層之上；形成一第二聚合物層於該第一聚合物層上方且在該半導體晶粒周圍；形成穿過該第一聚合物層和該第二聚合物層並且耦合至該接觸墊的複數個第一導電通路；以及形成一第一互連結構於電性連接至該第一導電通路之該第二聚合物層之一第一表面上。
  2. 如申請專利範圍第1項之方法，另包含形成複數個第二導電通路於該半導體晶粒之上。
  3. 如申請專利範圍第1項之方法，其中形成該第一互連結構包含提供一第三聚合物層，該第三聚合物層包含形成於該第三聚合物層之內的一導電層，該第一導電通路電性連接至該導電層。
  4. 如申請專利範圍第3項之方法，另包含：形成一凸塊於該第三聚合物層之上；以及形成複數個第二導電通路於該第三聚合物層之內。
  5. 如申請專利範圍第1項之方法，另包含形成該第一導電通路於環繞該半導體晶粒之一周圍處。
  6. 如申請專利範圍第1項之方法，另包含： 提供一半導體封裝；以及配置該半導體封裝至該WLCSP。
  7. 一種晶圓級晶片尺寸封裝(WLCSP)，包含：一第一聚合物層，包含形成在該第一聚合物層中的複數個接觸墊；一半導體晶粒，配置在該第一聚合物層之上；一第二聚合物層，形成於該半導體晶粒周圍及該第一聚合物層之上；複數個第一導電通路，穿過該第一和第二聚合物層中的開口而形成；以及一第一互連結構，形成於電性連接至該第一導電通路之該第二聚合物層之一第一表面上。
  8. 申請專利範圍第7項之WLCSP，其中該第一互連結構包含：一重分佈層，形成在該半導體晶粒以及該第二聚合物層之上；複數個第二導電通路，電性連接至該接觸墊；以及複數個凸塊。
  9. 申請專利範圍第7項之WLCSP，另包含一半導體封裝配置至該WLCSP。
  10. 一種半導體裝置，包含：一第一聚合物層，包含在該第一聚合物層之內的一第一導電層；一第一半導體晶粒，配置在該第一導電層對面的該第 一聚合物層的一表面之上；一第二聚合物層，形成在該第一聚合物層和該第一半導體晶粒之上；以及一第一導電通路，穿過該第一聚合物層和該第二聚合物層而形成，並且耦合至該第一導電層。
  11. 申請專利範圍第10項之半導體裝置，另包含：一第三聚合物層，形成在該第二聚合物層之上；以及一第二導電通路，穿過該第三聚合物層而形成。
  12. 申請專利範圍第10項之半導體裝置，另包含一第二導電層，形成在該第二聚合物層之上。
  13. 申請專利範圍第10項之半導體裝置，另包含一互連結構，形成在該第二聚合物層之上。
  14. 申請專利範圍第10項之半導體裝置，另包含一第二半導體晶粒，配置在該第一聚合物層之上。
  15. 申請專利範圍第10項之半導體裝置，另包含複數個第二導電通路，形成於環繞該第一半導體晶粒之一周圍處。
  16. 一種半導體裝置，包含：一第一聚合物層；一第一半導體晶粒，配置在該第一聚合物層之上；一第二聚合物層，形成在該第一聚合物層之上；以及一第一互連結構，穿過在該第一聚合物層和該第二聚合物層中的開口而形成。
  17. 申請專利範圍第16項之半導體裝置，另包含： 一第三聚合物層，形成在該第二聚合物層之上；以及一導電通路，穿過該第三聚合物層而形成。
  18. 申請專利範圍第16項之半導體裝置，另包含一第二互連結構，形成該第二聚合物層之上。
  19. 申請專利範圍第16項之半導體裝置，另包含：一第三聚合物層，形成在該第二聚合物層之上；一導電通路，穿過該第三聚合物層而形成；以及一導電層，形成該第三聚合物層之上，並且電性連接至該導電通路。
  20. 申請專利範圍第16項之半導體裝置，另包含一第二半導體晶粒，配置在該第一聚合物層之上。
  21. 申請專利範圍第16項之半導體裝置，另包含複數個導電通路，形成於環繞該第一半導體晶粒之一周圍處。
TW100127179A 2010-08-16 2011-08-01 半導體裝置及形成具有由聚合物層隔開的導電層和導電通路之扇出式晶圓級晶片尺寸封裝的方法 TWI538070B (zh)

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