TWI685936B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

Info

Publication number
TWI685936B
TWI685936B TW107137394A TW107137394A TWI685936B TW I685936 B TWI685936 B TW I685936B TW 107137394 A TW107137394 A TW 107137394A TW 107137394 A TW107137394 A TW 107137394A TW I685936 B TWI685936 B TW I685936B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
layer
circuit device
photosensitive adhesive
conductive
Prior art date
Application number
TW107137394A
Other languages
English (en)
Other versions
TW202002214A (zh
Inventor
余振華
余俊輝
余國寵
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202002214A publication Critical patent/TW202002214A/zh
Application granted granted Critical
Publication of TWI685936B publication Critical patent/TWI685936B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/0347—Manufacturing methods using a lift-off mask
    • H01L2224/0348—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05547—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/08057—Shape in side view
    • H01L2224/08058—Shape in side view being non uniform along the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/0805—Shape
    • H01L2224/0807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/1148—Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/24147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/3301—Structure
    • H01L2224/3303—Layer connectors having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73209—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8036—Bonding interfaces of the semiconductor or solid state body
    • H01L2224/80365—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80801—Soldering or alloying
    • H01L2224/80815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H01L2224/83201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一種裝置包括：第一裝置，包括：積體電路裝置，具有 第一連接件；第一感光性黏著層，位於所述積體電路裝置上；以及第一導電層，位於所述第一連接件上，所述第一感光性黏著層環繞所述第一導電層；第二裝置，包括：中介層，具有第二連接件；第二感光性黏著層，位於所述中介層上，所述第二感光性黏著層在實體上連接至所述第一感光性黏著層；以及第二導電層，位於所述第二連接件上，所述第二感光性黏著層環繞所述第二導電層；以及導電連接件，對所述第一導電層與所述第二導電層進行結合，所述導電連接件被空氣隙環繞。

Description

半導體裝置及其形成方法
本發明的實施例是有關於一種半導體裝置及其形成方法。
自積體電路(integrated circuit，IC)的開發，半導體行業已因各種電子組件(即電晶體、二極體、電阻器、電容器等)整合密度的不斷提升而經歷連續快速成長。最重要的是，整合密度的該些提升乃是源自最小特徵尺寸的不斷減小，而使得更多的組件能夠整合至給定面積之中。
該些整合度提升實質上是從二維(two-dimensional，2D)層面而言，原因在於積體組件所佔據的面積主要位於半導體晶圓的表面上。增大的密度及積體電路的面積的相應減小一般而言超出了將積體電路晶片直接結合至基底上的能力。已使用中介層(interposer)將球接觸面積自晶片重佈線至中介層的更大面積。此外，中介層已使得能夠實現包括多個晶片的三維(three-dimensional，3D)封裝。亦已開發出其他封裝來併入三維 態樣。
本發明的一實施例提供一種半導體裝置，包括：第一裝置，包括：積體電路裝置，具有第一連接件；第一感光性黏著層，位於所述積體電路裝置上；以及第一導電層，位於所述第一連接件上，所述第一感光性黏著層環繞所述第一導電層；第二裝置，包括：中介層，具有第二連接件；第二感光性黏著層，位於所述中介層上，所述第二感光性黏著層在實體上連接至所述第一感光性黏著層；以及第二導電層，位於所述第二連接件上，所述第二感光性黏著層環繞所述第二導電層；以及導電連接件，對所述第一導電層與所述第二導電層進行結合，所述導電連接件被空氣隙環繞。
本發明的一實施例提供一種形成半導體裝置的方法，包括：在第一感光性黏著層中形成第一開口，所述第一感光性黏著層相鄰於第一積體電路裝置的第一側；在所述第一開口中鍍覆第一可回焊層；在第二感光性黏著層中形成第二開口，所述第二感光性黏著層相鄰於第二積體電路裝置的第一側；在所述第二開口中鍍覆第二可回焊層；將所述第一感光性黏著層與所述第二感光性黏著層按壓於一起，藉此對所述第一積體電路裝置與所述第二積體電路裝置進行實體連接；以及對所述第一可回焊層及所述第二可回焊層進行回焊，藉此形成對所述第一積體電路裝置與所述 第二積體電路裝置進行電性連接的導電連接件。
本發明的一實施例提供一種形成半導體裝置的方法，包括：以第一模塑化合物包封多個第一積體電路裝置；在所述第一積體電路裝置之上形成第一感光性黏著層；在所述第一感光性黏著層中圖案化出第一開口；在所述第一開口中鍍覆第一導電層；在所述第一導電層上鍍覆第一可回焊層，所述第一導電層與所述第一可回焊層的組合厚度小於所述第一感光性黏著層的第一厚度，所述第一導電層及所述第一可回焊層電性連接至所述第一積體電路裝置；將第二積體電路裝置按壓至所述第一感光性黏著層，以對所述第一積體電路裝置與所述第二積體電路裝置進行實體連接；以及對所述第一可回焊層進行回焊以形成對所述第一積體電路裝置與所述第二積體電路裝置進行電性連接的導電連接件。
50‧‧‧積體電路裝置
50A‧‧‧第一積體電路裝置
50B‧‧‧第二積體電路裝置
52‧‧‧基底
54‧‧‧連接件
56‧‧‧感光性黏著膜
58‧‧‧開口
60‧‧‧導電層
62‧‧‧可回焊層
64‧‧‧穿孔/通孔
70‧‧‧晶圓
72‧‧‧基底
74‧‧‧穿孔
74a‧‧‧障壁層
74b‧‧‧導電材料
76‧‧‧連接件
78‧‧‧感光性黏著膜
80‧‧‧開口
82‧‧‧導電層
84‧‧‧可回焊層
100‧‧‧中間封裝
100A、100B‧‧‧裝置區域
102‧‧‧導電連接件
104‧‧‧空氣隙
106‧‧‧空氣隙
108‧‧‧包封體
110‧‧‧導電柱
112‧‧‧絕緣層
114‧‧‧切割線區域
116‧‧‧中介層
118‧‧‧載體基底
120‧‧‧黏著劑
122‧‧‧包封體
124‧‧‧重佈線結構
126‧‧‧導電連接件
132‧‧‧連接件
134‧‧‧感光性黏著膜
136‧‧‧導電連接件
138‧‧‧空氣隙
160‧‧‧切割線區域
200‧‧‧裝置封裝
200A、200B‧‧‧裝置區域
202‧‧‧封裝基底
204‧‧‧底部填充物
206‧‧‧導電連接件
300‧‧‧裝置封裝
400‧‧‧中間封裝
400A、400B‧‧‧裝置區域
402‧‧‧開口
404‧‧‧穿孔
406‧‧‧切割線區域
408‧‧‧載體基底
410‧‧‧黏著劑
412‧‧‧包封體
414‧‧‧重佈線結構
416‧‧‧導電連接件
418‧‧‧切割線區域
420‧‧‧介電層
422‧‧‧穿孔
424‧‧‧開口
500‧‧‧裝置封裝
500A、500B‧‧‧裝置區域
600‧‧‧裝置封裝
602‧‧‧載體基底
604‧‧‧後側重佈線結構
606‧‧‧穿孔
608‧‧‧積體電路晶粒
610‧‧‧黏著劑/介電層
612‧‧‧晶粒連接件
614‧‧‧介電材料
616‧‧‧包封體
618‧‧‧前側重佈線結構
620‧‧‧介電層
622‧‧‧金屬化圖案
624‧‧‧感光性黏著膜
626‧‧‧開口
628‧‧‧導電連接件
700‧‧‧裝置封裝
702‧‧‧載體基底
704‧‧‧積體電路晶粒
706‧‧‧黏著劑
708‧‧‧晶粒連接件
710‧‧‧介電材料
712‧‧‧包封體
714‧‧‧感光性黏著膜
716、718‧‧‧開口
720‧‧‧穿孔
722‧‧‧包封體
724‧‧‧前側重佈線結構
726‧‧‧導電連接件
802‧‧‧晶種層
804‧‧‧光阻
902‧‧‧晶種層
904、906‧‧‧光阻
908‧‧‧開口
952‧‧‧晶種層
954‧‧‧光阻
1002‧‧‧空腔
1004‧‧‧開口
G1、G2‧‧‧間隙
H1‧‧‧高度
R1、R2、R3、R4、R5、R6‧‧‧區域
T1、T2、T3、T4、T5、T6‧‧‧厚度
W1、W2‧‧‧寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本行業中的標準慣例，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1A至圖2B是根據一些實施例，在積體電路裝置的處理期間各中間步驟的各種圖式。
圖3A至圖4B是根據一些實施例，在晶圓的處理期間各中間 步驟的各種圖式。
圖5A至圖18是根據一些實施例，在形成裝置封裝的製程期間的各中間步驟的各種圖式。
圖19是根據一些實施例的裝置封裝的圖式。
圖20示出根據一些其他實施例的裝置封裝。
圖21示出根據再一些其他實施例的裝置封裝。
圖22至圖33是根據一些實施例，在形成裝置封裝的製程期間的各中間步驟的各種圖式。
圖34示出根據一些其他實施例的裝置封裝。
圖35示出根據再一些其他實施例的裝置封裝。
圖36示出根據再一些其他實施例的裝置封裝。
圖37至圖46是根據一些實施例，在形成裝置封裝的製程期間的各中間步驟的各種圖式。
圖47至圖57是根據一些實施例，在形成裝置封裝的製程期間的各中間步驟的各種圖式。
圖58A至圖58F示出根據另一實施例，形成導電連接件的製程。
圖59A至圖59K示出根據另一實施例，形成導電連接件的製程。
圖60A至圖60F示出根據另一實施例，形成導電連接件的製程。
圖61A及圖61B是根據一些其他實施例，裝置封裝的各種圖 式。
以下揭露內容提供用於實作本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，該些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本發明可能在各種實例中重複使用參考編號及/或字母。此種重複使用是出於簡潔及清晰的目的，但自身並不表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「位於...之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括裝置在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據一些實施例，形成一種導電連接件。在晶粒及晶圓上形成感光性黏著膜。在所述感光性黏著膜中形成開口，從而暴 露出晶粒及晶圓的連接件。在所述開口中鍍覆導電層及可回焊層。應注意，在每一開口中導電層與可回焊層的組合厚度小於感光性黏著膜的厚度。藉由感光性黏著膜將晶粒與晶圓彼此實體連接，且然後藉由對可回焊層進行回焊而將晶粒及晶圓彼此電性連接以形成導電連接件。由於開口利用可回焊材料進行底部填充，因此在所得的導電連接件周圍形成空氣隙。形成空氣隙可在導電連接件周圍提供緩衝，藉此避免在相鄰的導電連接件之間的減小的節距處形成短路的風險。
圖1A至圖2B是根據一些實施例，在積體電路裝置50的製程期間各中間步驟的各種圖式。圖1A至圖2B是剖視圖，其中以名稱「A」結束的圖示出整體圖式，且以名稱「B」結束的圖示出來自相應「A」圖的區域R1的詳細圖式。
積體電路裝置50可為邏輯晶粒(例如中央處理單元(central processing unit，CPU)、圖形處理單元(graphic processing unit，GPU)、系統晶片(system-on-a-chip，SoC)、微控制器等)、記憶體晶粒(例如動態隨機存取記憶體(dynamic random access memory，DRAM)晶粒、靜態隨機存取記憶體(static random access memory，SRAM)晶粒等)、電力管理晶粒(例如，電力管理積體電路(power management integrated circuit，PMIC)晶粒)、射頻(radio frequency，RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system，MEMS)晶粒、訊號處理晶粒(例如數位訊號處理(digital signal processing，DSP)晶粒)、前 端晶粒(例如類比前端(analog front-end，AFE)晶粒)等或其組合。可在晶圓中形成積體電路裝置50，所述晶圓可包括在後續的步驟中被單體化以形成多個積體電路裝置50的不同裝置區域。積體電路裝置50包括基底52及連接件54。
基底52可包括半導體基底、絕緣體上半導體(semiconductor-on-insulator，SOI)基底、多層式半導體基底等。基底52的半導體材料可為矽；鍺；化合物半導體，包括矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基底或梯度基底(gradient substrate)等其他基底。基底52可經摻雜或不經摻雜。可在基底52的主動面(active surface)(例如，面朝上的表面)中及/或基底52的主動面上形成裝置，例如電晶體、電容器、電阻器及二極體等。
在基底52的主動面上形成具有一或多個介電層及相應的金屬化圖案的互連結構。所述介電層可為金屬間介電(inter-metallization dielectric，IMD)層。金屬間介電層可藉由例如旋塗、化學氣相沉積(chemical vapor deposition，CVD)、電漿增強型化學氣相沉積(plasma-enchanced CVD，PECVD)、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition，HDP-CVD)等此項技術中已知的任意適當的方法由例如以下低介電常數介電(low-K dielectric)材料形成：例如未經摻 雜的矽酸鹽玻璃(undoped silicate glass，USG)、磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼磷矽酸鹽玻璃(borophosphosilicate glass，BPSG)、氟矽酸鹽玻璃(fluorosilicate glass，FSG)、SiOxCy、旋塗玻璃(spin-on-glass)、旋塗聚合物(spin-on-polymer)、矽碳材料、其化合物、其複合物、其組合等。介電層中的金屬化圖案可例如藉由通孔及/或跡線而路由裝置之間的電性訊號，且亦可容納各種電性裝置，例如電容器、電阻器、電感器等。可將各種裝置及金屬化圖案互連以執行一或多種功能。所述功能可包括記憶體結構、處理結構、感測器、放大器、功率分佈、輸入/輸出電路系統及/或類似功能。另外，在互連結構中及/或互連結構上形成例如導電柱或接觸墊等連接件54，以提供與電路系統及裝置的外部電性連接。此項技術中具有通常知識者將理解提供上述實例是出於說明性目的。可使用適合於給定應用的其他電路系統。
在圖1A及圖1B中，在基底52的主動面上形成感光性黏著膜56。感光性黏著膜56可由有機感光性聚合物層(photosensitive polymer layer，PSPL)(例如，苯並環丁烯(benzocyclobutene；BCB)、環氧樹脂膜(SU-8)、信越SINRTM聚醯亞胺等)形成，且可藉由旋轉塗布等形成。感光性黏著膜56亦可被稱為黏著層。在形成之後，可將感光性黏著膜56暴露至光進行圖案化。感光性黏著膜56的圖案對應於連接件54。所述圖案化形成穿過感光性黏著膜56的開口58的圖案，藉此暴露出連接 件54的一些部分。開口58中的每一者具有可小於連接件54的寬度的寬度W1，例如自約1微米至約40微米的寬度W1。寬度W1亦可大於或等於連接件54的寬度。在形成並圖案化感光性黏著膜56之後，藉由例如退火製程使感光性黏著膜56固化，所述退火製程可在烘箱中在小於約200℃的溫度下執行。所形成的感光性黏著膜56具有自約1微米至約10微米的厚度T1。開口58具有等於厚度T1的深度。
在圖2A及圖2B中，在連接件54上的開口58中形成導電層60。導電層60是由導電材料(例如鎳、銅、金等或其組合)形成，且是藉由例如利用連接件54代替晶種層的無電鍍覆等鍍覆製程形成。然後在開口58中在導電層60上形成可回焊層62。可回焊層62是自可回焊材料(例如，焊料、錫等或其組合)形成，且是藉由利用導電層60代替晶種層的鍍覆製程形成。
導電層60及可回焊層62具有自約1微米至約10微米的組合厚度T2。厚度T2小於厚度T1。根據寬度W1計算可回焊層62的厚度，使得形成充足的用於後續形成的導電連接件的可回焊材料。因此，感光性黏著膜56的頂表面延伸高於可回焊層62的頂表面。形成間隙G1，其中間隙G1具有等於厚度T1與T2之差的深度。
圖3A至圖4B是根據一些實施例，在晶圓70的處理期間各中間步驟的各種圖式。圖3A至圖4B是剖視圖，其中以名稱「A」結束的圖示出整體圖式，且以名稱「B」結束的圖示出來自 相應「A」圖的區域R2的詳細圖式。
晶圓70包括多個裝置區域100A及100B，其中可貼合積體電路裝置50以形成多個裝置。在晶圓70中形成的裝置可為中介層或積體電路晶粒等。晶圓70可包括基底72、穿孔74以及連接件76。
基底72可為半導體基底、絕緣體上半導體基底或多層式半導體基底等。基底72的半導體材料可為：矽；鍺；化合物半導體，包含矽鍺、碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦；合金半導體，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP及/或GaInAsP；或者其組合。亦可使用例如多層式基板或梯度基板等其他基板。基底72可為經摻雜的或未經摻雜的。在晶圓70中形成有中介層的實施例中，基底72一般而言不在其中包括主動裝置，但所述中介層可包括形成於基底72的前表面(例如，面朝上的表面)中及/或所述前表面上的被動裝置。在晶圓70中形成有積體電路晶粒的實施例中，可在基底72的前表面中及/或所述前表面上形成裝置，例如電晶體、電容器、電阻器及二極體等。
穿孔74被形成為自基底72的前表面延伸至基底72中。當基底72是矽基底時，穿孔74有時亦被稱為基底穿孔或矽穿孔(through-silicon via，TSV)。可藉由利用例如蝕刻、鑽孔、雷射技術及/或其組合等在基底72中形成凹陷而形成穿孔74。可例如利用氧化技術而在凹陷中形成薄介電材料。可例如藉由化學氣相 沉積、原子層沉積(atomic layer deposition；ALD)、物理氣相沉積(physical vapor deposition；PVD)、熱氧化及/或其組合等而在基底72的前側之上及在開口中共形地沉積薄障壁層74a。可由氧化物、氮化物、氮氧化物(例如，氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢及/或其組合等)形成障壁層74a。可在障壁層74a之上及在開口中沉積導電材料74b。可藉由電化學鍍覆製程、化學氣相沉積、原子層沉積、物理氣相沉積及/或其組合等而形成導電材料74b。導電材料74b的實例為銅、鎢、鋁、銀、金及/或其組合等。藉由例如化學機械拋光(chemical mechanical polish，CMP)而自基底72的前側移除過量的導電材料74b及障壁層74a。穿孔74共同地包括障壁層74a以及導電材料74b，其中障壁層74a位於導電材料74b與基底72之間。
在基底72的前表面之上形成互連結構，並使用所述互連結構將積體電路裝置(若存在)及/或穿孔74電性連接在一起及/或電性連接至外部裝置。互連結構可包括一或多個介電層以及位於所述介電層中的相應金屬化圖案。金屬化圖案可包括通孔及/或跡線以將任意裝置及/或穿孔74互連在一起及/或互連至外部裝置。介電層可由以下材料形成：氧化矽、氮化矽、碳化矽、氮氧化矽、低介電常數介電材料，例如PSG、BPSG、FSG、SiOxCy、旋塗玻璃、旋塗聚合物、矽碳材料、其化合物、其複合物、其組合等。可藉由此項技術中已知的任意適當的方法(例如，旋塗、化學氣相沉積、電漿增強型化學氣相沉積、高密度電漿化學氣相 沉積等)來沉積介電層。可例如利用光微影技術在介電層上沉積並圖案化光阻材料以暴露出介電層的將變為金屬化圖案的一些部分而在介電層中的每一者中形成金屬化圖案。可使用例如各向異性乾蝕刻製程等蝕刻製程在介電層中形成對應於介電層的被暴露出的部分的凹陷及/或開口。所述凹陷及/或開口可與擴散障壁層對齊且被填充以導電材料。擴散障壁層可由藉由原子層沉積等所沉積的TaN、Ta、TiN、Ti或CoW等的一或多個層形成，且導電材料可由銅、鋁、鎢、銀、或其組合等形成，且可藉由化學氣相沉積、物理氣相沉積等沉積。可例如利用化學機械拋光而移除位於介電層上的任意過量的擴散障壁層及/或導電材料。另外，在互連結構中及/或互連結構上形成例如導電柱或接觸墊等連接件76，以提供與穿孔74以及互連結構的金屬化圖案的外部電性連接。
在圖3A及圖3B中，在基底72的前表面上形成感光性黏著膜78。感光性黏著膜78可由與感光性黏著膜56類似的材料形成，其可由與用以形成感光性黏著膜56的方法類似的方法形成。在形成之後，可將感光性黏著膜78暴露至光進行圖案化。感光性黏著膜78的圖案對應於連接件76。所述圖案化形成穿過感光性黏著膜78從而暴露出連接件76的一些部分的開口80的圖案。開口80中的每一者具有可小於連接件76的寬度的寬度W2，例如自約1微米至約40微米的寬度W2。寬度W2亦可大於或等於連接件76的寬度。所形成的感光性黏著膜78具有約1微米至約5微米的厚度T3。開口80具有等於厚度T3的深度。在一些實施例中， 感光性黏著膜78並非在形成之後立即固化，而是在執行後續的處理步驟之後固化(參見例如圖6A及圖6B)。
在圖4A及圖4B中，在連接件76上在開口80中形成導電層82。導電層82可由與導電層60的材料類似的材料形成，且可由與用以形成導電層60的方法類似的方法形成。然後在開口80中的導電層82上形成可回焊層84。可回焊層84可由與可回焊層62的材料類似的材料形成，且可由與用以形成可回焊層62的方法類似的方法形成。
導電層82與可回焊層84具有自約1微米至約5微米的組合厚度T4。厚度T4小於厚度T3。因此，感光性黏著膜78的頂表面延伸高於可回焊層84的頂表面。形成間隙G2，其中間隙G2具有等於厚度T3與T4之差的深度。
根據一些實施例，藉由將積體電路裝置50結合至晶圓70的前側而形成積體電路裝置封裝。在結合之前，可根據以上所示的製程處理積體電路裝置50及晶圓70。可利用此類裝置形成多種積體電路裝置封裝。
圖5A至圖18是根據一些實施例，在形成裝置封裝200的製程期間的各中間步驟的各種圖式。在圖5A至圖11中，藉由將積體電路裝置50結合至晶圓70的前側而形成中間封裝100。將中間封裝100單體化。在圖12至圖18中，執行進一步的處理以形成裝置封裝200。在實施例中，裝置封裝200是CoW(chip-on-wafer)封裝，但應理解，實施例可應用於其他三維積體 電路(3DIC)封裝。圖19是根據一些實施例的裝置封裝300的圖式。圖5A至圖19是剖視圖，其中以名稱「A」結束的圖示出整體圖式，且以名稱「B」結束的圖示出來自相應「A」圖的區域R3的詳細圖式。具體而言，區域R3示出形成將積體電路裝置50的連接件54耦合至晶圓70的連接件76的導電連接件102(在圖6B中示出)。
在圖5A及圖5B中，將多個積體電路裝置50貼合至晶圓70。積體電路裝置50位於裝置區域100A及100B中，在後續的步驟中將積體電路裝置50單體化以形成中間封裝100。可利用例如拾取及放置工具(pick-and-place tool)將積體電路裝置50貼合至晶圓70。
藉由面對面結合將積體電路裝置50貼合至晶圓70。將積體電路裝置50按壓抵靠晶圓70，使得感光性黏著膜56及78黏合至彼此。在其中感光性黏著膜78並非在形成之後立即固化的實施例中，感光性黏著膜56及78在黏合時共享固化-非固化結合介面，其中感光性黏著膜56固化且感光性黏著膜78未固化。未固化的感光性黏著膜78在放置期間可更好地適形於固化的感光性黏著膜56的形狀。在將感光性黏著膜56及78按壓在一起時，感光性黏著膜56及78互混並形成聚合物鍵以變為一個連續的感光性聚合物層。相較於例如混合結合及熔融結合等其他結合技術，利用感光性黏著膜56及78使得積體電路裝置50能夠在利用較少退火及清潔製程的情況下黏合至晶圓70，從而減少製造成本。
在將積體電路裝置50貼合至晶圓70之後，在可回焊層62與84之間的區域中形成空氣隙104。積體電路裝置50因此實體連接至晶圓70，但可不電性連接。空氣隙104包括以間隙G1及G2為界線的區域(分別在圖2B及圖4B中示出)。空氣隙104各自具有兩個寬度：一個由開口58的寬度W1界定且另一個由開口80的寬度W2界定。空氣隙104亦各自具有等於間隙G1及G2的高度之和的高度H1，高度H1亦等於方程式1。
H 1 =(T 1 +T 3 )-(T 2 +T 4 )。 (1)
在圖6A及圖6B中，執行回焊製程，藉此將可回焊層62及84再成形為導電連接件102。導電連接件102包括可回焊層62及84的材料，且可在導電連接件102與導電層60及82的介面處形成介金屬化合物(intermetallic compound，IMC)。在回焊製程期間，可回焊層62及84的材料可因回焊材料的表面張力而改變形狀。可回焊層62及84的新形狀進行合併，使得可回焊層62及84接觸並形成導電連接件102。對應於間隙G2，保留空氣隙106。在導電連接件102的上部部分周圍形成空氣隙106，且導電連接件102的下部部分設置在空氣隙106與連接件76之間。形成空氣隙106在相鄰的導電連接件102之間生成緩衝空間，藉此使得導電連接件102能夠以更精細的節距形成。在其中感光性黏著膜78在形成之後不立即固化的實施例中，來自回焊製程的熱量亦可使感光性黏著膜78固化。
在圖7中，在各種組件上形成包封體108。包封體108 可為模製化合物、環氧樹脂等，且可藉由壓縮模製(compression molding)、轉移模製(transfer molding)等來施加。包封體108可形成於晶圓70之上使得積體電路裝置50被掩埋或覆蓋。包封體108亦形成於感光性黏著膜78上。然後使包封體108固化。在一些實施例中，使包封體108薄化使得包封體108的頂表面與積體電路裝置50的頂表面齊平。
在圖8中，使基底72薄化以暴露出穿孔74，使得穿孔74自基底72的後側突出。可以兩步薄化製程實現對穿孔74的暴露。首先，可執行研磨製程直至暴露出穿孔74。研磨製程可為例如化學機械拋光或其他可接受的移除製程。在研磨製程之後，基底72的後側與穿孔74可齊平。其次，可執行凹陷製程以在穿孔74周圍使基底72凹陷。所述凹陷製程可為例如適當的回蝕製程(etch-back process)。在所述薄化期間，亦可移除導電材料74b的一些部分。
在圖9中，在穿孔74的突出部分上形成導電柱110。導電柱110可藉由例如適當的光微影及鍍覆製程形成，且可由銅、鋁、鎢、銀或其組合等形成。然後在基底72的後側上環繞穿孔74的突出部分以及導電柱110形成絕緣層112。在一些實施例中，絕緣層112是由含矽絕緣體(例如，氮化矽、氧化矽或氮氧化矽等)形成，且可由適當的沉積方法(例如，旋轉塗布、化學氣相沉積、電漿增強型化學氣相沉積、高密度電漿化學氣相沉積等)形成。在沉積之後，可執行例如CMP等平坦化製程以移除過量介電材 料，使得絕緣層112的表面與導電柱110的表面齊平。
在一些實施例中，絕緣層112包括多個層。可在基底72的後側上環繞穿孔74的突出部分形成第一絕緣層。將第一絕緣層圖案化出暴露出穿孔74的開口。在第一絕緣層上且在所述開口中形成晶種層，且在所述晶種層上形成光阻。將光阻圖案化出對應於導電柱110的圖案的開口，並執行鍍覆製程，藉此在開口中形成導電柱110。移除光阻及晶種層的被暴露出的部分。然後在第一絕緣層上且在導電柱110周圍形成第二絕緣層。
在圖10中，在相鄰的裝置區域100A及100B之間沿切割線區域114將晶圓70單體化以形成中間封裝100。所述單體化可藉由鋸切、分割等來達成。
圖11示出單體化之後的中間封裝100。在單體化製程期間，形成中介層116，中介層116包括晶圓70以及絕緣層112的被單體化的部分。在一些實施例中，中介層116無主動裝置。在其他實施例中，中介層116包括主動裝置。中間封裝100中的每一者包括中介層116。感光性黏著膜78的被單體化的部分位於中介層116上。作為單體化製程的結果，中介層116的邊緣、包封體108的邊緣以及感光性黏著膜78的邊緣是相接的。換言之，中介層116的外側壁與包封體108的外側壁以及感光性黏著膜78的外側壁具有相同的寬度。
在圖12中，將被單體化的中間封裝100黏合至載體基底118。載體基底118可為玻璃載體基底、陶瓷載體基底等。載體 基底118可為晶圓，進而使得可同時在載體基底118上形成多個封裝。載體基底118包括多個裝置區域200A及200B，在所述多個裝置區域200A及200B中，藉由黏著劑120貼合中間封裝100。
黏著劑120位於中間封裝100的後側上且將中間封裝100黏合至載體基底118。黏著劑120可為任何適合的黏著劑、環氧樹脂、晶粒貼合膜(die attach film，DAF)等。可將黏著劑120施加至中間封裝100的後側，例如施加至相應包封體108的後側或可施加於載體基底118的表面之上。可使用例如拾取及放置工具藉由黏著劑120而將中間封裝100黏合至載體基底118。
在圖13中，在各種組件上形成包封體122。包封體122可為模製化合物、環氧樹脂等，且可藉由壓縮模製、轉移模製等來施加。包封體122可形成於中間封裝100之上使得導電柱110被掩埋或覆蓋。在固化之後，包封體122可經歷研磨製程以暴露出導電柱110。研磨製程亦可研磨絕緣層112。導電柱110的頂表面、絕緣層112的頂表面及包封體122的頂表面在研磨製程之後是共面的。研磨製程可例如為化學機械拋光。在一些實施例中，例如若已暴露出導電柱110，則可省略研磨。
圖14中，在包封體122及中間封裝100上形成重佈線結構124。重佈線結構124包括多個介電層及金屬化圖案。應理解，對重佈線結構124的例示為示意性的。舉例而言，重佈線結構124可被圖案化為藉由相應的介電層彼此分隔開的多個分立的部分。重佈線結構124可為例如重佈線層(redistribution layer， RDL)，且可包括金屬跡線(或金屬線)以及位於所述金屬跡線下方且連接至金屬跡線的通孔。作為形成重佈線結構124的實例，可沉積每一相應的介電層，且可在所沉積的介電層中形成開口。可藉由例如可接受的光微影及鍍覆製程而在所沉積的介電層上及開口中形成金屬跡線及通孔。
在圖15中，形成連接至重佈線結構124的導電連接件126。導電連接件126可在重佈線結構124的外側上形成於墊上。所述墊被形成為接觸重佈線結構124中的金屬化圖案，且可被稱作凸塊下金屬(under bump metallurgy，UBM)。導電連接件126可為球柵陣列(ball grid array，BGA)連接件、焊球、金屬柱、受控塌陷晶片連接(controlled collapse chip connection，C4)凸塊、微凸塊、化學鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique，ENEPIG)形成的凸塊等。導電連接件126可包含導電材料，例如焊料、銅、鋁、金、鎳、銀、鈀、錫等或其組合。在一些實施例中，藉由以下方式來形成導電連接件126：首先利用例如蒸鍍、電鍍、印刷、焊料轉移(solder transfer)、植球(ball placement)等常用方法形成焊料層。一旦已在所述結構上形成焊料層，則可執行回焊(reflow)以將所述材料造型成所期望凸塊形狀。在另一實施例中，導電連接件126為藉由濺鍍、印刷、電鍍、無電鍍覆、化學氣相沉積等而形成的金屬柱(例如銅柱)。所述金屬柱可無焊料且具有實質上垂直的側壁。
在圖16中，執行載體基底剝離(carrier substrate de-bonding)以將載體基底118自包封體122的後側及中間封裝100分離(剝離)。根據一些實施例，所述剝離包括在黏著劑120上投射例如雷射光或紫外光等光，以使得黏著劑120在所述光的熱量作用下分解，且可移除載體基底118。
在圖17中，沿切割線區域160將相鄰的裝置區域200A及200B單體化，以形成裝置封裝200。所述單體化可藉由鋸切、分割等來達成。圖18示出單體化之後所得的裝置封裝200。
在圖19中，藉由將裝置封裝200安裝至封裝基底202而形成裝置封裝300。在實施例中，裝置封裝300為CoWoS(chip-on-wafer-on-substrate)封裝，但應理解，實施例可應用至其他三維積體電路封裝。
封裝基底202可由例如矽或鍺等半導體材料製成。作為另一選擇，亦可使用例如矽鍺、碳化矽、砷化鎵、砷化銦、磷化銦、碳化矽鍺、磷化鎵砷、磷化鎵銦、其組合等化合物材料。另外，封裝基底202可為絕緣層上矽基底。一般而言，絕緣層上矽基底包括例如磊晶矽、鍺、矽鍺、絕緣層上矽、絕緣層上矽鍺或其組合等半導體材料的層。在一個替代性實施例中，封裝基底202是基於例如被玻璃纖維強化的樹脂芯體等絕緣芯體。一種示例性芯體材料為玻璃纖維樹脂(例如FR4)。所述芯體材料的替代材料包括雙馬來醯亞胺三嗪(bismaleimide-triazine)BT樹脂，或者作為另一選擇，為其他印刷電路板材料或膜。可對封裝基底202使用例如味之素增層膜等增層膜或其他層壓膜。
封裝基底202可包括主動裝置及被動裝置。如此技術中具有通常知識者將理解，可使用例如電晶體、電容器、電阻器、其組合等各種各樣的裝置來產生裝置封裝200的設計的結構性要求及功能性要求。可使用任何適合的方法來形成所述裝置。在一些實施例中，封裝基底202實質上無主動裝置及被動裝置。
封裝基底202亦可包括金屬化層及通孔以及位於所述金屬化層及通孔之上的結合墊。金屬化層可形成在主動裝置及被動裝置之上並被設計成連接各種裝置以形成功能性電路系統。金屬化層可由交錯的介電質(例如低介電常數介電材料)層及導電材料(例如銅)層形成且可藉由任何適合的製程(例如沉積、鑲嵌、雙鑲嵌等)來形成，其中由通孔對各層導電材料進行互連。
可對導電連接件126進行回焊以將裝置封裝200貼合至封裝基底202。導電連接件126將封裝基底202(包括封裝基底202中的金屬化層)電性地且實體地耦合至裝置封裝200。可在裝置封裝200與封裝基底202之間環繞導電連接件126形成底部填充物204。可在貼合裝置封裝200之後藉由毛細流動製程(capillary flow process)來形成底部填充物204或者可在貼合裝置封裝200之前藉由適合的沉積方法來形成底部填充物204。
在一些實施例中，在封裝基底202上在與導電連接件126相對的一側上形成導電連接件206。導電連接件206可為例如球柵陣列連接件，且可包含例如焊料、銅、鋁、金、鎳、銀、鈀、錫、類似材料或其組合等導電材料。
應理解，可以其他變型形成裝置封裝300。圖20示出根據一些其他實施例的裝置封裝300。圖21示出根據再一些其他實施例的裝置封裝300。
在圖20所示的實施例中，未將中間封裝100單獨地單體化並黏合至載體基底118。相反，在穿孔74被暴露出之後，在晶圓70上形成重佈線結構124。可省略導電柱110、絕緣層112以及包封體122，且可直接在晶圓70上形成重佈線結構124，例如重佈線結構124的底部介電層可實體地接觸基底72。然後將晶圓70及重佈線結構124同時地單體化以形成裝置封裝200。
在圖21所示的實施例中，將中間封裝100形成為包括多個堆疊的積體電路裝置50，例如第一積體電路裝置50A及第二積體電路裝置50B。舉例而言，可將第一積體電路裝置50A形成為在兩側上包括連接件54，且可在連接件54之間形成穿孔64。可在第一積體電路裝置50A的兩側上形成感光性黏著膜56。第二積體電路裝置50B可包括連接件132以及感光性黏著膜134，且可黏合至第一積體電路裝置50A。在連接件54與132之間形成具有空氣隙138的額外導電連接件136。可在中間封裝100中堆疊更多或更少積體電路裝置50。
根據一些實施例，現在將示出用於形成裝置封裝的額外的製程。可以與以上所論述的具有類似名稱的特徵類似的方式形成後續製程及裝置的一些特徵。因此，在本文中不再對形成細節進行贅述。
圖22至圖33是根據一些實施例，在形成裝置封裝500的製程期間的各中間步驟的各種圖式。在以下實施例的說明中，相同的參考編號指示與先前所述實施例相同的參考編號。在圖22至圖27中，藉由將積體電路裝置50結合至晶圓70的前側而形成中間封裝400。將中間封裝400單體化。在圖28至圖33中，執行進一步的處理以形成裝置封裝500。圖22至圖33是剖視圖，其中以名稱「A」結束的圖示出整體圖式，且以名稱「B」結束的圖示出來自相應「A」圖的區域R4的詳細圖式。
在圖22中，將感光性黏著膜78圖案化以形成暴露出連接件76中的一些連接件的開口402。可與開口80的圖案化同時地將開口402圖案化。開口80及402可為同一大小，抑或可為不同大小。
在圖23A及圖23B中，在連接件76上在開口80中形成導電層82。然後在開口80中的導電層82上形成可回焊層84。導電層82及可回焊層84形成於開口80中，而非形成於開口402中。
在圖24中，形成穿孔404。作為形成穿孔404的實例，在感光性黏著膜78上方及在開口402中形成晶種層。在一些實施例中，晶種層為金屬層，所述金屬層可為單層或包括由不同材料形成的多個子層的複合層。在一些實施例中，晶種層包括鈦層及位於所述鈦層之上的銅層。可使用例如物理氣相沉積等來形成晶種層。在晶種層上形成光阻並將所述光阻圖案化。可藉由旋轉塗佈等來形成光阻且可將所述光阻暴露至光以進行圖案化。光阻的 圖案對應於穿孔。所述圖案化會形成貫穿光阻的開口以暴露出晶種層。在光阻的開口中及在晶種層的暴露出的部分上形成導電材料。可藉由鍍覆(例如電鍍或無電鍍覆)等來形成導電材料。所述導電材料可包括金屬，如銅、鈦、鎢、鋁等。移除光阻以及晶種層的上面未形成有導電材料的部分。可藉由例如使用氧電漿等可接受的灰化製程或剝除製程來移除光阻。一旦光阻被移除，則例如使用可接受的蝕刻製程(例如藉由濕式蝕刻或乾式蝕刻)來移除晶種層的暴露出的部分。晶種層的剩餘部分與導電材料形成穿孔404。穿孔404可圍繞積體電路裝置50中的每一者對稱地或非對稱地形成。
在圖25A及圖25B中，將多個積體電路裝置50貼合至晶圓70。在貼合之前，可如在本文中所述對積體電路裝置50進行處理。舉例而言，在積體電路裝置50的主動側上形成連接件54，且可在積體電路裝置50中形成通孔64。在積體電路裝置50上形成感光性黏著膜56並將感光性黏著膜56圖案化。然後利用感光性黏著膜56及78作為黏著劑將積體電路裝置50以面對面方式結合至晶圓70，且執行回焊製程以形成被空氣隙106環繞的導電連接件102。
在圖26中，在相鄰的裝置區域400A及400B之間沿切割線區域406將晶圓70單體化，以形成中間封裝400。所述單體化可藉由鋸切、分割等來達成。圖27示出單體化之後的中間封裝400。
在圖28中，將被單體化的中間封裝400黏合至載體基底408。載體基底408可類似於載體基底118。載體基底408包括多個裝置區域500A及500B，在所述多個裝置區域500A及500B中，藉由黏著劑410貼合中間封裝400。黏著劑410位於中間封裝400的後側上。
在圖29中，在各種組件上形成包封體412。包封體412可類似於包封體122。包封體412可形成於中間封裝400之上使得穿孔404被掩埋或覆蓋。在固化之後，包封體412可經歷研磨製程以暴露出穿孔64及404。穿孔64及404的頂表面與包封體412的頂表面在研磨製程之後是共面的。
圖30中，在包封體412及中間封裝100上形成重佈線結構414。重佈線結構414可類似於重佈線結構124。然後形成連接至重佈線結構414的導電連接件416。導電連接件416可類似於導電連接件126。
在圖31中，執行載體基底剝離以將載體基底408自包封體412的後側及中間封裝400分離(de-bond)。
在圖32中，沿切割線區域418將相鄰的裝置區域500A及500B單體化，以形成裝置封裝500。所述單體化可藉由鋸切、分割等來達成。圖33示出單體化之後所得的裝置封裝500。
應理解，可以其他變型形成裝置封裝500。圖34示出根據一些其他實施例的裝置封裝500。圖35示出根據再一些其他實施例的裝置封裝500。圖36示出根據再一些其他實施例的裝置封 裝500。
在圖34所示的實施例中，未將中間封裝400單獨地單體化並黏合至載體基底408。相反，在貼合積體電路裝置50之後，直接在晶圓70上形成包封體412。包封體412可掩埋積體電路裝置50。然後將積體電路裝置50及包封體412平坦化，且在積體電路裝置50及包封體412上形成重佈線結構414。然後將晶圓70及重佈線結構414同時地單體化以形成裝置封裝500。
圖35所示的實施例類似於圖34所示的實施例，但中間封裝400被放置在介電層420上且包封在包封體412中。可相鄰於中間封裝400穿過包封體412形成穿孔422。在中間封裝400及穿孔422上形成重佈線結構414。在介電層420中形成開口424從而暴露出穿孔422。
圖36所示的實施例類似於圖34所示的實施例，只是將中間封裝400形成為包括多個堆疊的積體電路裝置50，例如第一積體電路裝置50A及第二積體電路裝置50B。類似於本文中所述的其他實施例，可在堆疊的積體電路裝置50中的一些積體電路裝置中形成穿孔64。
圖37至圖46是根據一些實施例，在形成裝置封裝600的製程期間的各中間步驟的各種圖式。在實施例中，裝置封裝600為整合扇出型(Integrated Fan-Out，InFO)封裝，但應理解，實施例可應用至其他三維積體電路封裝。圖37至圖46是剖視圖，其中以名稱「A」結束的圖示出整體圖式，且以名稱「B」結束的 圖示出來自相應「A」圖的區域R5的詳細圖式。
在圖37中，提供載體基底602，且在載體基底602上形成後側重佈線結構604。後側重佈線結構604包括多個介電層及金屬化圖案。後側重佈線結構604可以與後側重佈線結構124類似的方式形成。
在圖38中，在後側重佈線結構604上形成穿孔606。穿孔606可類似於穿孔404。
在圖39中，藉由黏著劑610而將積體電路晶粒608黏合至後側重佈線結構604。在其他實施例中，可將更多積體電路晶粒608黏合至後側重佈線結構604。晶粒連接件612(例如銅等金屬之導電柱)位於積體電路晶粒608的主動側上，且介電材料614位於積體電路晶粒608的主動側上圍繞晶粒連接件612。
在圖40中，在穿孔606及積體電路晶粒608上圍繞穿孔606及積體電路晶粒608形成包封體616。包封體616可類似於包封體122。可將包封體616平坦化，使得穿孔606的頂表面、晶粒連接件612的頂表面、介電材料614的頂表面以及包封體616的頂表面是齊平的。
在圖41中，在穿孔606、積體電路晶粒608以及包封體616上形成前側重佈線結構618。前側重佈線結構618包括多個介電層620及金屬化圖案622。前側重佈線結構618的最頂層是感光性黏著膜624，且形成於最頂部的金屬化圖案622上。將感光性黏著膜624圖案化以形成暴露出金屬化圖案622的開口626。
在圖42A及圖42B中，在金屬化圖案622上在開口626中形成導電層82。然後在開口626中的導電層82上形成可回焊層84。導電層82以及可回焊層84可形成於如在其他實施例中的位置中。
在圖43A及圖43B中，將積體電路裝置50貼合至前側重佈線結構618。在貼合之前，可如在本文中所述對積體電路裝置50進行處理；舉例而言，積體電路裝置可為處理器或記憶體等。舉例而言，在積體電路裝置50的主動側上形成連接件54。在積體電路裝置50上形成感光性黏著膜56並將感光性黏著膜56圖案化。將積體電路裝置50按壓抵靠前側重佈線結構618，使得感光性黏著膜56及624黏合至彼此。因此在可回焊層62與84之間形成空氣隙104。
在圖44A及圖44B中，執行回焊製程以對可回焊層62及84進行回焊，藉此形成導電連接件102。在導電連接件102周圍形成空氣隙106。
在圖45中，執行載體基底剝離以將載體基底602自後側重佈線結構604分離。
在圖46中，形成連接至後側重佈線結構604的導電連接件628。可在後側重佈線結構604的後側中形成開口，藉此暴露出後側重佈線結構604的金屬化圖案。然後在開口中形成導電連接件628。
圖47至圖57是根據一些實施例，在形成裝置封裝700 的製程期間的各中間步驟的各種圖式。在實施例中，裝置封裝700為多重堆疊(Multi-Stack，MUST)封裝，但應理解，實施例可應用至其他三維積體電路封裝。圖47至圖57是剖視圖，其中以名稱「A」結束的圖示出整體圖式，且以名稱「B」結束的圖示出來自相應「A」圖的區域R6的詳細圖式。
在圖47中，提供載體基底702，並藉由黏著劑706而將積體電路晶粒704黏合至載體基底702。晶粒連接件708(例如銅等金屬之導電柱)位於積體電路晶粒704的主動側上，且介電材料710位於積體電路晶粒704的主動側上圍繞晶粒連接件708。
在圖48中，在積體電路晶粒704上圍繞積體電路晶粒704形成包封體712。可將包封體712平坦化，使得晶粒連接件708的頂表面、介電材料710的頂表面以及包封體712的頂表面是齊平的。
在圖49中，在積體電路晶粒704以及包封體712上形成感光性黏著膜714。將感光性黏著膜714圖案化以形成暴露出晶粒連接件708的開口716及718。開口716及718位於積體電路晶粒704的不同區域中。
在圖50A及圖50B中，在晶粒連接件708上在開口716中形成導電層82。然後在開口716中的導電層82上形成可回焊層84。導電層82及可回焊層84不形成於開口718中。
在圖51中，在感光性黏著膜714上形成穿孔720。穿孔720可類似於穿孔404。
在圖52A及圖52B中，將積體電路裝置50貼合至感光性黏著膜714。在貼合之前，可如在本文中所述對積體電路裝置50進行處理。舉例而言，在積體電路裝置50的主動側上形成連接件54。在積體電路裝置50上形成感光性黏著膜56並將感光性黏著膜56圖案化。將積體電路裝置50按壓抵靠感光性黏著膜714，使得感光性黏著膜56及714黏合至彼此。因此在可回焊層62與84之間形成空氣隙104。
在圖53A及圖53B中，執行回焊製程以對可回焊層62及84進行回焊，藉此形成導電連接件102。在導電連接件102周圍形成空氣隙106。
在圖54中，在感光性黏著膜714上且在積體電路裝置50及穿孔720周圍形成包封體722。可將包封體722平坦化，使得積體電路裝置50的頂表面、穿孔720的頂表面以及包封體722的頂表面是齊平的。
在圖55中，在穿孔720、積體電路裝置50以及包封體722上形成前側重佈線結構724。前側重佈線結構724包括多個介電層及金屬化圖案。
在圖56中，執行載體基底剝離以將載體基底702自積體電路晶粒704及包封體712分離(剝離)。
在圖57中，形成連接至前側重佈線結構724的導電連接件726。可在前側重佈線結構724的前側中形成開口，藉此暴露出前側重佈線結構724的金屬化圖案。然後在開口中形成導電連 接件726。
應理解，可以其他方式形成導電連接件102。圖58A至圖58F示出根據一些其他實施例，用於形成導電連接件102的製程。圖59A至圖59K示出根據再一些其他實施例，用於形成導電連接件102的製程。圖60A至圖60F示出根據再一些其他實施例，用於形成導電連接件102的製程。根據後續闡述形成的導電連接件102可用於上述實施例中的任一者中。
在圖58A至圖58F所示的實施例中，在感光性黏著膜78的開口80中形成晶種層802。在感光性黏著膜78上形成光阻804，並將光阻804圖案化出暴露出連接件76的開口。導電層82及可回焊層84形成於光阻804中的開口中及連接件76上。因此，導電層82沿開口80的側面延伸。移除光阻804，且藉由例如CMP製程而移除位於開口80之外的導電層82及可回焊層84的過量材料。可在感光性黏著膜56的開口58中重複所述製程。隨後，如以上針對圖5A至圖6B所述，將感光性黏著膜56及78結合並使可回焊層62及84回焊。
在圖59A至圖59K所示的實施例中，在感光性黏著膜56的開口58中形成晶種層902。然後在晶種層902上形成光阻904。光阻904沿感光性黏著膜56延伸，且一些部分形成於開口58中。將光阻904圖案化出暴露出晶種層902的位於連接件54上的一些部分的開口。在用於形成導電層60的鍍覆製程中且在用於形成可回焊層62的鍍覆製程中使用晶種層902。晶種層902、 導電層60、以及可回焊層62的組合厚度T5可大於感光性黏著膜56的厚度T1。在形成導電層60及可回焊層62之後，移除光阻904以及晶種層902的被暴露出的部分。應注意，可回焊層62的寬度小於開口58的寬度，且因此在開口58中的光阻904被移除時，連接件54的一些部分被暴露出。
在基底72上形成光阻906，並將光阻906圖案化出暴露出連接件76的開口。執行例如乾式蝕刻或濕式蝕刻等金屬蝕刻製程以在連接件76中形成開口908。然後在開口908中形成導電層82及可回焊層84。導電層82及可回焊層84的組合厚度可大於或小於或小於開口908的深度，但不在後續形成的感光性黏著膜78的頂表面上方延伸。在所示的實施例中，以無電鍍覆製程在開口908中鍍覆導電層82及可回焊層84，但應理解，可在其他鍍覆製程中形成晶種層。然後移除光阻906，並形成感光性黏著膜78且將感光性黏著膜78圖案化出暴露出導電層82的開口。
然後將積體電路裝置50貼合至晶圓70。由於晶種層902、導電層60以及可回焊層62的厚度T5(參見圖59E)，可回焊層62延伸至感光性黏著膜78中的開口80中。在實施例中，在感光性黏著膜56固化之後但在感光性黏著膜78固化之前，貼合積體電路裝置50。如以上針對圖5A至圖6B所述，執行回焊製程，藉此形成被空氣隙106環繞的導電連接件102。回焊製程亦可固化感光性黏著膜78，藉此將感光性黏著膜56及78結合在一起。
在圖60A至圖60F所示的實施例中，在積體電路裝置 50的前側上形成晶種層952。然後在晶種層952上形成光阻954。將光阻954圖案化出暴露出晶種層952的位於連接件54上的一些部分的開口。在用於形成導電層60的鍍覆製程中且在用於形成可回焊層62的鍍覆製程中使用晶種層952。在形成導電層60及可回焊層62之後，移除光阻954以及晶種層952的被暴露出的部分。然後在基底52上且具體而言在可回焊層62之上形成感光性黏著膜56。然後在感光性黏著膜56中形成開口58，藉此暴露出導電層60以及可回焊層62。應注意，可回焊層62的寬度小於開口58的寬度，且因此在形成開口58時，連接件54的一些部分被暴露出。晶種層952、導電層60、以及可回焊層62的組合厚度T6可大於感光性黏著膜56的厚度T1。
然後將積體電路裝置50貼合至晶圓70。類似於上述實施例，可在晶圓70的連接件76中形成開口。由於晶種層952、導電層60以及可回焊層62的厚度T6，可回焊層62延伸至感光性黏著膜78中的開口80中。在所示的實施例中，在形成於連接件76中的開口中鍍覆導電層82及可回焊層84。在實施例中，在感光性黏著膜56固化之後但在感光性黏著膜78固化之前，貼合積體電路裝置50。然後固化感光性黏著膜78，藉此將感光性黏著膜56及78結合在一起。如以上針對圖5A至圖6B所述，執行回焊製程，藉此形成被空氣隙106環繞的導電連接件102。
圖61A至圖61B示出根據一些其他實施例，用於形成導電連接件102的製程。圖61B是圖61A所示的結構的俯視圖。在 所示的實施例中，將感光性黏著膜56及78圖案化，使得感光性黏著膜僅圍繞積體電路裝置50的周邊形成。因此，在結合及回焊之後，形成空腔1002，其中導電連接件102中的每一者被暴露至空腔1002。空腔1002可被形成有圍繞周邊的開口1004，開口1004提供空氣移動路徑。開口1004可具有約5微米至約50微米的寬度。在一些實施例中，在俯視圖中開口1004可被形成有彎折部，以防止包封體108流入空腔1002。
實施例可達成優點。形成空氣隙106在相鄰的導電連接件102之間生成緩衝空間，藉此使得導電連接件102能夠以更精細的節距形成。使用感光性黏著膜56及78可簡化面對面結合，從而減小製造成本。
在實施例中，一種半導體裝置包括：第一裝置，包括：積體電路裝置，具有第一連接件；第一感光性黏著層，位於所述積體電路裝置上；以及第一導電層，位於所述第一連接件上，所述第一感光性黏著層環繞所述第一導電層；第二裝置，包括：中介層，具有第二連接件；第二感光性黏著層，位於所述中介層上，所述第二感光性黏著層在實體上連接至所述第一感光性黏著層；以及第二導電層，位於所述第二連接件上，所述第二感光性黏著層環繞所述第二導電層；以及導電連接件，對所述第一導電層與所述第二導電層進行結合，所述導電連接件被空氣隙環繞。
在所述裝置的一些實施例中，所述第一導電層的第一寬度小於所述第二導電層的第二寬度。在所述裝置的一些實施例 中，所述導電連接件具有鄰近第一積體電路裝置的第一部分及鄰近第二積體電路裝置的第二部分，所述第一部分具有第一寬度，所述第二部分具有第二寬度。在所述裝置的一些實施例中，所述空氣隙將所述導電連接件的所述第二部分自所述第一感光性黏著層分隔開。在所述裝置的一些實施例中，在所述第一連接件與所述第一導電層之間或者在所述第一導電層與所述導電連接件之間不形成晶種層。在一些實施例中，所述裝置更包括：第一晶種層，形成於所述第一連接件與所述第一導電層之間，其中在所述第一導電層與所述導電連接件之間不形成晶種層。
在實施例中，一種形成半導體裝置的方法包括：在第一感光性黏著層中形成第一開口，所述第一感光性黏著層相鄰於第一積體電路裝置的第一側；在所述第一開口中鍍覆第一可回焊層；在第二感光性黏著層中形成第二開口，所述第二感光性黏著層相鄰於第二積體電路裝置的第一側；在所述第二開口中鍍覆第二可回焊層；將所述第一感光性黏著層與所述第二感光性黏著層按壓於一起，藉此對所述第一積體電路裝置與所述第二積體電路裝置進行實體連接；以及對所述第一可回焊層及所述第二可回焊層進行回焊，藉此形成對所述第一積體電路裝置與所述第二積體電路裝置進行電性連接的導電連接件。
在一些實施例中，所述方法更包括：以模塑化合物包封所述第一積體電路裝置，所述模塑化合物相鄰於所述第二積體電路裝置的所述第一側；將所述第一積體電路裝置單體化；形成相 鄰於所述第二積體電路裝置的第二側的重佈線結構；以及在所述重佈線結構上形成導電球。在一些實施例中，所述方法更包括：使用所述導電球將所述第二積體電路裝置結合至封裝基底。在一些實施例中，所述方法更包括：在第三感光性黏著層中形成第三開口，所述第三感光性黏著層相鄰於所述第一積體電路裝置的第二側；在所述第三開口中鍍覆第三可回焊層；以及使用所述第三感光性黏著層及所述第三可回焊層將第三積體電路裝置在實體上連接至所述第一積體電路裝置。在一些實施例中，所述方法更包括：在所述第二積體電路裝置的所述第一側上形成第一通孔；形成相鄰於所述第二積體電路裝置的第二側的重佈線結構，所述重佈線結構電性連接至所述第一通孔；在所述重佈線結構上形成導電連接件；以及將所述第一積體電路裝置及所述重佈線結構單體化。在一些實施例中，所述方法更包括：形成相鄰於所述第一積體電路裝置及所述第二積體電路裝置的第二通孔；以及以模塑化合物包封所述第一通孔及所述第二通孔。在所述方法的一些實施例中，在將所述第一可回焊層回焊之後，所述導電連接件被空氣隙環繞。
在實施例中，一種形成半導體裝置的方法包括：以第一模塑化合物包封多個第一積體電路裝置；在所述第一積體電路裝置之上形成第一感光性黏著層；在所述第一感光性黏著層中圖案化出第一開口；在所述第一開口中鍍覆第一導電層；在所述第一導電層上鍍覆第一可回焊層，所述第一導電層與所述第一可回焊 層的組合厚度小於所述第一感光性黏著層的第一厚度，所述第一導電層及所述第一可回焊層電性連接至所述第一積體電路裝置；將第二積體電路裝置按壓至所述第一感光性黏著層，以對所述第一積體電路裝置與所述第二積體電路裝置進行實體連接；以及對所述第一可回焊層進行回焊以形成對所述第一積體電路裝置與所述第二積體電路裝置進行電性連接的導電連接件。
在一些實施例中，所述方法更包括：在所述第一積體電路裝置之上形成第一重佈線結構，所述第一感光性黏著層是所述第一重佈線結構的最頂層，在對所述第一可回焊層進行回焊後，所述第二積體電路裝置結合至所述第一重佈線結構。在一些實施例中，所述方法更包括：將所述第一積體電路裝置放置於第二重佈線結構上。在一些實施例中，所述方法更包括：形成延伸穿過所述第一模塑化合物的通孔，所述通孔對所述第一重佈線結構與所述第二重佈線結構進行電性連接。在一些實施例中，所述方法更包括：以第二模塑化合物包封所述第二積體電路裝置；以及在所述第二積體電路裝置及所述第二模塑化合物之上形成第一重佈線結構。在一些實施例中，所述方法更包括：形成延伸穿過所述第二模塑化合物的通孔，所述通孔對所述第一重佈線結構與所述第一積體電路裝置進行電性連接。在所述方法的一些實施例中，在對所述第一可回焊層進行回焊後，所述導電連接件被空氣隙環繞。
以上概述了若干實施例的特徵，以使熟習此項技術者可 更佳地理解本發明的各個態樣。熟習此項技術者應知，其可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替、及變更。
52‧‧‧基底
54‧‧‧連接件
56‧‧‧感光性黏著膜
60‧‧‧導電層
72‧‧‧基底
74‧‧‧穿孔
76‧‧‧連接件
78‧‧‧感光性黏著膜
82‧‧‧導電層
102‧‧‧導電連接件
106‧‧‧空氣隙
G2‧‧‧間隙
W1、W2‧‧‧寬度

Claims (10)

  1. 一種半導體裝置，包括：第一裝置，包括：積體電路裝置，具有第一連接件；第一感光性黏著層，位於所述積體電路裝置上；以及第一導電層，位於所述第一連接件上，所述第一感光性黏著層環繞所述第一導電層；第二裝置，包括：中介層，具有第二連接件；第二感光性黏著層，位於所述中介層上，所述第二感光性黏著層在實體上連接至所述第一感光性黏著層；以及第二導電層，位於所述第二連接件上，所述第二感光性黏著層環繞所述第二導電層；以及導電連接件，對所述第一導電層與所述第二導電層進行結合，所述導電連接件被空氣隙環繞。
  2. 如申請專利範圍第1項所述的半導體裝置，其中在所述第一連接件與所述第一導電層之間或者在所述第一導電層與所述導電連接件之間不形成晶種層。
  3. 一種形成半導體裝置的方法，包括：在第一感光性黏著層中形成第一開口，所述第一感光性黏著層相鄰於第一積體電路裝置的第一側；在所述第一開口中鍍覆第一可回焊層； 在第二感光性黏著層中形成第二開口，所述第二感光性黏著層相鄰於第二積體電路裝置的第一側；在所述第二開口中鍍覆第二可回焊層；將所述第一感光性黏著層與所述第二感光性黏著層按壓於一起，藉此對所述第一積體電路裝置與所述第二積體電路裝置進行實體連接；以及對所述第一可回焊層及所述第二可回焊層進行回焊，藉此形成對所述第一積體電路裝置與所述第二積體電路裝置進行電性連接的導電連接件。
  4. 如申請專利範圍第3項所述的方法，更包括：以模塑化合物包封所述第一積體電路裝置，所述模塑化合物相鄰於所述第二積體電路裝置的所述第一側；將所述第一積體電路裝置單體化；形成相鄰於所述第二積體電路裝置的第二側的重佈結構；以及在所述重佈結構上形成導電球。
  5. 如申請專利範圍第3項所述的方法，更包括：在第三感光性黏著層中形成第三開口，所述第三感光性黏著層相鄰於所述第一積體電路裝置的第二側；在所述第三開口中鍍覆第三可回焊層；以及使用所述第三感光性黏著層及所述第三可回焊層將第三積體電路裝置在實體上連接至所述第一積體電路裝置。
  6. 如申請專利範圍第3項所述的方法，更包括：在所述第二積體電路裝置的所述第一側上形成第一通孔；形成相鄰於所述第二積體電路裝置的第二側的重佈結構，所述重佈結構電性連接至所述第一通孔；在所述重佈結構上形成導電連接件；以及將所述第一積體電路裝置及所述重佈結構單體化。
  7. 如申請專利範圍第3項所述的方法，其中在將所述第一可回焊層回焊之後，所述導電連接件被空氣隙環繞。
  8. 一種形成半導體裝置的方法，包括：以第一模塑化合物包封多個第一積體電路裝置；在所述第一積體電路裝置之上形成第一感光性黏著層；在所述第一感光性黏著層中圖案化出第一開口；在所述第一開口中鍍覆第一導電層；在所述第一導電層上鍍覆第一可回焊層，所述第一導電層與所述第一可回焊層的組合厚度小於所述第一感光性黏著層的第一厚度，所述第一導電層及所述第一可回焊層電性連接至所述第一積體電路裝置；將第二積體電路裝置按壓至所述第一感光性黏著層，以對所述第一積體電路裝置與所述第二積體電路裝置進行實體連接；以及對所述第一可回焊層進行回焊以形成對所述第一積體電路裝置與所述第二積體電路裝置進行電性連接的導電連接件。
  9. 如申請專利範圍第8項所述的方法，更包括：在所述第一積體電路裝置之上形成第一重佈結構，所述第一感光性黏著層是所述第一重佈結構的最頂層，在對所述第一可回焊層進行回焊後，所述第二積體電路裝置結合至所述第一重佈結構。
  10. 如申請專利範圍第8項所述的方法，更包括：以第二模塑化合物包封所述第二積體電路裝置；以及在所述第二積體電路裝置及所述第二模塑化合物之上形成第一重佈結構。
TW107137394A 2018-06-25 2018-10-23 半導體裝置及其形成方法 TWI685936B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/017,299 2018-06-25
US16/017,299 US10340249B1 (en) 2018-06-25 2018-06-25 Semiconductor device and method

Publications (2)

Publication Number Publication Date
TW202002214A TW202002214A (zh) 2020-01-01
TWI685936B true TWI685936B (zh) 2020-02-21

Family

ID=67069560

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107137394A TWI685936B (zh) 2018-06-25 2018-10-23 半導體裝置及其形成方法

Country Status (5)

Country Link
US (3) US10340249B1 (zh)
KR (1) KR102161031B1 (zh)
CN (1) CN110634847B (zh)
DE (1) DE102018116743B4 (zh)
TW (1) TWI685936B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI749920B (zh) * 2020-04-16 2021-12-11 台灣積體電路製造股份有限公司 半導體封裝及其形成方法
TWI813433B (zh) * 2022-08-31 2023-08-21 旺宏電子股份有限公司 半導體結構

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
TWI824467B (zh) 2016-12-14 2023-12-01 成真股份有限公司 標準大宗商品化現場可編程邏輯閘陣列(fpga)積體電路晶片組成之邏輯驅動器
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10734332B2 (en) * 2017-08-22 2020-08-04 Qualcomm Incorporated High aspect ratio interconnects in air gap of antenna package
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US10608642B2 (en) 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10340249B1 (en) * 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
CN109640521B (zh) * 2018-11-20 2020-06-30 奥特斯科技(重庆)有限公司 制造具有嵌入式集群的部件承载件的方法以及部件承载件
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11635566B2 (en) * 2019-11-27 2023-04-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of forming same
US11600526B2 (en) * 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
WO2022011622A1 (en) * 2020-07-16 2022-01-20 Yangtze Memory Technologies Co., Ltd. Methods for bonding semiconductor structures and semiconductor devices thereof
CN112435933B (zh) * 2020-12-03 2022-08-19 宝纳生(深圳)科技有限公司 一种cob封装结构及其制造方法
CN112509926B (zh) * 2020-12-03 2022-07-22 山东博通微电子有限公司 一种多芯片封装结构及其制造方法
US11658391B2 (en) 2020-12-21 2023-05-23 Qualcomm Incorporated Antenna module
CN113130420A (zh) * 2021-03-19 2021-07-16 南通越亚半导体有限公司 一种嵌埋封装结构及其制造方法
US20220375866A1 (en) * 2021-05-21 2022-11-24 Intel Corporation Hybrid conductive vias for electronic substrates
WO2023055429A1 (en) * 2021-09-29 2023-04-06 Microchip Technology Incorporated Integrated circuit package module including a bonding system
US11935824B2 (en) 2021-09-29 2024-03-19 Microchip Technology Incorporated Integrated circuit package module including a bonding system

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006295109A (ja) * 2005-03-14 2006-10-26 Citizen Watch Co Ltd 半導体装置とその製造方法
JP4454454B2 (ja) * 2004-06-29 2010-04-21 京セラ株式会社 半導体素子及びこの半導体素子を実装した半導体素子実装基板
KR101168511B1 (ko) * 2010-09-29 2012-07-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
TWI463573B (zh) * 2007-12-26 2014-12-01 Stats Chippac Ltd 半導體裝置及使用犧牲載體形成該裝置之方法
TWI472037B (zh) * 2005-01-28 2015-02-01 Semiconductor Energy Lab 半導體裝置，電子裝置，和半導體裝置的製造方法
US20150155255A1 (en) * 2013-11-29 2015-06-04 International Business Machines Corporation Substrate bonding and bump formation of a semiconductor device
TWI509703B (zh) * 2009-12-18 2015-11-21 Semiconductor Energy Lab 半導體裝置及其製造方法
US9245770B2 (en) * 2012-12-20 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of simultaneous molding and thermalcompression bonding
TWI538070B (zh) * 2010-08-16 2016-06-11 史達晶片有限公司 半導體裝置及形成具有由聚合物層隔開的導電層和導電通路之扇出式晶圓級晶片尺寸封裝的方法
TWI611582B (zh) * 2013-04-10 2018-01-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19749201A1 (de) 1997-11-07 1999-08-12 Degussa Verfahren zur intermolekularen Veretherung und zur Etherspaltung
US6190940B1 (en) 1999-01-21 2001-02-20 Lucent Technologies Inc. Flip chip assembly of semiconductor IC chips
EP1990833A3 (en) * 2000-02-25 2010-09-29 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
US7354798B2 (en) * 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
US6962835B2 (en) * 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US6982191B2 (en) * 2003-09-19 2006-01-03 Micron Technology, Inc. Methods relating to forming interconnects and resulting assemblies
US8563331B2 (en) * 2005-06-03 2013-10-22 E. I. Du Pont De Nemours And Company Process for fabricating and repairing an electronic device
EP1732116B1 (en) 2005-06-08 2017-02-01 Imec Methods for bonding and micro-electronic devices produced according to such methods
KR100609334B1 (ko) 2005-06-13 2006-08-08 삼성전자주식회사 감광성 폴리머가 갭필된 적층 회로부재 및 그의 제조 방법
US8759964B2 (en) 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US7993971B2 (en) * 2007-12-28 2011-08-09 Freescale Semiconductor, Inc. Forming a 3-D semiconductor die structure with an intermetallic formation
WO2011139619A1 (en) * 2010-04-26 2011-11-10 Hsio Technologies, Llc Semiconductor device package adapter
TWI502705B (zh) * 2009-08-19 2015-10-01 Xintec Inc 晶片封裝體及其製造方法
CN102859691B (zh) 2010-04-07 2015-06-10 株式会社岛津制作所 放射线检测器及其制造方法
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
US8884431B2 (en) 2011-09-09 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures for semiconductor devices
JP5636265B2 (ja) * 2010-11-15 2014-12-03 新光電気工業株式会社 半導体パッケージ及びその製造方法
WO2012070381A1 (ja) * 2010-11-22 2012-05-31 日本電気株式会社 実装構造及び実装方法
JP2012134318A (ja) * 2010-12-21 2012-07-12 Shinko Electric Ind Co Ltd 配線基板及び半導体装置と半導体装置の製造方法
CN102169845B (zh) * 2011-02-22 2013-08-14 中国科学院微电子研究所 一种用于三维封装的多层混合同步键合结构及方法
KR101828063B1 (ko) * 2011-05-17 2018-02-09 삼성전자주식회사 반도체 장치 및 그 형성방법
US8829676B2 (en) 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
CN103733330A (zh) 2011-08-01 2014-04-16 日本特殊陶业株式会社 半导体功率模块、半导体功率模块的制造方法、电路板
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US8680647B2 (en) 2011-12-29 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with passive devices and methods of forming the same
CN103426732B (zh) * 2012-05-18 2015-12-02 上海丽恒光微电子科技有限公司 低温晶圆键合的方法及通过该方法形成的结构
US8703542B2 (en) 2012-05-18 2014-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level packaging mechanisms
US9991190B2 (en) 2012-05-18 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging with interposer frame
US8809996B2 (en) 2012-06-29 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Package with passive devices and method of forming the same
US8785299B2 (en) 2012-11-30 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Package with a fan-out structure and method of forming the same
US8803306B1 (en) 2013-01-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package structure and methods for forming the same
US8778738B1 (en) 2013-02-19 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging devices and methods
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US8877554B2 (en) 2013-03-15 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices, methods of packaging semiconductor devices, and PoP devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9659891B2 (en) * 2013-09-09 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having a boundary structure, a package on package structure, and a method of making
JP2015122445A (ja) * 2013-12-24 2015-07-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9673119B2 (en) * 2014-01-24 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for bonding package lid
US9496196B2 (en) 2014-08-15 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods of manufacture thereof
US10319701B2 (en) * 2015-01-07 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded 3D integrated circuit (3DIC) structure
CN105185719B (zh) * 2015-06-24 2018-04-17 武汉新芯集成电路制造有限公司 一种锁扣式混合键合方法
US9911629B2 (en) * 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US10546836B2 (en) * 2016-09-22 2020-01-28 International Business Machines Corporation Wafer level integration including design/co-design, structure process, equipment stress management and thermal management
US10141253B2 (en) 2016-11-14 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10276505B2 (en) * 2017-03-08 2019-04-30 Samsung Electronics Co., Ltd. Integrated circuit device and method of manufacturing the same
US10163848B2 (en) * 2017-04-28 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package
US10522476B2 (en) * 2017-07-18 2019-12-31 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure, integrated fan-out package and method of fabricating the same
US10290611B2 (en) * 2017-07-27 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10340249B1 (en) * 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4454454B2 (ja) * 2004-06-29 2010-04-21 京セラ株式会社 半導体素子及びこの半導体素子を実装した半導体素子実装基板
TWI472037B (zh) * 2005-01-28 2015-02-01 Semiconductor Energy Lab 半導體裝置，電子裝置，和半導體裝置的製造方法
JP2006295109A (ja) * 2005-03-14 2006-10-26 Citizen Watch Co Ltd 半導体装置とその製造方法
TWI463573B (zh) * 2007-12-26 2014-12-01 Stats Chippac Ltd 半導體裝置及使用犧牲載體形成該裝置之方法
TWI509703B (zh) * 2009-12-18 2015-11-21 Semiconductor Energy Lab 半導體裝置及其製造方法
TWI538070B (zh) * 2010-08-16 2016-06-11 史達晶片有限公司 半導體裝置及形成具有由聚合物層隔開的導電層和導電通路之扇出式晶圓級晶片尺寸封裝的方法
KR101168511B1 (ko) * 2010-09-29 2012-07-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9245770B2 (en) * 2012-12-20 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of simultaneous molding and thermalcompression bonding
TWI611582B (zh) * 2013-04-10 2018-01-11 半導體能源研究所股份有限公司 半導體裝置及其製造方法
US20150155255A1 (en) * 2013-11-29 2015-06-04 International Business Machines Corporation Substrate bonding and bump formation of a semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI749920B (zh) * 2020-04-16 2021-12-11 台灣積體電路製造股份有限公司 半導體封裝及其形成方法
TWI813433B (zh) * 2022-08-31 2023-08-21 旺宏電子股份有限公司 半導體結構

Also Published As

Publication number Publication date
CN110634847B (zh) 2021-04-13
KR102161031B1 (ko) 2020-10-05
DE102018116743A1 (de) 2020-01-02
US20200411469A1 (en) 2020-12-31
US11929345B2 (en) 2024-03-12
CN110634847A (zh) 2019-12-31
DE102018116743B4 (de) 2023-11-09
KR20200000785A (ko) 2020-01-03
TW202002214A (zh) 2020-01-01
US10340249B1 (en) 2019-07-02
US20190393189A1 (en) 2019-12-26
US10770428B2 (en) 2020-09-08

Similar Documents

Publication Publication Date Title
TWI685936B (zh) 半導體裝置及其形成方法
KR102454016B1 (ko) 패키지 구조물 및 방법
US11721598B2 (en) Method of forming semiconductor device package having testing pads on an upper die
TWI670778B (zh) 封裝結構及其形成方法
TWI692838B (zh) 半導體封裝及其形成方法
TW202046479A (zh) 積體電路封裝及其製作方法
TW202209509A (zh) 積體電路封裝及其形成方法
TW202134713A (zh) 積體電路封裝及其形成方法
TW202117952A (zh) 半導體封裝件及製造方法
TWI803310B (zh) 積體電路元件和其形成方法
US20220262783A1 (en) Integrated Circuit Package and Method
US11810793B2 (en) Semiconductor packages and methods of forming same
TW202038396A (zh) 積體電路封裝體及其製造方法
US20230402403A1 (en) Semiconductor package and manufacturing method of semiconductor package
TWI776646B (zh) 積體電路封裝體及其形成方法
US12020997B2 (en) Methods of forming semiconductor device packages having alignment marks on a carrier substrate
TWI758129B (zh) 半導體封裝
TW202407951A (zh) 積體電路封裝及其製造方法