TWI537821B - 對每一核心提供電壓及頻率控制之技術 - Google Patents
對每一核心提供電壓及頻率控制之技術 Download PDFInfo
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Description
本發明係有關於對每一核心提供電壓及頻率控制之技術。
功率及熱能管理議題是電腦式系統之所有部段中需考量的因素。而於伺服器領域中,電力成本驅使行動系統電池組壽命中對低功率系統的需求,而熱能限制使該等議題有關。將一系統最佳化使得在最小功率耗損時達到最大效能通常使用該作業系統(OS)或系統軟體以控制硬體元件來完成。大多數現代OS使用該先進組態與功率介面(ACPI)標準,例如,2006年10月10日公佈之修訂版3.0b,以便於該等範圍最佳化該系統。一ACPI實施態樣可允許一處理器核心位於不同的省電狀態(亦稱為低功率或閒置狀態),通常參照為所謂C1至Cn狀態。類似的封裝C狀態存在於封裝準位的省電狀態但非OS可看見。
一核心作用中時,其於一所謂C0狀態下運作,而該核心閒置時,其可置於一核心低功率狀態,一所謂核心非零C狀態。該核心C1狀態代表最不省電但可幾乎立即進入或離開之低功率狀態,而一延伸的深低功率狀態(例如,C3)代表該靜止功率耗損可忽略之一功率狀態,但進入/離開該狀態及回應活動(亦即,回到C0)之時間較長。
除了省電狀態外,效能狀態或所謂P狀態亦於ACPI中提供。一核心位於一作用狀態(C0)時,該等效能狀態可允許效能功率準位的控制。一般而言,可有多個P狀態,即從P0-PN。一般而言,該ACPI P狀態控制演算法用來將功率耗損最佳化而不衝擊效能。對應P0之狀態可在該核心之一最大電壓及頻率組合時操作該核心,而每一P狀態,例如,P1-PN,可在不同的電壓及/或頻率組合時操作該核心。此方式中,該處理器根據該處理器之利用而作用中時,會出現一效能及功率耗損的平衡。一作用模式期間可使用不同的P狀態,針對在一多核心處理器之不同電壓及頻率操作的不同核心之獨立P狀態無任何功能,而因此,達到一所需的效能準位時無法獲得最佳省電狀態,因為最多所有作用中核心能夠於不同的頻率操作但其所有必須共享該相同電壓。
依據本發明之一實施例,係特地提出一種裝置,包含有:一包括多個核心以及一控制邏輯之處理器,該控制邏輯用以獨立控制將一電壓/頻率提供至該等多個核心之一第一核心,而與將一電壓/頻率提供至該等多個核心之至少一第二核心無關。
第1圖是一根據本發明之一實施例的一系統之方塊圖。
第2圖是一根據本發明之一實施例的一方法之流程圖。
第3圖是一根據本發明之另一實施例的一方法之流程圖。
第4圖是一根據本發明之一實施例的一處理器之方塊圖。
第5圖是一根據本發明之一實施例的一處理器核心之方塊圖。
第6圖是一根據本發明之一實施例的一系統之方塊圖。
於各種不同實施例中,具有一多核心架構之一處理器可,例如,根據一ACPI說明書來對每一核心提供功率效能(P)-狀態之控制。此方式中,可實現功率耗損及效能之較佳控制。例如,於一熱能限制環境中,於一多核心處理器中僅有數個核心可被賦能來於一較高核心頻率運作,使得降低功率耗損而因此降低溫度的情況下仍可執行一所欲工作負載。
因此於各種不同實施例中,一處理器中之多個核心的每一個可受控制來於一不同電壓及/或頻率操作。此方式中,非對稱工作負載可於該等多個核心執行以提供確定性的效能。本發明之範疇並不侷限於此方面,某些實施例中,該獨立電壓/頻率控制可使用一完全整合電壓調節器(FIVR)的實施態樣來實現,其中一處理器中之每一核心具有其本身的電壓調節器。亦即,包括多個核心之一單一半導體晶粒可進一步包括多個獨立的電壓調節器,每一調節器與一給定核心相關聯。此外,一或更多額外的電壓調節器可被提供來與一處理器中之其他構件一起使用,諸如非核心邏輯、記憶體控制器邏輯、功率控制單元、等等。當然,某些實施例中,一單一電壓調節器可與一處理器中之一或更多核心及/或其他構件相關聯。於一實施例中,可針對一處理器之非核心電路來提供一專屬電壓調節器,其允許該非核心於一不同電壓及頻率運作。針對一計算中心的工作負載,該非核心可於一較低電壓及頻率運作,導致將省電狀態應用在一插槽準位之較高核心頻率。針對記憶體及IO密集的工作負載,該非核心可於一較高電壓及頻率運作,而該等核心可於較低電壓/頻率運作,以補償該非核心之較高功率。
某些實施例中,ACPI表格可延伸來包括有關該等個別整合電壓調節器之資訊以便將每一核心P-狀態控制賦能。例如,一4位元欄位可用來傳遞P-狀態資訊並將其對映至每一調節器之控制電壓邏輯。因此使用本發明之實施例,針對一非對稱工作負載,每一核心可受控制來於一不同頻率及/或電壓操作。如一範例中,多個核心其中之一或某些核心可受控制來於較高頻率及/或電壓操作而其他核心可受控制來於較低電壓/頻率的組合操作而因此可位於一給定熱能設計功率(TDP)封套中。此方式中,針對給定的工作負載可實現確定性及最佳化效能功能的選擇。
例如,以一第一方法來尋找一較高效能準位以處理資料之核心可於一較高電壓/頻率操作,該類核心可執行諸如資料處理的使用,諸如資料複製服務、資料分析學、同位計算等等之任務,而執行,例如,管理任務之核心可於較低電壓/頻率操作以針對一TDP限制的環境提供一最佳化混合。因此可能(以及一所謂加速模式)給定一熱能或TDP預算時,並非於一較高頻率來機會性地運作所有核心,本發明實施例以一個別核心的基礎上來提供確定性的行為。
現參照第1圖,其顯示一根據本發明之一實施例的一系統之一部分的方塊圖。如第1圖所示,系統100可包括各種不同構件,包括如圖所示為一多核心處理器之一處理器110。處理器110可經由一外部電壓調節器160耦合至一電源供應器150,該調節器可執行一第一電壓轉換以便將一主要調節電壓提供至處理器110。
如圖所示,處理器110可以是包括多個核心120a-120n之一單一晶粒處理器。此外,每一核心可與一個別電壓調節器125a-125n相關聯。因此,可提供一完全整合電壓調節器(FIVR)的實施態樣來允許細分電壓控制以及每一個別核心之功率及效能。
再次參照第1圖,該處理器中可存有額外構件,包括一輸入/輸出介面132、另一介面134、以及一整合記憶體控制器136。如圖示,該等每一構件可由另一整合電壓調節器125x來供電。於一實施例中,介面132可根據英代爾快速路徑互連(QPI)協定,其於包括包含一實體層、一鏈接層以及一協定層之多個層的一快取同調協定中提供點對點(PtP)鏈接。接著,介面134可根據一快速週邊構件互連(PCIeTM)說明書,例如,該快速PCITM說明書基礎說明書第2.0版(2007年一月17日發布)。應了解為了簡化舉例解說而不顯示額外的構件,但其可存在處理器110中,諸如非核心邏輯、一功率控制單元、以及其他構件,諸如內部記憶體,例如,一快取記憶體階層之一或更多準位等等。此外,雖然以一整合電壓調節器顯示於第1圖之實施態樣中,但其他實施例並不受限於此。
現參照第2圖,其顯示一根據本發明之一實施例的一方法之流程圖。於一實施例中,方法200可由諸如一處理器之一整合功率控制單元(PCU)之一控制器來執行。然而,應了解本發明之範疇並不侷限於此方面,而方法200可由一系統中之其他控制器,諸如一管理引擎來執行。
參照第2圖,方法200可藉由於該PCU接收一效能狀態改變要求來開始(方塊210)。例如,許多實施態樣中,該要求可從該OS或系統軟體來接收。如一範例中,該要求可對應改變一或更多核心之一P-狀態的一要求。亦即,該類實施態樣中,該OS可察覺本發明之實施例提供的每一核心P-狀態之控制。其他實施例中,即使該OS或系統軟體無法察覺該特徵,如本文所述一效能狀態改變要求仍可被接收及處置。
於菱形220中,其可決定是否要求效能增加。亦即,該要求可為一較高效能準位之一識別(例如,對應一較低於目前P-狀態諸如從該P1狀態進入該P0狀態之一要求)。亦應注意該決定亦可確認其可能從該目前狀態來改變P-狀態。若是如此,控制流程經過方塊230。方塊230中,可作關於選擇一或更多核心來增加其電壓的一決定而與至少另一核心無關(方塊230)。如該決定之範例中,該PCU可根據TDP邊限來決定增加電壓及相關頻率,該邊限係根據諸如整體晶粒電流、功率、溫度、及微型架構活動(諸如負載/儲存緩衝器、一執行緒排程器等等)之各種不同因素。例如,決定一多核心處理器之一部分較冷(而於較低電壓/頻率操作)時,該部分中之一核心可選擇來增加電壓及頻率。
決定選擇來增加電壓之該一或更多核心時,控制流程經過方塊240,其中針對該(等)選擇的核心可計算一新的電壓及頻率。該類計算可至少部分根據該處理器之一TDP說明書、Icc頂部空間等等。
再次參照第2圖,控制流程經過下一方塊250,其中該新電壓之一控制信號可傳送至與該核心或多個核心相關聯之電壓調節器。如一範例中,該控制信號可為一數位控制信號或者其可為一類比信號,因此使該電壓調節器啟動改變至一不同的電壓準位。因此,與該(等)核心相關聯之該FIVR可調整為將一更新的電壓輸出至該核心。於是,控制流程經過方塊260,其中該核心可於該選擇電壓操作。應注意因為許多實施例中該電壓調節器可整合於該處理器中,所以相較於一晶片外調節器,該調整可偕同降低潛伏出現。
若反而菱形220中其決定要求效能降低,則控制流程經過方塊270。方塊270中,可作有關選擇一或更多核心來降低電壓的一決定而與至少另一核心無關(方塊270)。該類決定可根據諸如上述之因素,並可包括決定允許移動至一不同的P-狀態。
決定選擇來降低電壓之該一或更多核心時,控制流程經過方塊275,其中針對該(等)選擇的核心可計算一新的電壓及頻率。控制流程經過下一方塊280,其中該新電壓之一控制信號可傳送至與該核心或多個核心相關聯之電壓調節器,使與該(等)核心相關聯之該FIVR可將一降低的電壓輸出至該核心。於是,控制流程經過方塊290,其中該核心可於該選擇電壓操作。雖然本案以第2圖之實施例中的特別實施態樣來顯示,但應了解本發明之範疇並不侷限於此方面。例如,上述說明係假設該PCU及該等核心為,例如,一多核心處理器之相同半導體晶粒的一部分。其他實施例中,該等核心可位於相同多晶片封裝體但獨立的晶粒上。另外其他實施例中,核心可位於分開的封裝體但具有其共同受控制,例如,使用協調電壓調節器之電壓/頻率。
一替代實施例為一處理器不包括整合調節器之一實施態樣。該類處理器中,實施例仍適於提供每一核心P-狀態控制。為此目的,反而方塊250或280中,針對不同電壓之控制信號可直接提供至,例如,該等核心,其中該等核心可根據該接收一電壓來提供電壓調整。另一實施例中,方塊250或280中,針對該改變電壓之控制信號可於晶片外提供至一外部電壓調節器。該控制信號可於一單一接腳或多個接腳上發送,其中該等多個接腳之每一個與一不同的電壓準位相關聯而使該外部電壓調節器提供多個電壓的其中之一。特別是,該類實施態樣中,該外部電壓調節器可輸出多個電壓信號,其可耦合至該處理器並依次,例如,耦合至該處理器之一電壓傳輸邏輯,並可進一步從該功率控制單元接收控制信號而因此使選擇的電壓提供至如該功率控制單元所決定之該對應核心。
另外於其他實施例中,例如,於一多OS系統中,其中若干核心可專屬於一OS而一不同數量之核心可專屬於一不同OS,一OS領域中之每一核心可靜態設定為一固定(而可能不同的)V/F,而另一OS領域中之核心可於操作期間動態改變V/F。例如,一OS領域可專屬於諸如一系統之管理操作的決定性操作,而因此可從固定V/F控制來獲益。相對之下,根據本發明之一實施例,可執行各種不同的使用者準位應用之一OS領域可具有非決定性工作負載,而因此可從動態獨立的V/F控制來獲益。
某些實施例中,針對核心V/F之動態控制,該CPU可獨立於該OS來監控微型架構活動並決定一或更多核心之V/F是否可根據該所需的負載要求來被動態改變以降低/增加功率。
現參照第3圖,其顯示一根據本發明之一實施例的一方法之流程圖。如第3圖所示,方法300可由一處理器之一功率控制單元來執行。因此一OS無法察覺本發明之一實施例提供的每一核心P-狀態能力時該方法300是適當的。另外其他實施例中,該OS察覺該P-狀態能力的情況中,方法300可連結上述方法200來執行以提供改善的核心P-狀態之動態控制。
如第3圖所示,方法300可藉由監控一或更多核心之微型架構活動來開始(方塊310)。而本發明之範疇並不侷限於此方面,該類活動可包括決定於一時間視窗中執行的若干指令、撤回每一時間視窗等等。
用以回應從該微型架構活動取得之資訊,可由該功率控制單元來執行一分析。更特別是,方塊320中該功率控制單元可分析該活動以及該處理器之一負載需求。例如,該負載需求可根據有關排程至該等核心之執行緒數量以及該等執行緒受排程之程序類型的資訊。
控制流程之後經過菱形330,其中該功率控制單元可決定一或更多核心之電壓/頻率的至少其中之一作動態調整是否適當。例如,若該等活動及該負載需求指出功率及效能間之一適當交替已出現,則該功率控制單元可選擇不動態調整任何的電壓/頻率組合。因此,方法300可結束。
否則,若決定調整一給定核心之至少一個電壓/頻率對,則控制流程不經過方塊340。而針對該選擇的核心來計算一新的電壓及頻率對。
再次參照第3圖,控制流程經過下一方塊350,其中該新電壓之一控制信號可傳送至與以一新電壓來更新之該核心或多個核心相關聯的電壓調節器。此方式中,與該(等)核心相關聯之該FIVR可調整為將一更新的電壓輸出至該核心。於是,控制流程經過方塊360,其中該核心可於該選擇電壓操作。雖然本案以第3圖之實施例中的特別實施態樣來顯示,但應了解本發明之範疇並不侷限於此方面。
例如,其他實施例中,不僅一或更多核心之V/F可動態改變,而且該非核心頻率及電壓可改變來支援該所需的核心V/F需求。該非核心頻率無法被一OS看見,但可有助於該整體的晶粒省電狀態。該非核心省電狀態可應用在核心功率導致增加的核心效能。同樣地,該核心省電狀態可應用在增加的非核心電壓/頻率以適於需要較高非核心頻率之工作負載。某些實施態樣中,該動態非核心改變可使用第3圖之方法300來執行。
現參照第4圖,其顯示一根據本發明之一實施例的一處理器之方塊圖。如第4圖所示,處理器400可以是包括多個核心410a-410n之一多核心處理器。於一實施例中,每一該類核心可組配來於多個電壓及/或頻率操作。此外,如上所述,每一核心可獨立受控制來於一選擇的電壓及/或頻率操作。為此目的,每一核心可與一對應電壓調節器412a-412n相關聯。該等各種不同的核心可經由一互連體415來耦合至包括各種不同構件之一非核心420。如圖所示,該非核心420可包括可為一末級快取記憶體之一共享快取記憶體430。此外,該非核心可包括一整合記憶體控制器440、各種不同介面450以及一功率控制單元455。
於各種不同實施例中,功率控制單元455可與OS功率管理碼通訊。例如,根據從該OS接收之一要求以及有關該等核心處理之工作負載的資訊,功率控制單元455可決定一適當的電壓及頻率組合來操作諸如上述有關第2圖之該等每一核心。例如,功率控制單元455可包括具有項目之一表格,其每一項目關聯每一核心執行之一電壓及頻率。此外,單元455可包括具有有關一TDP或其他熱能預算之資訊的一儲存器。根據該所有資訊,功率控制單元455可動態及獨立地控制至一或更多核心之一頻率及/或電壓來賦能確定性操作以及提供該等核心之非對稱工作負載,而維持在該TDP預算中,並且更不需要機會性加速模式操作。因此為回應該類計算,功率控制單元455可產生多個控制信號使該等電壓調節器來因此控制提供至該等對應核心之電壓。
此外,功率控制單元455可獨立決定電壓/頻率之一改變適合如上述有關第3圖之一或更多核心。某些實施態樣中,功率控制單元455執行之分析可至少部分根據可為該功率控制單元之一部分的一活動監控邏輯決定之預測資訊。該邏輯可包括一緩衝器以儲存與操作核心相關聯之資訊。該活動監視器可從有關其目前活動準位之各種不同核心來接收進入的資料。該活動監視器之緩衝器可以各種不同方式來安排。於一實施例中,該緩衝器可配適成針對每一核心來儲存與每一功率狀態改變事件相關聯之一時間戳記的指示。該活動監視器因此截取並將核心進入及離開給定活動狀態之事件加上時間戳記。該監控資料可因此包括時間戳記資料以及該活動狀態以指出,儲存區間期間每一核心位於一給定狀態的時間,並可提供至,例如,該功率控制單元之一預測器,其可使用該資訊來決定該下一區間之預測核心狀態,其可用於選擇操作該(等)核心之獨立的頻率及/或電壓。
再次參照第4圖,處理器400可例如,經由一記憶體匯流排來與一系統記憶體460通訊。此外,由介面450,可達成與諸如週邊設備、大量儲存器等等之各種不同的晶片外構件之連接。雖然本案以第4圖之實施例中的特別實施態樣來顯示,但應了解本發明之範疇並不侷限於此方面。
現參照第5圖,其顯示一根據本發明之一實施例的一處理器核心之方塊圖。如第5圖所示,處理器核心500可為一多階段管線亂序處理器。如第5圖所示,核心500可操作由整合電壓調節器509產生之各種不同的電壓及頻率。於各種不同實施例中,該調節器可,例如,從一外部電壓調節器接收一進入的電壓信號,並可進一步,例如,從耦合至核心500之非核心邏輯接收一或更多控制信號。
如第5圖所示,核心500包括前端單元510,其可用來提取待執行指令並可將其準備來供該處理器稍後使用。例如,前端單元510可包括一提取單元501、一指令快取記憶體503、以及一指令解碼器505。某些實施態樣中,前端單元510可進一步包括一追蹤快取記憶體,以及微碼儲存器與一微操作儲存器。提取單元501可,例如,從記憶體或指令快取記憶體503提取巨集指令並將其饋送至指令解碼器505來解碼為基元,亦即,該處理器執行之微操作。
前端單元510與執行單元520間之耦合是可用來接收該等微指令並準備執行之一亂序(OOO)引擎515。更特別是OOO引擎515可包括各種不同的緩衝器來重新排列微指令串流並配置執行所需之各種不同資源、以及提供諸如暫存器檔案530與延伸暫存器檔案535之各種不同暫存器檔案中的儲存器位置之邏輯暫存器重新命名。暫存器檔案530可包括用於整數及浮點數操作之分開的暫存器檔案。延伸暫存器檔案535可提供儲存器給向量尺寸單元,例如,256或512位元的每一暫存器。
各種不同的資源可存在執行單元520中,包括,例如,各種不同的整數、浮點、以及單一指令多重資料(SIMD)邏輯單元、等等的專用硬體。例如,該類執行單元可包括一或更多算術邏輯單元(ALU)522、等等的該類執行單元。
來自該等執行單元之結果可提供至撤回邏輯,亦即,一重新排序緩衝器(ROB)540。更特別是,ROB 540可包括各種不同的陣列及邏輯來接收與執行指令相關聯的資訊。該資訊之後可由ROB 540檢查以決定該等指令是否可被正常撤回以及結果資料是否提交至該處理器之架構狀態、或者是否出現防止該等指令適當撤回之一或更多異常。當然,ROB 540可處置與撤回相關聯之其他操作。
如第5圖所示,ROB 540耦合至一快取記憶體550,於一實施例中,其可為一低準位快取記憶體(例如,一L1快取記憶體),但本發明之範疇並不侷限於此方面。此外,執行單元520可直接耦合至快取記憶體550。從快取記憶體550,資料通訊可偕同較高準位快取記憶體、系統記憶體等等來出現。雖然以第5圖之實施例中的高準位來顯示,但應了解本發明之範疇並不侷限於此方面。例如,雖然第5圖之實施態樣係有關諸如一所謂x86指令集架構(ISA)之一亂序機器,但本發明之範疇並不侷限於此方面。亦即,其他實施例可以一循序處理器、諸如一ARM式處理器之一縮減指令集計算(RISC)處理器、或可經由一仿真引擎及相關聯邏輯電路來仿真一不同ISA之指令及操作的另一ISA類型的處理器來執行。
該等實施例可以許多不同的系統類型來執行。現參照第6圖,其顯示一根據本發明之一實施例的一系統之方塊圖。如第6圖所示,多處理器系統600為一點對點互連系統,並包括經由一點對點互連體650耦合之一第一處理器670及一第二處理器680。如第6圖所示,處理器670及680之每一個可為多核心處理器,包括第一及第二處理器核心(亦即,處理器核心674a及674b以及處理器核心684a及684b),但該等處理器可潛在存有許多更多核心。使用存在該處理器中之多個獨立電壓調節器(第6圖之實施例中為了簡化舉例解說而未顯示),該等每一核心可於獨立電壓/頻率操作。
再次參照第6圖,第一處理器670更包括一記憶體控制器集線器(MCH)672以及點對點(P-P)介面676及678。同樣地,第二處理器680包括一MCH 682以及P-P介面686及688。如第6圖所示,MCH 672及682將該等處理器耦合至個別的記憶體,即是一記憶體632及一記憶體634,其可為本地附接於該等個別處理器之系統記憶體(例如,DRAM)之一部分。第一處理器670及第二處理器680可個別經由P-P互連體652及654來耦合至一晶片組690。如第6圖所示,晶片組690包括P-P介面694及698。
此外,晶片組690包括一介面692來由一P-P互連體639耦合晶片組690與一高效能圖形引擎638。再者,晶片組690可包括一介面695,其可為一儲存器控制器來與一儲存器619介接。接著,晶片組690可經由一介面696耦合至一第一匯流排616。如第6圖所示,各種不同輸入/輸出(I/O)設備614可耦合至第一匯流排616、以及將第一匯流排616耦合至一第二匯流排620之一匯流排橋接器618。各種不同設備可耦合至第二匯流排620,包括,例如,一鍵盤/滑鼠622、通訊設備626以及一資料儲存單元628,諸如一磁碟機或於一實施例中可包括編碼630之其他大量儲存設備。此外,一聲頻I/O 624可耦合至第二匯流排620。該等實施例可併入其他類型的系統,包括諸如一智慧型行動電話、平板電腦、輕薄筆電、等等的行動設備。
該等實施例可以編碼來執行並可儲存於一儲存媒體中,其儲存之指令可用來規劃一系統來執行該等指令。該儲存媒體可包括,但不侷限於,諸如磁碟之任何類型的非過渡儲存媒體,包括軟碟、光碟、固態驅動器(SSD)、光碟唯讀記憶體(CD-ROM)、可寫入光碟(CD-RW)、以及磁性光碟、半導體設備,諸如唯讀記憶體(ROM)、隨機存取記憶體(RAM),諸如動態隨機存取記憶體(DRAM)、靜態隨機存取記憶體(SRAM)、可抹除可程式化唯讀記憶體(EPROM)、快閃記憶體、電子可抹除可程式化唯讀記憶體(EEPROM)、磁性或光學卡、或適合儲存電子指令之任何其他類型的媒體。
本發明已相關有限數量之實施例來說明,業界熟於此技者可體認其可作許多修改及變化型態。可期待在本發明之真實精神及範疇中,該等後附申請專利範圍仍涵蓋所有該類修改及變化型態。
100...系統
110、400...處理器
120a-120n、410a-410n...核心
125a-125n、160、412a-412n、509...電壓調節器
132...輸入/輸出介面
134、450、692、695、696...介面
136、440...整合記憶體控制器
150...電源供應器
200、300...方法
210、230、240、250、260、270、275、280、290、310、320、340、350、360...方塊
220、330...菱形
415...互連體
420...非核心
430、550...快取記憶體
455...功率控制單元
460...系統記憶體
500、684a、684b...處理器核心
501...提取單元
503...指令快取記憶體
505...指令解碼器
510...前端單元
515...亂序引擎
520...執行單元
522...算術邏輯單元
530...暫存器檔案
535...延伸暫存器檔案
540...重新排序緩衝器
600...多處理器系統
614...輸入/輸出設備
616...第一匯流排
618...匯流排橋接器
619...儲存器
620...第二匯流排
622...鍵盤/滑鼠
624...聲頻I/O
626...通訊設備
628...資料儲存單元
630...編碼
632、634...記憶體
638...高效能圖形引擎
639、650、652、654...點對點互連體
670...第一處理器
672、682...記憶體控制器集線器
674a...第一處理器核心
674b...第二處理器核心
676、678、686、688、694、698...點對點介面
680...第二處理器
690...晶片組
第1圖是一根據本發明之一實施例的一系統之方塊圖。
第2圖是一根據本發明之一實施例的一方法之流程圖。
第3圖是一根據本發明之另一實施例的一方法之流程圖。
第4圖是一根據本發明之一實施例的一處理器之方塊圖。
第5圖是一根據本發明之一實施例的一處理器核心之方塊圖。
第6圖是一根據本發明之一實施例的一系統之方塊圖。
100...系統
110...處理器
120a-120n...核心
125a-125n、160...電壓調節器
132...輸入/輸出介面
134...介面
136...整合記憶體控制器
150...電源供應器
Claims (15)
- 一種處理器,包含有:多核處理器,其具有單一半導體晶粒,該單一半導體晶粒包括多個核心、多個整合電壓調節器,其各與該等多個核心的其中之一相關聯且各將獨立電壓提供至該等多個核心的至少其中之一,以及控制邏輯,該控制邏輯用以接收來自作業系統(OS)的效能狀態改變要求,以於OS操作期間動態更新該等多個核心的一或多個核心的電壓/頻率,該控制邏輯用以至少部分根據工作負載、熱能設計功率(TDP)邊限和該第一核心所在於該單一半導體晶粒的部分之溫度來決定是否更新該等多個核心的第一核心的電壓/頻率,以及控制提供至該第一核心的該電壓/頻率與提供至該等多個核心之至少一第二核心的電壓/頻率,其中該控制邏輯用以將控制信號提供至該等多個整合電壓調節器之每一個用以使該對應整合電壓調節器能夠將獨立電壓提供至該對應核心,以及其中第一電壓調節器係被耦合至該多核心處理器用以將第一調節電壓提供至該等多個整合電壓調節器。
- 如申請專利範圍第1項之處理器,其中該控制邏輯包括該處理器之非核心部分的功率控制單元。
- 如申請專利範圍第2項之處理器,其中該OS察覺提供至該等多個核心的該電壓/頻率之獨立控制。
- 如申請專利範圍第2項之處理器,其中該功率控制單元包括活動監視器,用以監視該等多個核心之微型架構 操作以及根據該微型架構監視來動態選擇該等多個核心的至少其中之一以對此提供更新的電壓/頻率,且與提供該效能狀態改變要求之作業系統(OS)無關。
- 一種方法,包含有下列步驟:於處理器之功率控制單元接收效能狀態改變要求,用以在操作期間動態調整提供至該處理器之至少一核心的電壓/頻率;選擇該處理器之該至少一核心來獨立調整對此提供的電壓/頻率而與該處理器之至少一個其他核心無關;針對該調整電壓將控制信號傳送至與該選擇核心相關聯之整合電壓調節器,用以使該核心能夠於該調整電壓操作;以及針對包括該至少一核心之該處理器的第一組核心來動態控制獨立電壓/頻率,以及靜態控制包括該至少一其他核心之該處理器的第二組核心,用以接收固定電壓/頻率,其中該第一組核心係與第一作業系統相關聯且該第二組核心係與第二作業系統相關聯。
- 如申請專利範圍第5項之方法,更包含選擇該至少一核心來確定性地而非機會性地調整對此提供之電壓/頻率。
- 如申請專利範圍第5項之方法,更包含調整第一組多個核心用以獨立執行於增加的電壓/頻率而與第二組多個核心無關,使得針對該處理器之熱能設計功率(TDP)預算得以維持。
- 如申請專利範圍第5項之方法,更包含從該第一作業系統來接收該效能狀態改變要求,其中該第一作業系統無法察覺該處理器之獨立電壓控制能力。
- 如申請專利範圍第5項之方法,其中該第一作業系統係用以執行非確定性操作且該第二作業系統係用以執行確定性操作。
- 如申請專利範圍第9項之方法,其中該非確定性操作包含使用者準位應用且該確定性操作包含管理操作。
- 一種系統,包含有:處理器,其包括多個核心、多個整合電壓調節器,每一調節器獨立將電壓提供至該等多個核心的至少其中之一,以及功率控制單元,其至少部分根據該處理器之工作負載、熱能設計功率(TDP)、和該至少一些核心所在的該處理器的晶粒的部分之溫度來控制該等多個整合電壓調節器,用以在作業系統操作期間,動態調整提供至該等多個核心的至少某些核心的一或多個獨立電壓,該處理器於單一半導體晶粒上形成;耦合至該處理器之外部電壓,用以將第一電壓提供至該等多個整合電壓調節器;以及耦合至該處理器之動態隨機存取記憶體(DRAM)。
- 如申請專利範圍第11項之系統,其中該功率控制單元包括活動監視器,用以監視該等多個核心之微型架構操作以及根據該監視來動態選擇該等多個核心的至少其中之一,以對此提供更新的電壓/頻率。
- 如申請專利範圍第11項之系統,其中該功率控制單元係用於造成提供至該處理器之非核心邏輯的電壓/頻率之動態調整,用以能夠省電,該非核心邏輯包括該功率控制單元,而其中該非核心邏輯操作之電壓及頻率無法被該作業系統看見,且用以應用該省電來造成提供至該等多個核心的至少其中之一的電壓/頻率之動態調整。
- 如申請專利範圍第11項之系統,其中該功率控制單元包括活動監視器,用以監視該等多個核心之微型架構操作以及動態選擇該等多個核心的至少其中之一以對此提供更新的電壓/頻率,而其中至少一個其他核心係被提供固定電壓/頻率。
- 如申請專利範圍第14項之系統,其中該功率控制單元係用於根據來自該活動監視器之資訊而預測於未來時間週期該至少一核心之使用。
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