TWI525720B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TWI525720B
TWI525720B TW102148373A TW102148373A TWI525720B TW I525720 B TWI525720 B TW I525720B TW 102148373 A TW102148373 A TW 102148373A TW 102148373 A TW102148373 A TW 102148373A TW I525720 B TWI525720 B TW I525720B
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Taiwan
Prior art keywords
protective layer
package
forming
via electrodes
semiconductor device
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TW102148373A
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TW201436067A (zh
Inventor
洪瑞斌
林俊成
蔡柏豪
林儀柔
陳碩懋
葉炅翰
葉德強
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其形成方法
本發明係有關一種半導體技術，且特別有關一種半導體裝置及其形成方法。
自積體電路發明以來，由於各種電子部件(即電晶體、二極體、電阻、電容等)之集積度不斷的改良，半導體產業已經歷持續且快速的成長。主要來說，這些集積度的改良來自於最小特徵尺寸一再的微縮，使得更多部件能被整合至特定的晶片區域內。
由於集積部件所佔據的體積基本上位於半導體晶圓的表面，此種集積度的改良本質上為二維(2D)的形式。雖然微影製程的大幅進步使二維積體電路製造有顯著的改良，在二維中所能達到的密度仍有其物理限制。其中一種限制為製造這些部件所需的最小尺寸。此外，當更多裝置置於同一晶片中時，亦需要更複雜的設計。另一額外的限制為當裝置數量增加時，裝置之間的內連線數量與長度亦會隨之大量增加。當內連線的數量與長度增加時，會同時增加線路的訊號延遲(RC delay)與功率消耗。
三維積體電路(3DICs)因此而形成，其中可堆疊兩 晶片或封裝體，並藉由形成於其中之一晶片或封裝體內的矽通孔電極(through-silicon vias,TSVs)來連結另一晶片至其他基板。層疊封裝(Package on Package,PoP)因可形成更高密度的電子產品，其已成為日益普遍的積體電路封裝技術。
本發明之實施例係揭示一種半導體裝置的形成方法，包括：於一承載基板上形成一保護層；形成複數個通孔電極，其自保護層向上延伸；貼附一或多個晶片至保護層；於此些通孔電極與一或多個晶片之間形成一模封化合物；電性耦接複數個電性連接體至此些通孔電極與一或多個晶片上的複數個電性接點；以及剝除承載基板並暴露保護層。
本發明之另一實施例係揭示一種半導體裝置，包括：一第一封裝體，包括：一或多層重佈線層；一或多個積體電路晶片，位於一或多層重佈線層上；一模封化合物，鄰近於一或多個積體電路晶片側壁；複數個通孔電極，延伸穿過模封化合物；以及一保護層，位於一或多個積體電路晶片上；以及一第二封裝體，裝設於第一封裝體上，第二封裝體係電性耦合至此些通孔電極。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
102‧‧‧承載基板
104‧‧‧黏著層
106‧‧‧保護層
208‧‧‧晶種層
310‧‧‧圖案化罩幕
412‧‧‧通孔電極
614‧‧‧第一積體電路晶片
616‧‧‧晶片貼附膜
716‧‧‧模封化合物
818‧‧‧重佈線層
820‧‧‧第一組電性連接體
922‧‧‧承載膠帶
1024‧‧‧接觸墊開口
1126‧‧‧第一積體電路封裝體
1128‧‧‧第二積體電路封裝體
1130‧‧‧積體電路晶片
1132‧‧‧封裝基板
1134‧‧‧第二組電性連接體
1136‧‧‧底膠材料
2402、2404、2406、2408、2410、2412、2414、2416、2502、2504、2506、2508、2510、2512、2514、2602、2604、2606、2608‧‧‧步驟
第1-11圖為根據本發明一實施例之一封裝體在不同中間製 造階段的剖面示意圖。
第12-18圖為根據本發明另一實施例之一封裝體在不同中間製造階段的剖面示意圖。
第19-22圖為根據本發明又一實施例之一封裝體在不同中間製造階段的剖面示意圖。
第23圖為根據本發明又另一實施例之一封裝體剖面示意圖。
第24圖為根據本發明一些實施例之方法流程圖。
第25圖為根據本發明另一些實施例之方法流程圖。
第26圖為根據本發明另一些實施例之方法流程圖。
以下詳細說明本發明實施例之製作與使用。然而，可輕易了解本發明提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅為示例性而非用以侷限本發明的範圍。
本發明在此提供一種新穎的三維積體電路(3DIC)及其製造方法，並說明本發明實施例之中間製造階段及討論本發明實施例之各種變化。在不同圖式及示例性實施例中，相似部件標號係用以表示類似的部件。
第1-11圖為一層疊封裝(PoP)結構在不同中間製造階段的剖面示意圖。在本實施例中，於下封裝體內的積體電路晶片上形成保護層(如聚苯噁唑(polybenzoxazole,PBO)層)，其中保護層係在下封裝體的上表面上延伸。接著，於保護層內形成複數個開口使其可形成電性連接。
首先參照第1圖，其繪示具有黏著層104的承載基板102及形成於其上的保護層106。一般來說，承載基板102可在如後所述的製程步驟中提供暫時的機械性及結構性支撐。承載基板102可包括例如玻璃、氧化矽、氧化鋁、上述組合及/或其類似物。黏著層104可為任何適合的黏著物，如紫外光(UV)膠，其當暴露於紫外光時會失去黏性，且可透過層壓、旋轉塗佈或其他適合的技術施加。其他種類的黏著物亦可採用，例如當暴露於熱能時會失去黏性的黏著物，上述熱能可藉由紫外光或雷射產生。
保護層106係形成於黏著層104上。如後所述，積體電路的背側將置放於保護層106上。保護層106將提供接合的結構性支撐及有助於減少晶片偏移與焊球破裂的問題。保護層106亦可在後續製程中保護黏著層104。目前已發現部分的黏著層104可於後續製程步驟中去除，而黏著層104的殘留物將負面地影響到後續製程步驟，包括造成不良的晶片置放。保護層106可形成自例如聚苯噁唑(PBO)、聚亞醯胺、防焊層、具有填料基材的環氧樹脂如LC膠帶、晶片貼附膜(die attach film,DAF)、ABF增層膜(Ajinomoto build-up films)、聚合物基材料、上述組合或其類似物，其厚度約為1μm至40μm。依上述材料及厚度所形成的保護層106有助於控制翹曲(warpage)，進而減少在晶片組裝時的不良接合。
第2圖繪示於保護層106的表面上沉積晶種層208。晶種層208係由導電材料所構成的薄膜層，其有助於在後續製程步驟中形成較厚的膜層。在一實施例中，晶種層208係 透過化學氣相沉積(chemical vapor deposition,CVD)或物理氣相沉積(physical vapor deposition,PVD)技術沉積一薄導電層，例如一或多層的鈦、銅、鉭、氮化鈦、氮化鉭、鈦鎢合金、上述組合或其類似物以形成。
之後，如第3圖所示，依據本發明一實施例，於晶種層208上形成圖案化罩幕310。圖案化罩幕310定義後續形成之貫穿模封化合物的通孔電極的形狀，進而提供封裝體第一側面與封裝體第二側面之間的電性連接。圖案化罩幕310可為圖案化光罩、硬罩幕、上述組合或其類似物。
第4圖繪示依據本發明一實施例，形成通孔電極412。通孔電極412可形成自任何適合的導電材料，包括銅、鎳、鉑、鋁、無鉛銲錫(例如錫銀、錫銅、錫銀銅)、上述組合或其類似物，且可透過任何適合的技術，包括電鍍、物理氣相沉積(PVD)、化學氣相沉積(CVD)、電化學沉積(electrochemical deposition,ECD)、分子束磊晶(molecular beam epitaxy,MBE)、原子層沉積(atomic layer deposition,ALD)或其類似製程以形成。應注意到在一些實施例中，例如於晶圓的整個表面上沉積順應性膜層(如透過物理氣相沉積或化學氣相沉積)時，可較佳地實施蝕刻或平坦化製程(如，化學機械研磨(chemical mechanical polishing,CMP)、機械研磨(grinding)或水平切刻(fly cutting))以自圖案化罩幕310表面去除多餘的導電材料。
第5圖繪示依據本發明一實施例，去除圖案化罩幕310。在由光阻材料形成的圖案化罩幕310的實施例中，光阻可透過例如乳酸乙酯、苯甲醚、甲基丁基乙酸酯、乙酸戊酯、甲 基酚醛樹脂及重氮感光化合物(稱作SPR9)之混合物所構成的化學溶液或其他剝除製程來剝除。在其他實施例中，光阻可透過溶劑(如二甲基亞碸(dimethyl sulfoxide,DMSP))、鹼性物(如氫氧化鉀或氫氧化四甲銨(tetramethylammonium hydroxide,(TMAH))及表面活性劑添加劑的混合物來剝除。
第5圖還繪示去除暴露出的晶種層208部分。可透過例如與2%的氫氟酸一同濕式浸漬(wet dip)於磷酸及過氧化氫的化學溶液(稱作DPP)中，或是其他的清洗製程來實施去除製程，以自保護層106表面去除暴露出的晶種層208部分與汙染物。
第6圖繪示依據本發明一實施例，置放一或多個第一積體電路晶片614。接合第一積體電路晶片614以使得積體電路晶片614的背側(如相對於電性接點的一側)係利用例如晶片貼附膜(DAF)616或其他黏著物而置放於保護層106上。第一積體電路晶片614可為裝置晶片，其內部包括如電晶體、電容、電導、電阻(未繪示)或其類似物的積體電路裝置。再者，第一積體電路晶片614可為邏輯晶片、中央處理單元(central processing unit,CPU)晶片、記憶體晶片或其類似晶片。此外，第6圖所繪示之兩個第一積體電路晶片614僅作為示例，其他實施例可包括更少或更多個積體電路晶片。另外，如後所述，所形成的結構將切割以形成個別的封裝體，每一封裝體包含單一積體電路晶片。然而，在其他的實施例中，每一封裝體可包含複數個積體電路晶片。
參照第7圖，於積體電路晶片614及通孔電極412上 塑造模封化合物(molding compound)716(或稱作封裝材料(encapsulating material))。模封化合物716的上表面可高於或齊平於第一積體電路晶片614及/或通孔電極412的上表面。在所形成的模封化合物716高度高於通孔電極412的實施例中，可實施薄化製程以暴露穿過模封化合物716的通孔電極412，進而達成類似第7圖所示之結果，並進而形成如後所述之通孔電極的電性連接。薄化製程可為機械研磨製程、化學研磨製程、蝕刻製程、上述組合或其類似製程。
通孔電極412可延伸高過第一積體電路晶片614，據此，通孔電極412與模封化合物716可進一步縮減使其可形成第一積體電路晶片614的電性接觸。通孔電極412可藉由研磨、蝕刻或其他適合的方法進行縮減。
可選擇性地實施一清洗製程。上述研磨製程可能造成研磨殘留物遺留在通孔電極412上。清洗製程可去除或減少此研磨殘留物，進而使通孔電極412能有較佳的電性接觸。上述清洗製程可能造成凹處(recess)，且可為利用例如氫氧化鉀、甲酸、硫酸、硝酸與氟化氫的混合物、過氯酸與醋酸的混合物或磷酸(H3PO4)溶液與的過氧化氫(H2O2)的混合物的濕蝕刻製程。
接著，如第8圖所示，依據本發明一實施例，形成一或多層(所繪示為一層)的重佈線層(redistribution layers,RDLs)818，以提供通孔電極412及/或通孔電極412與第一積體電路晶片614之間的電性連接。重佈線層818可包括介電層(如，鈍化層)，其具有導電層形成於其內。介電層可包括聚合 物材料，如環氧樹脂、聚亞醯胺、聚苯噁唑或其類似物，或由一般習知的介電材料所構成，如旋轉塗佈玻璃、氧化矽、氮氧化矽或其類似物，並可透過任何適合的方法形成，如旋轉塗佈。導線可形成自金屬，例如銅、銀、鋁、鎳、上述組合或其類似物。
第8圖亦繪示沿著重佈線層818的表面形成第一組電性連接體820。電性連接體820可為焊球、金屬墊、金屬柱及/或上述組合，且可形成自金、銀、鎳、鎢、鋁及/或上述合金。選擇性地，在形成第一組電性連接體820之前，可於重佈線層818上形成凸塊下金屬層(under-bump metallurgy,UBM)結構(未繪示)。一般來說，凸塊下金屬層結構包括形成在重佈線層上的導電墊，並於其上方置放第一組電性連接體820。
第9圖繪示依據本發明一實施例，在剝除承載基板102之後，接合第8圖的結構至承載結構，如承載膠帶922。在一實施例中，承載膠帶922具有一黏著面，其係用以將電性連接體820貼附至承載膠帶922。承載基板102係被剝除。在由光敏黏著物形成的黏著層104的實施例中，承載基板102可藉由例如將黏著層104暴露至紫外光或雷射中，使其失去黏著性來剝除。
其後，如第10圖所示，依據本發明一實施例，可穿過保護層106形成接觸墊開口1024。接觸墊開口1024暴露下方部分的通孔電極412。在後續製程中，接觸墊開口1024可形成每一個別通孔電極412的電性接觸。舉例來說，如後所述，具有一或多個積體電路晶片614的半導體封裝體可裝設在保護 層106上，並透過接觸墊開口1024與通孔電極412形成電性接觸。在形成電性連接體820之前，可選擇性地於暴露出的通孔電極412部份上方形成凸塊下金屬層結構。
接觸墊開口1024可藉由蝕刻或雷射鑽孔(laser drilling)技術形成。舉例來說，可透過微影技術以沉積及圖案化保護層106上方的罩幕。其後，可藉由乾式或濕式蝕刻製程來形成開口並去除罩幕。
可選擇性地透過蝕刻製程去除晶種層208及/或部分的通孔電極412，以使通孔電極412凹陷。如後所述，使晶種層208凹陷或是去除晶種層208可形成較佳的電性連接及提供可置放焊球的凹口(indentation)。此外，晶種層208及/或通孔電極412的凹處可提供更佳的結構支撐及減少晶片偏移。上述蝕刻製程可為濕式或乾式蝕刻，例如四氟化碳、氧氣及氬氣的氣體混合物、高錳酸鉀(KMnO4)、磷酸(H3PO4)及過氧化氫(H2O2)的化學溶液(被稱作DPP)或2%的氫氟酸(HF acid)。
第11圖繪示依據本發明一實施例，實施切割製程並堆疊多個積體電路封裝體的結果。對第10圖所示結構實施切割製程，以形成第一積體電路封裝體1126，並接合第二積體電路封裝體1128至第一積體電路封裝體1126上。第二積體電路封裝體1128包括例如將兩個積體電路晶片1130打線接合(wire bond)至封裝基板1132上。第二積體電路封裝體1128係透過例如第二組電性連接體1134以電性耦接至通孔電極412。第二組電性連接體1134可為焊球、金屬墊、金屬柱及/或其組合，且可形成自金、銀、鎳、鎢、鋁及/或其合金。
可選擇性地於第一積體電路封裝體1126與第二積體電路封裝體1128之間置入底膠(underfill)材料1136。底膠材料1136係分配在第一積體電路封裝體1126與第二積體電路封裝體1128之間。底膠材料1136可為液態環氧樹脂、可變形之凝膠、矽橡膠、可重工底膠(reworkable underfill)、上述組合及/或其類似物，且透過合適的分配設備來分配。
第12-18圖繪示層疊封裝結構製造的其他實施例。第12-18圖所使用的部件標號與第1-11圖中類似膜層/結構的部件標號相同。確切而言，具有相同部件標號的膜層與結構可使用如第1-11圖所述之類似材料與方法形成，於此不再重述。下列討論將提供第二實施例製造流程的簡要概述。
第12圖繪示於承載基板102上形成黏著層104，於黏著層104上形成晶種層208，及於晶種層208上形成保護層106。第12圖亦繪示於保護層106上形成圖案化罩幕310。圖案化罩幕310係圖案化以形成如第13圖所示之通孔電極412。在本實施例中，在形成通孔電極412之前，藉由圖案化罩幕310以圖案化保護層106。
第14圖繪示去除圖案化罩幕310及置放第一積體電路晶片614。第15圖繪示形成及研磨(若有需要)模封化合物716，形成一或多層重佈線層818，以及置放電性連接體820。
之後，第16圖繪示將上述結構貼附至承載結構，如承載膠帶922，以及剝除承載基板102。在第17圖中，去除晶種層208。晶種層208可透過例如研磨、蝕刻、上述組合或其類似製程去除。經過單體化(singulation)製程與貼附第二積體電 路封裝體1128後，最終結構如第18圖所示。
第12-18圖之實施例與第1-11圖之實施例不同之處至少在於晶種層208與保護層106的形成。特別來說，第1-11圖之實施例係先形成保護層106，再於保護層106上形成晶種層208。相反地，第12-18圖之實施例係先形成晶種層208，再於晶種層208上形成保護層106。由於上述順序的交換，第二實施例的晶種層208並不會藉由通孔電極412作為罩幕而圖案化，如第一實施例之第5圖所示。相反地，在實施第16圖之剝除製程之前，晶種層208均被保留下來。所形成的封裝體的保護層(如聚苯噁唑層)係在下方晶片上延伸，且部分沿著通孔電極412的側壁延伸。
相較之下，第1-11圖之實施例的保護層106係位在通孔電極412上，且藉由形成於保護層106內的開口來形成通孔電極412的電性接觸。
第19-22圖繪示層疊封裝結構製造的其他實施例。第19-22圖所使用的部件標號與第1-11圖中類似膜層/結構的部件標號相同。確切而言，具有相同部件標號的膜層與結構可使用如第1-11圖所述之類似材料與方法形成，於此不再重述。下列討論將提供第三實施例製造流程的簡要概述。
首先參照第19圖，於承載基板102上形成黏著層104，以及選擇性地形成晶種層208。形成圖案化罩幕310，及於圖案化罩幕310的開口內形成通孔電極412。在本實施例中，保護層106不再形成於承載基板102上，而將直接形成於晶片上，如後所述。
第20圖繪示去除圖案化罩幕310。暴露出的晶種層208部分(若存在)可透過通孔電極412作為罩幕來蝕刻，其類似第一實施例。可置放第一積體電路晶片614。形成(及研磨，若有需要)模封化合物716，形成重佈線層818，以及置放電性連接體820。在第21圖中，剝除承載基板102。經過切割製程與貼附第二積體電路封裝體1128後，最終結構如第22圖所示。
在其他實施例中，可利用類似上述的製程以形成無通孔電極的封裝體。舉例來說，第23圖繪示不使用通孔電極的實施例。可使用上述第19-22圖的製程，但省略與選擇性形成的晶種層及第二積體電路封裝體有關的步驟。上述實施例所提供的保護層(如聚苯噁唑層)係位在積體電路晶片的背側上。
第24圖為第1-11圖所述之製程流程圖。此製程起始於步驟2402，其於承載基板上形成黏著層與保護層，如第1圖所示。接著，在步驟2404中，於黏著層與保護層上形成晶種層，如第2圖所示。在步驟2406中，沉積及圖案化罩幕以形成開口，並在開口內填入導電材料以形成通孔電極，如第3及4圖所示。接著，在步驟2408中，去除圖案化罩幕，及去除暴露出的晶種層部分，如第5圖所示。在步驟2410中，貼附晶片及形成模封化合物，如第6及7圖所示。在步驟2412中，形成重佈線層及貼附焊球，如第8圖所示。在步驟2414中，將上述結構貼附至承載膠帶，剝除承載基板，以及圖案化保護層，如第9及10圖所示。最後，在步驟2416中，實施單體化製程及將第二封裝體貼附至上述形成的第一封裝體，如第11圖所示。
第25圖為第12-18圖所述之製程流程圖。此製程起 始於步驟2502，其於承載基板上形成黏著層、晶種層與保護層，如第12圖所示。同時亦形成罩幕，並將其圖案化以形成開口。接著，在步驟2504中，在圖案化罩幕的開口內填入導電材料以形成通孔電極，如第13圖所示。在步驟2506中，去除圖案化罩幕及貼附晶片，如第14圖所示。在步驟2508中，形成模封化合物與重佈線層及貼附焊球，如第15圖所示。接著，在步驟2510中，將上述結構貼附至承載膠帶，及剝除承載基板，如第16圖所示。在步驟2512中，去除多餘的晶種層材料，如第17圖所示。最後，在步驟2514中，實施單體化製程以形成第一封裝體，及於第一封裝體上形成第二封裝體，如第18圖所示。亦可在第一及第二封裝體之間置入底膠材料。
第26圖為第19-23圖所述之製程流程圖。此製程起始於步驟2602，其於承載基板上形成黏著層及選擇性形成晶種層。形成及圖案化罩幕以形成開口，並在開口內填入導電材料以形成通孔電極，如第19圖所示。接著，在步驟2604中，去除圖案化罩幕及去除暴露出的晶種層部分(若存在)。將表面貼附有保護層的晶片貼附至承載基板，及形成模封化合物與重佈線層。此外，貼附焊球，如第20圖所示。在步驟2606中，將上述結構貼附至承載膠帶，及剝除承載基板，如第21圖所示。最後，在步驟2608中，實施單體化製程以形成第一封裝體，及於第一封裝體上形成第二封裝體，如第22圖所示，或選擇性地實施切割製程以形成無通孔電極的第一封裝體，如第23圖所示。亦可在第一及第二封裝體之間置入底膠材料。
上述實施例可達成較佳的翹曲控制，特別是對薄 型整合式扇出(integrated fan-out,InFO)層疊封裝設計，其提供與重佈線層所引發之翹曲方向相反的應力。此外，由於在形成模封化合物之前已去除多餘的晶種層材料，可能導致研磨設備阻塞與導致研磨表面粗化的金屬研磨量可因此減少。保護層及/或形成於通孔電極的凹處亦提供額外的側向支撐，進而減少晶片偏移與焊球破裂的問題。
在一實施例中，提供一種半導體裝置的形成方法。此方法包括於一承載基板上形成一保護層，及形成複數個通孔電極自保護層向上延伸。貼附一或多個晶片至保護層，及於此些通孔電極與晶片之間置入一模封化合物。於此些通孔電極上置放複數個電性連接體並與此些晶片形成電性接觸。實施一剝除製程以去除承載基板並暴露保護層。
在另一實施例中，提供一半導體裝置。此半導體裝置包括一第一封裝體及裝設於第一封裝體上的一第二封裝體。第一封裝體包括一或多層重佈線層及位於重佈線層上的一或多個積體電路晶片。一模封化合物係置放於鄰近一或多個積體電路晶片側壁處，及使此些通孔電極延伸穿過模封化合物。一保護層係位於一或多個積體電路晶片上。
雖然本發明實施例及其優點已揭露如上，應了解到在不脫離本發明所附請求項定義之實施例之精神和範圍內，當可作出各種不同的更動、替代與潤飾。再者，本發明之範圍並未侷限於特定實施例中的製程、機器、製造、物質組成、手段、方法及步驟。所屬技術領域中具有通常知識者將可從本發明揭示內容中輕易理解現行或未來所發展出的製程、機器、 製造、物質組成、手段、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明所附請求項範圍包括上述製程、機器、製造、物質組成、手段、方法及步驟。另外，每一請求項構成個別的實施例，且本發明之範圍也包括各個請求項及實施例的組合。
106‧‧‧保護層
616‧‧‧晶片貼附膜
1126‧‧‧第一積體電路封裝體
1128‧‧‧第二積體電路封裝體
1130‧‧‧積體電路晶片
1132‧‧‧封裝基板
1134‧‧‧第二組電性連接體
1136‧‧‧底膠材料

Claims (10)

  1. 一種半導體裝置的形成方法，包括：於一承載基板上形成一保護層；形成複數個通孔電極，其自該保護層向上延伸；貼附一或多個晶片至該保護層；於該些通孔電極與該一或多個晶片之間形成一模封化合物；電性耦接複數個電性連接體至該些通孔電極與該一或多個晶片上的複數個電性接點；剝除該承載基板並暴露該保護層；以及在剝除該承載基板之後，於該保護層內形成複數個開口以暴露該些通孔電極。
  2. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該些通孔電極的步驟包括：於該保護層上形成一晶種層；於該保護層上形成一圖案化罩幕，該圖案化罩幕具有複數個開口形成於其內，以暴露部分的該晶種層；於該圖案化罩幕的該些開口內填入一導電材料，藉以形成該些通孔電極；以及去除該圖案化罩幕。
  3. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括在形成該模封化合物之後：薄化該模封化合物以暴露該一或多個晶片上的該些電性接點；以及 於該模封化合物上形成一或多層重佈線層。
  4. 如申請專利範圍第1項所述之半導體裝置的形成方法，更包括在剝除該承載基板之後：實施一單體化製程以形成一第一封裝體；將一第二封裝體貼附至該第一封裝體，該第二封裝體係藉由形成於該保護層內的該些開口電性耦接至該第一封裝體內的該些通孔電極；以及於該第一封裝體及該第二封裝體之間形成一底膠材料。
  5. 如申請專利範圍第1項所述之半導體裝置的形成方法，其中形成該些通孔電極的步驟包括：在形成該保護層之前，於該承載基板上形成一晶種層；於該晶種層上形成該保護層；於該保護層上形成一圖案化罩幕，該圖案化罩幕具有複數個開口形成於其內，以暴露部分的該晶種層；於該圖案化罩幕的該些開口內填入一導電材料，進而形成該些通孔電極；以及去除該圖案化罩幕。
  6. 一種半導體裝置，包括：一第一封裝體，包括：一或多層重佈線層；一積體電路晶片，位於該一或多層重佈線層上；一模封化合物，鄰近於該一或多個積體電路晶片側壁；複數個通孔電極，延伸穿過該模封化合物；以及一保護層，位於該些積體電路晶片上； 一第二封裝體，裝設於該第一封裝體上，該第二封裝體係電性耦合至該些通孔電極；以及一底膠材料，位於該第一封裝體與該第二封裝體之間。
  7. 如申請專利範圍第6項所述之半導體裝置，其中該保護層與該積體電路晶片的側壁相接，且該保護層的上表面延伸至該些通孔電極的上表面。
  8. 如申請專利範圍第6項所述之半導體裝置，其中該些通孔電極延伸穿過該保護層，且該保護層的上表面延伸至該些通孔電極的上表面。
  9. 如申請專利範圍第6項所述之半導體裝置，其中該保護層的下表面係高於或齊平於該些通孔電極的上表面。
  10. 如申請專利範圍第6項所述之半導體裝置，其中該第一封裝體係透過複數個電性連接體耦接至該第二封裝體，其中該些電性連接體延伸穿過該保護層。
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US20190252296A1 (en) 2019-08-15
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US11037861B2 (en) 2021-06-15
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