TWI521573B - 單步驟選擇性氮化方法與設備 - Google Patents

單步驟選擇性氮化方法與設備 Download PDF

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TWI521573B
TWI521573B TW100106719A TW100106719A TWI521573B TW I521573 B TWI521573 B TW I521573B TW 100106719 A TW100106719 A TW 100106719A TW 100106719 A TW100106719 A TW 100106719A TW I521573 B TWI521573 B TW I521573B
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甘古力尤達炎
瓜立尼泰瑞莎克拉莫
羅吉斯馬修史考特
橫田義孝
史文保喬哈那斯Ｓ
畢凡麥爾肯Ｊ
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Description

單步驟選擇性氮化方法與設備
所述實施例係關於製造半導體裝置。更特別地，所述實施例係關於浮置閘反及閘(NAND)記憶體裝置和其它電晶體閘極結構的製造。
隨著邏輯裝置持續依摩爾定律(Moore’s Law)縮小，各種處理難題應運而生。難題之一在於浮置閘(FG)反及閘(NAND)快閃記憶體晶片，該晶片特點為結合二閘極元件、一控制閘與一浮置閘的電晶體能使各電晶體取得一個以上的位元值。FG NAND記憶體構成大多數通用串列匯流排(USB)快閃記憶體裝置和現今所用記憶卡格式的基礎。
隨著FG NAND裝置的臨界尺寸微縮，各種部件的幾何形狀變得更難製造。深寬比增加將衍生均勻度、容差和可靠度問題。當NAND快閃記憶體越來越普及做為便利儲存媒體時，尤需改善NAND快閃記憶體裝置製造製程，以克服縮放困難。
所述實施例提供藉由產生含氮電漿、使含有矽區與氧化矽區的基板表面曝露至該含氮電漿、及選擇性將氮併 入基板之矽區以處理半導體裝置的方法。
第1圖為根據一實施例之浮置閘(FG)反及(NAND)快閃記憶體裝置100的示意截面圖。裝置100具有半導體元件區102、隔離區104、浮置閘106和控制閘108。浮置閘106具有形成於該浮置閘106的場面112與側壁表面114上的第一介電層110、和形成於第一介電層110上的第二介電層118。隔離區104通常為介電材料。在一實施例中，浮置閘106包含多晶矽。在另一實施例中，隔離區104包含氧化矽。
形成於浮置閘106之場面112與側壁表面114上的第一介電層110可為氮化物層，例如氮化矽或氮氧化矽。第二介電層118可為氧化物-氮化物-氧化物層。在一實施例中，氮化物層係藉由使浮置閘106之場面112與側壁表面114和隔離區104之頂表面116曝露至選擇性電漿氮化製程而形成。選擇性電漿氮化製程形成氮化矽的速度一般比形成氮氧化矽快。
在一實施例中，選擇性電漿氮化製程包含：形成含氮自由基、及使上述矽與氧化矽表面曝露至含氮自由基。因Si-Si鍵能較低(326千焦/莫耳，Si-O鍵能則為799千焦/莫耳)，故含氮自由基將優先與矽反應而選擇性形成Si-N鍵。與自由基和上述鍵能相比，離子具有高化學活 性(N2的第一游離能=1402千焦/莫耳，N2的原子化能=473千焦/莫耳)，因此離子無法達到自由基的選擇性，因而自由基為首選。選擇性(定義為在給定沉積製程後，矽中氮濃度除以氧中氮濃度)可為約10：1至約100：1，例如約20：1至約70：1，例如約40：1。延長曝露時間也可改善選擇性。
含氮自由基(如N、NH和NH2)最好以一些方法產生。利用壓力如高於約5托耳之高壓電漿製程可達成高自由基密度對離子密度。高壓會促進離子與電子快速再結合而留下中性自由基物種和非活性物種。在一些實施例中，形成自由基氣體。在一些實施例中，以各種方法使用遠端電漿來選擇性產生自由基物種。如微波、射頻(RF)或熱腔室等遠端電漿產生器可通過較長的途徑連接至處理腔室，以促進離子物種在抵達腔室前沿著此途徑再結合。在一些實施例中，自由基可以約1sLm(每分鐘標準升)至約20sLm之流率經由噴淋頭或自由基分配器流入腔室、或經由腔室側壁的入口流入腔室，該流率例如約5sLm至約20sLm，例如約10sLm。在一實施例中，氮自由基可藉由使含氮氣體(如氮氣、氨氣或氮氣與氨氣之混合物)，該含氮氣體選擇性伴隨載氣(如氦氣)，在高於約5托耳之壓力下曝露至約1至3千瓦之微波功率而形成。氮自由基可流入在約1托耳至約5托耳之壓力下操作的處理腔室，以處理基板。
在其它實施例中，可使用不同離子濾器，例如在如約 200伏特(RF或直流(DC))之偏壓下操作的靜電濾器、絲網或篩網濾器、或磁性濾器，該些濾器的任一種皆有介電塗層。在其它實施例中，可利用如含氮物種之反應物種氣流或如氬氣或氦氣之非反應物種氣流，調節遠端電漿產生器的滯留時間。在一些實施例中，可使用具低壓電漿產生之離子濾器，延長自由基半衰期。藉由整合處理腔室和遠端電漿腔室且不使用O形環來密封二個腔室間的途徑，有助於低壓操作。利用經塑形的連接器可改善自由基從遠端電漿產生腔室流入處理腔室的均勻度，以提供密切控制的流動圖案。
遠端產生之含氮自由基可經由基板支撐件旁的入口提供至具旋轉基板支撐件的腔室，使氮自由基流過置於基板支撐件上的基板。轉動基板支撐件可確保基板均勻曝露至含氮自由基。加熱基板可提高固態基板材料中氮自由基的溶解度，促使含氮自由基穿透基板表面而至約20埃(Å)至約100埃之深度，例如約25埃至約50埃，例如約35埃。在表面具有矽區與二氧化矽區之基板曝露至所述方法的實施例中，矽區的氮劑量通常為約5×1015原子數/平方公分(atoms/cm2)至約25×1015原子數/平方公分，例如約10×1015原子數/平方公分至約20×1015原子數/平方公分，例如約15×1015原子數/平方公分。
在許多實施例中，氮化製程係以約300℃至約1200℃之基板溫度進行，例如約800℃至約1000℃，該基板溫度可隨著氮化進行而提高，以應付表面飽和。當氮化繼 續進行而增加基板上的氮濃度時，將有利氮的表面沉積。表面沉積易於阻擋可能讓氮穿透表面的位置。提高基板溫度會使表面沉積物種揮發，以致重新露出這些位置進行氮化反應。故當基板曝露至氮自由基時，可提高基板溫度而使表面沉積氮揮發，且增加更多氮穿透到基板內。
此外，可執行多步驟氮化製程，該製程包含以下步驟：例如，在約400℃之低溫下進行的第一步驟，以形成第一氮化物區，及在約800℃或更高之高溫下進行的第二步驟，以形成第二氮化物區，該第二氮化物區包圍第一氮化物區、或位於第一氮化物區上方或下方(假設受試裝置呈適當位向)。低溫形成之第一氮化物區可當作擴散阻障層，以避免基板之摻質在高溫時減少。可使用燈具加熱、雷射加熱、經加熱的基板支撐件或電漿加熱來進行加熱。
氮化可藉由單獨使用熱裝置、單獨使用電漿裝置或使用二者之組合來進行。選擇性熱氮化可藉由使用氨氣(NH3)做為含氮物種來進行。自由基氮化可藉由使用任何較低分子量之含氮物種來進行。適合自由基氮化的前驅物包括，但不以此為限，氮氣(N2)、氨氣(NH3)、聯胺(N2H4)、低取代聯胺(N2R2，其中R分別為氫、甲基、乙基、丙基、乙烯基或丙烯基)、和低級胺(NRaHb，其中a和b分別為整數0至3且a+b=3，R分別為氫、甲基、乙基、丙基、乙烯基或丙烯基)、醯胺(RCONR’R”，其中R、 R’和R”分別為氫、甲基、乙基、丙基、乙烯基或丙烯基)、亞胺(RR’C=NR”，其中R、R’和R”分別為氫、甲基、乙基、丙基、乙烯基或丙烯基)、或醯亞胺(RCONR’COR”，其中R、R’和R”分別為氫、甲基、乙基、丙基、乙烯基或丙烯基)。
在一些實施例中，可以設於氣體分配器與腔室之基板支撐件間的離子濾器(如上述任何離子濾器)或離子屏蔽(如篩網或多孔板)施行原位電漿產生製程，該製程例如由微波、紫外線(UV)、RF或電子同步輻射供給能量。在一實施例中，具離子濾器功能之噴淋頭(如電性絕緣或具受控電位)可設在電漿產生區與基板處理區之間，以容許在過濾離子時，自由基進入基板處理區。
可以任何合宜之裝置施加熱至基板，例如設於基板上方或下方的加熱燈或燈具陣列、埋設基板支撐件的電阻加熱器、或雷射系加熱設備。一些選擇性氮化製程實施例可藉由使用購自美國加州聖大克勞拉市之應用材料公司的RPN腔室來進行。在此腔室中，使用一組加熱燈從下方施加熱至基板，同時轉動基板，以增進處理均勻度。
雖然所述方法係以形成浮置閘NAND快閃記憶體裝置為例說明，但所述方法不限於此裝置應用。所述方法也可用於把氮添加到其它閘極結構，例如氧化鉿(HfOx)和矽酸鉿(HfSixOy)。此外，所述處理條件可用於處理300毫米基板。
雖然以上敘述係針對本發明之實施例，然在不脫離本 發明的基本範圍內，本發明當可推演出其它和進一步之實施例。
100‧‧‧快閃記憶體裝置
102‧‧‧元件區
104‧‧‧隔離區
106‧‧‧浮置閘
108‧‧‧控制閘
110、118‧‧‧介電層
112‧‧‧場面
114‧‧‧側壁表面
116‧‧‧頂表面
本發明的更特定描述、以上簡單概述，可藉由參考附圖中所敘述的一些實施例來瞭解，因此可更詳細瞭解本發明的上述特徵。然而，須注意，所附圖式僅說明本發明典型實施例，故其並非用以限定本發明之精神與範圍，因為本發明可接納其它等效實施例。
第1圖為根據一實施例之浮置閘NAND快閃記憶體裝置的示意截面圖。
為助於了解，各圖中相同的元件符號盡可能代表相似的元件。應理解某一實施例的元件當可用於其它實施例，在此不特別詳述。
100．．．快閃記憶體裝置
102．．．元件區
104．．．隔離區
106．．．浮置閘
108．．．控制閘
110、118．．．介電層
112．．．場面
114．．．側壁表面
116．．．頂表面

Claims (18)

  1. 一種處理一半導體基板的方法，該半導體基板具有一表面，該表面具有一矽區和一氧化矽區，該方法包含：將該基板設置在一處理腔室中；提供包含含氮自由基之一混合氣體至該處理腔室內；在該混合氣體提供至該處理腔室之前，將離子從該混合氣體移除；使該基板曝露至該混合氣體；以及藉由在約400℃之一溫度形成一第一氮化物區與在約800℃或更高的一溫度形成一第二氮化物區，選擇性將氮併入該基板之該矽區。
  2. 如申請專利範圍第1項之方法，其中該提供包含該含氮自由基之該混合氣體至該處理腔室內包含：在至少5托耳之一壓力下由一含氮氣體形成一電漿。
  3. 如申請專利範圍第1項之方法，其中該提供包含該含氮自由基之該混合氣體至該處理腔室內包含：由一含氮氣體形成一電漿，以及過濾來自該電漿的離子。
  4. 如申請專利範圍第1項之方法，其中該提供包含該含氮自由基之該混合氣體至該處理腔室內包含：由一含氮氣體形成一原位電漿，以及利用一離子屏蔽，過濾來自 該電漿的離子。
  5. 如申請專利範圍第1項之方法，其中該第一氮化物區在該基板之一表面形成一擴散阻障層。
  6. 一種選擇性氮化一基板的方法，該基板具有一半導體區與一介電質區，該方法包含：由一含氮前驅物氣體形成一自由基氣體；將離子從該自由基氣體移除；以及在約300℃至約1200℃之一溫度下，將該基板曝露至該自由基氣體，藉由在該基板表面形成一氮化物擴散阻障層區，然後形成包圍至少一部分之該氮化物擴散阻障層區之一氮化物區，以將氮併入該半導體區。
  7. 如申請專利範圍第6項之方法，其中形成該自由基氣體包含：由該含氮前驅物氣體形成一原位電漿，以及過濾來自該電漿的離子。
  8. 如申請專利範圍第6項之方法，其中形成該自由基氣體包含：在一遠端腔室中施加微波功率至該含氮前驅物氣體。
  9. 如申請專利範圍第6項之方法，其中將該基板曝露至該自由基氣體包含：使該自由基氣體流過該基板表面， 同時轉動該基板。
  10. 如申請專利範圍第6項之方法，其中該含氮前驅物氣體包含氮氣、氨氣或氮氣與氨氣之組合物。
  11. 如申請專利範圍第10項之方法，其中形成該自由基氣體包含：施加微波功率至該含氮前驅物氣體。
  12. 如申請專利範圍第11項之方法，其中該含氮前驅物氣體更包含氦氣。
  13. 一種在一處理腔室中形成一浮置閘反及閘(NAND)快閃記憶體裝置的方法，包含：形成一氧化矽隔離結構於一矽基板上；形成一主要為矽之浮置閘於該隔離結構上；提供一含氮前驅物氣體；在該含氮前驅物氣體提供至該處理腔室之前，將離子從該含氮前驅物氣體移除；藉由在約400℃之一低溫於該浮置閘上形成一第一氮化物層，然後在約800℃或更高的一高溫於該浮置閘上形成一第二氮化物層，選擇性將一氮自由基添加到該浮置閘；形成一介電層於該氮化物層和該隔離結構上；以及形成一控制閘於該介電層上。
  14. 如申請專利範圍第13項之方法，其中該浮置閘係多晶矽，且選擇性將該氮自由基添加到該浮置閘包含：使該氮自由基流入含有該基板的一處理腔室內，以及加熱該基板。
  15. 如申請專利範圍第13項之方法，其中選擇性將該氮自由基添加到該浮置閘包含：提供能量小於一矽-氧鍵能的一氮自由基。
  16. 如申請專利範圍第13項之方法，其中選擇性將該氮自由基添加到該浮置閘包含：使該含氮前驅物氣體曝露至微波或射頻(RF)功率，以形成一經活化的前驅物氣體；在至少約5托耳之一壓力下，使該經活化的前驅物氣體流入含有該基板的一處理腔室內；藉由加熱該基板，提高該浮置閘中該氮自由基的溶解度；以及轉動該基板。
  17. 如申請專利範圍第13項之方法，其中選擇性將該氮自由基添加到該浮置閘包含：在使該基板曝露至該氮自由基時，提高該基板之一溫度。
  18. 如申請專利範圍第13項之方法，其中該第一氮化物層在該基板之一表面形成一擴散阻障層。
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8748259B2 (en) * 2010-03-02 2014-06-10 Applied Materials, Inc. Method and apparatus for single step selective nitridation
US9054038B2 (en) 2011-01-25 2015-06-09 Applied Materials, Inc. Floating gates and methods of formation
TWI549163B (zh) 2011-09-20 2016-09-11 應用材料股份有限公司 減少摻質擴散之表面穩定化製程
US8741785B2 (en) 2011-10-27 2014-06-03 Applied Materials, Inc. Remote plasma radical treatment of silicon oxide
US8994089B2 (en) * 2011-11-11 2015-03-31 Applied Materials, Inc. Interlayer polysilicon dielectric cap and method of forming thereof
US8846509B2 (en) * 2011-11-15 2014-09-30 Applied Materials, Inc. Remote radical hydride dopant incorporation for delta doping in silicon
US9133412B2 (en) * 2012-07-09 2015-09-15 Tribofilm Research, Inc. Activated gaseous species for improved lubrication
CN113981414A (zh) * 2015-03-20 2022-01-28 应用材料公司 用于3d共形处理的原子层处理腔室
JP6690496B2 (ja) 2016-03-17 2020-04-28 東京エレクトロン株式会社 成膜方法及び成膜装置
KR102306570B1 (ko) * 2016-06-01 2021-09-30 어플라이드 머티어리얼스, 인코포레이티드 3d 낸드 응용들을 위한 터널 산화물의 고압 암모니아 질화
US10510545B2 (en) 2016-06-20 2019-12-17 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
US10103027B2 (en) 2016-06-20 2018-10-16 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
US10468412B2 (en) 2016-06-28 2019-11-05 International Business Machines Corporation Formation of a semiconductor device with selective nitride grown on conductor
US9704754B1 (en) 2016-09-22 2017-07-11 International Business Machines Corporation Self-aligned spacer for cut-last transistor fabrication
CN108987402A (zh) 2017-05-31 2018-12-11 华邦电子股份有限公司 存储元件的制造方法
US11830725B2 (en) 2020-01-23 2023-11-28 Applied Materials, Inc. Method of cleaning a structure and method of depositing a capping layer in a structure
CN115863151B (zh) * 2022-12-25 2023-10-27 北京屹唐半导体科技股份有限公司 工件处理方法、工件处理设备及半导体器件

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221092A (ja) * 1994-02-09 1995-08-18 Fujitsu Ltd 半導体装置の製造方法
US6281141B1 (en) * 1999-02-08 2001-08-28 Steag Rtp Systems, Inc. Process for forming thin dielectric layers in semiconductor devices
JP4792620B2 (ja) * 2000-06-21 2011-10-12 ソニー株式会社 不揮発性半導体記憶装置およびその製造方法
US6800830B2 (en) * 2000-08-18 2004-10-05 Hitachi Kokusai Electric, Inc. Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication
US20020084482A1 (en) * 2000-12-31 2002-07-04 Cetin Kaya Scalable dielectric
JP2004022902A (ja) * 2002-06-18 2004-01-22 Fujitsu Ltd 半導体装置の製造方法
JP4268429B2 (ja) * 2003-03-17 2009-05-27 東京エレクトロン株式会社 基板処理装置および基板処理方法
JP4522916B2 (ja) * 2005-06-27 2010-08-11 東京エレクトロン株式会社 プラズマ窒化処理方法、制御プログラム、コンピュータ記憶媒体およびプラズマ処理装置
US7138691B2 (en) 2004-01-22 2006-11-21 International Business Machines Corporation Selective nitridation of gate oxides
JP2005235987A (ja) * 2004-02-19 2005-09-02 Toshiba Corp 半導体記憶装置及び半導体記憶装置の製造方法
US7629270B2 (en) * 2004-08-27 2009-12-08 Asm America, Inc. Remote plasma activated nitridation
JP4564310B2 (ja) * 2004-09-01 2010-10-20 株式会社日立国際電気 半導体装置の製造方法
CN101156234B (zh) * 2005-03-31 2012-01-25 东京毅力科创株式会社 基板的氮化处理方法和绝缘膜的形成方法
JP4509864B2 (ja) * 2005-05-30 2010-07-21 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置
CN100587923C (zh) * 2005-09-22 2010-02-03 东京毅力科创株式会社 选择性等离子体处理方法和等离子体处理装置
KR100777016B1 (ko) * 2006-06-20 2007-11-16 재단법인서울대학교산학협력재단 기둥 구조를 갖는 낸드 플래시 메모리 어레이 및 그제조방법
JP4764267B2 (ja) * 2006-06-27 2011-08-31 株式会社東芝 半導体装置およびその製造方法
US8158535B2 (en) * 2006-12-28 2012-04-17 Tokyo Electron Limited Method for forming insulating film and method for manufacturing semiconductor device
US7867923B2 (en) * 2007-10-22 2011-01-11 Applied Materials, Inc. High quality silicon oxide films by remote plasma CVD from disilane precursors
US8216913B2 (en) * 2007-12-24 2012-07-10 Texas Instruments Incorporated Strain modulation in active areas by controlled incorporation of nitrogen at si-SiO2 interface
JP2009289902A (ja) 2008-05-28 2009-12-10 Toshiba Corp Ｎａｎｄ型フラッシュメモリおよびその製造方法
US8748259B2 (en) * 2010-03-02 2014-06-10 Applied Materials, Inc. Method and apparatus for single step selective nitridation

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