CN102782816A - 单步骤选择性氮化方法与设备 - Google Patents

单步骤选择性氮化方法与设备 Download PDF

Info

Publication number
CN102782816A
CN102782816A CN2011800119138A CN201180011913A CN102782816A CN 102782816 A CN102782816 A CN 102782816A CN 2011800119138 A CN2011800119138 A CN 2011800119138A CN 201180011913 A CN201180011913 A CN 201180011913A CN 102782816 A CN102782816 A CN 102782816A
Authority
CN
China
Prior art keywords
substrate
nitrogen
gas
free radical
floating grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2011800119138A
Other languages
English (en)
Other versions
CN102782816B (zh
Inventor
乌陀衍·甘古利
特里萨·克莱默·瓜里尼
马修·斯科特·罗杰斯
横田义孝
约翰内斯·S·斯温伯格
马尔科姆·J·贝文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of CN102782816A publication Critical patent/CN102782816A/zh
Application granted granted Critical
Publication of CN102782816B publication Critical patent/CN102782816B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324Gate electrodes for transistors with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Formation Of Insulating Films (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

提供选择性单步骤氮化半导体基板的方法与设备。利用选择性氮化工艺,将氮选择性地并入具有硅区和氧化硅区的半导体基板的硅区。通过形成含氮等离子体及过滤或去除等离子体中的离子,可将含氮自由基导向基板,或者可执行使用选择性前驱物的热氮化工艺。远程等离子体产生器可耦接至处理腔室,其所述远程等离子体产生器选择性地包括一个或多个离子滤器、喷淋头和自由基分配器,或者可产生原位等离子体并且一个或多个离子滤器或屏蔽设置在腔室内并位于等离子体产生区与基板支撑件之间。

Description

单步骤选择性氮化方法与设备
领域
在此描述的实施例涉及制造半导体器件。更特别地,在此描述的实施例涉及浮置栅极NAND存储器器件和其他晶体管栅极结构的制造。
背景
随着逻辑器件按照摩尔定律(Moore’s Law)持续缩小,各种处理挑战应运而生。一个这样的挑战出现在浮置栅极(FG)NAND闪存芯片,所述闪存芯片的特点为结合两个栅极元件、控制栅极与浮置栅极的晶体管能使各晶体管取得大于一个的比特值。FG NAND存储器构成现今所用的大多数USB闪存器件和存储器卡格式的基础。
随着FG NAND器件的临界尺寸缩小,各种部件的几何形状变得对制造商来说更具挑战性。深宽比(aspect ratio)增加并且均匀性、公差和可靠性问题增加。当NAND闪存作为方便的存储介质越来越受欢迎时,需要改善制造工艺,特别是NAND闪存器件的制造工艺,以克服缩放方面的挑战。
概述
在此描述的实施例提供通过产生含氮等离子体、将含有硅区与氧化硅区的基板的表面暴露至所述含氮等离子体、以及选择性地将氮并入基板的硅区而处理半导体器件的方法。
附图简要说明
本发明的更特定描述、以上简要概述,可由参考附图中所叙述的一些实施例来理解,因此可更详细了解本发明的上述特征。然而,应注意的是,附图仅描绘本发明的典型实施例,因此不应视为对本发明的范围的限制,因为本发明可允许其他等效实施例。
图1是根据一个实施例的浮置栅极NAND闪存器件的示意截面图。
为便于理解,在可能的情况下使用相同标号来表示附图所共有的相同元件。预期一个实施例中公开的元件可有利地用于其他实施例而不需特别叙述。
具体描述
图1是根据一个实施例的FG NAND闪存器件100的示意截面图。器件100具有半导体元件区102、隔离区104、浮置栅极106和控制栅极108。浮置栅极106具有形成在浮置栅极106的场表面(field surface)112和侧壁表面114上的第一电介质层110、以及形成在第一电介质层110上的第二电介质层118。隔离区104通常为电介质材料。在一个实施例中,浮置栅极106包含多晶硅。在另一个实施例中,隔离区104包含氧化硅。
形成在浮置栅极106的场表面112和侧壁表面114上的第一电介质层110可为氮化物层,所述氮化物例如是氮化硅或氮氧化硅。第二电介质层118可为氧化物-氮化物-氧化物层。在一个实施例中,氮化物层可通过将浮置栅极106的场表面112和侧壁表面114以及隔离区104的顶表面116暴露至选择性等离子体氮化工艺而形成。选择性等离子体氮化工艺形成氮化硅的速度一般比形成氮氧化硅快。
在一个实施例中,选择性等离子体氮化工艺包括:形成含氮自由基、以及将上述硅与氧化硅表面暴露至含氮自由基。因为较低的Si-Si键能(326千焦/摩尔,Si-O键能则为799千焦/摩尔),所以含氮自由基将优先与硅反应而选择性地形成Si-N键。与自由基和上述键能相比,离子具有高化学活性(N2的第一离子化能=1402千焦/摩尔;N2的原子化能=473千焦/摩尔),因此离子无法达到自由基的选择性,因而自由基为首选。选择性(定义为给定沉积工艺后的硅中氮浓度除以氧中氮浓度)可为在约10:1与约100:1之间,例如约20:1与约70:1之间,例如约40:1。延长暴露时间也可改善选择性。
含氮自由基(例如N、NH和NH2)可以优选地由一些方法产生。利用例如压强高于约5托的高压等离子体工艺可获得高的自由基密度对离子密度。高压会促进离子与电子快速再结合而留下中性自由基物种和非活性物种。在某些实施例中,形成自由基气体。在某些实施例中,以各种方法可使用远程等离子体来选择性地产生自由基物种。例如微波、RF或热腔室等的远程等离子体产生器可通过较长的途径连接至处理腔室,以促进离子物种在到达腔室前沿着此途径再结合。在某些实施例中,自由基可以约1sLm至约20sLm之间的流量经由腔室侧壁中的入口流入腔室,或者经由喷淋头或自由基分配器流入腔室,所述流量例如在约5sLm至约20sLm之间,例如约10sLm。在一个实施例中,氮自由基可通过将含氮气体(例如氮气、或氨气、或氮气和氨气的组合)在高于约5托的压力下暴露至约1至3千瓦的微波功率而形成,该含氮气体可选择性地伴随载气(例如氦气)。氮自由基可流入在约1托至约5托之间的压力下操作的处理腔室,以处理基板。
在其他实施例中,可使用不同的离子滤器,例如丝网或筛网滤器、磁性滤器、或在例如约200V(RF或DC)的偏压下操作的静电滤器,这些滤器的任一种都可具有电介质涂层。在其他实施例中,可利用例如含氮物种的反应物种气流或例如氩气或氦气的非反应物种气流,调节远程等离子体产生器中的滞留时间。在某些实施例中,可使用具低压等离子体产生的离子滤器来延长自由基半衰期。通过整合处理腔室和远程等离子体腔室且不使用O形环来密封两个腔室之间的途径,可有助于低压操作。利用经塑形的连接器可改善自由基从远程等离子体产生腔室流入处理腔室的均匀性,以提供密切控制的流动图案。
远程产生的含氮自由基可经由与腔室的旋转基板支撑件邻近的入口提供给具有该旋转基板支撑件的腔室,从而使氮自由基流过设置在基板支撑件上的基板。转动该基板支撑件可确保基板均匀暴露至含氮自由基。加热基板可提高固态基板材料中氮自由基的溶解度,促使含氮自由基穿透基板表面而至约
Figure BDA00002086975200031
至约
Figure BDA00002086975200032
之间的深度,例如在约
Figure BDA00002086975200033
至约之间,例如约
Figure BDA00002086975200035
在表面具有硅区与二氧化硅区的基板暴露至这里所述方法的实施例中,硅区中获得的氮剂量通常为约5×1015atom/cm2至约25×1015atom/cm2之间,例如在约10×1015atom/cm2与约20×1015atom/cm2之间,例如约15×1015atom/cm2
在许多实施例中,氮化工艺是以约300°C至约1200°C之间的基板温度执行的,例如在约800°C至约1000°C之间,所述基板温度可随着氮化进行而提高,以对抗表面饱和。当氮化继续进行而增加基板中的氮浓度时,将更有利于氮的表面沉积。表面沉积有助于阻挡可能让氮穿透表面的位置。提高基板温度会使表面沉积的物种挥发,以致重新暴露这些位置进行氮化反应。因此,当基板暴露至氮自由基时,可提高基板温度而使表面沉积的氮挥发,且增加更多氮穿透到基板内。
此外,可执行多步骤氮化工艺,所述工艺包括以下步骤:例如在约400°C的低温下执行的第一步骤,以形成第一氮化物区,以及在约800°C或更高的高温下执行的第二步骤,以形成第二氮化物区,该第二氮化物区可包围第一氮化物区、或可位于第一氮化物区上方或下方(假设对象器件呈适当方向)。低温形成的第一氮化物区可当作扩散阻挡层,以避免基板的掺杂剂在高温时减少。可使用灯具加热、激光加热、经加热的基板支撑件或等离子体加热来进行加热。
氮化可通过单独使用热装置、单独使用等离子体装置或使用两者的组合来执行。选择性热氮化可通过使用氨气(NH3)作为含氮物种来执行。自由基氮化可通过使用任何较低分子量的含氮物种来执行。适合自由基氮化的前驱物包括但不限于:氮气(N2)、氨气(NH3)、联胺(N2H4)、低取代联胺(N2R2,其中R分别为氢、甲基、乙基、丙基、乙烯基或丙烯基)、和低级胺(NRaHb,其中a和b分别为0至3的整数,且a+b=3,并且R分别为氢、甲基、乙基、丙基、乙烯基或丙烯基)、酰胺(RCONR’R”,其中R、R’和R”分别为氢、甲基、乙基、丙基、乙烯基或丙烯基)、亚胺(RR’C=NR”,其中R、R’和R”分别为氢、甲基、乙基、丙基、乙烯基或丙烯基)、或酰亚胺(RCONR’COR”,其中R、R’和R”分别为氢、甲基、乙基、丙基、乙烯基或丙烯基)。
在某些实施例中,可利用设置在腔室中的基板支撑件与气体分配器之间的离子滤器(例如上述任何离子滤器)或离子屏蔽(例如筛网或多孔板)施行原位等离子体产生工艺,并且例如由微波、UV、RF或电子同步辐射供给能量。在一个实施例中,具有离子滤器功能的喷淋头(例如电绝缘的或具有受控电位)可设置在等离子体产生区与基板处理区之间,以允许在过滤离子时,自由基进入基板处理区。
可通过任何合适的装置给基板施加热,例如设置在基板上方或下方的加热灯或灯具阵列、嵌入基板支撑件的电阻加热器、或基于激光的加热设备。选择性氮化工艺的某些实施例可通过使用购自美国加州圣大克劳拉市的应用材料公司的RPN腔室来进行。在这种腔室中,使用一组加热灯从下方给基板施加热,同时转动基板,以增进处理均匀性。
虽然在此公开的方法以形成浮置栅极NAND闪存器件为例来描述,但所述方法的应用不限于此种器件。在此公开的方法也可用来将氮添加到其他栅极结构,例如氧化铪(HfOx)和硅酸铪(HfSixOy)。此外,在此描述的处理条件可用于处理300毫米基板。
尽管以上描述涉及本发明的各个实施例,但在不背离本发明的基本范围的情况下,可设想本发明的其他与进一步的实施例。
权利要求书(按照条约第19条的修改)
1.一种处理半导体基板的方法,所述半导体基板具有一表面,所述表面具有硅区和氧化硅区,所述方法包括以下步骤:
将所述基板设置在处理腔室中;
将包含含氮自由基的气体混合物提供给所述处理腔室;
在将所述气体混合物提供给所述处理腔室之前,从所述气体混合物中去除离子;
使所述基板暴露至所述气体混合物;以及
选择性地将氮并入所述基板的所述硅区。
2.如权利要求1所述的方法,其中所述选择性地将氮并入所述基板的所述硅区包括:将所述基板加热至约300℃至约1200℃之间。
3.如权利要求1所述的方法,其中所述将包含含氮自由基的气体混合物提供给所述处理腔室包括:在至少5托的压力下由含氮气体形成等离子体。
4.如权利要求1所述的方法,其中所述将包含含氮自由基的气体混合物提供给所述处理腔室包括:由含氮气体形成等离子体,以及过滤来自所述等离子体的离子。
5.如权利要求1所述的方法,其中所述将包含含氮自由基的气体混合物提供给所述处理腔室包括:由含氮气体形成原位等离子体,以及利用离子屏蔽,过滤来自所述等离子体的离子。
6.如权利要求2所述的方法,其中所述选择性地将氮并入所述基板的所述硅区包括:在低温下形成第一氮化物区,然后在高温下形成第二氮化物区。
7.如权利要求1所述的方法,进一步包括在所述基板的一表面中形成扩散阻挡层。
8.如权利要求1所述的方法,进一步包括在将所述基板暴露至所述气体混合物时,提高所述基板的温度。
9.一种选择性地氮化基板的方法,所述基板具有半导体区与电介质区,所述方法包括以下步骤:
由含氮前驱物气体形成自由基气体;
从所述自由基气体中去除离子;以及
在约300℃至约1200℃之间的温度下,将所述基板暴露至所述自由基气体。
10.如权利要求9所述的方法,其中所述将所述基板暴露至所述自由基气体进一步包括:在所述基板表面中形成扩散阻挡层。
11.如权利要求9所述的方法,其中所述形成所述自由基气体包括:在远程腔室中将微波功率施加至所述含氮前驱物气体。
12.如权利要求9所述的方法,其中将所述基板暴露至所述自由基气体包括:使所述自由基气体流过所述基板表面,同时转动所述基板。
13.如权利要求9所述的方法,其中所述含氮前驱物气体包含氮气、氨气或氮气和氨气的组合。
14.如权利要求13所述的方法,其中形成所述自由基气体包括:将微波功率施加给所述含氮前驱物气体。
15.如权利要求14所述的方法,其中所述含氮前驱物气体进一步包含氦气。
16.一种形成浮置栅极NAND闪存器件的方法,所述方法包括以下步骤:
在硅基板上形成氧化硅隔离结构;
在所述隔离结构上形成主要为硅的浮置栅极;
选择性地将氮自由基添加到所述浮置栅极,以在所述浮置栅极之上形成氮化物层;
在所述氮化物层和所述隔离结构之上形形成电介质层;以及
在所述电介质层之上形成控制栅极。
17.如权利要求16所述的方法,其中所述浮置栅极是多晶硅,并且选择性地将所述氮自由基添加到所述浮置栅极包括:使所述氮自由基流入含有所述基板的处理腔室内,并且加热所述基板。
18.如权利要求16所述的方法,其中选择性地将所述氮自由基添加到所述浮置栅极包括:提供能量小于硅-氧键能的氮自由基。
19.如权利要求16所述的方法,其中选择性地将所述氮自由基添加到所述浮置栅极包括:
使含氮前驱物气体暴露至微波或RF功率,以形成经活化的前驱物气体;
在至少约5托的压力下,使所述经活化的前驱物气体流入含有所述基板的处理腔室内;
通过加热所述基板,提高所述浮置栅极中的所述氮自由基的溶解度;以及
转动所述基板。
20.如权利要求16所述的方法,其中选择性地将所述氮自由基添加到所述浮置栅极包括:在使所述基板暴露至所述氮自由基时,提高所述基板的温度。

Claims (20)

1.一种处理半导体基板的方法,所述半导体基板具有一表面,所述表面具有硅区和氧化硅区,所述方法包括以下步骤:
将所述基板设置在处理腔室中;
将包含含氮自由基的气体混合物提供给所述处理腔室;
使所述基板暴露至所述气体混合物;以及
选择性地将氮并入所述基板的所述硅区。
2.如权利要求1所述的方法,其中所述选择性地将氮并入所述基板的所述硅区包括:将所述基板加热至约300°C至约1200°C之间。
3.如权利要求1所述的方法,其中所述将包含含氮自由基的气体混合物提供给所述处理腔室包括:在至少5托的压力下由含氮气体形成等离子体。
4.如权利要求1所述的方法,其中所述将包含含氮自由基的气体混合物提供给所述处理腔室包括:由含氮气体形成等离子体,以及过滤来自所述等离子体的离子。
5.如权利要求1所述的方法,其中所述将包含含氮自由基的气体混合物提供给所述处理腔室包括:由含氮气体形成原位等离子体,以及利用离子屏蔽,过滤来自所述等离子体的离子。
6.如权利要求2所述的方法,其中所述选择性地将氮并入所述基板的所述硅区包括:在低温下形成第一氮化物区,然后在高温下形成第二氮化物区。
7.如权利要求1所述的方法,进一步包括在所述基板的一表面中形成扩散阻挡层。
8.如权利要求1所述的方法,进一步包括在将所述基板暴露至所述气体混合物时,提高所述基板的温度。
9.一种选择性地氮化基板的方法,所述基板具有半导体区与电介质区,所述方法包括以下步骤:
由含氮前驱物气体形成自由基气体;以及
在约300°C至约1200°C之间的温度下,将所述基板暴露至所述自由基气体。
10.如权利要求9所述的方法,其中所述将所述基板暴露至所述自由基气体进一步包括:在所述基板表面中形成扩散阻挡层。
11.如权利要求9所述的方法,其中所述形成所述自由基气体包括:在远程腔室中将微波功率施加至所述含氮前驱物气体。
12.如权利要求9所述的方法,其中将所述基板暴露至所述自由基气体包括:使所述自由基气体流过所述基板表面,同时转动所述基板。
13.如权利要求9所述的方法,其中所述含氮前驱物气体包含氮气、氨气或氮气和氨气的组合。
14.如权利要求13所述的方法,其中形成所述自由基气体包括:将微波功率施加给所述含氮前驱物气体。
15.如权利要求14所述的方法,其中所述含氮前驱物气体进一步包含氦气。
16.一种形成浮置栅极NAND闪存器件的方法,所述方法包括以下步骤:
在硅基板上形成氧化硅隔离结构;
在所述隔离结构上形成主要为硅的浮置栅极;
选择性地将氮自由基添加到所述浮置栅极,以在所述浮置栅极之上形成氮化物层;
在所述氮化物层和所述隔离结构之上形形成电介质层;以及
在所述电介质层之上形成控制栅极。
17.如权利要求16所述的方法,其中所述浮置栅极是多晶硅,并且选择性地将所述氮自由基添加到所述浮置栅极包括:使所述氮自由基流入含有所述基板的处理腔室内,并且加热所述基板。
18.如权利要求16所述的方法,其中选择性地将所述氮自由基添加到所述浮置栅极包括:提供能量小于硅-氧键能的氮自由基。
19.如权利要求16所述的方法,其中选择性地将所述氮自由基添加到所述浮置栅极包括:
使含氮前驱物气体暴露至微波或RF功率,以形成经活化的前驱物气体;
在至少约5托的压力下,使所述经活化的前驱物气体流入含有所述基板的处理腔室内;
通过加热所述基板,提高所述浮置栅极中的所述氮自由基的溶解度;以及转动所述基板。
20.如权利要求16所述的方法,其中选择性地将所述氮自由基添加到所述浮置栅极包括:在使所述基板暴露至所述氮自由基时,提高所述基板的温度。
CN201180011913.8A 2010-03-02 2011-02-28 单步骤选择性氮化方法与设备 Active CN102782816B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US30974410P 2010-03-02 2010-03-02
US61/309,744 2010-03-02
US13/033,330 2011-02-23
US13/033,330 US8748259B2 (en) 2010-03-02 2011-02-23 Method and apparatus for single step selective nitridation
PCT/US2011/026423 WO2011109266A2 (en) 2010-03-02 2011-02-28 Method and apparatus for single step selective nitridation

Publications (2)

Publication Number Publication Date
CN102782816A true CN102782816A (zh) 2012-11-14
CN102782816B CN102782816B (zh) 2016-05-18

Family

ID=44531708

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180011913.8A Active CN102782816B (zh) 2010-03-02 2011-02-28 单步骤选择性氮化方法与设备

Country Status (6)

Country Link
US (2) US8748259B2 (zh)
JP (1) JP2013521653A (zh)
KR (1) KR101861202B1 (zh)
CN (1) CN102782816B (zh)
TW (1) TWI521573B (zh)
WO (1) WO2011109266A2 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107431033A (zh) * 2015-03-20 2017-12-01 应用材料公司 用于3d共形处理的原子层处理腔室
CN115863151A (zh) * 2022-12-25 2023-03-28 北京屹唐半导体科技股份有限公司 工件处理方法、工件处理设备及半导体器件

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8748259B2 (en) * 2010-03-02 2014-06-10 Applied Materials, Inc. Method and apparatus for single step selective nitridation
US9054038B2 (en) 2011-01-25 2015-06-09 Applied Materials, Inc. Floating gates and methods of formation
TWI549163B (zh) * 2011-09-20 2016-09-11 應用材料股份有限公司 減少摻質擴散之表面穩定化製程
US8741785B2 (en) 2011-10-27 2014-06-03 Applied Materials, Inc. Remote plasma radical treatment of silicon oxide
US8994089B2 (en) * 2011-11-11 2015-03-31 Applied Materials, Inc. Interlayer polysilicon dielectric cap and method of forming thereof
US8846509B2 (en) * 2011-11-15 2014-09-30 Applied Materials, Inc. Remote radical hydride dopant incorporation for delta doping in silicon
US9133412B2 (en) * 2012-07-09 2015-09-15 Tribofilm Research, Inc. Activated gaseous species for improved lubrication
JP6690496B2 (ja) * 2016-03-17 2020-04-28 東京エレクトロン株式会社 成膜方法及び成膜装置
US20170349996A1 (en) * 2016-06-01 2017-12-07 Applied Materials, Inc. High pressure ammonia nitridation of tunnel oxide for 3dnand applications
US10103027B2 (en) 2016-06-20 2018-10-16 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
US10510545B2 (en) 2016-06-20 2019-12-17 Applied Materials, Inc. Hydrogenation and nitridization processes for modifying effective oxide thickness of a film
US10468412B2 (en) 2016-06-28 2019-11-05 International Business Machines Corporation Formation of a semiconductor device with selective nitride grown on conductor
US9704754B1 (en) 2016-09-22 2017-07-11 International Business Machines Corporation Self-aligned spacer for cut-last transistor fabrication
CN108987402A (zh) 2017-05-31 2018-12-11 华邦电子股份有限公司 存储元件的制造方法
WO2021150625A1 (en) 2020-01-23 2021-07-29 Applied Materials, Inc. Method of cleaning a structure and method of depositiing a capping layer in a structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040063284A1 (en) * 2000-12-31 2004-04-01 Texas Instruments Incorporated Scalable dielectric
US6800830B2 (en) * 2000-08-18 2004-10-05 Hitachi Kokusai Electric, Inc. Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication
US6960502B2 (en) * 2002-06-18 2005-11-01 Fujitsu Limited Semiconductor device fabrication method
CN101080810A (zh) * 2005-09-22 2007-11-28 东京毅力科创株式会社 选择性等离子体处理方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221092A (ja) * 1994-02-09 1995-08-18 Fujitsu Ltd 半導体装置の製造方法
US6281141B1 (en) * 1999-02-08 2001-08-28 Steag Rtp Systems, Inc. Process for forming thin dielectric layers in semiconductor devices
JP4792620B2 (ja) * 2000-06-21 2011-10-12 ソニー株式会社 不揮発性半導体記憶装置およびその製造方法
JP4268429B2 (ja) * 2003-03-17 2009-05-27 東京エレクトロン株式会社 基板処理装置および基板処理方法
JP4522916B2 (ja) * 2005-06-27 2010-08-11 東京エレクトロン株式会社 プラズマ窒化処理方法、制御プログラム、コンピュータ記憶媒体およびプラズマ処理装置
US7138691B2 (en) * 2004-01-22 2006-11-21 International Business Machines Corporation Selective nitridation of gate oxides
JP2005235987A (ja) * 2004-02-19 2005-09-02 Toshiba Corp 半導体記憶装置及び半導体記憶装置の製造方法
US7629270B2 (en) * 2004-08-27 2009-12-08 Asm America, Inc. Remote plasma activated nitridation
JP4564310B2 (ja) * 2004-09-01 2010-10-20 株式会社日立国際電気 半導体装置の製造方法
CN101156234B (zh) * 2005-03-31 2012-01-25 东京毅力科创株式会社 基板的氮化处理方法和绝缘膜的形成方法
JP4509864B2 (ja) * 2005-05-30 2010-07-21 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置
KR100777016B1 (ko) * 2006-06-20 2007-11-16 재단법인서울대학교산학협력재단 기둥 구조를 갖는 낸드 플래시 메모리 어레이 및 그제조방법
JP4764267B2 (ja) * 2006-06-27 2011-08-31 株式会社東芝 半導体装置およびその製造方法
JPWO2008081724A1 (ja) * 2006-12-28 2010-04-30 東京エレクトロン株式会社 絶縁膜の形成方法および半導体装置の製造方法
US7867923B2 (en) * 2007-10-22 2011-01-11 Applied Materials, Inc. High quality silicon oxide films by remote plasma CVD from disilane precursors
US8216913B2 (en) * 2007-12-24 2012-07-10 Texas Instruments Incorporated Strain modulation in active areas by controlled incorporation of nitrogen at si-SiO2 interface
JP2009289902A (ja) * 2008-05-28 2009-12-10 Toshiba Corp Nand型フラッシュメモリおよびその製造方法
US8748259B2 (en) * 2010-03-02 2014-06-10 Applied Materials, Inc. Method and apparatus for single step selective nitridation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6800830B2 (en) * 2000-08-18 2004-10-05 Hitachi Kokusai Electric, Inc. Chemistry for boron diffusion barrier layer and method of application in semiconductor device fabrication
US20040063284A1 (en) * 2000-12-31 2004-04-01 Texas Instruments Incorporated Scalable dielectric
US6960502B2 (en) * 2002-06-18 2005-11-01 Fujitsu Limited Semiconductor device fabrication method
CN101080810A (zh) * 2005-09-22 2007-11-28 东京毅力科创株式会社 选择性等离子体处理方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107431033A (zh) * 2015-03-20 2017-12-01 应用材料公司 用于3d共形处理的原子层处理腔室
CN107431033B (zh) * 2015-03-20 2021-10-22 应用材料公司 用于3d共形处理的原子层处理腔室
CN115863151A (zh) * 2022-12-25 2023-03-28 北京屹唐半导体科技股份有限公司 工件处理方法、工件处理设备及半导体器件
CN115863151B (zh) * 2022-12-25 2023-10-27 北京屹唐半导体科技股份有限公司 工件处理方法、工件处理设备及半导体器件

Also Published As

Publication number Publication date
KR20130029056A (ko) 2013-03-21
WO2011109266A3 (en) 2012-03-01
US20140342543A1 (en) 2014-11-20
US9023700B2 (en) 2015-05-05
TWI521573B (zh) 2016-02-11
CN102782816B (zh) 2016-05-18
US8748259B2 (en) 2014-06-10
US20110217834A1 (en) 2011-09-08
WO2011109266A2 (en) 2011-09-09
TW201145363A (en) 2011-12-16
JP2013521653A (ja) 2013-06-10
KR101861202B1 (ko) 2018-06-29
WO2011109266A4 (en) 2012-04-19

Similar Documents

Publication Publication Date Title
CN102782816A (zh) 单步骤选择性氮化方法与设备
KR102588666B1 (ko) 기판 상의 구조물 형성 방법
US20220220608A1 (en) Films of desired composition and film properties
KR102515238B1 (ko) 실리콘 카바이드 막들의 컨포멀한 증착
US10002787B2 (en) Staircase encapsulation in 3D NAND fabrication
TWI714504B (zh) 沉積氮化矽薄膜的方法
TWI718131B (zh) 超薄原子層沉積膜精度厚度控制
JP6661625B2 (ja) 高温酸化ケイ素原子層堆積技術
TWI398925B (zh) 氮化硼及氮化硼衍生材料之沉積方法
TW202115275A (zh) 在反應空間中的基板的表面上形成氮化矽薄膜之方法
KR20180077093A (ko) 기판 상에 구조물을 형성하는 방법
US20050145177A1 (en) Method and apparatus for low temperature silicon nitride deposition
WO2010048236A2 (en) Non-volatile memory having silicon nitride charge trap layer
TWI691001B (zh) 用於3d共形處理的原子層製程腔室
KR20240112358A (ko) 컨포멀한 (conformal), 탄소-도핑된 실리콘 나이트라이드 막들 및 이의 방법들
TWI670391B (zh) 具有氣體分佈及個別泵送的批次固化腔室
WO2023102440A1 (en) Conformal, carbon-doped silicon nitride films and methods thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant