TWI506794B - 具有摻雜子鰭區域的非平面半導體裝置及其製造方法 - Google Patents
具有摻雜子鰭區域的非平面半導體裝置及其製造方法 Download PDFInfo
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- TWI506794B TWI506794B TW103115368A TW103115368A TWI506794B TW I506794 B TWI506794 B TW I506794B TW 103115368 A TW103115368 A TW 103115368A TW 103115368 A TW103115368 A TW 103115368A TW I506794 B TWI506794 B TW I506794B
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Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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Description
本發明之實施例係在半導體裝置及處理的領域中,且特別地,係具有摻雜子鰭區域的非平面半導體裝置及具有摻雜子鰭區域的非平面半導體裝置之製造方法。
關於過去的數十年,在積體電路中之特徵的縮放已變成不斷成長之半導體產業後面的驅動力。對越變越小之特徵的縮放使半導體晶片之受限的實際所有域上的功能性單元能增加密度。例如,縮減的電晶體尺寸允許晶片上之增大數目的記憶體或邏輯裝置之結合,而適合於具有增大容量之產品的製造。然而,對於更多容量的驅動器並非毫無問題。使各裝置之性能最佳化的必要性變成漸增地重要。
在積體電路裝置的製造中,當裝置尺寸持續縮小比例時,諸如三閘極電晶體之多重閘極電晶體已變成更加流行。在習知處理中,三閘極電晶體係通常製造於巨塊矽基板上或矽在絕緣體上之基板上。在若干情況中,由於其較
低的成本以及與現有高產能之巨塊矽基板基礎結構的可相容性,巨塊矽基板係較佳的。
然而,縮放多重閘極電晶體並非毫無後果。當縮減微電子電路之該等基本建構區塊的尺寸時,以及當增加給定區域中所製造之基本建構區塊的絕對數目時,則在使用以製造該等建構區塊之半導體處理上的約束變成不可抵抗。
100,200‧‧‧巨塊半導體基板
102,202‧‧‧鰭
104‧‧‧硬遮罩層
106‧‧‧墊氧化物層
108,208‧‧‧P型固態摻雜物源層
108’,208’‧‧‧圖案化之P型固態摻雜物源層
110,210,214‧‧‧地表遮罩部分
112‧‧‧抗反射塗佈層
114,209,215‧‧‧絕緣緩衝層或阻隔層
116,216‧‧‧電介質填充層
118‧‧‧遮罩層
120‧‧‧阱及/或逆行佈植操作
122‧‧‧N型摻雜鰭
122’,124’,222’,224’‧‧‧共同摻雜區
124,222‧‧‧P型摻雜子鰭區域
126,223,226,380‧‧‧介面
209’‧‧‧圖案化之絕緣緩衝層或阻隔層
212‧‧‧N型固態摻雜物源層
212’‧‧‧圖案化之N型固態摻雜物源層
224‧‧‧N型摻雜子鰭區域
300‧‧‧半導體結構或裝置
302‧‧‧基板
304‧‧‧凸出鰭部分
304A‧‧‧源極區
304B‧‧‧汲極區
305‧‧‧子鰭區域
306‧‧‧隔離區
308‧‧‧閘極線
314‧‧‧閘極接點
316‧‧‧上方閘極接觸通孔
350‧‧‧閘極電極
352‧‧‧閘極電介質層
354‧‧‧電介質帽蓋層
360‧‧‧上方金屬互連
370‧‧‧層間電介質堆疊或互連
400,402‧‧‧模擬的2D輪廓圖表
500‧‧‧測量的1D:SIMS摻雜物縱剖面
600‧‧‧計算裝置
602‧‧‧板
604‧‧‧處理器
606‧‧‧通訊晶片
第1A至1I圖描繪依據本發明實施例之具有摻雜子鰭區域的非平面半導體裝置之製造方法中之種種操作的橫剖面視圖,其中:第1A圖描繪具有被蝕刻於其中之鰭的巨塊半導體基板;第1B圖描繪被形成於第1A圖之結構上的P型固態摻雜物源層;第1C圖描繪僅被形成於第1B圖之鰭的一部分上之圖案化的遮罩;第1D圖描繪用以形成圖案化的P型固態摻雜物源層之P型固態摻雜物源層108的圖案化;第1E圖描繪與第1D圖之暴露的鰭及圖案化的P型固態摻雜物源層共形之絕緣緩衝層或阻隔層的形成;第1F圖描繪與第1E圖的結構上之電介質填充層的形成及平坦化,用以暴露出鰭的頂部表面;第1G圖描繪專用於NMOS裝置製造之鰭的遮罩,伴
隨有阱及/或逆行佈植操作,用以自暴露之PMOS專用的鰭形成N型摻雜鰭;第1H圖描繪電介質填充層、圖案化的P型固態摻雜物源層、及絕緣緩衝層或阻隔層之凹進,用以暴露出第1G圖之鰭的凸出部分;以及第1I圖描繪驅入退火,用以提供專用於NMOS裝置之鰭的摻雜子鰭區域。第2A至2I圖描繪依據本發明實施例之具有摻雜子鰭區域的非平面半導體裝置之另一製造方法中之種種操作的橫剖面視圖,其中:第2A圖描繪具有被蝕刻於其中之鰭的巨塊半導體基板;第2B圖描繪被形成於第2A圖之結構上的P型固態摻雜物源層及與該P型固態摻雜物源層共形之絕緣緩衝層或阻隔層的形成;第2C圖描繪僅被形成於第2B圖之鰭的一部分上之圖案化的遮罩和絕緣緩衝層或阻隔層及P型固態摻雜物源層的圖案化;第2D圖描繪被形成於第2C圖之暴露的鰭和圖案化的絕緣緩衝層或阻隔層及圖案化的P型固態摻雜物源層上之N型固態摻雜物源層的形成;第2E圖描繪僅被形成於第2D圖之鰭的一部分上之圖案化的遮罩及N型固態摻雜物源層的圖案化;第2F圖描繪與該N型固態摻雜物源層共形之絕緣緩
衝層或阻隔層的形成;第2G圖描繪第2F圖的結構上之電介質填充層的形成;第2H圖描繪電介質填充層、圖案化的P型固態摻雜物源層、圖案化的N型固態摻雜物源層、及絕緣緩衝層或阻隔層之平坦化及凹進,用以暴露出第2G圖之鰭的凸出部分;以及第2I圖描繪驅入退火,用以提供專用於NMOS及PMOS裝置二者之鰭的摻雜鰭區域。第3A圖描繪依據本發明實施例之具有具備摻雜子鰭區域的鰭之非平面半導體裝置的橫剖面視圖。第3B圖描繪依據本發明實施例之沿著第3A圖的半導體裝置之a-a’軸所取得的平面視圖。第4A圖係依據本發明實施例之模擬的2D輪廓圖表,用以說明對子鰭區域的硼摻雜物局限。第4B圖係依據本發明實施例之模擬的2D輪廓圖表,用以說明對子鰭區域的磷摻雜物局限。第5圖係依據本發明實施例之測量的1D SIMS摻雜物縱剖面,用以說明自摻雜絕緣體層至矽基板內之摻雜物的擴散。第6圖描繪依據本發明之一實施例的計算裝置。
將敘述具有摻雜子鰭區域的非平面半導體裝置及具有
摻雜子鰭區域的非平面半導體裝置之製造方法。在以下說明中,係陳明諸如特定的集成和材料體制之許多特定的細節,以便提供本發明之實施例的完全瞭解。對熟習本項技藝之人士將呈明顯的是,本發明可無需該等特定的細節而予以實施。在其他情況中,為了要免於非必要地使本發明之實施例混淆,諸如積體電路設計佈局之熟知的特徵將不予以詳細敘。再者,應被瞭解的是,在圖式中所示的種種實施例係描繪性的表示,且無需一定要按比例地予以繪製。
在此所敘述之一或多個實施例係針對例如,藉三閘極摻雜之玻璃子鰭向外擴散而選擇性地摻雜被製造在巨塊矽晶圓上之三閘極或FinFET電晶體之子鰭區域的處理。例如,在此所敘述係用以選擇性地摻雜三閘極或FinFET電晶體之子鰭區域以減緩子鰭漏洩而同時保持鰭摻雜低的處理。結合固態摻雜物源(例如,p型及n型摻雜氧化物、氮化物、或碳化物)至從鰭側壁凹進之後的電晶體處理流程內,將遞送阱摻雜至子鰭區域內,且同時保持鰭本體相對地未被摻雜。此外,在實施例中,本文所敘述之一或多個途徑使巨塊鰭之主動部分的底部能與該主動部分和剩餘巨塊部分(例如,在閘極控制區域下方的部分)之間的摻雜邊界自行對齊。
更一般而言,使用巨塊矽以供鰭或三閘極之用,可係所欲的。然而,卻具有使在裝置之主動矽鰭部分下方的區域(子鰭)(例如,閘極控制區域、或HSi)減少或無閘極控
制之利害關係。同樣地,若源極或汲極區係在HSi點或在HSi點下方時,則漏洩路線可穿過子鰭區域而存在。依據本發明之實施例,為了要解決上述問題,足夠的摻雜係穿過子鰭摻雜而加以提供,無需一定要遞送相同位準之摻雜到鰭的HSi部分。
實施例可包含以下特徵或考慮之一或多者:(1)具有高摻雜子鰭區域的低摻雜鰭;(2)做為用於NMOS子鰭區域的摻雜物源之硼摻雜氧化物(例如,BSG)的使用;(3)做為用於PMOS子鰭區域的摻雜物源之磷摻雜氧化物(例如,PSG)或砷摻雜氧化物(例如,AsSG)的使用;(4)低摻雜NMOS鰭/BSG摻雜子鰭加上標準佈植之PMOS鰭(例如,包含圖案化處理以自PMOS結構去除硼摻雜氧化物,而隨後,NMOS阱摻雜係由硼摻雜層所遞送,且PMOS阱摻雜係由習知佈植處理所達成);(5)低摻雜PMOS鰭/PSG或AsSG摻雜子鰭加上標準佈植之NMOS鰭(例如,包含圖案化處理以自NMOS結構去除磷或砷摻雜氧化物,而隨後,PMOS阱摻雜係由磷或砷摻雜層所遞送,且NMOS阱摻雜係由習知佈植處理所達成);(6)藉由BSG/(PSG或AsSG)摻雜子鰭之集成而被形成於相同的晶圓上之低摻雜PMOS及NMOS鰭(例如,包含圖案化處理以積集由BSG摻雜物向外擴散所形成之NMOS子鰭區域及由PSG或AsSG摻雜物向外擴散所形成之PMOS子鰭區域於相同的晶圓上)。此處所敘述之處理可在NMOS及PMOS裝置二者中,使低摻雜NMOS及PMOS鰭能以高的子鰭摻雜予
以製造。更概括地,應被瞭解的是,取代BSG、PSG、或AsSG,N型或P型固態摻雜物源層係分別結合N型或P型摻雜物於其中之電介質層,諸如N型或P型摻雜氧化物、氮化物、或碳化物層,但並未受限於該等者。
謹提供前後關聯,要解決上述問題之習知途徑已包含阱佈植操作的使用,其中子鰭區域係重摻雜(例如,極大於2×1018
/cm3
),其將切斷子鰭漏洩且亦在鰭中引起實質的摻雜。環形佈植的添加進一步地增加鰭摻雜,以致使排列之鰭的末端被以高位準摻雜(例如,約大於1×1018
/cm3
)。相較之下,本文所敘述的一或多個實施例在鰭中提供低摻雜,其可係有益的;因為較高的電流驅動係藉由增進載子遷移率而予以致能,但在其他方面,則將由於用於高摻雜通道裝置之游離的雜質散射而被降級。再者,因為臨限電壓(Vt)的隨機變化係直接成比例於摻雜密度的平方根,所以低摻雜裝置亦具有減低Vt中之隨機不匹配的優點。此使產品能在較低電壓中操作,而無功能性之失效。同時,正好在鰭下方之區域(亦即,子鰭)必須被高度摻雜,以便防止子鰭之源極-汲極漏洩。為遞送此摻雜至子鰭區域所使用之習知佈植步驟亦實質地摻雜鰭,而無法達成低摻雜鰭及同時抑制子鰭漏洩。
如下文所更完整敘述地,在此所敘述之一或多個實施例可包含在鰭蝕刻後之沈積在鰭上之固體源摻雜層(例如,硼摻雜氧化物)的使用。稍後,在溝渠填充及研磨之後,該摻雜層係與溝渠填充材料一起凹進,以界定裝置的
鰭高度(HSi)。操作從HSi上方的鰭側壁去除摻雜層。因此,摻雜層僅沿著子鰭區域中之鰭側壁而存在,此確保摻雜配置的精確控制。在驅入退火之後,高摻雜係受限至子鰭區域,而在HSi上方之鰭的鄰近區域中快速地躍遷至低摻雜(其形成電晶體的通道區)。一或多個優點或實施例包含:(1)固態源摻雜層的使用;(2)圖案化以自相反極性裝置去除摻雜層;(3)在一操作中之使溝渠材料及摻雜層凹進的蝕刻操作;(4)增進之電晶體電流驅動及改善的Vt不匹配;(5)自裝置流程完全地去除阱佈植的可能性(在該情況中,固態摻雜的使用提供電晶體間之隔離,且因此,個別的阱形成可不再係必要的)。
在第一實例中,第1A至1I圖描繪依據本發明實施例之具有摻雜子鰭區域的非平面半導體裝置之製造方法中之種種操作的橫剖面視圖。在一特定實施例中,第一代表性處理流程可被敘述成為硼矽酸鹽玻璃(BSG)NMOS及佈植PMOS製造方案。
請參閱第1A圖,諸如巨塊單晶矽基板之巨塊半導體基板100係設置具有被蝕刻於其中的鰭102。在實施例中,該等鰭係直接形成於巨塊基板100中,且同樣地,係延續巨塊基板100而被形成。殘留自鰭102之製造的人工製品亦可存在。例如,如第1A圖中所描繪地,諸如氮化矽硬遮罩層之硬遮罩層104,及諸如二氧化矽層之墊氧化物層106留在鰭102的頂部。在一實施例中,巨塊基板100,且因此,該等鰭102,係在此階段未摻雜或微摻
雜。例如,在特殊的實施例中,巨塊基板100,且因此,該等鰭102,具有小於大約1×1017
原子/cm3
之硼摻雜物雜質原子的濃度。
請參閱第1B圖,P型固態摻雜物源層108係形成於第1A圖的結構上。在一實施例中,P型固態摻雜物源層108係諸如,但未受限於P型摻雜氧化物、氮化物、或碳化物層之結合P型摻雜物於其中的電介質層。在特定的該實施例中,P型固態摻雜物源層108係硼矽酸鹽玻璃層。P型固態摻雜物源層108可藉由適合以在鰭102上提供共形層的處理而予以形成。例如,在一實施例中,P型固態摻雜物源層108係藉由化學氣相沈積(CVD)處理或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而在第1A圖的整個結構上方被形成為共形層。在特殊的實施例中,P型固態摻雜物源層108係具有硼濃度約在0.1至10重量百分比的範圍中之BSG層。在另一實施例中,可將帽蓋層形成於P型固態摻雜物源層108上,做為在原處形成之帽蓋層,用以在隨後暴露至周遭情形的期間,保護該P型固態摻雜物源層108。在一該實施例中,帽蓋層係氮化物、碳化物、或氧化鋁(Al2
O3
)帽蓋層。應予以瞭解的是,若有的話,可在與被使用於P型固態摻雜物源層108相同的圖案化操作中,使該帽蓋層圖案化。
請參閱第1C圖,圖案化之遮罩係僅形成於該等鰭102的一部分之上。如將與隨後之處理操作相關聯而予以
敘述地,此遮罩操作致能用於NMOS裝置的鰭與用於PMOS裝置的鰭之間的區別。在一實施例中,該遮罩係由地形遮罩部分110與抗反射塗佈(ARC)層112所構成。在特殊之該實施例中,地形遮罩部分110係碳硬遮罩(CHM)層,以及抗反射塗佈層112係矽ARC層。該地形遮罩部分110及該ARC層112可以以習知的微影術及蝕刻處理技術予以圖案化。
請參閱第1D圖,且在例如,適用於NMOS或PMOS裝置之鰭102的指明上,係自此處以後指示於處理流程中。特別地,請參閱第1D圖,P型固態摻雜物源層108係例如,藉由電漿、氣相、或濕蝕刻處理而予以圖案化,用以形成圖案化之P型固態摻雜物源層108’。而且,所描繪的係抗反射塗佈層112之去除,其亦可使用電漿、氣相、或濕蝕刻處理而予以執行。P型固態摻雜物源層108的圖案化及抗反射塗佈層112之去除可在相同的或不同的處理操作中予以執行。
請參閱第1E圖,地形遮罩部分110被去除,其可使用電漿、氣相、或濕蝕刻處理而予以執行。地形遮罩部分110的去除可在與抗反射塗佈層112之去除相同的處理操作中,或在隨後的處理操作中予以執行。而且,在第1E圖中所描繪之諸如隔離氮化物層的絕緣緩衝層或阻隔層114係與例如,該等暴露之鰭102及該圖案化之P型固態摻雜物源層108’共形而予以形成,用以帽蓋該圖案化之P型固態摻雜物源層108’。絕緣緩衝層或阻隔層114可藉由
適合以在暴露之鰭102及圖案化之P型固態摻雜物源層108’上提供共形層之處理,而予以形成。例如,在一實施例中,絕緣緩衝層或阻隔層114係藉由化學氣相沈積(CVD)處理或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而予以形成。
請參閱第1F圖,電介質填充層116係形成於第1E圖的結構上,且隨後,被平坦化以暴露出鰭102的頂部表面(例如,暴露出NMOS及PMOS專用的鰭102二者)。在一實施例中,電介質填充層116係由諸如被使用於淺溝渠隔離製造處理中的二氧化矽所構成。電介質填充層116可藉由化學氣相沈積(CVD)處理或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而予以沈積,且可藉由化學機械研磨(CMP)技術而予以平坦化。若存在的話,該平坦化亦自鰭102的頂部去除圖案化之P型固態摻雜物源層108’及絕緣緩衝層或阻隔層114之部分。如在第1F圖中亦被描繪地,來自鰭圖案化之諸如硬遮罩層104及墊氧化物層106的任何人工製品可在CMP處理期間予以去除,而暴露出鰭102。在選擇性的實施例中,為了要消除或降低來自鰭之頂部的閘極控制,可將硬遮罩或其他電介質層保留在鰭的頂部上(例如,如在雙閘極裝置對三閘極裝置中)。
請參閱第1G圖,專用於NMOS裝置製造的鰭102係藉由遮罩層118而予以遮罩。在一實施例中,遮罩層118係如本項技藝中所已知地由光阻層所構成,且可藉由習知
之微影術及顯影處理而予以圖案化。在特殊實施例中,所曝光至光源之光阻層的部分係在顯影該光阻層時被去除。因此,圖案化之光阻層係由正光阻材料所構成。在特定實施例中,該光阻層係由諸如,但未受限於,248nm阻體、193nm阻體、157nm阻體、遠紫外光(EUV)阻體、電子束印記層、或具有重氮萘醌增感劑之酚醛樹脂基質的正光阻材料所構成。在另一特殊實施例中,所曝光至光源之光阻層的部分係在顯影該光阻層時被保留。因此,光阻層係由負光阻材料所構成。在特定實施例中,該光阻層係由諸如,但未受限於,由聚異丙烯或聚乙烯醇肉桂酸酯所組成之負光阻材料所構成。
此外,請再參閱第1G圖,阱及/或逆行佈植操作120係執行以自暴露之PMOS專用鰭形成N型摻雜鰭122。暴露之鰭的摻雜可導致巨塊基板部分100之內的摻雜,其中鄰近的鰭122分享巨塊基板100中之共同摻雜區122’。在一實施例中,N型摻雜鰭122,以及共同摻雜區122’(若存在的話),係摻雜以包含具有2×1018
原子/cm3
或更大之總濃度的磷及/或砷之N型摻雜物。
請參閱第1H圖,電介質填充層116係凹進以暴露出鰭102及122的突出部分。此外,圖案化之P型固態摻雜物源層108’及絕緣緩衝層或阻隔層114(若存在的話),係凹進至與電介質填充層116大約相同的位準,如第1H圖中所描繪地。該等層的凹進可藉由電漿、氣相、或濕蝕刻處理而予以執行。在一實施例中,係使用適合於矽鰭的乾
蝕刻處理,該乾蝕刻處理係根據由諸如,但未受限於NF3
、CHF3
、C4
F8
、HBr、及O2
之氣體,而典型地以在30至100毫托之範圍中的壓力及50至1000瓦的電漿偏壓所產生之電漿。在實施例中,電介質填充層116及圖案化之P型固態摻雜物源層108’係以大約1:1之選擇性予以同時地凹進。在另一實施例中,電介質填充層116及圖案化之P型固態摻雜物源層108’係順序地凹進。
請參閱第1I圖,驅入退火係執行以提供專用於NMOS裝置之鰭的摻雜子鰭區域。更特別地,當加熱時,諸如硼摻雜物原子之來自圖案化之P型固態摻雜物源層108’的摻雜物被擴散至子鰭區域內(在凹進之電介質填充層116下方的該等區域),而形成P型摻雜子鰭區域124。該擴散亦可導致巨塊基板部分100之內的摻雜,其中鄰近的鰭102分享巨塊基板100中之共同摻雜區124’。在此方式中,NMOS裝置之鰭102的凸出部分,例如,凸出部分102’,保持未摻雜或微摻雜,例如,本質地保持與第1A圖相關聯所敘述之原始巨塊基板100及鰭102的摻雜縱剖面。因而,介面126存在於凸出部分102’與P型摻雜子鰭區域124之間。在一該實施例中,介面126表示摻雜濃度步階或迅速梯度改變,其中P型摻雜子鰭區域124具有2×1018
原子/cm3
或更大的總摻雜物濃度,而凸出部分102’主要具有小於2×1018
原子/cm3
,例如,大約5×1017
原子/cm3
或更小的總摻雜物濃度。躍遷區域可相對地陡峭,如與第4A及4B圖相關聯而在下文中予以更詳細敘述地。
請參閱第1I圖,P型摻雜子鰭區域124係摻雜跨越整個子鰭區域。在一該實施例中,各鰭約係10奈米寬,以及第1G圖的摻雜物驅入處理僅需來自圖案化之P型固態摻雜物源層108’的各側之摻雜物的5奈米驅入。在實施例中,驅入操作係執行於大約在800至1500攝氏度之範圍中的溫度處。
概括地,請再參閱第1A至1I圖,在實施例中,硼矽酸鹽玻璃(BSG)之摻雜層係使用以摻雜NMOS裝置的子鰭區域。BSG之層係在鰭蝕刻後,沈積在鰭之上。晶圓被圖案化,以致使BSG自PMOS區域予以去除。阻隔或勢壘層可被沈積以在BSG與溝渠填充(電介質116)材料之間形成勢壘,而使強勁的硼之向內擴散能自BSG膜進入至矽子鰭之內。在溝渠填充及研磨之後,PMOS鰭係以標準的阱佈植物予以摻雜。溝渠填充凹進操作自NMOS鰭上的鰭凸出物去除BSG。最終地,驅入退火操作驅動硼摻雜至子鰭之內,而留下無需有效摻雜之鰭的凸出部分。將被瞭解的是,在另一實施例中,與第1A至1I圖相關聯所敘述之導電類型可予以顛倒,例如,N型用於P型,且反之亦然。
在另一觀點中,對於NMOS及PMOS裝置二者之製造而言,可使用固態摻雜源以摻雜子鰭區域。因此,在第二實例中,第2A至2I圖描繪依據本發明實施例之具有摻雜子鰭區域的非平面半導體裝置之另一製造方法中之種種操作的橫剖面視圖。在一特定實施例中,第二代表性處理
流程可被敘述成為硼矽酸鹽玻璃(BSG)NMOS及磷矽酸鹽玻璃(PSG)或砷矽酸鹽玻璃(AsSG)PMOS製造方案。
請參閱第2A圖,諸如巨塊單晶矽基板之巨塊半導體基板200係設置具有被蝕刻於其中的鰭202。在實施例中,該等鰭係直接形成於巨塊基板200中,且同樣地,係延續巨塊基板200而被形成。殘留自鰭202之製造的人工製品(例如,氮化矽硬遮罩層及在下方的墊氧化物層)可在此階段予以去除,如在第2A圖中所描繪地。選擇性地,諸如氮化矽硬遮罩層之硬遮罩層,及諸如二氧化矽層之墊氧化物層可留在鰭的頂部,如與第1A圖相關聯而予以敘述地。在一實施例中,巨塊基板200,且因此,該等鰭202係在此階段未摻雜或微摻雜。例如,在特殊的實施例中,巨塊基板200,且因此,該等鰭202,具有小於大約5×1017
原子/cm3
之硼摻雜物雜質原子的濃度。
請參閱第2B圖,P型固態摻雜物源層208係形成於第2A圖的結構上。在一實施例中,P型固態摻雜物源層208係諸如,但未受限於P型摻雜氧化物、氮化物、或碳化物層之結合P型摻雜物於其中的電介質層。在特定的該實施例中,P型固態摻雜物源層208係硼矽酸鹽玻璃層。P型固態摻雜物源層208可藉由適合以在鰭202上提供共形層的處理而予以形成。例如,在一實施例中,P型固態摻雜物源層208係藉由化學氣相沈積(CVD)處理或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而在第2A圖的整個結構上方被形成為共形
層。在特殊的實施例中,P型固態摻雜物源層208係具有硼濃度約在0.1至10重量百分比的範圍中之BSG層。在另一實施例中,可將帽蓋層形成於P型固態摻雜物源層208上,做為在原處形成之帽蓋層,用以在隨後暴露至周遭情形的期間,保護該P型固態摻雜物源層208。在一該實施例中,帽蓋層係氮化物、碳化物、或氧化鋁(Al2
O3
)帽蓋層。應予以瞭解的是,若有的話,可在與被使用於P型固態摻雜物源層208相同的圖案化操作中,使該帽蓋層圖案化。
請再參閱第2B圖,諸如隔離氮化物層的絕緣緩衝層或阻隔層209係與例如,P型固態摻雜物源層208共形而予以形成,用以帽蓋該P型固態摻雜物源層208。絕緣緩衝層或阻隔層209可藉由適合以P型固態摻雜物源層208上提供共形層之處理,而予以形成。例如,在一實施例中,絕緣緩衝層或阻隔層209係藉由化學氣相沈積(CVD)處理或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而予以形成。
請參閱第2C圖,且在例如,適用於NMOS或PMOS裝置之鰭202的指明上,係自此處以後指示於處理流程中。特別地,請參閱第2C圖,圖案化之遮罩係僅形成於該等鰭202的一部分之上。如將與隨後的處理操作相關聯而予以敘述地,此遮罩操作致能用於NMOS裝置的鰭與用於PMOS裝置的鰭之間的區別。在一實施例中,該遮罩係由地形遮罩部分210及可能地,抗反射塗佈(ARC)層(未顯
示)所構成。在特殊之該實施例中,地形遮罩部分210係碳硬遮罩(CHM)層,以及抗反射塗佈層係矽ARC層。該地形遮罩部分210及該ARC層可以以習知的微影術及蝕刻處理技術予以圖案化。請再參閱第2C圖,絕緣緩衝層或阻隔層209,及P型固態摻雜物源層208係例如,藉由電漿、氣相、或濕蝕刻處理而予以圖案化,用以分別地形成圖案化之絕緣緩衝層或阻隔層209’及圖案化之P型固態摻雜物源層208’。
請參閱第2D圖,地形遮罩部分210被去除,其可使用電漿、氣相、或濕蝕刻處理而予以執行。而且,在第2D圖中所描繪之N型固態摻雜物源層212係與暴露之鰭共形,且與圖案化之絕緣緩衝層或阻隔層209’及圖案化之P型固態摻雜物源層208’共形,而被形成。在一實施例中,N型固態摻雜物源層212係諸如,但未受限於N型摻雜氧化物、氮化物、或碳化物層之結合N型摻雜物於其中的電介質層。在特定的該實施例中,N型固態摻雜物源層212係磷矽酸鹽玻璃層或砷矽酸鹽玻璃層。N型固態摻雜物源層212可藉由適合以在暴露之鰭以及圖案化之絕緣緩衝層或阻隔層209’及圖案化之P型固態摻雜物源層208’上提供共形層的處理,而予以形成。例如,在一實施例中,N型固態摻雜物源層212係藉由化學氣相沈積(CVD)處理或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而在第2C圖的整個結構上方被形成為共形層(已自該處去除210)。在特殊的實施例
中,N型固態摻雜物源層212係分別具有磷或砷濃度約在0.1至10重量百分比的範圍中之PSG層或AsSG層。在另一實施例中,可將帽蓋層形成於N型固態摻雜物源層212上,做為在原處形成之帽蓋層,用以在隨後暴露至周遭情形的期間,保護該N型固態摻雜物源層212。在一該實施例中,帽蓋層係氮化物、碳化物、或氧化鋁(Al2
O3
)帽蓋層。應予以瞭解的是,若有的話,可在與被使用於N型固態摻雜物源層212相同的圖案化操作中,使該帽蓋層圖案化。
請參閱第2E圖,圖案化之遮罩係僅形成於該等鰭的一部分之上。如將與隨後之處理操作相關聯而予以敘述地,此遮罩操作致能用於NMOS裝置的鰭與用於PMOS裝置的鰭之間的區別。在一實施例中,該遮罩係由地形遮罩部分214及可能地,抗反射塗佈(ARC)層(未顯示)所構成。在特殊之該實施例中,地形遮罩部分214係碳硬遮罩(CHM)層,以及抗反射塗佈層係矽ARC層。該地形遮罩部分214及該ARC層可以以習知的微影術及蝕刻處理技術予以圖案化。請再參閱第2E圖,N型固態摻雜物源層212係例如,藉由電漿、氣相、或濕蝕刻處理而予以圖案化,用以形成圖案化之N型固態摻雜物源層212’。
在選擇性實施例中,與第2E圖相關聯而予以敘述之遮罩操作係自處理流程消除,而降低所需之遮罩操作的總數。在一該實施例中,接著,N型固態摻雜物源層212不被圖案化,且係保持於NMOS及PMOS位置二者中。圖
案化之絕緣緩衝層或阻隔層209’防止來自該未圖案化之N型固態摻雜物源層212的摻雜物進入至其中打算使圖案化之P型固態摻雜物源層208’做為摻雜源的位置中。
請參閱第2F圖,地形遮罩部分214被去除,其可使用電漿、氣相、或濕蝕刻處理而予以執行。而且,在第2F圖中所描繪之諸如隔離氮化物層的絕緣緩衝層或阻隔層215係與例如,圖案化之N型固態摻雜物源層212’及圖案化之絕緣緩衝層或阻隔層209’共形而予以形成,用以帽蓋圖案化之N型固態摻雜物源層212’。絕緣緩衝層或阻隔層215可藉由適合以提供共形層之處理,而予以形成。例如,在一實施例中,絕緣緩衝層或阻隔層215係藉由化學氣相沈積(CVD)處理或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而予以形成。不論N型固態摻雜物源層212是否被圖案化,絕緣緩衝層或阻隔層215可予以沈積。
請參閱第2G圖,電介質填充層216係形成於第2F圖的結構上。在一實施例中,電介質填充層216係由諸如被使用於淺溝渠隔離製造處理中的二氧化矽所構成。電介質填充層216可藉由化學氣相沈積(CVD)或其他沈積處理(例如,ALD、PECVD、PVD、HDP協助之CVD、低溫CVD),而予以沈積。
請參閱第2H圖,電介質填充層216係接著平坦化以暴露出鰭202的頂部表面(例如,暴露出NMOS及PMOS專用的鰭202二者)。電介質填充層216可藉由化學機械
研磨(CMP)技術而予以平坦化。若存在的話,該平坦化亦自鰭202的頂部去除圖案化之P型固態摻雜物源層208’、圖案化之N型固態摻雜物源層212’、及絕緣緩衝層或阻隔層209’及215。在選擇性的實施例中,為了要消除或降低來自鰭之頂部的閘極控制,可將硬遮罩或其他電介質層保留在鰭的頂部上(例如,如在雙閘極裝置對三閘極裝置中)。
請再參閱第2H圖,電介質填充層216係凹進以暴露出鰭202的突出部分。此外,圖案化之P型固態摻雜物源層208’、圖案化之N型固態摻雜物源層212’、及絕緣緩衝層或阻隔層209’及215(若存在的話),係凹進至與電介質填充層216大約相同的位準,如第2H圖中所描繪地。該等層的凹進可藉由電漿、氣相、或濕蝕刻處理而予以執行。在一實施例中,係使用適合於矽鰭的乾蝕刻處理,該乾蝕刻處理係根據由諸如,但未受限於NF3
、CHF3
、C4
F8
、HBr、及O2
之氣體,而典型地以在30至100毫托之範圍中的壓力及50至1000瓦的電漿偏壓所產生之電漿。
請參閱第2I圖,驅入退火係執行以提供專用於NMOS及PMOS裝置二者之鰭的摻雜子鰭區域。更特別地,當加熱時,諸如硼摻雜物原子之來自圖案化之P型固態摻雜物源層208’的摻雜物被擴散至子鰭區域內(在凹進之電介質填充層216下方的該等區域),而形成P型摻雜子鰭區域222。該擴散亦可導致巨塊基板部分200之內的摻雜,其
中鄰近的鰭202’分享巨塊基板200中之共同摻雜區222’。在此方式中,NMOS裝置之鰭202’的凸出部分保持未摻雜或微摻雜,例如,本質地保持與第2A圖相關聯所敘述之原始巨塊基板200及鰭202的摻雜縱剖面。因而,介面223存在於凸出部分202’與P型摻雜子鰭區域222之間。在一該實施例中,介面223表示摻雜濃度步階或迅速梯度改變,其中P型摻雜子鰭區域222且有2×1018
原子/cm3
或更大的的總摻雜物濃度,而凸出部分202’主要具有小於2×1018
原子/cm3
,例如,大約5×1017
原子/cm3
或更小的總摻雜物濃度。躍遷區域可相對地陡峭,如與第4A及4B圖相關聯而在下文中予以更詳細敘述地。
此外,當加熱時,諸如磷或砷摻雜物原子之來自圖案化之N型固態摻雜物源層212’的摻雜物被擴散至子鰭區域內(在凹進之電介質填充層216下方的該等區域),而形成N型摻雜子鰭區域224。該擴散亦可導致巨塊基板部分200之內的摻雜,其中鄰近的鰭202”分享巨塊基板200中之共同摻雜區224’。在此方式中,PMOS裝置之鰭202”的凸出部分保持未摻雜或微摻雜,例如,本質地保持與第2A圖相關聯所敘述之原始巨塊基板200及鰭202的摻雜縱剖面。因而,介面226存在於凸出部分222”與N型摻雜子鰭區域224之間。在一該實施例中,介面226表示摻雜濃度步階或迅速梯度改變,其中N型子鰭區域224具有2×1018
原子/cm3
或更大的總摻雜物濃度,而凸出部分222”主要具有小於2×1018
原子/cm3
,例如,大約5×1017
原子/cm3
或更小的總摻雜物濃度。躍遷區域可相對地陡峭,如與第4A及4B圖相關聯而在下文中予以更詳細敘述地。
請參閱第2I圖,P型摻雜子鰭區域222及N型摻雜子鰭區域224係摻雜跨越個別的整個子鰭區域。在一該實施例中,各鰭約係10奈米寬,以及第2G圖的摻雜物驅入處理僅需來自個別的圖案化之P型固態摻雜物源層208’或圖案化之N型固態摻雜物源層212’的各側之摻雜物的5奈米驅入。在實施例中,驅入操作係執行於大約在800至1050攝氏度之範圍中的溫度處。
概括地,請再參閱第2A至2I圖,在實施例中,硼矽酸鹽玻璃(BSG)係實施用於NMOS鰭摻雜,而磷矽酸鹽玻璃(PSG)或砷矽酸鹽玻璃(AsSG)層係實施用於PMOS鰭摻雜。將被瞭解的是,在另一實施例中,與第2A至2I圖相關聯所敘述之導電類型可予以顛倒,例如,N型用於P型。且反之亦然。
將被瞭解的是,由上述代表性之處理方案所產生的結構,例如,第1I及2I圖之結構,可以以相同或相似的形式予以使用於隨後的處理操作,以完成諸如PMOS及NMOS裝置製造之裝置製造。做為完成之裝置的實例,第3A及3B圖分別描繪依據本發明實施例之具有具備摻雜子鰭區域的鰭之非平面半導體裝置的橫剖面視圖及平面視圖(沿著該橫剖面視圖之a-a’軸所取得)。
請參閱第3A圖,半導體結構或裝置300包含形成自
基板302且在隔離區306內的非平面主動區(例如,包含凸出鰭部分304及子鰭區域305的鰭結構)。閘極線308係設置在非平面主動區的凸出部分304上,以及在隔離區306的一部分上。如所顯示地,閘極線308包含閘極電極350及閘極電介質層352。在一實施例中,閘極線308亦可包含電介質帽蓋層354。閘極接點314及上方閘極接觸通孔316亦係連同上方金屬互連360而被一起觀察自此透視畫法,其所有者係設置在層間電介質堆疊或層370之中。而且,可自第3A圖之透視畫法觀察到的是,在一實施例中,閘極接點314係設置在隔離區306之上,而不在非平面主動區之上。例如,亦被描繪在第3A圖中的是,介面380存在於凸出鰭部分304及子鰭區域305的摻雜縱剖面之間。介面380可係相對陡峭的躍遷區域,如與第4A及4B圖相關聯而在下文中予以更詳細敘述地。
請參閱第3B圖,閘極線308係顯示成為被設置在凸出鰭部分304之上。該等凸出鰭部分304的源極區及汲極區304A及304B可被觀察自此透視畫法。在一實施例中,源極區及汲極區304A及304B係凸出鰭部分304之原始材料的摻雜部分。在另一實施例中,凸出鰭部分304之材料被去除,且例如,藉由磊晶沈積,而以另一半導體材料予以置換。在各情況中,源極區及汲極區304A及304B可在電介質層306的高度下方延伸,亦即,進入至子鰭區域305之內。在本發明之實施例中,更重摻雜之子鰭區域,亦即,在介面380之下方的鰭之摻雜部分可透過
巨塊半導體鰭之此部分而抑制源極及汲極的漏洩。
在實施例中,半導體結構或裝置300係諸如,但未受限於鰭式FET或三閘極裝置之非平面裝置。在該實施例中,對應之半導電通道區係由三維體所構成,或被形成於三維體之中。在一該實施例中,閘極線308的閘極電極堆疊包圍該三維體的至少頂部表面及一對側壁。
基板302可藉由能耐受製造處理且其中電荷可遷移之半導體材料,而予以構成。在實施例中,基板302係巨塊基板,由摻雜有諸如,但未受限於磷、砷、硼、或其組合之電荷載體,以形成主動區304的結晶矽、矽/鍺、或鍺層所構成。在一實施例中,於巨塊基板302中之矽原子的濃度係大於97%。在另一實施例中,巨塊基板302係由磊晶層成長在獨特結晶基板頂部上,例如,矽磊晶層成在硼摻雜巨塊矽單晶基板頂部上所構成。巨塊基板302可選擇性地由三五族材料所構成。在實施例中,巨塊基板302係由諸如,但未受限於氮化鎵、磷化鎵、砷化鎵、磷化銦、銻化銦、砷化銦鎵、砷化鋁鎵、磷化銦鎵、或其組合之三五族材料所構成。在一實施例中,巨塊基板302係由三五族材料所構成,以及電荷載體摻雜物雜質原子係諸如,但未受限於碳、矽、鍺、氧、硫、硒、或碲者。
隔離區306可由適合以最終地電性隔離永久閘極結構之部分與下方巨塊基板,或諸如隔離鰭主動區之隔離被形成於下方巨塊基板內之主動區,或促成該等者之隔離的材料所構成。例如,在一實施例中,隔離區306係由諸如,
但未受限於二氧化矽、氮氧化矽、氮化矽、或碳摻雜氮化矽之電介質材料所構成。
閘極線308可由包含閘極電介質層352及閘極電極層350之閘極電極堆疊所構成。在實施例中,閘極電極堆疊的閘極電極係由金屬閘極所構成,以及閘極電介質層係由高K材料所構成。例如,在一實施例中,閘極電介質層係由諸如,但未受限於氧化鉿、氮氧化鉿、矽酸鉿、氧化鑭、氧化鋯、矽酸鋯、氧化鉭、鈦酸鋇鍶、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、氧化鉛鈧鉭、鈮酸鉛鋅、或其組合之材料所構成。再者,閘極電介質層的一部分可包含由基板302之頂部少數層所形成之天然氧化物的層。在實施例中,閘極電介質層係由頂部高k部分及由半導體材料之氧化物所組成的下方部分所構成。在一實施例中,閘極電介質層係由氧化鉿的頂部部分及二氧化矽或氮氧化矽的底部部分所構成。
在一實施例中,閘極電極係由諸如,但未受限於金屬氮化物、金屬碳化物、金屬矽化物、金屬鋁化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷、鎳、或導電金屬氧化物之金屬層所構成。在特定實施例中,閘極電極係由被形成在金屬功函數設定層上方之非功函數設定填充材料所構成。
與閘極電極堆疊相關聯之間隔物可由適合以最終地電性隔離永久閘極結構與諸如自行對齊接點之鄰近導電接點,或促成該等者之隔離的材料所構成。例如,在一實施
例中,該等間隔物係由諸如,但未受限於二氧化矽、氮氧化矽、氮化矽、或碳摻雜氮化矽之電介質材料所構成。
閘極接點314及上方閘極接觸通孔316可由導電材料所構成。在實施例中,一或多個接點或通孔係由金屬物種所構成。該等金屬物種可係諸如鎢、鎳、或鈷之純金屬,或可係諸如金屬-金屬合金或金屬-半導體合金(例如,諸如矽化物材料)之合金。
在實施例中,(雖然並未被顯示),提供之結構300包含接點圖案之形成,其係與現有閘極圖案本質上較佳地對齊,而排除具有過度嚴格登記預算之微影術步驟的使用。在一該實施例中,此途徑致能本徵高度選擇性之濕蝕刻的使用(例如,對習知佈植之乾或電漿蝕刻),以產生接點開口。在實施例中,接點圖案係藉由使用與接點柱塞微影術操作結合之現有閘極圖案,而予以形成。在一該實施例中,該途徑致能排除用於除此之外的決定性之微影術的需要,以產生接點圖案,如在習知途徑中所使用地。在實施例中,溝渠接點格柵並未被個別地圖案化,而係形成於多叉(閘極)線之間。例如,在一該實施例中,溝渠格柵係在閘極格柵圖案化之後,且在閘極格柵切割之前形成。
再者,閘極堆疊結構308可藉由置換閘極處理而予以製造。在該方案中,虛擬閘極諸如多晶矽或氮化矽柱材料可予以去除,且以永久閘極電極材料予以置換。在一該實施例中,永久閘極電介質層亦係在此處理之中形成,而不是透過較早處理所帶有的。在實施例中,虛擬閘極係藉由
乾蝕刻或濕蝕刻處理而予以去除。在一實施例中,虛擬閘極係由多晶矽或非晶矽所構成,且係以包含SF6
之使用的乾蝕刻予以去除。在另一實施例中,虛擬閘極係由多晶矽或非晶矽所構成,且係以包含水NH4
OH或四甲基氫氧化銨之使用的濕蝕刻予以去除。在一實施例中,虛擬閘極係由氮化矽所構成,且係以包含水磷酸之濕蝕刻予以去除。
在實施例中,於此處所敘述之一或多個途徑本質地打算結合虛擬及置換閘極處理與虛擬及置換接點處理,以得到結構300。在一該實施例中,置換接點處理係在置換閘極處理之後執行,以允許永久閘極堆疊之至少一部分的高溫退火。例如,在特定之該實施例中,永久閘極堆疊之至少一部分的退火,例如,在形成閘極電介質層之後,係執行於大於約600攝氏度的溫度處。該退火係在永久接點的形成之前執行。
請再參閱第3A圖,半導體結構或裝置300的配置安置閘極接點於隔離區之上。該配置可被視為佈局空間之無效率使用。然而,在另一實施例中,半導體裝置具有閘極電極的接點部分形成於主動區之上的接點結構。通常,在形成閘極接點結構(諸如通孔)於閘極的主動區之上以及在與溝渠接點通孔相同的層中之前(例如,除此之外),本發明之一或多個實施例包含先使用閘極對齊之溝渠接點處理。該處理可予以實施以形成用於半導體結構製造,例如,用於積體電路製造的溝渠接點結構。在實施例中,溝渠接點圖案係形成為與現有閘極圖案對齊。對照之下,習
知之途徑典型地包含額外的微影術處理,其具有對與選擇性之接點蝕刻結合的現有閘極圖案之微影接點圖案的嚴格登記。例如,習知處理可包含具有接點特徵的個別圖案化之多叉(閘極)格柵的圖案化。
如上述,一或多個實施例局限,或本質地局限來自摻雜處理的摻雜物至半導體裝置的子鰭區域。例如,第4A圖係依據本發明實施例之模擬的2D輪廓圖表400,用以說明對子鰭區域的硼摻雜物局限。在另一實例中,第4B圖係依據本發明實施例之模擬的2D輪廓圖表402,用以說明對子鰭區域的磷摻雜物局限。請參閱第4A及4B圖,摻雜濃度的躍遷自子鰭區域快速地掉落至凸出鰭區域。在一該實施例中,該躍遷係本質立即以小於約5×1017
原子/cm3
之摻雜物濃度以供凸出部分的各者之用,以及以大於約2×1018
原子/cm3
之摻雜物濃度以供對應的子鰭區域之用。
此外,亦係如上文所敘述地,在子鰭區域下方的基板部分可以以形成阱區之一觀念而予以摻雜。為了要例示自固態摻雜源向下擴散至下方基板內的概念。第5圖係依據本發明實施例之測量的1D SIMS摻雜物縱剖面500,用以說明自摻雜絕緣體層至矽基板內之摻雜物的擴散。
將被瞭解的是,並非在上文所敘述之該等處理的所有觀點需予以實施以落在本發明之實施例的範疇及精神之內。例如,在一實施例中,於製造閘極接點於閘極堆疊的主動部分上之前,甚至無需形成虛擬閘極。閘極堆疊可如
初始所形成地,實際地成為永久閘極堆疊。而且,在此所敘述之該等處理可被使用以製造一或複數個半導體裝置。該等半導體裝置可係電晶體或類似之裝置。例如,在實施例中,該等半導體裝置係用於邏輯或記憶體之金氧半(MOS)電晶體,或雙極性電晶體。而且,在實施例中,該等半導體裝置具有諸如三閘極裝置、獨立存取雙閘極裝置、或FIN-FET之三維架構。一或多個實施例可特別地有用於以10奈米(10nm)或更小技術節點而製造半導體裝置。
第6圖描繪依據本發明之一實施例的計算裝置600。計算裝置600收容板602。該板602可包含若干組件,包含,但未受限於處理器604及至少一通訊晶片606。處理器604係實體地及電性地耦接至板602。在若干實施例中,該至少一通訊晶片606亦係實體地及電性地耦接至板602。在進一步的實施例中,通訊晶片606係處理器604的一部分。
根據其應用,計算裝置600可包含可實體地及電性地或可不實體地及不電性地耦接至板602的其他組件。該等其他組件包含,但並未受限於揮發性記憶體(例如,DRAM)、非揮發性記憶體(例如,ROM)、快閃記憶體、繪圖處理器、數位信號處理器、加密處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、聲頻編碼解碼器、視頻編碼解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速度計、迴轉儀、揚
聲器、相機、及主儲存裝置(諸如硬碟驅動器、小型碟片(CD)、數位多功能碟片(DVD)、等等)。
通訊晶片606致能無線電通訊,用於資料至計算裝置600的轉移及來自計算裝置600之資料的轉移。“無線電”之用語及其衍生語可被使用以描繪可透過非固體媒體之調變電磁輻射的使用而通訊資料的電路、裝置、系統、方法、技術、通訊頻道、等等。該用語並未暗指相關聯的裝置不包含任何佈線,雖然在某些實施例中,它們可不包含。通訊晶片606可實施若干無線電標準或協定的任何者,包含,但未受限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生物,以及被指明為3G、4G、5G、及以上之任何其他的無線電協定。計算裝置600可包含複數個通訊晶片606。例如,第一通訊晶片606可專用於諸如Wi-Fi及藍芽之較短距離無線電通訊,以及第二通訊晶片606可專用於諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、等等之較長距離無線電通訊。
計算裝置600的處理器604包含被封裝於處理器604內之積體電路晶粒。在本發明實施例之若干實施中,該處理器的積體電路晶粒包含諸如依據本發明實施例所建立之MOS-FET電晶體的一或多個裝置。“處理器”之用語可意指可處理來自暫存器及/或記憶體之電子資料,以轉換該
電子資料成為可被儲存於暫存器及/或記憶體中之其他電子資料的任何裝置或裝置的一部分。
通訊晶片606亦包含被封裝於通訊晶片606內之積體電路晶粒。依據本發明之另一實施例,該通訊晶片的積體電路晶粒包含諸如依據本發明實施例所建立之MOS-FET電晶體的一或多個裝置。
在進一步的實施例中,收容於計算裝置600之內的另外組件可包含積體電路晶粒,其包含諸如依據本發明實施例之實施所建立之MOS-FET電晶體的一或多個裝置。
在種種實施例中,計算裝置600可係膝上型個人電腦、小筆電、筆記型個人電腦、超筆電、智慧型手機、平板電腦、個人數位助理(PDA)、超級行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜帶式音樂播放器、或數位錄影機。在進一步的實施例中,計算裝置600可係可處理資料之任何其他電子裝置。
因此,本發明之實施例包含具有摻雜子鰭區域的非平面半導體裝置及具有摻雜子鰭區域的非平面半導體裝置之製造方法。
在實施例中,半導體結構之製造方法包含在半導體基板上方形成複數個半導體鰭。固態摻雜物源層係形成於該半導體基板上方,而與該複數個半導體鰭共形。電介質層係形成於該固態摻雜物源層上方。該電介質層及該固態摻雜物源層係凹進到該複數個半導體鰭之頂部表面下方大約
相同的位準,而暴露出該複數個半導體鰭的各者之子鰭區域上方之該複數個半導體鰭的各者之凸出部分。該方法亦包含自該固態摻雜物源層驅動摻雜物至該複數個半導體鰭的各者之該等子鰭區域內。
在一實施例中,形成該固態摻雜物源層包含形成硼矽酸鹽玻璃(BSG)層。
在一實施例中,形成該固態摻雜物源層包含形成磷矽酸鹽玻璃(PSG)層或砷矽酸鹽玻璃(AsSG)層。
在一實施例中,該方法進一步包含形成與該複數個半導體鰭的各者之該等凸出部分共形的閘極電極,以及在該閘極電極的兩側上形成源極區及汲極區於該複數個半導體鰭的各者之該等凸出部分中。
在一實施例中,自該固態摻雜物源層驅動摻雜物至該複數個半導體鰭的各者之該等子鰭區域內包含形成摻雜物濃度介面於該複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間。
在一實施例中,在該半導體基板上方形成該複數個半導體鰭包含形成延續巨塊單晶基板的複數個單晶矽鰭。
在實施例中,半導體結構之製造方法包含在半導體基板上方形成第一及第二複數個半導體鰭。P型固態摻雜物源層係在該半導體基板上方形成於該第一複數個半導體鰭上,且與該第一複數個半導體鰭共形。電介質層係形成於該P型固態摻雜物源層上方。該電介質層及該P型固態摻雜物源層係平坦化,以暴露出該第一及第二複數個半導體
鰭的各者之頂部表面。N型摻雜物係佈植至該第二複數個鰭之內,但不進入至該第一複數個鰭之內。該電介質層及該P型固態摻雜物源層係凹進到該第一及第二複數個半導體鰭的各者之該頂部表面下方大約相同的位準,而暴露出該第一及第二複數個半導體鰭的各者之子鰭區域上方之該第一及第二複數個半導體鰭的各者之凸出部分。該方法亦包含自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內,但不到該第二複數個半導體鰭的各者之該等子鰭區域內。
在一實施例中,形成該P型固態摻雜物源層包含形成全面P型固態摻雜物源層於該第一及第二複數個半導體鰭上,且與該第一及第二複數個半導體鰭共形,以及自該第二複數個半導體鰭,但非自該第一複數個半導體鰭,去除該全面P型固態摻雜物源層。
在一實施例中,該方法進一步包含,在自該第二複數個半導體鰭,但非自該第一複數個半導體鰭去除該全面P型固態摻雜物源層之後,形成緩衝電介質層於該P型固態摻雜物源層上並與該P型固態摻雜物源層共形,且於該第二複數個半導體鰭上並與該第二複數個半導體鰭共形。
在一實施例中,形成該P型固態摻雜物源層包含形成硼矽酸鹽玻璃(BSG)層。
在一實施例中,該方法進一步包含形成與該第一複數個半導體鰭的各者之該等凸出部分共形的N型閘極電極,形成與該第二複數個半導體鰭的各者之該等凸出部分共形
的P型閘極電極,以及在對應的該閘極電極的兩側上形成源極區及汲極區於該第一及第二複數個半導體鰭的各者之該等凸出部分中。
在一實施例中,自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內包含形成摻雜物濃度介面於該第一複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間。
在一實施例中,於該半導體基板上方形成該第一及第二複數個半導體鰭包含形成延續巨塊單晶基板的第一及第二複數個單晶矽鰭。
在實施例中,半導體結構之製造方法包含在半導體基板上方形成第一及第二複數個半導體鰭。P型固態摻雜物源層係在該半導體基板上方形成於該第一複數個半導體鰭上,且與該第一複數個半導體層共形。N型固態摻雜物源層係在該半導體基板上方形成於該第二複數個半導體鰭上,且與該第二複數個半導體鰭共形。電介質層係形成於該P型固態摻雜物源層上方,且於該N型固態摻雜物源層上方,該電介質層、該P型固態摻雜物源層、及該N型固態摻雜物源層係凹進到該第一及第二複數個半導體鰭的各者之頂部表面下方大約相同的位準,而暴露出該第一及第二複數個半導體鰭的各者之子鰭區域上方之該第一及第二複數個半導體鰭的各者之凸出部分。該方法亦包含自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內,但不到該第二複數個半導體
鰭的各者之該等子鰭區域內,以及自該N型固態摻雜物源層驅動摻雜物至該第二複數個半導體鰭的各者之該等子鰭區域內,但不到該第一複數個半導體鰭的各者之該等子鰭區域內。
在一實施例中,自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內,及自該N型固態摻雜物源層驅動摻雜物至該第二複數個半導體鰭的各者之該等子鰭區域內,係在相同的處理操作中執行。
在一實施例中,形成該P型固態摻雜物源層包含形成全面P型固態摻雜物源層於該第一及第二複數個半導體鰭上,且與該第一及第二複數個半導體鰭共形,以及自該第二複數個半導體鰭,但非自該第一複數個半導體鰭,去除該全面P型固態摻雜物源層。
在一實施例中,該方法進一步包含,在自該第二複數個半導體鰭去除該全面P型固態摻雜物源層之後,形成緩衝電介質層於該P型固態摻雜物源層上並與該P型固態摻雜物源層共形。
在一實施例中,形成該N型固態摻雜物源層包含形成全面N型固態摻雜物源層於該第二複數個半導體鰭上並與該第二複數個半導體鰭共形,且在該P型固態摻雜物源層上方,以及自該P型固態摻雜物源層上方,但非自該第二複數個半導體鰭,去除該全面N型固態摻雜物源層。
在一實施例中,該方法進一步包含,在自該P型固態
摻雜物源層上方去除該全面N型固態摻雜物源層之後,形成緩衝電介質層於該N型固態摻雜物源層上並與該N型固態摻雜物源層共形,且於該P型固態摻雜物源層上並與該P型固態摻雜物源層共形。
在一實施例中,形成該P型固態摻雜物源層包含形成硼矽酸鹽玻璃(BSG)層,以及形成該N型固態摻雜物源層包含形成磷矽酸鹽玻璃(PSG)層或砷矽酸鹽玻璃(AsSG)層。
在一實施例中,該方法進一步包含形成與該第一複數個半導體鰭的各者之該等凸出部分共形的N型閘極電極,形成與該第二複數個半導體鰭的各者之該等凸出部分共形的P型閘極電極,以及在對應的該閘極電極的兩側上形成源極區及汲極區於該第一及第二複數個半導體鰭的各者之該等凸出部分中。
在一實施例中,自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內包含形成摻雜物濃度介面於該第一複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間,以及自該N型固態摻雜物源層驅動摻雜物至該第二複數個半導體鰭的各者之該等子鰭區域內包含形成摻雜物濃度介面於該第二複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間。
在一實施例中,於該半導體基板上方形成該第一及第二複數個半導體鰭包含形成延續巨塊單晶基板的第一及第
二複數個單晶矽鰭。
在實施例中,半導體結構包含複數個半導體鰭,設置在半導體基板上方。固態摻雜物源層係設置在該半導體基板上方,而與該複數個半導體鰭的各者之子鰭區域共形,但僅到該複數個半導體鰭之頂部下方的位準,以暴露出該複數個半導體鰭的各者之該等子鰭區域上方之該複數個半導體鰭的各者之凸出部分。電介質層係設置在該固態摻雜物源層上方,該電介質層具有與在該複數個半導體鰭之該頂部表面下方的該位準大約共平面的頂部表面。摻雜物濃度介面係在該複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間。
在一實施例中,該固態摻雜物源層係硼矽酸鹽玻璃(BSG)層。
在一實施例中,該固態摻雜物源層係磷矽酸鹽玻璃(PSG)層或砷矽酸鹽玻璃(AsSG)層。
在一實施例中,該半導體結構進一步包含閘極電極,設置與該複數個半導體鰭的各者之該等凸出部分共形,以及源極區及汲極區,設置在該閘極電極的兩側上之該複數個半導體鰭的各者之該等凸出部分中。
在一實施例中,設置在該半導體基板上方之該複數個半導體鰭係延續巨塊單晶基板的複數個單晶矽鰭。
在一實施例中,該摻雜物濃度介面係用於該複數個半導體鰭的各者之該等凸出部分的各者之小於約5×1017
原子/立方公分,及用於對應的該等子鰭區域之大於約2×1018
原
子/立方公分的陡峭躍遷。
100‧‧‧巨塊半導體基板
102‧‧‧鰭
104‧‧‧硬遮罩層
106‧‧‧墊氧化物層
108‧‧‧P型固態摻雜物源層
108'‧‧‧圖案化之P型固態摻雜物源層
110‧‧‧地表遮罩部分
112‧‧‧抗反射塗佈層
114‧‧‧絕緣緩衝層或阻隔層
116,216‧‧‧電介質填充層
118‧‧‧遮罩層
120‧‧‧阱及/或逆行佈植操作
122‧‧‧N型摻雜鰭
122',124'‧‧‧共同摻雜區
124‧‧‧P型摻雜子鰭區域
126‧‧‧介面
Claims (29)
- 一種半導體結構之製造方法,該方法包含:在半導體基板上方形成複數個半導體鰭;在該半導體基板上方形成與該複數個半導體鰭共形的固態摻雜物源層;在該固態摻雜物源層上方形成電介質層;使該電介質層及該固態摻雜物源層凹進到該複數個半導體鰭之頂部表面下方大約相同的位準,而暴露出該複數個半導體鰭的各者之子鰭區域上方之該複數個半導體鰭的各者之凸出部分;以及自該固態摻雜物源層驅動摻雜物至該複數個半導體鰭的各者之該等子鰭區域內。
- 如申請專利範圍第1項之方法,其中形成該固態摻雜物源層包含形成硼矽酸鹽玻璃(BSG)層。
- 如申請專利範圍第1項之方法,其中形成該固態摻雜物源層包含形成磷矽酸鹽玻璃(PSG)層或砷酸鹽玻璃(AsSG)層。
- 如申請專利範圍第1項之方法,進一步包含:形成與該複數個半導體鰭的各者之該等凸出部分共形的閘極電極;以及在該閘極電極的兩側上形成源極區及汲極區於該複數個半導體鰭的各者之該等凸出部分中。
- 如申請專利範圍第1項之方法,其中自該固態摻雜物源層驅動摻雜物至該複數個半導體鰭的各者之該等子鰭 區域內包含形成摻雜物濃度介面於該複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間。
- 如申請專利範圍第1項之方法,其中在該半導體基板上方形成該複數個半導體鰭包含形成延續巨塊單晶基板的複數個單晶矽鰭。
- 一種半導體結構之製造方法,該方法包含:在半導體基板上方形成第一及第二複數個半導體鰭;在該半導體基板上方形成P型固態摻雜物源層於該第一複數個半導體鰭上,且與該第一複數個半導體鰭共形;在該P型固態摻雜物源層上方形成電介質層;使該電介質層及該P型固態摻雜物源層平坦化,以暴露出該第一及第二複數個半導體鰭的各者之頂部表面;佈植N型摻雜物至該第二複數個鰭之內,但不進入至該第一複數個鰭之內;使該電介質層及該P型固態摻雜物源層凹進到該第一及第二複數個半導體鰭的各者之該頂部表面下方大約相同的位準,而暴露出該第一及第二複數個半導體鰭的各者之子鰭區域上方之該第一及第二複數個半導體鰭的各者之凸出部分;以及自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內,但不到該第二複數個半導體鰭的各者之該等子鰭區域內。
- 如申請專利範圍第7項之方法,其中形成該P型固態摻雜物源層包含: 形成全面P型固態摻雜物源層於該第一及第二複數個半導體鰭上,且與該第一及第二複數個半導體鰭共形;以及自該第二複數個半導體鰭,但非自該第一複數個半導體鰭,去除該全面P型固態摻雜物源層。
- 如申請專利範圍第8項之方法,進一步包含:在自該第二複數個半導體鰭,但非自該第一複數個半導體鰭去除該全面P型固態摻雜物源層之後,形成緩衝電介質層於該P型固態摻雜物源層上並與該P型固態摻雜物源層共形,且形成於該第二複數個半導體鰭上並與該第二複數個半導體鰭共形。
- 如申請專利範圍第7項之方法,其中形成該P型固態摻雜物源層包含形成硼矽酸鹽玻璃(BSG)層。
- 如申請專利範圍第7項之方法,進一步包含:形成與該第一複數個半導體鰭的各者之該等凸出部分共形的N型閘極電極;形成與該第二複數個半導體鰭的各者之該等凸出部分共形的P型閘極電極;以及在對應的該閘極電極的兩側上形成源極區及汲極區於該第一及第二複數個半導體鰭的各者之該等凸出部分中。
- 如申請專利範圍第7項之方法,其中自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內包含形成摻雜物濃度介面於該第一複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區 域間。
- 如申請專利範圍第7項之方法,其中在該半導體基板上方形成該第一及第二複數個半導體鰭包含形成延續巨塊單晶基板的第一及第二複數個單晶矽鰭。
- 一種半導體結構之製造方法,該方法包含:在半導體基板上方形成第一及第二複數個半導體鰭;在該半導體基板上方形成P型固態摻雜物源層於該第一複數個半導體鰭上,且與該第一複數個半導體鰭共形;在該半導體基板上方形成N型固態摻雜物源層於該第二複數個半導體鰭上,且與第二複數個半導體鰭共形;在該P型固態摻雜物源層上方且在該N型固態摻雜物源層上方形成電介質層;使該電介質層、該P型固態摻雜物源層、及該N型固態摻雜物源層凹進到該第一及二複數個半導體鰭的各者之頂部表面下方大約相同的位準,而暴露出該第一及第二複數個半導體鰭的各者之子鰭區域上方之該第一及第二複數個半導體鰭的各者之凸出部分;自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內,但不到該第二複數個半導體鰭的各者之該等子鰭區域內;以及自該N型固態摻雜物源層驅動摻雜物至該第二複數個半導體鰭的各者之該等子鰭區域內,但不到該第一複數個半導體鰭的各者之該等子鰭區域內。
- 如申請專利範圍第14項之方法,其中該自該P型 固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內,及該自該N型固態摻雜物源層驅動摻雜物至該第二複數個半導體鰭的各者之該等子鰭區域內,係在相同的處理操作中執行。
- 如申請專利範圍第14項之方法,其中形成該P型固態摻雜物源層包含:形成全面P型固態摻雜物源層於該第一及第二複數個半導體鰭上,且與該第一及第二複數個半導體鰭共形;以及自該第二複數個半導體鰭,但非自該第一複數個半導體鰭,去除該全面P型固態摻雜物源層。
- 如申請專利範圍第16項之方法,進一步包含:在自該第二複數個半導體鰭去除該全面P型固態摻雜物源層之後,形成緩衝電介質層於該P型固態摻雜物源層上並與該P型固態摻雜物源層共形。
- 如申請專利範圍第14項之方法,其中形成該N型固態摻雜物源層包含:形成全面N型固態摻雜物源層於該第二複數個半導體鰭上並與該第二複數個半導體鰭共形,且形成在該P型固態摻雜物源層上方;以及自該P型固態摻雜物源層上方,但非自該第二複數個半導體鰭,去除該全面N型固態摻雜物源層。
- 如申請專利範圍第18項之方法,進一步包含:在自該P型固態摻雜物源層上方去除該全面N型固 態摻雜物源層之後,形成緩衝電介質層於該N型固態摻雜物源層上並與該N型固態摻雜物源層共形,且形成於該P型固態摻雜物源層上並與該P型固態摻雜物源層共形。
- 如申請專利範圍第14項之方法,其中形成該P型固態摻雜物源層包含形成硼矽酸鹽玻璃(BSG)層,以及其中形成該N型固態摻雜物源層包含形成磷矽酸鹽玻璃(PSG)層或砷酸鹽玻璃(AsSG)層。
- 如申請專利範圍第14項之方法,進一步包含:形成與該第一複數個半導體鰭的各者之該等凸出部分共形的N型閘極電極;形成與該第二複數個半導體鰭的各者之該等凸出部分共形的P型閘極電極;以及在對應的該閘極電極的兩側上形成源極區及汲極區於該第一及第二複數個半導體鰭的各者之該等凸出部分中。
- 如申請專利範圍第14項之方法,其中自該P型固態摻雜物源層驅動摻雜物至該第一複數個半導體鰭的各者之該等子鰭區域內包含形成摻雜物濃度介面於該第一複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間,以及其中自該N型固態摻雜物源層驅動摻雜物至該第二複數個半導體鰭的各者之該等子鰭區域內包含形成摻雜物濃度介面於該第二複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間。
- 如申請專利範圍第14項之方法,其中在該半導體基板上方形成該第一及第二複數個半導體鰭包含形成延續 巨塊單晶基板的第一及第二複數個單晶矽鰭。
- 一種半導體結構,包含:複數個半導體鰭,設置在半導體基板上方;固態摻雜物源層,設置在該半導體基板上方,與該複數個半導體鰭的各者之子鰭區域共形,但僅到該複數個半導體鰭頂部表面下方的位準,而暴露出該複數個半導體鰭的各者之該等子鰭區域上方之該複數個半導體鰭的各者之凸出部分;電介質層,設置在該固態摻雜物源層上方,該電介質層具有與在該複數個半導體鰭之該頂部表面下方該位準大約共平面的頂部表面;以及摻雜物濃度介面,在該複數個半導體鰭的各者之該等凸出部分的各者與對應的子鰭區域間。
- 如申請專利範圍第24項之半導體結構,其中該固態摻雜物源層係硼矽酸鹽玻璃(BSG)層。
- 如申請專利範圍第24項之半導體結構,其中該固態摻雜物源層係磷矽酸鹽玻璃(PSG)層或砷酸鹽玻璃(AsSG)層。
- 如申請專利範圍第24項之半導體結構,進一步包含:閘極電極,設置與該複數個半導體鰭的各者之該等凸出部分共形的;以及源極區及汲極區,設置在該閘極電極的兩側上之該複數個半導體鰭的各者之該等凸出部分中。
- 如申請專利範圍第24項之半導體結構,其中設置在該半導體基板上方之該複數個半導體鰭係延續巨塊單晶基板的複數個單晶矽鰭。
- 如申請專利範圍第24項之半導體結構,其中該摻雜物濃度介面係用於該複數個半導體鰭的各者之該等凸出部分的各者之小於約5×1017 原子/立方公分的陡峭躍遷,及用於該複數個半導體的各者對應的該等子鰭區域之大於約2×1018 原子/立方公分的陡峭躍遷。
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