CN107026126B - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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CN107026126B
CN107026126B CN201610072825.3A CN201610072825A CN107026126B CN 107026126 B CN107026126 B CN 107026126B CN 201610072825 A CN201610072825 A CN 201610072825A CN 107026126 B CN107026126 B CN 107026126B
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fin structure
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doped layer
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CN107026126A (zh
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童宇诚
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United Microelectronics Corp
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Abstract

本发明公开一种半导体元件及其制作方法。首先提供一基底，该基底具有一第一区域以及一第二区域，然后形成一第一鳍状结构于第一区域以及一第二鳍状结构于第二区域，形成一第一凸块于第一区域以及一第二凸块于第二区域，形成一第一掺杂层于第一鳍状结构及第一凸块上，之后再形成一第二掺杂层于第二鳍状结构及第二凸块上。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种半导体元件及其制作方法，尤其是涉及一种利用固态掺质(solidstate doping,SSD)技术于鳍状结构下半部形成掺杂层的半导体元件及其制作方法。
背景技术
近年来，随着场效晶体管(field effect transistors,FETs)元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin fieldeffect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子通道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(draininduced barrier lowering,DIBL)效应，并可以抑制短通道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的通道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而，在现行的鳍状场效晶体管元件制作工艺中，鳍状结构的设计仍存在许多瓶颈，进而影响整个元件的漏电流及整体电性表现。因此如何改良现有鳍状场效晶体管制作工艺即为现今一重要课题。
发明内容
本发明较佳实施例公开一种制作半导体元件的方法。首先提供一基底，该基底具有一第一区域以及一第二区域，然后形成一第一鳍状结构于第一区域以及一第二鳍状结构于第二区域，形成一第一凸块于第一区域以及一第二凸块于第二区域，形成一第一掺杂层于第一鳍状结构及第一凸块上，之后再形成一第二掺杂层于第二鳍状结构及第二凸块上。
本发明另一实施例公开一种半导体元件，包含：一基底，该基底具有一第一区域以及一第二区域；一第一鳍状结构设于第一区域上以及一第二鳍状结构设于第二区域上；一凸块设于第一区域及第二区域之间；一第一掺杂层设于第一鳍状结构及凸块上；以及一第二掺杂层设于第二鳍状结构及凸块上，其中第二掺杂层接触该第一掺杂层。
本发明又一实施例公开一种半导体元件，包含：一基底，该基底具有一第一区域以及一第二区域；一第一鳍状结构设于第一区域上以及一第二鳍状结构设于第二区域上；一第一凸块设于第一区域上；一第二凸块设于第二区域上；一第一掺杂层设于第一鳍状结构及第一凸块上；以及一第二掺杂层设于第二鳍状结构及第二凸块上。
附图说明
图1至图9为本发明较佳实施例制作一CMOS半导体元件的方法示意图；
图10为本发明另一实施例的半导体元件的结构示意图；
图11为本发明另一实施例的半导体元件的结构示意图。
主要元件符号说明
12 基底 14 NMOS区域
16 PMOS区域 18 鳍状结构
20 凸块 22 凸块
24 硬掩模 26 掺杂层
28 衬垫层 30 图案化光致抗蚀剂
32 掺杂层 34 图案化光致抗蚀剂
36 衬垫层 38 绝缘层
40 浅沟隔离 42 上半部
44 下半部 46 栅极介电层
48 栅极结构 50 凸块
52 多晶硅材料 54 间隙壁
56 层间介电层 58 高介电常数介电层
60 功函数金属层 62 低阻抗金属层
64 硬掩模
具体实施方式
请继续参照图1至图9，图1至图9为本发明较佳实施例制作一CMOS半导体元件的方法示意图。如图1所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有一第一区域与一第二区域，例如本实施例的第一区域较佳为一NMOS区域14而第二区域较佳为一PMOS区域16，但不局限于此。然后分别形成至少一鳍状结构18以及一凸块20于NMOS区域14以及至少一鳍状结构18与另一凸块22于PMOS区域16，其中各鳍状结构18上可设有一由氮化硅或氧化硅所构成的硬掩模24。
鳍状结构18的形成方式可以包含先形成一图案化掩模(图未示)，例如前述的掩模层于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成各鳍状结构18。除此之外，鳍状结构18的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于图案化硬掩模层所暴露出的基底12上成长出半导体层，此半导体层即可作为相对应的鳍状结构18。另外，当基底12为硅覆绝缘(SOI)基板时，则可利用图案化掩模来蚀刻基底12的一底氧化层上的一半导体层，并且不蚀穿此半导体层以形成各鳍状结构18。
凸块20、22的形成方式可比照前述形成鳍状结构18的方式先于基底12上形成多个鳍状结构，然后再利用光刻暨蚀刻制作工艺方式降低其中一根鳍状结构18的高度，以于NMOS区域14形成凸块20以及于PMOS区域16形成凸块22。由于凸块20、22是与鳍状结构18一同形成，因此两者较佳由相同材料所构成。
接着依序形成一掺杂层26以及一衬垫层28并覆盖NMOS区域14与PMOS区域16的鳍状结构18与凸块20、22，其中衬垫层28较佳由氮化硅所构成，掺杂层26较佳包含具有P型掺质的材料层，例如硼硅酸盐(borosilicate glass,BSG)。
如图2所示，然后去除PMOS区域16的衬垫层28与掺杂层26。举例来说，可先形成一图案化光罩，例如一图案化光致抗蚀剂30于NMOS区域14的衬垫层28上，接着进行一蚀刻制作工艺去除PMOS区域16的衬垫层28与掺杂层26，并由此暴露出PMOS区域16的鳍状结构18与凸块22。接着去除图案化光致抗蚀剂30。
随后如图3所示，全面性形成另一掺杂层32并覆盖于PMOS区域16的鳍状结构18与凸块22以及NMOS区域16的衬垫层28上。其中掺杂层32较佳与之前的掺杂层26为相反导电型式，例如此步骤的掺杂层32较佳包含具有N型掺质的材料层，例如磷硅酸盐(phosphosilicate glass,PSG)。
如图4所示，接着形成另一图案化光罩，例如一图案化光致抗蚀剂34于PMOS区域16的掺杂层32上，然后进行一蚀刻制作工艺去除NMOS区域14上的掺杂层32并暴露出下面的衬垫层28。需注意的是，由于部分掺杂层32是设于NMOS区域14与PMOS区域16的交界处，因此本实施例利用前述蚀刻制作工艺去除NMOS区域14上的掺杂层32时较佳暴露出NMOS区域14与PMOS区域16交界处的部分基底12表面。但不局限于此，本发明另一实施例又可调整图案化光致抗蚀剂34所设置的位置，例如可使图案化光致抗蚀剂34切齐掺杂层32与衬垫层28的交界处，以于去除NMOS区域14上的掺杂层32后不暴露出任何基底12表面，此实施例也属本发明所涵盖的范围。随后去除图案化光致抗蚀剂34。
之后如图5所示，形成另一衬垫层36覆盖PMOS区域16的掺杂层32以及NMOS区域14的衬垫层28，并同时填满掺杂层32与衬垫层28之间的空间。在本实施例中，衬垫层36的材料可选择与衬垫层28相同或不同，例如本实施例的衬垫层36较佳由氮化硅所构成，但不局限于此。
然后如图6所示，沉积一绝缘层38于NMOS区域14与PMOS区域16的衬垫层36上并高于各鳍状结构18顶部，其中绝缘层38较佳由氧化硅所构成，但不局限于此。
如图7所示，接着进行一平坦化制作工艺，例如利用化学机械研磨(chemicalmechanical polishing,CMP)制作工艺去除部分绝缘层38、硬掩模24甚至部分鳍状结构18，使剩余的绝缘层38上表面与鳍状结构18上表面齐平。然后进行一蚀刻制作工艺去除部分绝缘层38、NMOS区域14的部分衬垫层36、部分衬垫层28与部分掺杂层26以及PMOS区域16的部分衬垫层36与部分掺杂32层以形成浅沟隔离40，其中浅沟隔离40上表面略低于鳍状结构18上表面并同时将NMOS区域14与PMOS区域16的各鳍状结构18分隔为上半部42与下半部44。其中浅沟隔离40上表面较佳与各鳍状结构18的上半部42下表面齐平。更具体而言，此时浅沟隔离40较佳切齐剩余的衬垫层36、剩余的掺杂层32、剩余的衬垫层28以及剩余的掺杂层26上表面且浅沟隔离40同时环绕NMOS区域14与PMOS区域16的鳍状结构18下半部44。
然后可选择性进行一退火制作工艺，将掺杂层36、26中的掺质趋入各鳍状结构18下半部44以及凸块20、22中以形成掺杂区，例如一抗接面击穿(anti-punch-through,APT)层用来避免漏电。
随后如图8所示，可依据制作工艺需求进行后续晶体管制作工艺以形成栅极结构，例如可先形成一介质层(图未示)和/或栅极介电层46于NMOS区域14与PMOS区域16，然后分别形成一栅极结构48于NMOS区域14与PMOS区域16的鳍状结构18上。其中栅极结构48较佳由多晶硅材料所构成，NMOS区域14的栅极结构48较佳覆盖NMOS区域14的鳍状结构18与凸块20，PMOS区域16的栅极结构48也较佳覆盖PMOS区域16的鳍状结构18与凸块22。
在本实施例中，栅极结构48的制作方式可依据制作工艺需求以先栅极(gatefirst)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺以及后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，如图9所示，可先于鳍状结构18上形成前述包含栅极介电层46与多晶硅材料52所构成的栅极结构48，然后于栅极结构48侧壁形成间隙壁54。在本实施例中，间隙壁54可为一单一间隙壁或复合式间隙壁，其可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。
随后可形成源极/漏极区域于栅极结构48两侧的鳍状结构18，依据制作工艺需求形成外延层、硅化金属层、接触洞蚀刻停止层以及层间介电层56等元件，再进行一金属栅极置换(replacement metal gate,RMG)制作工艺将多晶硅所构成的栅极结构48转换为金属栅极。
如图9所示，NMOS区域14与PMOS区域16的各金属栅极或栅极结构48较佳包含一U型高介电常数介电层58、一U型功函数金属层60以及一低阻抗金属层62。
在本实施例中，高介电常数介电层58包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalum oxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层60较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层60可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层60可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层60与低阻抗金属层62之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层62则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是此领域者所熟知技术，在此不另加赘述。
之后可去除部分高介电常数介电层58、部分功函数金属层60与部分低阻抗金属层62形成凹槽(图未示)，然后再填入一硬掩模64于凹槽内并使硬掩模64与层间介电层56表面齐平，其中硬掩模64可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。至此即完成本发明较佳实施例的一半导体元件的制作。
请再参照图9，图9为本发明一实施例的半导体元件的结构示意图。如图9所示，半导体元件较佳包含至少一鳍状结构18分别设于基底12上的NMOS区域14与PMOS区域16、一凸块20设于NMOS区域14、一凸块22设于PMOS区域16、一掺杂层26设于NMOS区域14的鳍状结构18与凸块20上、一掺杂层32设于PMOS区域16的鳍状结构18与凸块22上、一衬垫层28设于NMOS区域14的掺杂层26与凸块20上以及一衬垫层36设于PMOS区域16的掺杂层32、PMOS区域16的凸块22、NMOS区域14的凸块20以及NMOS区域14的衬垫层28上。
更具体而言，NMOS区域14与PMOS区域16的各鳍状结构18包含一上半部42与一下半部44，其中NMOS区域14的掺杂层26、衬垫层28以及衬垫层36较佳环绕于鳍状结构18的下半部44侧壁上，而PMOS区域16的掺杂层32与衬垫层36较佳环绕于鳍状结构18的下半部44侧壁。
在本实施例中，凸块20、22较佳与鳍状结构18为相同材料，且各凸块20、22的高度较佳介于掺杂层26或掺杂层32厚度的2倍至20倍。另外各鳍状结构18下半部44与凸块20、22均较佳包含掺杂区(图未示)，例如抗接面击穿层用来避免漏电，其中NMOS区域14的鳍状结构18下半部44与凸块20较佳包含相同导电型式的掺杂区，而PMOS区域16的鳍状结构18下半部44与凸块22则较佳包含相同导电型式的掺杂区。
半导体元件另包含一浅沟隔离40环绕NMOS区域14与PMOS区域16的鳍状结构18下半部44，其中浅沟隔离40上表面除了切齐各鳍状结构18下半部44的上表面之外，又同时切齐NMOS区域14的掺杂层26、衬垫层28与衬垫层36上表面以及PMOS区域16的掺杂层32与衬垫层36上表面。
请继续参照图10，图10为本发明另一实施例的半导体元件的结构示意图。如图10所示，本实施例的半导体元件包含至少一鳍状结构18分别设于基底12上的NMOS区域14与PMOS区域16、一凸块50设于NMOS区域14与PMOS区域16之间、一掺杂层26设于NMOS区域14的鳍状结构18与凸块50上、一掺杂层32设于PMOS区域16的鳍状结构18与凸块50上、一衬垫层28设于NMOS区域14的掺杂层26与凸块50上以及一衬垫层36设于PMOS区域16的掺杂层32、凸块50以及NMOS区域14的衬垫层28上。
相较于图9实施例中NMOS区域14与PMOS区域16各设有一凸块20、22，本实施例仅设置单一凸块50于NMOS区域14与PMOS区域16之间的交界处，NMOS区域14的掺杂层26与衬垫层28较佳切齐于凸块50上，且PMOS区域16的掺杂层32较佳同时接触掺杂层26与衬垫层28在凸块50上。如同图9的实施例，凸块50较佳与鳍状结构18为相同材料，且凸块50的高度较佳介于掺杂层26或掺杂层32厚度的2倍至20倍。
另外需注意的是，本发明可比照前述实施例于形成图10的结构后选择性进行一退火制作工艺，将掺杂层26、32中的掺质趋入各鳍状结构18下半部44以及凸块50中以形成一掺杂区，例如一抗接面击穿(APT)层用来避免漏电。由于本实施例的单一凸块50上同时设置有两种不同导电型态的掺杂层26与掺杂层32，因此经由退火制作工艺后凸块50较佳同时包含N型掺质与P型掺质。
此外，本实施例又可比照前述实施例于形成图10结构后先形成一介质层或栅极介电层于NMOS区域14与PMOS区域16，然后分别形成一栅极结构于NMOS区域14与PMOS区域16的鳍状结构18上。由于本实施例仅有单一凸块50，因此可选择以NMOS区域14的栅极结构覆盖凸块50、以PMOS区域16的栅极结构覆盖凸块50或两个区域的栅极结构均不覆盖凸块50，这些均属本发明所涵盖的范围。
请继续参照图11，图11为本发明另一实施例的半导体元件的结构示意图。如图11所示，本实施例的半导体元件包含至少一鳍状结构18分别设于基底12上的NMOS区域14与PMOS区域16、一凸块50设于NMOS区域14与PMOS区域16之间、一掺杂层26设于NMOS区域14的鳍状结构18与凸块50上、一掺杂层32设于PMOS区域16的鳍状结构18与凸块50上、一衬垫层28设于NMOS区域14的掺杂层26与凸块50上以及一衬垫层36设于PMOS区域16的掺杂层32、凸块50以及NMOS区域14的衬垫层28上。
有别于图10的实施例中PMOS区域16的掺杂层32较佳同时接触掺杂层26与衬垫层28在凸块50上，本实施例的掺杂层32较佳完全包覆凸块50且掺杂层32较佳接触掺杂层26在NMOS区域14的基底12表面。另外不局限于本实施例是以PMOS区域16的掺杂层32完全包覆凸块50，本发明另一实施例又可选择以NMOS区域14的掺杂层26来完全包覆凸块50，且在此状况下，掺杂层26将接触掺杂层32在PMOS区域14的基底12表面。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (16)

1.一种制作半导体元件的方法，包含：
提供一基底，该基底具有一第一区域以及一第二区域；
形成一第一鳍状结构于该第一区域以及一第二鳍状结构于该第二区域；
形成一第一凸块于该第一区域以及一第二凸块于该第二区域；
形成一第一掺杂层于该第一鳍状结构及该第一凸块上；
形成一第一衬垫层于该第一掺杂层上；
形成一第二掺杂层于该第二鳍状结构及该第二凸块上；
形成一第二衬垫层于该第二掺杂层及该第一衬垫层上；
形成该第二衬垫层后，进行一退火制作工艺；以及
形成一第一栅极结构覆盖该第一鳍状结构及该第一凸块，并形成一第二栅极结构覆盖该第二鳍状结构及该第二凸块。
2.如权利要求1所述的方法，另包含：
形成该第一掺杂层以及该第一衬垫层于该第一区域及该第二区域；
去除该第二区域的该第一衬垫层及该第一掺杂层；
形成该第二掺杂层于该第一区域及该第二区域；
去除该第一区域的该第二掺杂层；
形成该第二衬垫层于该第一区域及该第二区域；以及
形成一浅沟隔离环绕该第一鳍状结构及该第二鳍状结构。
3.如权利要求2所述的方法，其中各该第一鳍状结构及该第二鳍状结构包含一上半部以及一下半部，该方法包含：
形成一绝缘层于该第二衬垫层上；以及
去除部分该绝缘层、环绕该第一鳍状结构的该上半部的该第一衬垫层及该第一掺杂层以及环绕该第二鳍状结构的该上半部的该第二衬垫层及该第二掺杂层以形成该浅沟隔离环绕该第一鳍状结构的该下半部及该第二鳍状结构的该下半部。
4.如权利要求1所述的方法，另包含：
形成该第一掺杂层以及该第一衬垫层于该第一鳍状结构、该第一凸块、该第二凸块以及该第二鳍状结构；
去除该第二凸块及该第二鳍状结构上的该第一衬垫层及该第一掺杂层；
形成该第二掺杂层于该第二鳍状结构、该第二凸块以及该第一衬垫层上；
去除该第一衬垫层上的该第二掺杂层；
形成该第二衬垫层于该第二掺杂层及该第一衬垫层上；以及
形成一浅沟隔离环绕该第一鳍状结构及该第二鳍状结构。
5.如权利要求4所述的方法，其中各该第一鳍状结构及该第二鳍状结构包含一上半部以及一下半部，该方法包含：
形成一绝缘层于该第二衬垫层上；以及
去除部分该绝缘层、环绕该第一鳍状结构的该上半部的该第一衬垫层及该第一掺杂层以及环绕该第二鳍状结构的该上半部的该第二衬垫层及该第二掺杂层以形成该浅沟隔离环绕该第一鳍状结构的该下半部及该第二鳍状结构的该下半部。
6.一种半导体元件，包含：
基底，该基底具有一第一区域以及一第二区域；
第一鳍状结构，设于该第一区域上以及一第二鳍状结构设于该第二区域上；
凸块，设于该第一区域及该第二区域之间；
第一掺杂层和第一衬垫层，设于该第一鳍状结构及该凸块上；
第二掺杂层，设于该第二鳍状结构及该凸块上，其中该第二掺杂层接触该第一掺杂层；
第二衬垫层，设置于该第二掺杂层、该凸块以及该第一衬垫层上，其中该第一衬垫层位于该第二衬垫层与该第一掺杂层之间；以及
栅极结构，覆盖该凸块。
7.如权利要求6所述的半导体元件，其中各该第一鳍状结构及该第二鳍状结构包含一上半部以及一下半部，该第一掺杂层环绕该第一鳍状结构的该下半部且该第二掺杂层环绕该第二鳍状结构的该下半部。
8.如权利要求7所述的半导体元件，另包含一浅沟隔离，环绕该第一鳍状结构及该第二鳍状结构，其中该浅沟隔离的上表面切齐该第一鳍状结构及该第二鳍状结构的该下半部的上表面。
9.如权利要求6所述的半导体元件，其中该凸块的高度介于该第一掺杂层厚度或该第二掺杂层厚度的2倍至20倍。
10.如权利要求6所述的半导体元件，其中该凸块包含N型掺质及P型掺质。
11.如权利要求6所述的半导体元件，其中该第二掺杂层接触该第一掺杂层于该基底上。
12.一种半导体元件，包含：
基底，该基底具有第一区域以及第二区域；
第一鳍状结构，设于该第一区域上以及一第二鳍状结构设于该第二区域上；
第一凸块，设于该第一区域上；
第二凸块，设于该第二区域上；
第一掺杂层，设于该第一鳍状结构及该第一凸块上；
第一衬垫层，设置于该第一掺杂层及该第一凸块上；
第二掺杂层，设于该第二鳍状结构及该第二凸块上；
第二衬垫层，设置于该第二掺杂层、该第一凸块、该第二凸块以及该第一衬垫层上，其中该第一衬垫层位于该第二衬垫层与该第一掺杂层之间；
第一栅极结构，覆盖该第一鳍状结构及该第一凸块；以及
第二栅极结构，覆盖该第二鳍状结构及该第二凸块。
13.如权利要求12所述的半导体元件，其中各该第一鳍状结构及该第二鳍状结构包含一上半部以及一下半部，该第一掺杂层环绕该第一鳍状结构的该下半部且该第二掺杂层环绕该第二鳍状结构的该下半部。
14.如权利要求13所述的半导体元件，另包含一浅沟隔离环绕该第一鳍状结构及该第二鳍状结构，其中该浅沟隔离的上表面切齐该第一鳍状结构及该第二鳍状结构的该下半部的上表面。
15.如权利要求12所述的半导体元件，其中该第一凸块的高度介于该第一掺杂层厚度的2倍至20倍。
16.如权利要求12所述的半导体元件，其中该第一掺杂层覆盖该第一凸块的上表面及侧壁。
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