CN105140207A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN105140207A
CN105140207A CN201510342188.2A CN201510342188A CN105140207A CN 105140207 A CN105140207 A CN 105140207A CN 201510342188 A CN201510342188 A CN 201510342188A CN 105140207 A CN105140207 A CN 105140207A
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China
Prior art keywords
interconnection
circuit substrate
layer
interconnection layer
exposed surface
Prior art date
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Granted
Application number
CN201510342188.2A
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English (en)
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CN105140207B (zh
Inventor
山田启寿
石田正明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Publication of CN105140207A publication Critical patent/CN105140207A/zh
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Publication of CN105140207B publication Critical patent/CN105140207B/zh
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Abstract

根据一个实施例，半导体装置包括：电路基板、半导体元件、密封树脂层和导电屏蔽层。该电路基板包括：绝缘层、形成设置在绝缘层的上表面侧上的第一互连层的多个互连、形成设置在绝缘层的下表面侧上的第二互连层的多个互连，以及从绝缘层的上表面穿通到下表面的多个过孔。半导体元件安装在电路基板的上表面侧上。导电屏蔽层覆盖密封树脂层和电路基板端部的一部分。多个过孔中的任何一个与导电屏蔽层电连接。

Description

半导体装置
本申请是申请日为2012年1月31日、发明名称为“半导体装置”的专利申请201210021621.9的分案申请。
相关申请的交叉引用
本申请基于2011年1月31日提交的在先日本专利申请No.2011-019273并要求享有其优先权权益；通过引用将其全部内容并入本文。
技术领域
本文描述的实施例一般地涉及半导体装置。
背景技术
通常，当电流流过半导体元件或***电路时，在电流周围感应出电场和磁场，从而产生不必要的电磁噪声。不必要的电磁噪声影响其它电路、元件等的运转。例如，存在如下情况：安装在诸如蜂窝电话等移动通信设备中的半导体装置发射的电磁噪声入射到天线上，从而引起对无线电波接收的干扰。
为了屏蔽这种电磁噪声并且保护半导体元件，存在一种提供覆盖电路模块的屏蔽板的方法。然而，以屏蔽板覆盖电路模块的方法在电路模块的尺寸缩小方面可能存在困难。
相反，存在一种半导体装置(半导体封装)，其中在半导体元件本身的***上形成屏蔽膜。通过在电路模块中安装这种半导体装置，可以将电路模块尺寸缩小。对于半导体元件而言需要更高的运转速度，并且希望得到更多地屏蔽电磁噪声的高可靠性半导体装置。
发明内容
一个问题是获得更多地屏蔽电磁噪声的高可靠性半导体装置。
通常，根据一个实施例，半导体装置包括：电路基板、半导体元件、密封树脂层和导电屏蔽层。所述电路基板包括：绝缘层、形成设置在所述绝缘层上表面侧上的第一互连层的多个互连、形成设置在所述绝缘层下表面侧上的第二互连层的多个互连，以及从所述绝缘层的所述上表面穿通到所述下表面的多个过孔。所述半导体元件安装在所述电路基板的所述上表面侧上。所述密封树脂层设置在所述电路基板的所述上表面上并且将所述半导体元件密封。所述导电屏蔽层覆盖所述密封树脂层和所述电路基板的端部的一部分。将所述多个过孔中的任何一个与所述导电屏蔽层电连接。形成所述第二互连层的所述多个互连中的任何一个被电连接到能够变为地电位的外部连接端子。
通常，根据另一个实施例，半导体装置包括：电路基板、半导体元件、密封树脂层和导电屏蔽层。所述电路基板包括：绝缘层、形成设置在所述绝缘层上表面侧上的第一互连层的多个互连和形成设置在所述绝缘层下表面侧上的第二互连层的多个互连。所述半导体元件安装在所述电路基板的所述上表面侧上。所述密封树脂层设置在所述电路基板的所述上表面上并且将所述半导体元件密封。所述导电屏蔽层覆盖所述密封树脂层和所述电路基板的端部的一部分。形成所述第二互连层的所述多个互连不与所述导电屏蔽层接触、被电连接到形成所述第一互连层的所述多个互连中的任何一个上并且被拉到(bedrawnto)所述电路基板的端部以便在所述电路基板的侧表面处暴露。
附图说明
图1是用于描述根据第一实施例的半导体装置的概观的示意性截面图；
图2A和2B是根据第一实施例的半导体装置的示意性平面示图；
图3A和3B是根据第一实施例的半导体装置的示意性平面示图；
图4A到4D是用于描述根据第一实施例的半导体装置的制造过程的示意性截面图；
图5A和5B是用于描述屏蔽电磁噪声的效果的仿真结果；
图6是根据第二实施例的半导体装置的示意性截面图；
图7A和7B分别是根据第三实施例的半导体装置的示意性平面示图和用于描述屏蔽效果的示图；以及
图8是根据第四实施例的半导体装置的示意性截面图。
具体实施方式
在下文中，将参考附图描述实施例。在以下的描述中，以相同的附图标记标注同样的部件，并且适当地省略对已描述过的部件的描述。可以适当地将以下描述的实施例结合。
第一实施例
图1是用于描述根据第一实施例的半导体装置的概观的示意性截面图。
图1示出根据第一实施例的半导体装置1并且还示出安装基板100，半导体装置1安装在该安装基板100上。
半导体装置1是FBGA(细间距球栅阵列)半导体封装。半导体装置1包括电路基板10。电路基板10也被称作内插器(interposer)基板。电路基板10包括：绝缘层11、形成设置在绝缘层11的上表面侧的***上的第一互连层的多个互连12和形成设置在绝缘层11的下表面侧上的第二互连层的多个互连13。电路基板10还包括从绝缘层11的上表面(第一主表面)穿通到下表面(第二主表面)的多个过孔14。在电路基板10的上表面上形成覆盖第一互连层12的一部分的阻焊层15。在电路基板10的下表面上形成覆盖第二互连层13的一部分的阻焊层16。形成第二互连层的多个互连13中的每个都是焊盘形(land-shaped)互连层。作为焊球的外部连接端子17连接到形成第二互连层的多个互连13中的每个上。延长线19从***的外部连接端子17延伸到电路基板10的外部。延长线19连接到在电路基板10的侧表面10w处暴露的过孔14。延长线19是连接***的外部连接端子17和最接近***的外部连接端子17的过孔14的连接线。外部连接端子17连接到设置在安装基板100的上表面侧上的互连层101上。
半导体元件20安装在电路基板10的上表面侧上。导线(键合线)21的一个端部连接到半导体元件20的上表面。导线21的另一个端部连接到第一互连层12。导线21是导电构件，并且对形成第一互连层的多个互连12中的至少一个和设置在半导体元件表面上的电极(未示出)进行电连接。
半导体元件20的***和导线21由设置在电路基板10的上表面侧上的密封树脂层30密封。在半导体元件20和电路基板10之间的空间中形成管芯键合材料22。以导电屏蔽层40覆盖密封树脂层30和电路基板10的侧表面10w的一部分。导电屏蔽层40连接到设置在电路基板10的侧表面(外端部)10w处的过孔14。在电路基板10的侧表面10w处暴露的过孔14中的至少一个可以设置在地(GND)电位处。因此，半导体元件20的***、导线21、电路基板10的上表面侧和导电屏蔽层40(其覆盖电路基板10的侧表面10w的一部分)的电位可以设置成地(GND)电位。
半导体元件20例如是诸如闪速存储器和DRAM等存储器元件、诸如微处理器等运算元件、信号处理元件，等等。导线21的材料例如是金(Au)、铝(Al)、铜(Cu)，等等。第一互连层12和第二互连层13是铜(Cu)薄片、包含银(Ag)和/或铜(Cu)的导电膏等，而根据需要以镍(Ni)、金(Au)等对表面进行镀覆。过孔14例如是柱状电极。过孔14可以是其中全部部件由导电材料制成的柱状电极，或可以具有包括除了柱状电极之外的圆柱形的圆柱形电极和嵌入圆柱形电极的中空空间中的树脂等的结构。过孔14的材料是铜(Cu)、钨(W)等。
导电屏蔽层40优选地由电阻率尽可能低的材料制成，以便屏蔽由半导体元件20发射的高频噪声。作为导电屏蔽层40的材料，选择例如银(Ag)、铜(Cu)、镍(Ni)、铝(Al)等。更具体地，导电屏蔽层40是具有固化的银(Ag)膏的含银(Ag)层，并且将其薄层电阻调节为0.1(Ω/□)或更小。导电屏蔽层40具有几个μm(微米)到几个10μm的厚度，优选地为1到90μm。
图2A和2B是根据第一实施例的半导体装置的示意性平面示图，其中图2A是电路基板的上表面侧的示意性平面示图，而图2B是电路基板的下表面侧的示意性平面示图。图2A和2B是从垂直于绝缘层11的上表面(或下表面)的方向观察的电路基板10的示图。
如在图2A中所示，在电路基板10的上表面侧上设置多个过孔14。多个过孔14从绝缘层11的上表面穿通到下表面。由附图标记23围绕的矩形区域是用于半导体元件20的元件安装区域23。在元件安装区域23中和/或元件安装区域23外部设置多个过孔14。形成第一互连层的多个互连12设置在元件安装区域23外部。从元件安装区域23中的过孔14到第一互连层12设置延长线18。延长线18是半导体元件20的信号线、地互连等。延长线18是铜(Cu)薄片、包含银(Ag)和/或铜(Cu)的导电膏等。
如在图2B中所示，多个外部连接端子17以垂直和水平行设置在电路基板10的下表面侧上。多个外部连接端子17中的每个经由过孔14电连接到上表面侧上的延长线18。即，外部连接端子17经由第二互连层13、过孔14和延长线18电连接到第一互连层12。虽然在图1中示出的第二互连层13未在图2B中示出，但是第二互连层13实际上与外部连接端子17接触(见图1)。
在半导体装置1中，由在数量上小于所述多个外部连接端子17的多个外部连接端子17构成的组可以变为地电位。例如，在半导体装置1安装在安装基板100上之后，外部连接端子17中的一些通过设置在安装基板100中的地互连而变为地电位。在附图中，可以变为地电位的外部连接端子由附图标记17g表示并且被称为外部连接端子17g。换句话说，由在数量上小于形成第二互连层的所述多个互连13的形成第二互连层的多个互连13构成的组可以变为地电位。而且，与外部连接端子17g接触的第二互连层13可以变为地电位。
在图2B中，变为地电位的外部连接端子17g(或与外部连接端子17g接触的第二互连层13)分别位于元件安装区域23的四个拐角处。换句话说，外部连接端子17g(或与外部连接端子17g接触的第二互连层13)中的每个都位于半导体元件的拐角处。
在电路基板10中，设置由在数量上小于设置在电路基板10的整个主表面上的所述多个过孔14的多个过孔14构成的组，以便在电路基板10的侧表面10w处将它们暴露。设置在侧表面10w处的多个过孔14中的每个都通过制造过程中使用的划片刀片而在电路基板10的侧表面处被切割，并且都具有暴露的表面。在半导体装置1中，将设置在侧表面10w处的多个过孔14中的每个的暴露表面和导电屏蔽层40连接。
延长线19从变为地电位的外部连接端子17g(或与外部连接端子17g接触的第二互连层13)延伸。延长线19是铜(Cu)薄片、包含银(Ag)和/或铜(Cu)的导电膏等。
延长线19还连接到设置在侧表面10w处的多个过孔14中的一些上。在图2B中，连接到延长线19的过孔由附图标记14g表示并且被称为过孔14g。因此，设置在电路基板10的侧表面10w处的多个过孔14g可以变为地电位。
在半导体装置1中，外部连接端子17g(或与外部连接端子17g接触的第二互连层13)中的每个都电连接到多个过孔14g中的每个上，所述多个过孔14g是设置在侧表面10w处的过孔14的另外一部分；因此，导电屏蔽层40可以变为地电位。即，在半导体装置1中，在导电屏蔽层40和地电位之间设置多个触点。为过孔14g提供地电位的延长线19可以设置在电路基板10的上表面侧上。
变为地电位的外部连接端子17g(或与外部连接端子17g接触的第二互连层13)的数量和布置不受限于以上描述的示例。以下描述另一个示例。
图3A和3B是根据第一实施例的半导体装置的示意性平面示图，其中图3A是第一改型示例的电路基板的示意性平面示图，而图3B是第二改型示例的电路基板的示意性平面示图。图3A和3B示出电路基板10的下表面侧。
在图3A示出的电路基板10中，变为地电位的外部连接端子17g(或与外部连接端子17g接触的第二互连层13)中的每个都位于元件安装区域23一侧的中央部分中。换句话说，外部连接端子17g(或与外部连接端子17g接触的第二互连层13)中的每个都位于半导体元件20的相邻拐角之间。
延长线19从变为地电位的外部连接端子17g(或与外部连接端子17g接触的第二互连层13)延伸。延长线19还连接到设置在侧表面10w处的多个过孔14g。过孔14g连接到导电屏蔽层40。
在图3B示出的电路基板10中，将图2B的结构和图3A的结构结合。即，变为地电位的外部连接端子17g(或与外部连接端子17g接触的第二互连层13)中的每个都位于半导体元件20的拐角处和/或相邻拐角之间。
将相邻的外部连接端子17g(或与外部连接端子17g接触的相邻的第二互连层13)之间的距离调节为不超过半导体元件20等发射的电磁噪声波长的一半。
接下来，描述半导体装置1的制造过程。
图4A到4D是用于描述根据第一实施例的半导体装置的制造过程的示意性截面图。
首先，如在图4A中所示，形成单片化(fragmentation)前的半导体装置1。在该阶段，电路基板10处于切割前的状态中，并且多个半导体装置1被连接。
然后，将划片刀片90沿着划片线DL***电路基板10中。在该阶段，执行所谓的半划片，并且防止划片刀片90到达电路基板10的下表面侧。即，在接近划片线DL的过孔14的深度方向上在中途停止划片刀片90的***，并且过孔14使通过在电路基板10的深度方向上进行切割而获得的其切割表面暴露。在图4B中示出该状态。
过孔14的切割表面并非必须位于过孔14的中央，并且过孔14的一部分包括在切割表面中。为了增加过孔14和导电屏蔽层40之间的接触面积，过孔14的切割表面优选地接近过孔14的中央。
然后，将密封树脂层30固化，并且随后将导电屏蔽层40放置在如图4C中所示的密封树脂层30上。导电屏蔽层40也被掩埋在通过半划片形成的凹槽90h中。
通过例如转移方法、丝网印刷方法、喷洒施加方法、喷射式点胶方法、喷墨方法、气溶胶方法、无电镀覆方法、电解镀覆方法、溅射方法、蒸镀方法等执行导电屏蔽层40的形成。
通过在凹槽90h中掩埋导电屏蔽层40，导电屏蔽层40与过孔14的切割表面接触。之后，根据需要将导电屏蔽层40固化。
然后，如在图4D中所示，执行用于单片化的划片以形成半导体装置1。
现在将描述半导体装置1的效果。
图5A和5B是用于描述屏蔽电磁噪声的效果的仿真结果。
图5A的水平轴线表示从半导体元件20等发射的噪声频率(MHz)，而垂直轴线表示屏蔽效果(dB)。图5A的线(1)至(4)是分别基于图5B的图案(1)至(4)计算的仿真结果。
在图案(1)中，以电气连续性将一个外部连接端子17g连接到导电屏蔽层40。即，导电屏蔽层40与地电位接触的位置的数量为1。
在图案(2)中，除了图案(1)之外，以电气连续性将设置在半导体元件20的拐角(4个拐角)处的另外的外部连接端子17g连接到导电屏蔽层40。即，导电屏蔽层40与地电位接触的位置的数量为5。
在图案(3)中，除了图案(1)之外，以电气连续性将设置在半导体元件20的相邻拐角之间的另外的外部连接端子17g连接到导电屏蔽层40。即，导电屏蔽层40与地电位接触的位置的数量为5。
在图案(4)中，除了图案(1)之外，以电气连续性将设置在半导体元件20的拐角(4个拐角)处以及半导体元件20的相邻拐角之间的另外的外部连接端子17g连接到导电屏蔽层40。即，导电屏蔽层40与地电位接触的位置的数量为9。
在从50MHz到900MHz的噪声频率范围中，线(1)显示6dB到9dB，然而线(2)和(3)显示13dB到14dB的增加值。而且，线(4)显示大约15dB的增加值。例如，在噪声频率为最高的900MHz处，(2)和(3)高于(1)大约6dB，而(4)高于(1)大约8dB。因此，屏蔽效果随着导电屏蔽层40与地电位接触的位置的数量的增加而提高。
在半导体装置1中，由于设置在电路基板10的侧表面10w处的过孔14在厚度方向上穿过电路基板10，从电路基板10的整个侧表面的电磁波泄漏被抑制。
而且，在半导体装置1中，设置多个导电屏蔽层40与地电位接触的位置，并且将所述位置之间的距离调节为不超过从半导体装置20等发射的电磁噪声波长的一半。因此，可以更确定地由导电屏蔽层40屏蔽电磁噪声。
在导电屏蔽层40与地电位接触的位置的数量仅为1的情况下，噪声可以容易地从电路基板10和导电屏蔽层40之间泄漏。例如，当半导体元件20从特定地方发射噪声时，在该特定地方与导电屏蔽层40与地电位接触的位置彼此远离的情况下，噪声可以从电路基板10和导电屏蔽层40之间容易地泄漏。
相反，在半导体装置1中，设置多个导电屏蔽层40与地电位接触的位置，并且导电屏蔽层40均匀地设置成地电位。因此，可以由导电屏蔽层40更确定地屏蔽电磁噪声。
(第二实施例)
图6是根据第二实施例的半导体装置的示意性截面图。
半导体装置2的基本结构与半导体装置1的基本结构相同。然而，在根据第二实施例的电路基板10中，设置在电路基板10的侧表面10w上的过孔14不在电路基板10的侧表面10w处暴露。在根据第二实施例的电路基板10中，设置在接近电路基板10的侧表面10w处的过孔14g上的互连层14m在电路基板10的侧表面10w处暴露。互连层14m由与过孔14g相同的材料制成。连接到过孔14g的焊盘形互连层14m被连接到导电屏蔽层40。互连层14m电连接到变为地电位的外部连接端子17g(或与外部连接端子17g接触的第二互连层13)。
换句话说，外部连接端子17g(或与外部连接端子17g接触的第二互连层13)中的每个都电连接到侧表面10w处的互连层14m；因此，导电屏蔽层40可以变为地电位。在半导体装置2中，经由互连层14m在导电屏蔽层40和地电位之间设置多个触点。而且由此构成的半导体装置2提供与半导体装置1相似的效果。
(第三实施例)
图7A和7B分别是根据第三实施例的半导体装置的示意性平面示图和用于描述屏蔽效果的示图。图7A示出半导体装置的电路基板的示意性平面示图，图7B示出用于描述屏蔽效果的示图。
图7A示出电路基板10的下表面侧上的平面示图。
在根据第三实施例的电路基板10中，作为第二互连层，环形的互连层19r设置在垂直和水平布置的外部连接端子17(或与外部连接端子17接触的第二互连层13)的***处。即，电路基板10还包括围绕设置在绝缘层11下表面侧上的外部连接端子17(或与外部连接端子17接触的第二互连层13)的环形互连层19r。互连层19r电连接到外部连接端子17g(或与外部连接端子17g接触的第二互连层13)中的任何一个上。
例如，当外部连接端子17g变为地电位时，全部互连层19r和过孔14g都变为地电位。
当外部连接端子17g和互连层19r以比电磁噪声波长的一半窄的间距电连接时，它们是有效的；并且它们连接的间距越窄，屏蔽效果越高。而且，当互连层19r和过孔14g以比电磁噪声波长的一半窄的间距电连接时，它们是有效的；并且它们连接的间距越窄，屏蔽效果越高。当环形互连层19r具有0.035mm或更多的线宽时，它是有效的，并且使宽度加宽到大约0.5mm提供了对电磁波更高的屏蔽效果。
图7B示出将外部连接端子17g和互连层19r之间的间距设置为1.6mm或更小，将互连层19r和过孔14g之间的间距设置为0.4mm，并且将互连层19r的线宽设置为0.5mm的情况下的屏蔽效果。水平轴线表示从半导体元件20等发射的噪声频率(MHz)，而垂直轴线表示屏蔽效果(dB)。
在根据第三实施例的电路基板中，磁场屏蔽效果与第一和第二实施例相比是高的。
(第四实施例)
图8是根据第四实施例的半导体装置的示意性截面图。
根据第四实施例的半导体装置3包括电路基板10。电路基板10包括：绝缘层11、形成设置在绝缘层11的上表面侧上的第一互连层的多个互连12和形成设置在绝缘层11的下表面侧上的第二互连层的多个互连13。半导体装置3还包括：安装在电路基板10的上表面侧上的半导体元件20、密封半导体元件20并设置在电路基板10的上表面上的密封树脂层30，以及覆盖密封树脂层30和电路基板10的端部的一部分的导电屏蔽层40。
在半导体装置3中，在电路基板10的下侧上多处设置与形成第一互连层的多个互连12和形成第二互连层的多个互连13不同的形成第二互连层的多个互连50。形成第二互连层的多个互连50不电连接到导电屏蔽层40，并且设置在绝缘层11的下表面侧上的区域(其中不设置形成第二互连层的多个互连13)中。例如，当在第一互连层12上以及电路基板10的上表面侧上的延长线18上执行镍(Ni)、金(Au)等的电解镀覆处理时，形成第二互连层的多个互连50起到用于电镀的互连的作用。因此，第二互连层的互连50电连接到形成第一互连层的多个互连12中的任何一个上。
通过使由此构成的第二互连层的互连50围绕在电路基板10的下侧上的周围，电路基板10的上表面侧的互连设计的允许边界(margin)增加。而且，由于在电路基板10的下侧上设置形成第二互连层的多个互连50，形成第二互连层的多个互连50和导电屏蔽层40不接触(不以电气连续性而连接)。因此，即使在第一互连层12和延长线18上执行镀覆处理后第二互连层的互连50还存在，第二互连层的互连50和导电屏蔽层40也不接触。即，第二互连层的互连50不需要通过蚀刻过程去除，从而不引起制造过程的成本增加。将多个互连50拉到电路基板10的端部，以便在侧表面10w处暴露。
另外在半导体装置3中，如在附图中所示，还在电路基板10中设置从绝缘层11的上表面穿通到下表面的多个过孔14，而由数量上小于所述多个过孔14的多个过孔构成的第一组可以在电路基板10的侧表面10w处暴露。在该情况中，将第一组的过孔14的暴露表面中的每个和导电屏蔽层连接。在侧表面10w处暴露的过孔14中的一些形成变为地电位的过孔14g。
在第一到第四实施例中描述的外部连接端子17(17g)可以根据需要而被完全地除去；并且LGA(焊盘栅格阵列)结构(其中在电路基板10的下表面侧上使形成第二互连层的多个互连13中的每个都暴露)的半导体装置1到3也包括在实施例中。
另外，在设置在电路基板10的侧表面10w处的多个过孔14中，可以根据需要去除未电连接到外部连接端子17g的那些过孔14。这种结构也包括在实施例中。
在上文中，参考具体示例描述了实施例。然而，实施例不限于这些具体的示例。即，本领域技术人员可以适当地对这些具体示例进行设计改型，并且在包括实施例的精神的意义上，这些改型也包括在实施例的范围中。以上描述的具体示例的部件以及其布置、材料、条件、形状、尺寸等不限于举例说明的那些，而可以被适当地改变。
此外，本领域技术人员可以在实施例的思想内实现各种改变和改型。这种改变和改型也应该被视为在实施例的范围内。另外，在技术可行性的范围内可以组合实施例的部件，并且在包括实施例的精神的意义上它们的组合也包括在实施例的范围中。
虽然已经描述了特定实施例，但是仅借助于示例介绍了这些实施例，并不旨在限制本发明的范围。实际上，可以以各种其它形式实施本文描述的新颖的实施例；而且，在不脱离本发明精神的情况下，可以以本文描述的实施例的形式进行各种省略、替换和改变。随附的权利要求及其等同物旨在包括落入本发明范围和精神内的这种形式或改型。

Claims (18)

1.一种半导体装置，包括：
电路基板，所述电路基板包括：绝缘层、形成设置在所述绝缘层的上表面侧上的第一互连层的多个互连、形成设置在所述绝缘层的下表面侧上的第二互连层的多个互连、以及暴露表面，所述暴露表面在所述电路基板的侧表面处暴露；
半导体元件，所述半导体元件安装在所述电路基板的所述上表面侧上；
密封树脂层，所述密封树脂层设置在所述电路基板的所述上表面上并且将所述半导体元件密封；以及
导电屏蔽层，所述导电屏蔽层覆盖所述密封树脂层和所述电路基板的端部的一部分，
所述导电屏蔽层的多个位置中的任何一个位置与所述暴露表面电连接，
所述暴露表面被电连接到形成所述第二互连层的所述多个互连中的任何一个互连，
所述导电屏蔽层被电连接到能够变为地电位的外部连接端子中的任何一个外部连接端子；
其中相邻的能够变为所述地电位的外部连接端子之间的距离、相邻的能够变为所述地电位的第二互连层之间的距离以及与能够变为所述地电位的位置连接的暴露表面之间的距离不超过所述半导体元件发射的电磁噪声的波长的一半。
2.根据权利要求1所述的装置，其中与所述位置连接的多个所述暴露表面中的每一个暴露表面都在所述电路基板的侧表面处暴露，并且暴露在所述侧表面处的与所述位置连接的多个所述暴露表面中的每一个暴露表面都与所述导电屏蔽层连接。
3.根据权利要求1所述的装置，其中从垂直于所述绝缘层的所述上表面的方向观察，能够变为地电位的所述第二互连层中的每个第二互连层都位于所述半导体元件的拐角处。
4.根据权利要求1所述的装置，其中从垂直于所述绝缘层的所述上表面的方向观察，能够变为地电位的所述第二互连层中的每个第二互连层都位于所述半导体元件的相邻拐角之间。
5.根据权利要求1所述的装置，其中
所述电路基板还包括焊盘形互连层，所述焊盘形互连层设置在所述电路基板的侧表面附近并且在所述电路基板的侧表面处暴露，
与所述位置连接的多个所述暴露表面中的任何一个暴露表面都电连接到所述焊盘形互连层，并且
所述焊盘形互连层连接到所述导电屏蔽层。
6.根据权利要求1所述的装置，其中所述电路基板还包括环形互连层，所述环形互连层设置在所述绝缘层的下表面侧上、围绕所述第二互连层并且电连接到与所述位置连接的多个所述暴露表面中的任何一个暴露表面。
7.根据权利要求1所述的装置，其中所述导电屏蔽层包含银(Ag)、铜(Cu)、镍(Ni)和铝(Al)中的至少一种。
8.根据权利要求1所述的装置，其中所述暴露表面由铜(Cu)或钨(W)构成。
9.一种半导体装置，包括：
电路基板，所述电路基板包括：绝缘层、形成设置在所述绝缘层的上表面侧上的第一互连层的多个互连、形成设置在所述绝缘层的下表面侧上的第二互连层的多个互连、以及暴露表面，所述暴露表面在所述电路基板的侧表面处暴露；
半导体元件，所述半导体元件安装在所述电路基板的所述上表面侧上；
密封树脂层，所述密封树脂层设置在所述电路基板的所述上表面上并且将所述半导体元件密封；
导电屏蔽层，所述导电屏蔽层覆盖所述密封树脂层和所述电路基板的端部的一部分，
形成所述第二互连层的所述多个互连不与所述导电屏蔽层接触、被电连接到形成所述第一互连层的所述多个互连中的任何一个互连并且被拉到所述电路基板的端部以便在所述电路基板的侧表面处暴露；
形成与形成设置在所述绝缘层的下表面侧上的所述第二互连层的所述多个互连不同的其它第二互连层的多个互连；以及
所述导电屏蔽层的多个位置中的任何一个位置与所述暴露表面电连接，
与所述位置连接的任何暴露表面被电连接到形成所述其它第二互连层的所述多个互连中的任何一个互连，并且
所述导电屏蔽层被电连接到能够变为地电位的外部连接端子中的任何一个外部连接端子；
其中相邻的能够变为所述地电位的外部连接端子之间的距离、与能够变为所述地电位的所述位置连接的暴露表面之间的距离以及形成能够变为所述地电位的所述其它第二互连层的互连之间的距离不超过所述半导体元件发射的电磁噪声的波长的一半。
10.根据权利要求9所述的装置，其中与所述位置连接的多个所述暴露表面中的每一个暴露表面都在所述电路基板的侧表面处暴露，并且在所述侧表面处暴露的与所述位置连接的多个所述暴露表面中的每一个暴露表面都与所述导电屏蔽层连接。
11.根据权利要求9所述的装置，其中从垂直于所述绝缘层的所述上表面的方向观察，能够变为地电位的所述其它第二互连层中的每个其它第二互连层都位于所述半导体元件的拐角处。
12.根据权利要求9所述的装置，其中从垂直于所述绝缘层的所述上表面的方向观察，能够变为地电位的所述其它第二互连层中的每个其它第二互连层都位于所述半导体元件的相邻拐角之间。
13.根据权利要求9所述的装置，其中所述第一互连层包含银(Ag)和铜(Cu)中的至少一种。
14.根据权利要求9所述的装置，其中所述第一互连层的表面被以镍(Ni)和金(Au)中的至少一种部分地镀覆。
15.根据权利要求9所述的装置，其中所述第二互连层包含银(Ag)和铜(Cu)中的至少一种。
16.根据权利要求9所述的装置，其中所述第二互连层的表面被以镍(Ni)和金(Au)中的至少一种部分地镀覆。
17.根据权利要求9所述的装置，其中所述导电屏蔽层包含银(Ag)、铜(Cu)、镍(Ni)和铝(Al)中的至少一种。
18.根据权利要求9所述的装置，其中所述暴露表面由铜(Cu)或钨(W)构成。
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CN101978492A (zh) * 2008-03-24 2011-02-16 株式会社村田制作所 电子元器件组件的制造方法
CN101635281A (zh) * 2008-07-21 2010-01-27 日月光半导体制造股份有限公司 具有电磁干扰防护体的半导体封装件及其形成方法

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CN106206332A (zh) * 2016-07-17 2016-12-07 王培培 一种集成电路封装结构的制造方法
CN106206332B (zh) * 2016-07-17 2019-04-05 山东华芯电子有限公司 一种集成电路封装结构的制造方法

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