TWI479642B - 具有間隔件之積體電路封裝件系統 - Google Patents

具有間隔件之積體電路封裝件系統 Download PDF

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Publication number
TWI479642B
TWI479642B TW097107273A TW97107273A TWI479642B TW I479642 B TWI479642 B TW I479642B TW 097107273 A TW097107273 A TW 097107273A TW 97107273 A TW97107273 A TW 97107273A TW I479642 B TWI479642 B TW I479642B
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integrated circuit
package
cavity
circuit package
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TW097107273A
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TW200837926A (en
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Seng Guan Chow
Il Kwon Shim
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Stats Chippac Ltd
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

具有間隔件之積體電路封裝件系統 [優先權之主張]
本申請案係主張2007年3月3日所提出申請之美國臨時專利申請案第60/892,851號的優先權，於此併入該專利申請案之內容，以供參考。
本發明大體上係關於一種積體電路封裝件系統，特別是關於一種具有間隔件之積體電路封裝件系統。
電子裝置(例如智慧型電話、數位私人助理、定位裝置、數位相機、隨身聽、電腦或運輸工具)目前已變成很多日常活動不可缺少的部分。這些電子裝置的關鍵組件就是積體電路裝置。這些極小的積體電路必須在日常活動(包含大量的環境變化與潛在的外力損害下)期間仍然可以運作。很多各式各樣用於保護、安裝或相互連結的封裝方式，已被開發出來用於積體電路裝置中。
積體電路晶粒(die)通常被封入塑膠封裝件中用以提供於惡劣環境下的保護並使能夠於積體電路晶粒與下層基板(例如印刷電路板(PCB))之間建立電性相互連結(electrical interconnect)。這種封裝件的元件包含引線框架或基板、積體電路晶粒、使積體電路晶粒附接至引線框架或基板之黏接材料、焊接電線或其他連接器，該連接器將積體電路晶粒上之焊墊電性連接至引線框架或基板。該封裝件也可包含塑膠或其他絕緣材料，該絕緣材料包覆各組件並形成封 裝件之外表面。
晶片製程努力的減少電晶體或電容器的特徵尺寸，係為了增加電路密度並強化其功能。具有亞微米型(sub-micron)線寬之裝置構形是相當常見的，以致於單一晶片通常包括上百萬個電子裝置。對於改善電子系統，縮小特徵尺寸的技術已經相當成功，且預期未來仍會持續發展。然而，對於進一步縮小特徵尺寸的技術目前已遭遇到很大的障礙。這些障礙包括缺陷密度控制、光學系統解析限制、以及製程材料與裝備的獲得。因此注意力已漸漸轉移到半導體封裝作業，尋找是否有方法可滿足強化系統效能這種無止境的需求。
習知設計的缺點包含在主機板(motherboard)的安裝表面上有相當大的封裝足跡(footprint)。該封裝足跡顯示典型最大封裝件的尺寸，也就是封裝件在X-Y軸的最大尺寸。在安裝空間受重視之產品中(例如傳呼機、攜帶式電話、個人電腦與其他產品)，大的封裝足跡係非常不理想。為了達成在封裝件中增加電路量但不增加面積的目標，使得封裝件不會佔用電路板上任何額外的空間，製造者已經在單一封裝件中堆疊兩個或更多個的晶粒。不幸的，電性互連接大量的重疊、封裝件上層大足跡，裝置整合度增加、預先測試、與互連接長度等問題一直挑戰著習知封裝件的設計。
因此，目前仍對改善積體電路封裝件系統之面積與體積有需求存在。考慮到持續增加的商業競爭壓力、消費者的期待與減少產品在市場上產生差異的機會，找出這些問 題的答案仍然非常重要。此外，因為對於降低成本、增加性能和效率與面對競爭壓力的需求，更增加了對於尋找這些問題解答之急迫性。
許多人長期尋找這些問題的解決方案，但是先前技術並沒有對這些解決方案提出任何建議或指導，因此這些問題的解決方式已長期被熟悉此項技術者所規避。
本發明提供一種積體電路封裝件系統，包含：提供可安裝之積體電路系統，該積體電路系統具有含有空腔在其中之封裝體與藉由該空腔而暴露於外之第一間隔件；將第二間隔件安裝於該第一間隔件上方用以在該第二間隔件上僅堆疊分離裝置，而該第二間隔件係於該封裝體與該空腔之上；以及將電子組件安裝於該第二間隔件之上。
本發明之某些具體實施例除了上述系統以外仍有其他態樣與替代上述系統之態樣。藉由閱讀後面詳細的描述同時參考附件圖示可使本發明態樣對熟悉此項技術領域者變得非常明顯。
透過以下具體實施例詳細且充分的描述，能使此技術領域之人可據以使用與實施本發明。根據本說明書所揭露之內容將會使其他實施例變得非常明顯，該系統，程序或機械上的改變皆可於不偏於本發明之範圍內據以實施。
以下的描述中，會提供數個具體詳細說明藉以了解本發明內容。然而，非常明顯地即使沒有這些詳細說明本發 明仍可實施。為了避免混淆本發明，一些習知的電路、系統架構與程序步驟不會於本說明書中詳細描述。同樣地，顯示本系統具體實施例之圖式僅為一部分的說明圖而並不按尺寸繪製，尤其是某些的尺寸為了清楚表示係誇大顯示於圖式中。一般而言，本發明能夠操作於任何方向。
另外，許多被描述與揭露之具體實施例具有一些共同的特徵，為了使其圖解、描述與理解清楚與容易，這些相似或相同的特徵將會藉由相同的參考數值來描述。這些具體實施例被標示為第一具體實施例、第二具體實施例‥等等以方便說明，且並未具備其他含義或是意圖對本發明作限制。
為了說明目的，用於本文之名詞“水平”定義為與積體電路之平面或表面呈平行，且無關於其方向。而名詞“垂直”意指與剛才所定義的“水平”成垂直的方向。一些名詞例如“在…上方(above)”，“在…下方(below)”，“下部(bottom)”，“上部(top)”，“側邊(side)”(如在側壁)，“較高(higher)”，“較低(lower)”，“較上面(upper)”，“在…之上(over)”和“之下(under)”係根據該水平平面作定義。名詞“在…上(on)”代表在元件之間有直接相連接。使用於本文之名詞“程序”包含材料沉積、圖案化、曝露、顯影、蝕刻、清洗、壓模與/或材料清除或是製成上述結構所需者。使用於本文之名詞“系統”意指並相關於依據使用本文之名詞所實現的本發明之方法或設備。
參考第1圖，顯示本發明之積體電路封裝件系統100 於第一具體實施例中之下視圖。該下視圖顯示基板102(例如疊片基板)與附著於基板102之外部互連接104(例如焊錫球)。
為了例示目的，積體電路封裝件系統100顯示具有相等間隔開之外部互連接104。雖然，應了解在積體電路封裝件系統100上某些部位可以空無一物，而使得該積體電路封裝件系統100上之外部互連接104其間隔不相同。
參考第2圖，顯示第1圖之積體電路封裝件系統100沿著直線2--2之截面圖。該截面圖中顯示具有含有空腔210之封裝體208(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔210而暴露於外之第一間隔件212之可安裝的積體電路系統206。第二間隔件214(例如疊片基板)係安裝於封裝體208與空腔210之上。該第二間隔件214與第一間隔件212相連接。電子組件216(例如覆晶)安裝於第二間隔件214之上。
在此範例中該可安裝的積體電路系統206包括位於基板102(例如疊片基板)之上之積體電路封裝件218與被動裝置220。第一內部互連接222(例如焊接線或帶狀焊接線(ribbon bond wire))，係將積體電路封裝件218上之第一間隔件212與基板102連接。封裝體208位於基板102之上用以覆蓋該積體電路封裝件218、第一內部互連接222與被動裝置220。
積體電路封裝件218包含積體電路晶粒224。該積體電路晶粒224包含非主動側226及主動側228，其中，該 主動側228包含製造於其上之主動電路。該非主動側226以黏著劑230(例如晶粒黏著劑)附著於第一間隔件212上。第一內部互互連接222(例如焊接線或帶狀焊接線帶)，能將積體電路封裝件218之第一間隔件212與基板102連接。該外部互連接104可附接下方並到達基板102，以連接至下一個系統層次(system level)(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
該第二間隔件214包含電性連接器232，例如焊錫球。在範例中，該第二間隔件214以電性連接器232與第一間隔件212互相連接。
在此範例中，電子組件216安裝於該第二間隔件214之上。該電子組件可為經過功能測試之已知良好裝置(Known Good Device, KGD)。
如此可發現本發明提供一種於封裝系統上之積體電路封裝件，可藉由使用該第二間隔件來減少高度。該第二間隔件係組構成具有再分配層與通孔，用以在該第二間隔件下方之積體電路與該第二間隔件上方之電子組件之間提供相互電性橋接。
可發現在本發明中，該第二間隔件可為了在最後組裝之前對其作測試而預先連接於積體電路系統或電子組件之其中任一者。此特性可進一步降低製造成本及增加可靠度。
參考第3圖，顯示於本發明之第二具體實施例中積體電路封裝件系統300沿著第1圖之直線2--2之截面圖。該截面圖顯示具有含有空腔310之封裝體308(例如包含環氧 壓模化合物之覆蓋件)與具有藉由空腔310而暴露於外之第一間隔件312之可安裝的積體電路系統306。第二間隔件314(例如疊置之基板)係安裝於封裝體308與空腔310之上。該第二間隔件314與第一間隔件312相連接。電子組件316(例如覆晶)安裝於第二間隔件314之上。
在此範例中該可安裝的積體電路系統306包含位於基板302(例如疊置之基板)之上之積體電路封裝件318與被動裝置320。第一內部互連接322(例如焊接線或帶狀焊接線)，係將積體電路封裝件318之第一間隔件312與基板302連接。封裝體308位於基板302之上用以覆蓋該積體電路封裝件318、第一內部互連接322與被動裝置320。
舉例來說，該積體電路封裝件318可以是晶圓級晶片規模封裝件(Wafer Level Chip Seale Package, WLCSP)，再分配層(Redistributed Layer, RDL)晶粒或覆晶。該積體電路封裝件318包含該第一間隔件312。該積體電路封裝件318以黏著劑330(例如晶粒附著黏著劑)附著於基板302上。第一內部互連接322(例如焊接線或帶狀焊接線)，能將第一間隔件312與基板302連接。外部互連接304可附接下方並到達基板302，以連接至下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
該第二間隔件314包含電性連接器332，例如焊錫球。在範例中，該第二間隔件314係以電性連接器332而與第一間隔件312互相連接。
在此範例中，電子組件316安裝於該第二間隔件314 之上。該電子組件可為經過功能測試之已知良好裝置(KGD)。
參考第4圖，顯示於本發明第三具體實施例中之積體電路封裝件系統400沿著第1圖之直線2--2之截面圖。該截面圖顯示具有含有空腔410之封裝體408(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔410而暴露於外之第一間隔件412之可安裝的積體電路系統406。第二間隔件414(例如疊置之基板)係安裝於封裝體408與空腔410之上。該第二間隔件414與第一間隔件412相連接。電子組件416(例如覆晶)安裝於第二間隔件414之上。
在此範例中該可安裝的積體電路系統406包括位於基板402(例如疊置之基板)之上之積體電路封裝件418與被動裝置420。第一內部互連接422(例如焊接線或帶狀焊接線)，係將積體電路封裝件418之第一間隔件412與基板402連接。封裝體408位於基板402之上用以覆蓋該積體電路封裝件418、第一內部互連接422與被動裝置420。
積體電路封裝件418包含積體電路晶粒424。該積體電路晶粒424包含非主動側426及主動側428，其中，該主動側428包含製造於其上之主動電路。該非主動側426附著以黏著劑430(例如晶粒附著黏著劑)附著於基板402。第二內部互連接434(例如焊接線或焊接線帶)，係將該主動側428與基板402連結。內在封裝體436(例如包含環氧壓模化合物之覆蓋件)位於基板402之上，該基板402用以覆蓋該積體電路晶粒424與第二內部互連接434。
該第一間隔件412係以第二黏著劑439安裝於積體電路封裝件418之內在封裝體436之上。該第二間隔件414包含電性連接器432，例如焊錫球。作為一範例，該第二間隔件414係以電性連接頭432而與第一間隔件412互相連接。在此範例中，該電子組件416安裝於該第二間隔件414上。外部互連接404可附接下方並到達基板402，用以連接至下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
參考第5圖，顯示於本發明第四具體實施例中之積體電路封裝件系統500沿著第1圖之直線2--2之截面圖。該截面圖顯示具有含有空腔510之封裝體508(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔510而暴露於外之第一間隔件512之可安裝的積體電路系統506。第二間隔件514(例如疊置之基板)係安裝於封裝體508與空腔510之上。該第二間隔件514與第一間隔件512相連接。電子組件516(例如覆晶)安裝於第二間隔件514之上。
在此範例中該可安裝的積體電路系統506包括在基板502(例如疊置之基板)之上之第一積體電路封裝件518、第二積體電路封裝件538與被動裝置520。該第二積體電路封裝件538係位於該第一積體電路封裝件518上。
第一內部互連接522(例如焊接線或帶狀焊接線)，係將第二積體電路封裝件538之第一間隔件512與基板502連接。封裝體508位於基板502之上用以覆蓋第一積體電路封裝件518、第二積體電路封裝件538、第一內部互連線 522與被動裝置520。
該第一積體電路封裝件518包含積體電路晶粒524。該積體電路晶粒524包括第一非主動側526及第一主動側528，其中，該第一主動側528包含製造於其上之主動電路。該第一非主動側526以第一黏著劑530(例如晶粒附著黏著劑)附著於基板502上。第二內部互連接534(例如焊接線或帶狀焊接線)能將該第一主動側528與基板502連接。內在封裝體536(例如包含環氧壓模化合物之覆蓋件)位於基板502之上，該基板502用以覆蓋該積體電路晶粒524與第二內部互連接534。
該第二積體電路封裝件538以第二黏著劑539安裝於第一積體電路封裝件518之上。該第二積體電路封裝件538包含第二積體電路晶粒540。該第二積體電路晶粒540包含第二非主動側542及第二主動側544，其中，該第二主動側544上包含製造於其上之主動電路。該第二非主動側542以第三黏著劑546附著於第一間隔件512上。該第二主動側544以第三內部互連接548連接於第一間隔件512。
該第二間隔件514包含電性連接器532，例如焊錫球。作為一範例，該第二間隔件514係以電性連接器532而與第一間隔件512互相連接。外部互連接504可附接下方並到達基板502，用以連接下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
參考第6圖，顯示於本發明第五具體實施例中之積體電路封裝件系統600沿著第1圖之直線2--2之截面圖。該 截面圖顯示具有含有空腔610之封裝體608(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔610而暴露於外之第一間隔件612之可安裝的積體電路系統606。第二間隔件614(例如疊置之基板)係安裝於封裝體608與空腔610之上。該第二間隔件614與第一間隔件612相連接。電子組件616(例如覆晶或封裝之積體電路裝置)安裝於第二間隔件614之上。
為了例示目的，積體電路封裝件系統600顯示其具有作為單一裝置之電子組件。然而，應了解積體電路封裝件系統600在不同的架構中於第二間隔件614之上可具有電子組件。舉例來說，該電子組件616可代表一些組件。
在此範例中該可安裝的積體電路系統606包含在基板602(例如疊置之基板)上之積體電路封裝件618與被動裝置620。第一內部互連接622(例如焊接線或帶狀焊接線)，係將積體電路封裝件618之第一間隔件612與基板602連接。
封裝體608位於基板602之上用以覆蓋積體電路封裝件618、第一內部互連接622與被動裝置620。為了例示目的，該積體電路封裝件系統600顯示具有封裝體608在基板602之上側之上具有垂直側壁，然而，應了解積體電路封裝件系統600對於封裝體608可具有不同的架構。舉例來說，封裝體608可以非垂直之側壁部分地覆蓋在基板602上側。
積體電路封裝件618包含積體電路晶粒624。該積體電路晶粒624包括非主動側626及主動側628，其中，該 主動側628包含製造於其上之主動電路。該非主動側626以黏著劑630(例如晶粒附著黏著劑)附著於基板602上。第二內部互連接634(例如焊接線或帶狀焊接線)能將該主動側628與基板602連接。外部互連接604可附接下方並到達基板602，用以連接下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
該第二間隔件614包含電性連接器632，例如焊錫球。舉例來說，該第二間隔件614係以電性連接器632而與第一間隔件612互相連接。再一個例子，該第二間隔件614延長封裝體608上側的長度而且被動裝置646安裝於該第二間隔件614之上。
參考第7圖，顯示於本發明第六具體實施例中之積體電路封裝件系統700沿著第1圖之直線2--2之截面圖。該截面圖顯示具有含有空腔710之封裝體708(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔710而暴露於之第一間隔件712之可安裝的積體電路系統706。第二間隔件714(例如疊置之基板)係安裝於封裝體708與空腔710之上。該第二間隔件714包含位於空腔710之上之縫隙(slot)740。該第二間隔件714與第一間隔件712相連接。電子組件716(例如封裝之積體電路裝置)安裝於第二間隔件714之上。
在此範例中該可安裝的積體電路系統706包含在基板702(例如疊置之基板)之上之積體電路封裝件718與被動裝置720。第一內部互連接722(例如焊接線或帶狀焊接線)， 係將積體電路封裝件718之第一間隔件712與基板702連接。封裝體708位於基板702之上用以覆蓋積體電路封裝件718、第一內部互連接722與第一被動裝置720。
積體電路封裝件718包含積體電路晶粒724。該積體電路晶粒724包括非主動側726及主動側728，其中，該主動側728包含製造於其上之主動電路。該非主動側726以黏著劑730(例如晶粒附著黏著劑)附著於第一間隔件712上。第二內部互連接734(例如焊接線或帶狀焊接線)能將該主動側728與第一間隔件712連接。外部互連接704可附接下方並到達基板702，用以連接下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
該第二間隔件714包含電性連接器732，例如焊錫球。舉例來說，該第二間隔件714係以電性連接器732而與第一間隔件712互相連接。底層填料(under fill)742包圍該電性連接器732四周，充滿空腔710，且也包圍該電子組件716之組件連接器744四周。該底層填料742也充滿該縫隙740。縫隙740可用於使該底層填料742流動。另外的被動裝置746安裝於該第二間隔件714之上。
參考第8圖，顯示於本發明第七具體實施例中之積體電路封裝件系統800沿著第1圖之直線2--2之截面圖。該截面圖顯示具有含有空腔810之封裝體808(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔810而暴露於外之第一間隔件812之可安裝的積體電路系統806。第二間隔件814(例如疊置之基板)係安裝於封裝體808與空腔810 之上。該第二間隔件814包含位於空腔810之上並沿著空腔810的側邊之縫隙840。該第二間隔件814與第一間隔件812相連接。電子組件816(例如覆晶)安裝於第二間隔件814之上。
在此範例中該可安裝的積體電路系統806包含在基板802(例如疊置之基板)上之積體電路封裝件818與被動裝置820。第一內部互連接822(例如焊接線或帶狀焊接線)，係將積體電路封裝件818上之第一間隔件812與基板802連接。封裝體808位於基板802之上用以覆蓋積體電路封裝件818、第一內部互連接822與第一被動裝置820。
積體電路封裝件818包含積體電路晶粒824。該積體電路晶粒824包含非主動側826及主動側828，其中，該主動側828包含製造於其上之主動電路。該非主動側826以黏著劑830(例如晶粒附著黏著劑)附著於第一間隔件812上。第二內部互連接834(例如焊接線或帶狀焊接線)能將該主動側828與第一間隔件812連接。外部互連接804可附接下方並到達基板802，用以連接下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
該第二間隔件814包含電性連接器832，例如焊錫球。舉例來說，該第二間隔件814係以電性連接器832而與第一間隔件812互相連接。底層填料842包圍該電性連接器832四周，充滿空腔810，且包圍該電子組件816之組件連接器844四周。該底層填料842包含低黏性材料以致於其無法作為封裝體使用，例如封裝體808。縫隙840可用於 使該底層填料842流動。另外的被動裝置846安裝於該第二間隔件814之上。
參考第9圖，顯示於本發明第八具體實施例中之積體電路封裝件系統900沿著第1圖之直線2--2之截面圖。該截面圖顯示具有含有空腔910之封裝體908(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔910而暴露於外之第一間隔件912之可安裝的積體電路系統906。第二間隔件914(例如疊置之基板)係安裝於封裝體908與空腔910之上。該第二間隔件914與第一間隔件912相連接。電子組件916(例如覆晶)安裝於第二間隔件914之上。
在此範例中該可安裝的積體電路系統906包含在基板902(例如疊置之基板)之上之積體電路封裝件918與被動裝置920。第一內部互連接922(例如焊接線或帶狀焊接線)，係將積體電路封裝件918之第一間隔件912與基板902連接。
積體電路封裝件918包括積體電路晶粒924。該積體電路晶粒924包括非主動側926及主動側928，其中，該主動側928包含製造於其上之主動電路。該非主動側926以黏著劑930(例如晶粒附著黏著劑)附著於載體952(例如疊置之基板)上。
該第一間隔件912，例如疊置之基板，安裝於積體電路封裝件918之上並以內部連接器948(例如焊錫球)而與積體電路封裝件918連接。另外的被動裝置946安裝於該第一間隔件912下方。
該第二間隔件914包含電性連接器932，例如焊錫球。舉例來說，該第二間隔件914係以電性連接器932而與第一間隔件912互相連接。該第二間隔件914能夠延長封裝體908之上側的長度。另外的被動裝置950安裝於該第二間隔件914之上。
封裝體908位於基板902之上用以覆蓋積體電路封裝件918、第一內部互連接922、被動裝置920、與另外的被動裝置946。外部互連接904可附接下方並到達基板902，用以連接下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
參考第10圖，顯示於本發明第九具體實施例中之積體電路封裝件系統1000沿著第1圖之直線2--2之截面圖。該截面圖顯示具有含有空腔1010之封裝體1008(例如包含環氧壓模化合物之覆蓋件)，與具有藉由空腔1010而暴露於外之第一間隔件1012之可安裝的積體電路系統1006。
該第二間隔件1014，例如疊置之基板，以黏著劑1030安裝於封裝體1008之上與空腔1010之上。第二間隔件1014包含縫隙1040於空腔1010之上。電子組件1016(例如封裝之積體電路裝置)安裝於第二間隔件1014之上。
在此範例中該可安裝的積體電路系統1006包含在基板1002(例如疊置之基板)之上之積體電路封裝件1018與被動裝置1020。第一內部互連接1022(例如焊接線或帶狀焊接線)，係將積體電路封裝件1018之第一間隔件1012與基板1002連接。第二內部互連接1034，穿過縫隙1040， 連接該第一間隔件1012與該第二間隔件1014之中央焊接墊。封裝體1008，例如包含環氧壓模化合物之覆蓋件，位於基板1002之上用以覆蓋積體電路封裝件1018、第一內部互連接1022與被動裝置1020。空腔覆蓋件1048，例如包含液態封膠(glob top)材料之覆蓋件，填滿縫隙1040且空腔1010覆蓋住第二內部互連接1034。
另外的第二被動裝置1046安裝於該第二間隔件1014上。外部互連接1004可附接下方並到達基板1002，用以連接下一個系統層次(無顯示)，例如印刷電路板或另一個積體電路封裝件系統。
參考第11圖，顯示於本發明之具體實施例中用於製造積體電路封裝件系統100之積體電路封裝件系統1100之流程圖。系統1100包含於方塊1102中提供具有含有空腔於其中之封裝體之可安裝的積體電路系統與藉由該空腔曝露於外之第一間隔件；於方塊1104中將第二間隔件安裝於該第一間隔件之上用以於其上僅堆疊分離裝置，而該第二間隔件位於該封裝體與該空腔之上；以及於方塊1106中將電子組件安裝於該第二間隔件之上。
本發明另一個重要的目的係對於降低成本、簡化系統與增加效能這些既定的發展趨勢提供有價值的支援和服務。
依據本發明這些有價值的態樣可將目前技術狀態向前推進至少一個等級。
因此，可以發現本發明之積體電路封裝件系統提供重 要且迄今尚未了解與不可獲得之解決方案、功能與實用態樣，用以改善產量、增加可靠度以及降低電路系統成本。最後獲得的程序與結構係簡單明顯、高成本效益、不複雜、多功能、準確、靈敏與有效，且可藉由應用已知的元件來具體實施用以提供完備的、有效率的且經濟的製程以及各方面的應用與利用。
雖然本發明已搭配具體最佳模式來作說明，但是此領域具有通常技術之人依據上述說明可明白了解本發明可作各種替代、修正與變化。因此將包括所有落入本發明之申請專利範圍內之替代、修正與變化。以上說明之本文之內容或顯示於附加圖示者應理解係作為本發明之解釋而並不限制本發明之範圍。
100、300、400、500、600、700、800、900、1000、1100‧‧‧積體電路封裝件系統
102、302、402、502、602、702、802、902、1002‧‧‧基板
104、304、404、504、604、704、804、904、1004‧‧‧外部 互連接
206、306、406、506、606、706、806、906、1006‧‧‧可安裝的積體電路系統
208、308、408、508、608、708、808、908、1008‧‧‧封裝體
210、310、410、510、610、710、810、910、1010‧‧‧空腔
212、312、412、512、612、712、812、912、1012‧‧‧第一間隔件
214、314、414、514、614、714、814、914、1014‧‧‧第二間隔件
216、716‧‧‧電子組件(分離裝置)
218、318、418、618、718、818、918、1018‧‧‧積體電路封裝件
220、320、420、520‧‧‧被動裝置
222、322、422、522、622、722、822、922、1022‧‧‧第一內部互連接
224、424、524、624、724、824、924‧‧‧積體電路晶粒
226、426、626、726、826、926‧‧‧非主動側
228、428、628、728、828、928‧‧‧主動側
230、330、430、630、730、830、930、1030‧‧‧黏著劑
232、332、432、532、632、732、832、932‧‧‧電性連接器
316、416、516、816、616、916、1016‧‧‧電子組件
434、534、634、734、834、1034‧‧‧第二內部互連接
436、536‧‧‧內在封裝體
439、539‧‧‧第二黏著劑
518‧‧‧第一積體電路封裝件
526‧‧‧第一非主動側
528‧‧‧第一主動側
530‧‧‧第一黏著劑
538‧‧‧第二積體電路封裝件
540‧‧‧第二積體電路晶粒
542‧‧‧第二非主動側
544‧‧‧第二主動側
546‧‧‧第三黏著劑
548‧‧‧第三內部互連接
620、720、820、920、1020‧‧‧第一被動裝置
646、746、846、946、1046‧‧‧第二被動裝置
740、840、1040‧‧‧縫隙
742、842‧‧‧底層填料
744、844‧‧‧組件連接器
948‧‧‧內部互連接
950‧‧‧第三被動裝置
952‧‧‧載體
1048‧‧‧空腔覆蓋件
1102、1104、1106‧‧‧流程方塊
第1圖為本發明之積體電路封裝件系統於第一具體實施例中之下視圖；第2圖為第1圖之積體電路封裝件系統沿著直線2--2之截面圖；第3圖為本發明之積體電路封裝件系統於第二具體實施例中以第1圖之下視圖為範例沿著第1圖之直線2--2之截面圖；第4圖為本發明之積體電路封裝件系統於第三具體實施例中以第1圖之下視圖為範例沿著第1圖之直線2--2之截面圖；第5圖為本發明之積體電路封裝件系統於第四具體實 施例中以第1圖之下視圖為範例沿著第1圖之直線2--2之截面圖；第6圖為本發明之積體電路封裝件系統於第五具體實施例中以第1圖之下視圖為範例沿著第1圖之直線2--2之截面圖；第7圖為本發明之積體電路封裝件系統於第六具體實施例中以第1圖之下視圖為範例沿著第1圖直線2--2之截面圖；第8圖為本發明之積體電路封裝件系統於第七具體實施例中以第1圖之下視圖為範例沿著第1圖直線2--2之截面圖；第9圖為本發明之積體電路封裝件系統於第八具體實施例中以第1圖之下視圖為範例沿著第1圖直線2--2之截面圖；第10圖為本發明之積體電路封裝件系統於第九具體實施例中以第1圖之下視圖為範例沿著第1圖直線2--2之截面圖；以及第11圖為本發明之積體電路封裝件系統於一具體實施例中製造該積體電路封裝件之流程圖。
100‧‧‧積體電路封裝件系統
102‧‧‧基板
104‧‧‧外部互連接
206‧‧‧可安裝之積體電路系統
208‧‧‧封裝體
210‧‧‧空腔
212‧‧‧第一間隔件
214‧‧‧第二間隔件
216‧‧‧電子組件
218‧‧‧積體電路封裝件
220‧‧‧被動裝置
222‧‧‧第一內部互連接
224‧‧‧積體電路晶粒
226‧‧‧非主動側
228‧‧‧主動側
230‧‧‧黏著劑
232‧‧‧電性連接器

Claims (10)

  1. 一種積體電路封裝方法(1100)，包括下列步驟：提供具有含有空腔(210)於其中之封裝體(208)與具有藉由該空腔(210)而曝露於外之第一間隔件(212)之可安裝的積體電路系統(206)，該空腔具有空腔寬度；將第二間隔件(214)安裝於該第一間隔件(212)及該封裝體之上，且該第二間隔件具有大於該空腔寬度之間隔件寬度；以及藉由電性連接器將電子組件(216)安裝於該第二間隔件(214)之上，且該電子組件具有大於該空腔寬度之電子組件寬度，其中，該電子組件及該電性連接器易於自該第二間隔件拆卸用於功能測試。
  2. 如申請專利範圍第1項之積體電路封裝方法(1100)，進一步包括以黏著劑(1030)將該第二間隔件(1014)安裝於該封裝體(1008)與該空腔(1010)上。
  3. 如申請專利範圍第1項之積體電路封裝方法(1100)，其中，安裝該第二間隔件(714)之步驟包含在該空腔(710)上安裝具有孔洞(hole)(740)之該第二間隔件(714)。
  4. 如申請專利範圍第1項之積體電路封裝方法(1100)，進一步包括施加底層填料(742)穿過該第二間隔件(714)之該孔洞(740)。
  5. 如申請專利範圍第1項之積體電路封裝方法(1100)，其中，將該第二間隔件(214)安裝於該第一間隔件(212)之上之步驟包含：將該第二間隔件(214)與該第一間隔件 (212)互相連接。
  6. 一種積體電路封裝件系統(100)，包括：可安裝的積體電路系統(206)，係具有包含空腔(210)之封裝體(208)與藉由該空腔(210)而暴露於外之第一間隔件(212)，該空腔具有空腔寬度；第二間隔件(214)，係位於該第一間隔件(212)及該封裝體之上，且該第二間隔件具有大於該空腔寬度之間隔件寬度；以及電子組件(216)，係藉由電性連接器而位於該第二間隔件(214)之上，且該電子組件具有大於該空腔寬度之電子組件寬度，其中，該電子組件及該電性連接器易於自該第二間隔件拆卸用於功能測試。
  7. 如申請專利範圍第6項之積體電路封裝件系統(1000)，進一步包括位於該第二間隔件(1014)與該第一間隔件(1012)之間的黏著劑(1030)。
  8. 如申請專利範圍第6項之積體電路封裝件系統(700)，其中，該第二間隔件(714)包含位於該空腔(710)之上之孔洞(740)。
  9. 如申請專利範圍第6項之積體電路封裝件系統(700)，進一步包括位於該第二間隔件(714)之孔洞(740)中的底層填料(742)。
  10. 如申請專利範圍第6項之積體電路封裝件系統(100)，其中，該第二間隔件(214)係與該第一間隔件(212)相互連接。
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