TWI429054B - 具有偏置堆疊之積體電路封裝系統 - Google Patents

具有偏置堆疊之積體電路封裝系統 Download PDF

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Publication number
TWI429054B
TWI429054B TW096121103A TW96121103A TWI429054B TW I429054 B TWI429054 B TW I429054B TW 096121103 A TW096121103 A TW 096121103A TW 96121103 A TW96121103 A TW 96121103A TW I429054 B TWI429054 B TW I429054B
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Taiwan
Prior art keywords
integrated circuit
circuit device
carrier
internal
interconnect
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TW096121103A
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English (en)
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TW200807679A (en
Inventor
Jong Wook Ju
Taeg Ki Lim
Hyun Joung Kim
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Stats Chippac Ltd
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Publication of TW200807679A publication Critical patent/TW200807679A/zh
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Publication of TWI429054B publication Critical patent/TWI429054B/zh

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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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Description

具有偏置堆疊之積體電路封裝系統 交叉引用相關申請案
本申請案係主張2006年6月12日所提出申請之美國暫時專利申請案第60/804,545號之優先權。
本發明係大致有關積體電路封裝系統，且尤係有關具有多個積體電路之積體電路封裝系統。
電子設備需求更多的積體電路於積體電路封裝件中，然而卻矛盾地在系統中提供更少的實體空間給增加之積體電路內容。某些技術主要專注於將更多功能整合至各積體電路中。其它技術專注在將這些積體電路堆疊至單一封裝件中。雖然這些方式於積體電路內提供更多的功能，然其不能完全滿足對低高度、小空間、及成本降低之需求。
現代的電子設備(例如，智慧型手機、個人數位助理、行動定位服務(location based service)、伺服器、以及儲存陣列)期望降低成本而將更多的積體電路裝入比以往更小的實體空間中。許多技術已被研發來迎合這些需求。某些研發策略專注於新的封裝技術，而其它研發策略則專注於改進現行的封裝技術。現行封裝技術中的研發可採取相當多的不同方向。
一個已被證實用來降低成本的方法係使用現行製造方法與設備的封裝技術。矛盾的是現行的製程之重複利用一般不會產生封裝件尺寸的減小。現行的封裝技術對成本效益不斷努力以符合今日之積體電路與封裝件從未有之整合需求。
許多封裝方法係堆疊多個積體電路晶粒或封裝件中封裝件(package in package,PIP)或其組合。該等電性連接至各該堆疊式積體電路一般需要如矽或中介層(interposer)之間隔物(spacer)所形成之空間。目前的間隔物需要額外的步驟及結構，因而增加製造成本，並且降低製造良率。這些間隔物也限制了高度減小量。
除了該等間隔物，堆疊式積體電路晶粒或堆疊式封裝積體電路通常遭受接合線(bond wire)之疏忽性的短路。輸入/輸出(I/O)密度與封裝件剖面(profile)需求條件驅使該等接合墊與該等接合線越來越接近。當諸接合線越接近時，該等接合線在模壓製程(molding process)期間變得更容易受到引線迴圈(wire loop)偏移的影響，而造成疏忽性的短路。
因此，仍存在著對積體電路封裝系統提供低成本製造、增進良率、以及增進可靠度的需要。有鑑於對節省成本與增進效益之日益增長的需求，找出這些問題的解答也就越來越重要。
這些問題之解決方案長期以來一直被尋求，但先前之研究成果尚未教示或暗示任何解決方案，這些問題之解決方案已長期困惑熟習該技術領域。
本發明提供一種積體電路封裝系統，包括安裝第一積體電路裝置於載體之上；以偏置組構方式安裝具有黏著間隔物(adhesive spacer)之第二積體電路裝置於該第一積體電路裝置之上；連接第一內部互連件(internal interconnect)於該載體與該第一積體電路裝置之間，該第一內部互連件在該黏著間隔物內；連接第二內部互連件於該載體與該第二積體電路裝置之間；以及包覆該第一積體電路裝置、該第二積體電路裝置、該第一內部互連件及該第二內部互連件。
本發明之特定實施例除了或替代以上提及之這些實施例外，還具有其它態樣。該等態樣於參考附加圖式時，配合閱讀以下詳細說明對熟習此技術領域者而言將變得顯而易見。
以下的說明係以足夠詳細的說明來描述以使在此技術領域具有通常知識者能夠作出本發明並且使用本發明。應該瞭解，其它實施例根據本發明係明顯的，且在不脫離本發明之範疇下可作出系統、製程、或機械性改變。
在以下的說明中，給定多個特定細節以提供本發明之徹底瞭解。然而，本發明可在沒有這些特定細節下實作係顯而易見的。為了避免模糊本發明，一些已知的電路、系統組構、以及製程步驟均不詳細揭露。同樣地，顯示該系統之實施例的該等圖式均是部分圖解(semi－diagrammatic)且不按比例的，特別是，一些尺寸係為了本發明之清晰而於圖式中以極為誇大方式來顯示。
此外，多個實施例被揭露且描述成共同具有一些特徵，為了說明、描述、及其理解之清晰及容易起見，彼此類似或相似的特徵通常將以相似的元件符號來描述。為求描述方便，該等實施例已被編號為第一實施例、第二實施例等，而不是欲有任何其它重要性或對本發明提供限制。
為了說明的目的，如用於本文之用辭“水平(horizontal)”係定義為平行於該積體電路之平面或表面而無關其方向之平面。用辭“垂直(vertical)”係指垂直於方才所定義之水平的方向。用辭“在…上方(above)”，“在…下面(below)”，“底部(bottom)”，“頂部(top)”，“側邊(side)”(如“側壁(sidewall)”中)，“較高”，“較低”，“上面(upper)”，“在…之上(over)”，“在…之下(under)”均相對於該水平面來定義。用辭“在…上(on)”意涵元件間有直接接觸。如用於本文之用辭“製程(processing)”包括材料之沈積、圖案化、曝光、顯影(development)、蝕刻、清洗、模壓(molding)、及/或移除該材料或如需要形成所述之結構。如本文所用之用辭“系統”係根據該用辭用於上下文中而意涵且稱為本發明之方法及裝置。
茲參考第1圖，其中係顯示本發明之第一實施例中之積體電路封裝系統100之平面圖。該平面圖繪示沒有覆蓋物之該積體電路封裝系統100。該積體電路封裝系統100較佳具有第一積體電路裝置104(例如積體電路晶粒)於如層疊式基板(laminate substrate)之載體106之上。第二積體電路裝置108(例如積體電路晶粒)係以偏置組構在該第一積體電路裝置104之上較佳。該偏置組構較佳地具有暴露該第一積體電路裝置104之第一側邊110之該第二積體電路裝置108。
第一內部互連件118(例如接合線(bond wire)或帶式接合線)較佳連接該第一積體電路裝置104與該載體106。該等第一內部互連件118連接至相鄰於該第一側邊110之該第一積體電路裝置104之暴露部分。該等第一內部互連件118也連接至在該第二積體電路裝置108之下之該第一積體電路裝置104之部分。
第二內部互連件120(例如接合線或帶式接合線)較佳連接該第二積體電路裝置108與該載體106。該等第二內部互連件120可相鄰於或在該等第一內部互連件118之間或可在該等第一內部互連件118之上，而不會與該等第一內部互連件118造成疏忽性的短路。
為了說明的目的，雖然第一積體電路裝置104與該第二積體電路裝置108可以是不同大小係可理解的，但該第一積體電路裝置104與該第二積體電路裝置108係顯示為大體上相同大小。同樣為了說明之目的，該積體電路封裝系統100係顯示具有作為層疊式基板之載體106，然而該載體106可以是不同之類型係可理解的。例如，該載體106可自具有引線(lead)(圖中未顯示)之導線架(lead frame)(圖中未顯示)及晶粒接附焊盤(die－attach paddle)(圖中未顯示)來形成。
現參考第2圖，其中係顯示沿著第1圖之線2－2之該積體電路封裝系統100之剖面圖。該剖面圖繪示用黏著劑206(例如晶粒黏著劑)接附在該載體106之上之第一積體電路裝置104(其具有第一非主動面202與第一主動面204)。該第一非主動面202面對該載體106。該第一主動面204包括製造於其上之主動電路且面向遠離該載體106之面。該等第一內部互連件118連接該第一主動面204與該載體106。
該第二積體電路裝置108具有第二非主動面208與第二主動面210，其中，該第二主動面210具有製造於其上之主動電路。黏著間隔物212(例如膜狀間隔物、厚膜、或厚膏黏著劑)包覆第二非主動面208。具有該黏接間隔物212之該第二積體電路裝置108以偏置組構方式安裝在該第一積體電路裝置104之上，使得該第一積體電路裝置104之一部分沿著該第一側邊110而暴露。該第二積體電路裝置108沒有阻礙該等第一內部互連件118與相鄰於該第一側邊110之該第一積體電路裝置104間之連接。
該黏著間隔物212安裝在該第一積體電路裝置104除了該第一側邊110之側邊之上。該黏著間隔物212提供許多功能。例如，該黏著間隔物212可作用為該第一積體電路裝置104與該第二積體電路裝置108間之黏著劑。再舉另一個例子，該黏著間隔物212也可作用為該第一積體電路裝置104與該第二積體電路裝置108間之間隔物，而不會以不被該第二積體電路裝置108所暴露之該第一積體電路裝置104之部分妨礙或擾亂該等第一內部互連件118的連接。在該第二積體電路裝置108之下之該等第一內部互連件118在該黏著間隔物212內較佳。
該等第二內部互連件120接附該第二積體電路裝置108與該載體106。該黏著間隔物212亦提供該等第一內部互連件118與該等第二內部互連件120間之額外的距離，使得該等第二內部互連件120可在該等第一內部互連件118之上建立迴路而不會有疏忽性的短路。
封裝件包覆物(package encapsulation)214(例如環氧封壓化合物(epoxy molding compound)覆蓋在該載體106之上之該第一積體電路裝置104、該第二積體電路裝置108、該等第一內部互連件118、以及該等第二內部互連件120。外部互連件216(例如銲球(solder ball))接附在該載體106之下。
現參考第3圖，其中係顯示本發明之第二實施例中之積體電路封裝系統300之平面圖。該平面圖繪示沒有覆蓋物(例如第2圖之封裝件包覆物214)之積體電路封裝系統300。該積體電路封裝系統300較佳具有第一積體電路裝置304(例如積體電路晶粒)於例如層疊式基板之載體306上方。第二積體電路裝置308(例如積體電路晶粒)以偏置組構方式在該第一積體電路裝置304之上較佳。
該偏置組構較佳具有暴露該第一積體電路裝置304之第一側邊310之一部分、第二側邊312之一部分、第三側邊314、以及第四側邊316之第二積體電路裝置308。該第一側邊310與該第二側邊312彼此係相鄰邊。該第一側邊310與該第三側邊314彼此間係相對邊。
第一內部互連件318(例如接合線或帶式接合線)較佳連接該第一積體電路裝置304與該載體306。該等第一內部互連件318連接至相鄰於該第三側邊314與該第四側邊316之該第一積體電路裝置304之暴露部分。該等第一內部互連件318也連接至相鄰於兩者都在該第二積體電路裝置308之下之該第一側邊310與該第二側邊312之該第一積體電路裝置304之部分。第2圖之黏著間隔物212同樣在該第一積體電路裝置304與該第二積體電路裝置308間較佳，而提供與第2圖之該積體電路封裝系統100所描述之大體上相同之功能。
第二內部互連件320(例如接合線或帶式接合線)較佳連接該第二積體電路裝置308與該載體306。該等第二內部互連件320可相鄰於或在該等第一內部互連件318之間，或可在該等第一內部互連件318之上，而不會與該等第一內部互連件318造成疏忽性短路。
為了說明之目的，雖然該第一積體電路裝置304與第二積體電路裝置308可以是不同之大小係可理解的，但該第一積體電路裝置304與第二積體電路裝置308係顯示為大體上幾乎相同之大小。同樣為了說明之目的，該積體電路封裝系統300係顯示具有作為層疊式基板之載體306，然而該載體306可以是不同之類型係可理解的。例如，該載體306可自具有引線(圖中未顯示)之導線架(圖中未顯示)及晶粒接附焊盤(圖中未顯示)來形成。
現參考第4圖，其中係顯示本發明之第三實施例中之積體電路封裝系統400之平面圖。該平面圖繪示沒有覆蓋物(例如第2圖之封裝件包覆物214)之積體電路封裝系統400。該積體電路封裝系統400較佳具有第一積體電路裝置404(例如積體電路晶粒)於例如層疊式基板之載體406之上。第二積體電路裝置408(例如積體電路晶粒)以偏置組構方式在該第一積體電路裝置404之上較佳。
該偏置組構較佳具有暴露該第一積體電路裝置404之第一側邊410之部分、第二側邊412之部分、第三側邊414、以及第四側邊416之第二積體電路裝置408。該第一側邊410與該第二側邊412彼此係相鄰邊。該第一側邊410與該第三側邊414彼此間係相對邊。
第一內部互連件418(例如接合線或帶式接合線)較佳連接該第一積體電路裝置404與該載體406。該等第一內部互連件418連接至相鄰於該第一側邊410與該第二側邊412之該第一積體電路裝置404之暴露部分。該等第一內部互連件418也連接至相鄰於兩者都在該第二積體電路裝置408之下之該第三側邊414與該第四側邊416之該第一積體電路裝置404之部分。第2圖之黏著間隔物212同樣在該第一積體電路裝置404與該第二積體電路裝置408間較佳，而提供與第2圖之該積體電路封裝系統100所描述之大體上相同之功能。
第二內部互連件420(例如接合線或帶式接合線)較佳連接該第二積體電路裝置408與該載體406。該等第二內部互連件420可相鄰於或在該等第一內部互連件418之間，或可在該等第一內部互連件418之上，而不會與該等第一內部互連件418造成疏忽性短路。
為了說明之目的，雖然該第一積體電路裝置404與第二積體電路裝置408可以是不同之大小係可理解的，但該第一積體電路裝置404與第二積體電路裝置408係顯示為大體上幾乎相同之大小。同樣為了說明之目的，該積體電路封裝系統400係顯示具有作為層疊式基板之載體406，然而該載體406可以是不同之類型係可理解的。例如，該載體406可自具有引線(圖中未顯示)之導線架(圖中未顯示)及晶粒接附焊盤(圖中未顯示)來形成。
現參考第5圖，其中係顯示本發明之第四實施例中之積體電路封裝系統500之平面圖。該平面圖繪示沒有覆蓋物之積體電路封裝系統500。該積體電路封裝系統500較佳具有第一積體電路裝置502(例如積體電路晶粒)於例如層疊式基板之載體504之上。第二積體電路裝置506(例如積體電路晶粒)以偏置組構方式在該第一積體電路裝置502之上較佳。該偏置組構較佳具有暴露該第一積體電路裝置502之第一側邊508與第二側邊510之部分之該第二積體電路裝置506。
第一內部互連件516(例如接合線或帶式接合線)較佳連接該第一積體電路裝置502之第一端部518(例如端部墊或連接點(connection site))以及該載體504之接觸墊(contact pad)520。該等第一內部互連件516較佳連接至相鄰於該第一側邊508與該第二側邊510之該第一積體電路裝置502。該等第一內部互連件516也連接至在該第二積體電路裝置506之下之該第一積體電路裝置502之部分。
第二內部互連件522(例如接合線或帶式接合線)較佳連接該第二積體電路裝置506之第二端部524(例如端部墊或連接點)以及該接觸墊520。該等第二內部互連件522可相鄰於或在該等第一內部互連件516之間，或可在該等第一內部互連件516之上，而不會與該等第一內部互連件516造成疏忽性的短路。
為了說明之目的，有限數目的第一內部互連件516顯示於該第一積體電路裝置502與該載體504間，然而應可理解該等第一積體電路裝置502與該載體504間之第一內部互連件516之數目可以視適用情況而定出預定數目。同樣為了說明之目的，有限數目的第二內部互連件522顯示於該第二積體電路裝置506與該載體504間，然而應可理解該第二積體電路裝置506與該載體504間之第二內部互連件522數目可以視適用情況而定出預定數目。
現參考第6圖，其中係顯示沿著第5圖之線6－6之該積體封裝系統500之剖面圖。該剖面圖繪示該積體電路封裝系統500為具有該第一積體電路裝置502以及該第二積體電路裝置506的積體之封裝中封裝件(package－in－package)之系統。
該第一積體電路裝置502包括第一包覆物602(例如環氧模壓化合物)以及第一基板604。該第一積體電路裝置502安裝在該載體504之上且該第一包覆物602面向該載體504。該等第一內部互連件516較佳地連接該第一基板604之第一端部518與該等接觸墊520。
該第二積體電路裝置506包括第二包覆物606(例如環氧模壓化合物)以及第二基板608。黏著間隔物610(例如膜狀間隔物、厚膜、或厚膏黏著劑)覆蓋該第二包覆物606之水平部分。具有該黏著間隔物610之該第二積體電路裝置506安裝在該第一積體電路裝置502之上，以致該第二積體電路裝置506不會阻礙該等第一內部互連件516與該第一積體電路裝置502間的連接關係。該黏著間隔物610安裝在該第一基板604之上。
該黏著間隔物610提供許多功能。例如，該黏著間隔物610可作用為該第一積體電路裝置502與該第二積體電路裝置506間之黏著劑。再舉另一例子，該黏著間隔物610也作用為該第一積體電路裝置502與該第二積體電路裝置506間之間隔物，而不會阻礙或干擾該等第一內部互連件516與該第一基板604之第一端部之連接關係。在該第二積體電路裝置506之下之該等第一內部互連件516較佳地係在該黏著間隔物610內。
該第二內部互連件522接附該第二基板608和該載體504。該黏著間隔物610也提供該等第一內部互連件516與該第二內部互連件522間之額外的距離，使得該等第二內部互連件522可在該等第一內部互連件516之上建立迴路，而不會有疏忽性的短路。
封裝件包覆物612(例如環氧模壓化合物)覆蓋在該載體504之上之該第一積體電路裝置502、該第二積體電路裝置506、該等第一內部互連件516、以及該等第二內部互連件522。外部互連件614(例如銲球)接附在該載體504之下。
該第一積體電路裝置502進一步較佳地包括安裝在第一基板604之下之第一積體電路晶粒616。該第一積體電路裝置502亦較佳地包括以暴露該第一積體電路晶粒616之第一接合墊620(例如連接點)之偏置組構方式而安裝於該第一積體電路晶粒616下方之第二積體電路晶粒618。第一內部互連件622(例如接合線或帶式接合線)較佳地連接該等第一接合墊620與該第一基板604。第二內部互連件624(例如接合線或帶式接合線)較佳地連接該第二積體電路晶粒618之該第一基板604與第二接合墊626(例如連接點)。該第一包覆物602覆蓋在該第一基板604之下之該第一積體電路616、該第二積體電路晶粒618、該等第一內部互連件622、以及該等第二內部互連件624。
該第二積體電路裝置506係顯示較佳地具有大體上相同之結構。為了說明之目的，該第一積體電路裝置502與該第二積體電路裝置506均以偏置組構方式而顯示具有堆疊式之積體電路，然而應可理解該第一積體電路裝置502與該第二積體電路裝置506可以是其它類型之積體電路裝置。例如，該第一積體電路裝置502與該第二積體電路裝置506可不具有堆疊式積體電路。再舉另一例子，該第一積體電路裝置502與該第二積體電路裝置506可具有不同類型之積體電路，例如大小、半導體技術、或功能。
現參考第7圖，其中係顯示本發明之第五實施例中之積體電路封裝系統700之平面圖。該平面圖繪示沒有覆蓋物之積體電路封裝系統700。該積體電路封裝系統700較佳地具有第一積體電路裝置702(例如封裝式積體電路)於例如層疊式基板之載體704之上。第二積體電路裝置706(例如封裝式積體電路)以偏置組構方式在該第一積體電路裝置702之上較佳。
該偏置組構較佳地具有暴露該第一積體電路裝置702之第一側邊708與第二側邊710之一部分以及第四側邊714之一部分的該第二積體電路裝置706。該第一積體電路裝置702之第三側邊712係在該第二積體電路裝置706之下。
第一內部互連件716(例如接合線或帶式接合線)較佳地連接該第一積體電路裝置702之第一端部718(例如端部墊或連接點)以及該載體704之接觸墊720。該等第一內部互連件716較佳地連接至相鄰於該第一側邊708、該第二側邊710、該第三側邊712、以及該第四側邊714之該第一積體電路裝置702。
第二內部互連件722(例如接合線或帶式接合線)較佳地連接該第二積體電路裝置706之第二端部724(例如端部墊或連接點)以及該接觸墊720。該等第二內部互連件722可相鄰於或在該等第一內部互連件716之間，或可在該等第一內部互連件716之上，而不會與該等第一內部互連件716造成疏忽性的短路。
為了說明之目的，有限數目的該等第一內部互連件716顯示於該第一積體電路裝置702與該載體704間，然而應可理解該第一積體電路裝置702與該載體704間之該等第一內部互連件716之數目可以視適用情況而定出預定數目。同樣為了說明之目的，有限數目的該等第二內部互連件722顯示於該第二積體電路裝置706與該載體704間，然而應可理解該第二積體電路裝置706與該載體704間之該等第二內部互連件722數可以視適用情況而定出預定數目。
現參考第8圖，其中係顯示沿著第7圖之線8－8之該積體封裝系統700之剖面圖。該剖面圖繪示該積體電路封裝系統700為具有該第一積體電路裝置702以及該第二積體電路裝置706的積體之封裝中封裝件之系統。
該第一積體電路裝置702包括第一包覆物802(例如環氧模壓化合物)以及第一基板804。該第一積體電路裝置702安裝在該載體704之上且該第一包覆物802面向該載體704。該等第一內部互連件716較佳地沿著該第二側邊710與該第四側邊714連接該第一基板804之該等接觸墊720與該等第一端部718。
該第二積體電路裝置706包括第二包覆物806(例如環氧模壓化合物)以及第二基板808。黏著間隔物810(例如膜狀間隔物、厚膜、或厚膏黏著劑)覆蓋該第二包覆物806之水平部分。具有該黏著間隔物810之該第二積體電路裝置706安裝在該第一積體電路裝置702之上，以致該第二積體電路裝置706不會阻礙該等第一內部互連件716與該第一積體電路裝置702間的連接關係。該黏著間隔物810安裝在該第一基板804之上。
該黏著間隔物810提供許多功能。例如，該黏著間隔物810可作用為該第一積體電路裝置702與該第二積體電路裝置706間之黏著劑。再舉另一例子，該黏著間隔物810也作用為該第一積體電路裝置702與該第二積體電路裝置706間之間隔物，而不會阻礙或干擾該等第一內部互連件716與該第一基板804之第一端部之連接關係。在該第二積體電路裝置706之下之該等第一內部互連件716較佳地係在該黏著間隔物810內。
該等第二內部互連件722接附該第二基板808和該載體704。該黏著間隔物810也提供該等第一內部互連件716與該等第二內部互連件722間之額外的距離，使得該等第二內部互連件722可在該等第一內部互連件716之上建立迴路，而不會有疏忽性的短路。
封裝件包覆物812(例如環氧模壓化合物)覆蓋在該載體704之上之該第一積體電路裝置702、該第二積體電路裝置706、該等第一內部互連件716、以及該等第二內部互連件722。外部互連件814(例如銲球)接附在該載體704之下。
該第一積體電路裝置702進一步較佳地包括安裝在第一基板804之下之第一積體電路晶粒816。該第一積體電路裝置702亦較佳地包括安裝在暴露該第一積體電路晶粒816之第一接合墊820(例如連接點)之該第一積體電路晶粒816下方之第二積體電路晶粒818。第一內部互連件822(例如接合線或帶式接合線)較佳地連接該等第一接合墊820與該第一基板804。第二內部互連件824(例如接合線或帶式接合線)較佳地連接該第一基板804與該第二積體電路晶粒818之第二接合墊826(例如連接點)。該第一包覆物802覆蓋在該第一基板804之下之該第一積體電路晶粒816、該第二積體電路晶粒818、該等第一內部互連件822、以及該等第二內部互連件824。
該第二積體電路裝置706係顯示較佳地具有大體上相同之結構。為了說明之目的，該第一積體電路裝置702與該第二積體電路裝置706均顯示其具有堆疊式積體電路，然而應可理解該第一積體電路裝置702與該第二積體電路裝置706可以是其它類型之積體電路裝置。例如，該第一積體電路裝置702與該第二積體電路裝置706可不具有堆疊式積體電路。再舉另一例子，該第一積體電路裝置702與該第二積體電路裝置706可具有不同類型之積體電路，例如大小、半導體技術、或功能。
現參考第9圖，其中係顯示本發明之第六實施例中之積體電路封裝系統900之平面圖。該平面圖繪示沒有覆蓋物之積體電路封裝系統900。該積體電路封裝系統900較佳地具有第一積體電路裝置902(例如封裝式積體電路)於例如層疊式基板之載體904之上。第二積體電路裝置906(例如封裝式積體電路)以偏置組構方式在該第一積體電路裝置902之上較佳。該偏置組構較佳地具有暴露該第一積體電路裝置902之第一側邊908之一部分、第二側邊910、第三側邊912、以及第四側邊914之一部分的第二積體電路裝置906。
第一內部互連件916(例如接合線或帶式接合線)較佳地連接該第一積體電路裝置902之第一端部918(例如終端墊或連接點)以及該載體904之接觸墊920。該等第一內部互連件916較佳地連接至相鄰於該第一側邊908、該第二側邊910、該第三側邊912、以及該第四側邊914之該第一積體電路裝置902。
第二內部互連件922(例如接合線或帶式接合線)較佳地連接該第二積體電路裝置906之第二端部924(例如端部墊或連接點)以及該接觸墊920。該等第二內部互連件922可相鄰於或在該等第一內部互連件916之間，或可在該等第一內部互連件916之上，而不會與該等第一內部互連件916造成疏忽性的短路。
為了說明之目的，有限數目的該等第一內部互連件916顯示於該第一積體電路裝置902與該載體904間，然而應可理解該第一積體電路裝置902與該載體904間之該等第一內部互連件916之數目可以視適用情況而定出預定數目。同樣為了說明之目的，有限數目的該等第二內部互連件922顯示於該第二積體電路裝置906與該載體904間，然而應可理解該第二積體電路裝置906與該載體904間之第二內部互連件922之數目可以視適用情況而定出預定數目。
現參考第10圖，其中係顯示沿著第9圖之線10－10之該積體封裝系統900之剖面圖。該剖面圖繪示該積體電路封裝系統900為具有該第一積體電路裝置902以及該第二積體電路裝置906的積體之封裝中封裝件之系統。
該第一積體電路裝置902包括第一包覆物1002(例如環氧模壓化合物)以及第一基板1004。該第一積體電路裝置902安裝在該載體904之上且該第一包覆物1002面向該載體904。該等第一內部互連件916較佳地沿著該第二側邊910與該第四側邊914連接該第一基板1004之第一端部918與該接觸墊920。
該第二積體電路裝置906包括第二包覆物1006(例如環氧模壓化合物)以及第二基板1008。黏著間隔物1010(例如膜狀間隔物、厚膜、或厚膏黏著劑)覆蓋該第二包覆物1006之水平部分。具有該黏著間隔物1010之該第二積體電路裝置906以偏置組構方式安裝在該第一積體電路裝置902之上，以致該黏著間隔物1010和該第二積體電路裝置906沿著該第二側邊910暴露該等第一端部918。該黏著間隔物1010安裝在該第一基板1004之上。
該黏著間隔物1010提供許多功能。例如，該黏著間隔物1010可作用為該第一積體電路裝置902與該第二積體電路裝置906間之黏著劑。再舉另一例子，該黏著間隔物1010也作用為該第一積體電路裝置902與該第二積體電路裝置906間之間隔物，而不會阻礙或干擾該等第一內部互連件916與該第一基板1004之第一端部之連接關係。在該第二積體電路裝置906之下之該等第一內部互連件916較佳地係在該黏著間隔物1010內。
該第二內部互連件922接附該第二基板1008和該載體904。該黏著間隔物1010也提供該等第一內部互連件916與該等第二內部互連件922間之額外的距離，使得該第二內部互連件922可在該第一內部互連件916之上建立迴路，而不會有疏忽性的短路。
封裝件包覆物1012(例如環氧模壓化合物)覆蓋在該載體904之上之該第一積體電路裝置902、該第二積體電路裝置906、該等第一內部互連件916、以及該等第二內部互連件922。外部互連件1014(例如銲球)接附在該載體904之下。
該第一積體電路裝置902進一步較佳地包括安裝在第一基板1004之下之第一積體電路晶粒1016。該第一積體電路裝置902亦較佳地包括安裝在暴露該第一積體電路晶粒1016之第一接合墊1020(例如連接點)之該第一積體電路晶粒1016下方之第二積體電路晶粒1018。第一內部互連件1022(例如接合線或帶式接合線)較佳地連接該等第一接合墊1020與該第一基板1004。第二內部互連件1024(例如接合線或帶式接合線)較佳地連接該第一基板1004與該第二積體電路晶粒1018之第二接合墊1026(例如連接點)。該第一包覆物1002覆蓋在該第一基板1004之下之該第一積體電路晶粒1016、該第二積體電路晶粒1018、該等第一內部互連件1022、以及該等第二內部互連件1024。
該第二積體電路裝置906係顯示較佳地具有大體上相同之結構。為了說明之目的，該第一積體電路裝置902與該第二積體電路裝置906均顯示其具有堆疊式積體電路，然而應可理解該第一積體電路裝置902與該第二積體電路裝置906可以是其它類型之積體電路裝置。例如，該第一積體電路裝置902與該第二積體電路裝置906可不具有堆疊式積體電路。再舉另一例子，該第一積體電路裝置902與該第二積體電路裝置906可具有不同類型之積體電路，例如大小、半導體技術、或功能。
現參考第11圖，其中係顯示於本發明之實施例中，用於製造積體電路封裝系統100之積體電路封裝系統1100之流程圖。於方塊1102中，該系統1100包括安裝第一積體電路裝置在載體之上；於方塊1104中，以偏置組構方式安裝具有黏著間隔物之第二積體電路裝置在該第一積體電路裝置之上；於方塊1106中，連接第一內部互連件於該載體與該第一積體電路裝置之間，且該等第一內部互連件在該黏著間隔物內；於方塊1108中，連接第二內部互連件於該載體與該第二積體電路裝置之間；以及於方塊1110中，包覆該第一積體電路裝置、該第二積體電路裝置、該第一內部互連件、以及該第二內部互連件。
本發明之又另一重要態樣係其可貴地支持與提供降低成本、簡化系統、以及增加效能的歷史趨勢。
本發明之這些及其它有價值之態樣因而促進該技術之狀態至少到下一個層次。
因此，已發現本發明之積體電路封裝系統提供重要且迄今未知與不可得之解決方案、潛在能力、以及功能態樣，用於改善良率、增加可靠度、以及降低積體電路封裝系統之成本。所產生之製程以及組構係明確、符合成本效益、不複雜的、高度通用的、準確的、靈敏的、以及有效的，且能藉由改造用於立即、有效率、以及經濟製造、應用、及利用性之已知的元件來施行。
雖然本發明已結合特定之最佳模式來描述，但可瞭解有鑑於先前描述，許多替代物、修改、以及變化對在此技術領域具有通常知識者會是顯而易見的。因此，本發明係要包含落於所附之申請專利範圍之範疇內之所有此種替代物、修改、以及變化。本文迄今提及或顯示於附加圖式中之所有事項均以例示性或非限制性之含意來詮釋。
100、300、400、500、700、900．．．積體電路封裝系統
104．．．第一積體電路裝置
106．．．載體
108．．．第二積體電路裝置
110．．．第一側邊
118．．．第一內部互連件
120．．．第二內部互連件
202．．．第一非主動面
204．．．第一主動面
206．．．黏著劑
208．．．第二非主動面
210．．．第二主動面
212．．．黏著間隔物
214．．．封裝件包覆物
216．．．外部互連件
304、404．．．第一積體電路裝置
306、406．．．載體
308、408．．．第二積體電路裝置
310、410．．．第一側邊
312、412．．．第二側邊
314、414．．．第三側邊
316、416．．．第四側邊
318、418．．．第一內部互連件
502、702、902．．．第一積體電路裝置
504、704、904．．．載體
506、706、906．．．第二積體電路裝置
508、708、908．．．第一側邊
510、710、910．．．第二側邊
516、716、916．．．第一內部互連件
518、718、918．．．第一端部
520、720、920．．．接觸墊
522、722、922．．．第二內部互連件
524、721、924．．．第二端部
712、912．．．第三側邊
714、914．．．第四側邊
602、802、1002．．．第一包覆物
604、804、1004．．．第一基板
606、806、1006．．．第二包覆物
608、808、1008．．．第二基板
610、810、1010．．．黏著間隔物
612、812、1012．．．封裝件包覆物
614、814、1014．．．外部互連件
616、816、1016．．．第一積體電路晶粒
618、818、1018．．．第二積體電路晶粒
620、820、1020．．．第一接合墊
622、822、1022．．．第一內部互連件
624、824、1024．．．第二內部互連件
626、826、1026．．．第二接合墊
1100．．．積體電路封裝系統
1102、1104、1106、1108、1110．．．方塊
第1圖係本發明之第一實施例中之積體電路封裝系統之平面圖；第2圖係沿著第1圖之線2－2的該積體電路封裝系統之剖面圖；第3圖係本發明之第二實施例中之積體電路封裝系統之平面圖；第4圖係本發明之第三實施例中之積體電路封裝系統之平面圖；第5圖係本發明之第四實施例中之積體電路封裝系統之平面圖；第6圖係沿著第5圖之線6－6的該積體電路封裝系統之剖面圖；第7圖係本發明之第五實施例中之積體電路封裝系統之平面圖；第8圖係沿著第7圖之線8－8的該積體電路封裝系統之剖面圖；第9圖係本發明之第六實施例中之積體電路封裝系統之平面圖；第10圖係沿著第9圖之線10－10的該積體電路封裝系統之剖面圖；以及第11圖係本發明之實施例中之用於製造積體電路封裝系統之積體封裝系統的流程圖。
100．．．積體電路封裝系統
104．．．第一積體電路裝置
106．．．載體
108．．．第二積體電路裝置
110．．．第一側邊
118．．．第一內部互連件
120．．．第二內部互連件
202．．．第一非主動面
204．．．第一主動面
206．．．黏著劑
208．．．第二非主動面
210．．．第二主動面
212．．．黏著間隔物
214．．．封裝件包覆物
216．．．外部互連件

Claims (10)

  1. 一種積體電路封裝系統(1100)，包括：安裝第一積體電路裝置(104)於載體(106)之上；以二維偏置組構方式安裝具有黏著間隔物(212)之第二積體電路裝置(108)於該第一積體電路裝置(104)之上；連接第一內部互連件(118)於該載體(106)與該第一積體電路裝置(104)之間，該第一內部互連件(118)在該黏著間隔物(212)內；連接第二內部互連件(120)於該載體(106)與該第二積體電路裝置(108)之間；以及覆蓋該第一積體電路裝置(104)、該第二積體電路裝置(108)、該第一內部互連件(118)及該第二內部互連件(120)。
  2. 如申請專利範圍第1項之系統(1100)，其中，連接該第一內部互連件(118)於該載體(106)與該第一積體電路裝置(104)之間包含連接不在該黏著間隔物(212)內之該第一內部互連件(118)。
  3. 如申請專利範圍第1項之系統(1100)，其中：安裝該第一積體電路裝置(104)包含：安裝第一積體電路晶粒(104)；以及安裝該第二積體電路裝置(108)包含：安裝第二積體電路晶粒(108)。
  4. 如申請專利範圍第1項之系統(1100)，其中： 安裝該第一積體電路裝置(502)包含：安裝第一積體電路封裝系統(502)；以及安裝該第二積體電路裝置(506)包含：安裝第二積體電路封裝系統(506)。
  5. 如申請專利範圍第1項之系統(1100)，進一步包括接附外部互連件(216)於該載體(106)之下。
  6. 一種積體電路封裝系統(100)，包括：載體(106)；於該載體(106)之上之第一積體電路裝置(104)；以二維偏置組構方式位在該第一積體電路裝置(104)之上之具有黏著間隔物(212)之第二積體電路裝置(108)；在該載體(106)與該第一積體電路裝置(104)之間之第一內部互連件(118)，該第一內部互連件(118)在該黏著間隔物(212)內；在該載體(106)與該第二積體電路裝置(108)之間之第二內部互連件(120)；以及覆蓋在該第一積體電路裝置(104)、該第二積體電路裝置(108)、該第一內部互連件(118)、以及該第二內部互連件(120)之上之封裝件包覆物(214)。
  7. 如申請專利範圍第6項之系統(100)，其中，於該載體(106)與該第一積體電路裝置(104)之間之該第一內部互連件(118)包含不在該黏接間隔物(212)內之該第一內部互連件(118)。
  8. 如申請專利範圍第6項之系統(100)，其中：該第一積體電路裝置(104)係第一積體電路晶粒(104)；以及該第二積體電路裝置(108)係第二積體電路晶粒(108)。
  9. 如申請專利範圍第6項之系統(500)，其中：該第一積體電路裝置(502)係第一積體封裝系統(502)；以及該第二積體電路裝置(506)係第二積體封裝系統(506)。
  10. 如申請專利範圍第6項之系統(100)，進一步包括在該載體(106)之下之外部互連件(216)。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7727816B2 (en) 2006-07-21 2010-06-01 Stats Chippac Ltd. Integrated circuit package system with offset stacked die
US7618848B2 (en) * 2006-08-09 2009-11-17 Stats Chippac Ltd. Integrated circuit package system with supported stacked die
US7994624B2 (en) * 2008-09-24 2011-08-09 Stats Chippac Ltd. Integrated circuit package system with adhesive segment spacer
US7785925B2 (en) * 2008-12-19 2010-08-31 Stats Chippac Ltd. Integrated circuit packaging system with package stacking and method of manufacture thereof
US8492884B2 (en) 2010-06-07 2013-07-23 Linear Technology Corporation Stacked interposer leadframes
US20200118991A1 (en) * 2018-10-15 2020-04-16 Intel Corporation Pre-patterned fine-pitch bond pad interposer

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2670322B1 (fr) * 1990-12-05 1997-07-04 Matra Espace Modules de memoire a l'etat solide et dispositifs de memoire comportant de tels modules
AU4242693A (en) * 1992-05-11 1993-12-13 Nchip, Inc. Stacked devices for multichip modules
US5323060A (en) 1993-06-02 1994-06-21 Micron Semiconductor, Inc. Multichip module having a stacked chip arrangement
US6472758B1 (en) 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
JP3913481B2 (ja) 2001-01-24 2007-05-09 シャープ株式会社 半導体装置および半導体装置の製造方法
US6388313B1 (en) 2001-01-30 2002-05-14 Siliconware Precision Industries Co., Ltd. Multi-chip module
US6900528B2 (en) 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
US6843421B2 (en) * 2001-08-13 2005-01-18 Matrix Semiconductor, Inc. Molded memory module and method of making the module absent a substrate support
US6680219B2 (en) 2001-08-17 2004-01-20 Qualcomm Incorporated Method and apparatus for die stacking
KR20030018204A (ko) * 2001-08-27 2003-03-06 삼성전자주식회사 스페이서를 갖는 멀티 칩 패키지
US6569709B2 (en) 2001-10-15 2003-05-27 Micron Technology, Inc. Assemblies including stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween, packages including the assemblies, and methods
JP3688249B2 (ja) * 2002-04-05 2005-08-24 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
KR100498488B1 (ko) 2003-02-20 2005-07-01 삼성전자주식회사 적층형 반도체 패키지 및 그 제조방법
JP3718205B2 (ja) 2003-07-04 2005-11-24 松下電器産業株式会社 チップ積層型半導体装置およびその製造方法
US20050067694A1 (en) * 2003-09-30 2005-03-31 Pon Florence R. Spacerless die stacking
US20050212144A1 (en) * 2004-03-25 2005-09-29 Rugg William L Stacked die for inclusion in standard package technology
US7629695B2 (en) * 2004-05-20 2009-12-08 Kabushiki Kaisha Toshiba Stacked electronic component and manufacturing method thereof
JP4188337B2 (ja) 2004-05-20 2008-11-26 株式会社東芝 積層型電子部品の製造方法
US20060267173A1 (en) * 2005-05-26 2006-11-30 Sandisk Corporation Integrated circuit package having stacked integrated circuits and method therefor
US7420269B2 (en) * 2006-04-18 2008-09-02 Stats Chippac Ltd. Stacked integrated circuit package-in-package system

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