TWI499032B - 積體電路層疊封裝件堆疊系統 - Google Patents

積體電路層疊封裝件堆疊系統 Download PDF

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Publication number
TWI499032B
TWI499032B TW096128350A TW96128350A TWI499032B TW I499032 B TWI499032 B TW I499032B TW 096128350 A TW096128350 A TW 096128350A TW 96128350 A TW96128350 A TW 96128350A TW I499032 B TWI499032 B TW I499032B
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Taiwan
Prior art keywords
interposer
lead frame
package
integrated circuit
substrate
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TW096128350A
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English (en)
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TW200818456A (en
Inventor
Dioscoro A Merilo
Heap Hoe Kuan
You Yang Ong
Seng Guan Chow
Ma Shirley Asoy
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Stats Chippac Ltd
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Publication of TW200818456A publication Critical patent/TW200818456A/zh
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Publication of TWI499032B publication Critical patent/TWI499032B/zh

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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description

積體電路層疊封裝件堆疊系統
本發明係大致有關積體電路封裝件系統，且更特定有關用於具有堆疊封裝件之積體電路封裝件系統之系統。
為了使積體電路與其它電路介接(interface)，通常將積體電路安裝在導線架或基板上。各積體電路具有接合墊(bonding pad)，該等接合墊係使用極細的金或鋁線而個別連接至導線架之引腳指墊(lead finger pad)。此等組件然後藉由將其個別封裝於模壓塑膠或陶瓷體中而被封裝，以形成積體電路封裝件。
積體電路封裝技術已見到安裝在單一電路板或基板上之積體電路之數目的增加。新的封裝設計在外形因素(form factor)上更加小型(例如積體電路之實體尺寸與形狀)，並提供整體積體電路密度之顯著增加。然而，積體電路密度持續被可用於在基板上安裝個別積體電路之“實際地域(real estate)”所限制。甚至更大的外形因素系統(例如PC、運算型伺服器(compute server)、以及儲存伺服器)在相同或更小之“實際地域”中需要更多積體電路。特別明顯的是，對於可攜式個人電子裝置(例如行動電話、數位相機、音樂播放器、個人數位助理(PDA)、以及適地定位裝置(location－based device))之需求已進一步驅使對積體電路密度之需求。
這樣增加的積體電路密度已引領超過一個積體電路可被封裝於其中之多晶片封裝件的發展。各封裝件提供對個別積體電路及一或多層互連線路(使該積體電路能電性連接至周遭電路)之機械支撐(mechanical support)。目前的多晶片封裝件(通常也稱為多晶片模組)一般由一組單獨的積體電路元件直接黏貼至其上之PCB基板所組成。此種多晶片封裝件已被發現用來增加積體電路密度及小型化、改善訊號傳播速度、減少整體積體電路尺寸及重量、改善效能、及降低成本－－電腦業之所有主要目標。
多晶片封裝件不論是垂直或水平配置同樣會產生問題，因為在積體電路及積體電路連接點被測試前，通常該多晶片封裝件必須被預先組裝。因此，當積體電路被安裝且連接於多晶片模組中時，個別積體電路及連接點不能被個別測試，而無法在組裝成較大電路前確定是良品晶粒(known－good－die,KGD)。因此，習知多晶片封裝件導致組裝製程良率問題。這種製造程序(不能確定是良品晶粒)因此較不可靠且更易於有組裝瑕疵。
此外，垂直堆疊積體電路於一般多晶片封裝件中可產生超出水平配置積體電路封裝件者的問題，故進一步複雜化製造程序。垂直堆疊積體電路更難測試及據以決定個別積體電路之實際失敗模式。此外，基板和積體電路在組裝或測試期間經常受損，而使製造程序複雜化且增加成本。該垂直堆疊積體電路的問題可能遠大於其優點。
封裝件堆疊也有產生設計限制。在許多之堆疊結構中，頂層封裝件不能在中央處有系統互連件(interconnect)，因為該區域通常被下層裝置的塑膠封裝覆蓋物所浪費掉。為了擴展更多之積體功能(integrated function)，這樣的限制可能使設計停止使用封裝件類型。封裝件重疊(package overlap)長久以來一直是對額外互連件之障礙，該重疊可能是於該封裝件之外部附近具有高數目的互連件之裝置的問題。
因此，仍存在著改善封裝方法、系統及設計的需求。有鑒於消費性電子裝置之縮小尺寸及於有限的空間中對更複雜功能之要求，找出這些問題的解決辦法就日益重要。鑒於不斷增加的商業競爭壓力、日益增加的消費者期待、以及縮小針對市場中重要產品區隔化的機會，找出這些問題的解決辦法就日益重要。此外，節省成本、改善效率、以及對抗此種競爭壓力之不斷增加的需求對找出這些問題之解決辦法之重要必要性更增加其急迫性。
這些問題之解決方案長期以來一直被尋求，但先前發展尚未教示或暗示任何解決方案，而因此這些問題之解決方案已長期困惑在此技術領域具有通常知識者。
本發明提供一種積體電路層疊封裝件堆疊系統，其包括：形成導線架中介層，形成該導線架中介層包括：形成導線架、形成模壓基底於該導線架上、以及將該導線架中介層自該導線架單顆化分離出來；設置基底積體電路封裝件，使該導線架中介層安裝於其上；以及設置上層積體電路封裝件於該導線架中介層上。
本發明之特定實施例除了或替代以上提及的實施例外還有其它態樣。該等態樣於參考附加圖式時研讀以下之詳細說明對在此技術領域具有通常知識者將會變得清楚。
以下實施例以足夠詳細之說明使在此技術領域具有通常知識者能完成及使用本發明。應該瞭解，其它實施例依據本發明之揭露內容將會是顯而易見的，且製程或機械改變在不脫離本發明之範疇下可被完成。
在以下說明中，給予數個特定細節以對本發明提供完整的瞭解。然而，明顯的是本發明可在沒有這些特定的細節下被實行。為了避免模糊本發明，一些熟知的電路、系統組構、以及製程步驟將不詳細揭露。
同樣地，顯示系統之實施例的圖式係部分概略的(semi－diagrammatic)且非按比例繪製的，以及特別是一些尺寸係為了清晰呈現而非常誇大地顯示於該等圖式中。此外，為了本發明之說明、描述及理解上的清晰及容易起見，所揭露及描述的多個實施例具有一些共同特徵時，彼此之間類似或同類的特徵通常將用同類的元件符號來描述。
為了說明的目的，如用於本文中的用語“水平(horizontal)”係定義為平行於封裝件基板之平面或表面之平面，而不論其方向。用語“垂直(vertical)”係指垂直於如剛才定義之水平之方向。例如“在...上方(above)”、“在...下方(below)”、“底(bottom)”、“頂(top)”、側(side)”(如“側壁(sidewall)”中)、“較高”、“較低”、“上層(upper)”、“在...之上(over)”、以及“在...之下(under)”等用語均相對於該水平面來定義。用語“在...上(on)”意指元件間有直接接觸。用語“系統”意指本發明之方法及設備。如用於本文中的用語“製程”包括衝壓(stamping)、鍛造(forging)、圖案化、曝光、顯影、蝕刻、清洗、及/或材料移除或雷射修整，如於形成所述結構所需者。
茲參考第1圖，其中係顯示本發明之實施例中積體電路層疊封裝件堆疊系統100之剖面圖。該積體電路層疊封裝件堆疊系統100之剖面圖繪示了基底積體電路封裝件102(例如球柵陣列封裝件(ball grid array package)或接點柵格陣列封裝件(land grid array package))，其具有基底基板104，該基底基板104具有基底頂部表面106及基底底部表面108。第一積體電路110係用黏著劑112(例如晶粒黏接材料)安裝於該基底頂部表面106上。該第一積體電路110係藉由電性互連件114(例如銲線(bond wire)、銲錫凸塊、銲錫柱或栓球凸塊(stud bump))耦接至該基底頂部表面106。基底封裝體116(例如模壓化合物(molded compound))係模壓注入圍繞於該第一積體電路110、該電性互連件114、以及該基底頂表面106的一部分。系統互連件118(例如銲錫球、銲錫柱中介層或栓球凸塊)係黏接至該基底底部表面108，以用於黏接下一層的系統(圖中未顯示)。接觸墊(contact pad)120之陣列係分佈於該基底封裝體116附近的區域。
導線架中介層122包括由在該基底封裝體116上的模壓基底126所支撐的外引腳(outer lead)124。該導線架中介層122係用於訊號之再分佈層(redistribution layer)，否則該訊號無法用於該系統(圖中未顯示)。上層積體電路封裝件128(其包含具有頂部表面132與底部表面134之上層基板130)係安裝於該導線架中介層122上之中央位置。該上層積體電路封裝件128具有用黏著劑112安裝於該頂部表面132上之第二積體電路136。該第二積體電路136藉由該電性互連件114而耦接到該頂部表面132。上層封裝體138(例如該模壓化合物)係模壓注入於該第二積體電路136、該頂部表面132以及該電性互連件114之上。該系統互連件118係黏接至該上層基板130之底部表面134。該上層積體電路封裝件128係安裝於該基底積體電路封裝件102，使得該上層基板130之基底表面134置放於該導線架中介層122與該系統互連件118上。該導線架中介層122提供該上層基板130與該基底基板104間之額外互連路徑。
現參考第2圖，其中係顯示於本發明之實施例中用於該積體電路層疊封裝件堆疊系統100之導線架中介層122之俯視圖。該導線架中介層122之俯視圖繪示了成陣列的訊號接點202，該導線架中介層122具有由該模壓基底(molded base)126所支撐的外引腳124。斷面線3－3指出該導線架中介層顯示於第3圖中之部份。所顯示之組構是該訊號接點202之四乘四陣列，但這僅是範例而已，且陣列中實際的接點數目可能會不同。
現參考第3圖，其中係顯示第2圖之導線架中介層122在引腳彎曲前沿著斷面線3－3之剖面圖。該導線架中介層122之剖面圖繪示了該訊號接點202與外引腳124成共平面位置。該模壓基底126維持該訊號接點202及該外引腳124之相對位置。該外引腳124可被組構成將模壓基底126升高至各種高度以符合不同封裝件之需求。
現參考第4圖，其中係顯示第2圖之導線架中介層122在引腳彎曲後沿著斷面線3－3之剖面圖。該導線架中介層122之剖面圖繪示了已被彎曲之該外引腳124以支撐第1圖之該基底封裝體116之向上堆疊高度(stack－up height)402，其目的係供組構之用。延伸基底404係形成於該外引腳124上該延伸基底404之彎曲位置決定該模壓基底126之向上堆疊高度402，並提供用於連接至第1圖之該基底積體電路封裝件102之接觸表面。
現參考第5圖，其中係顯示於本發明之實施例中用於該層疊封裝件堆疊系統之導線架500的俯視圖。該導線架500的俯視圖繪示了於未處理狀態下該導線架中介層122中之四個導線架中介層。該導線架500係出自導電材料片(例如銅、錫、鋅或者銅、錫或鋅之合金)的蝕刻、衝壓或鍛造。該導線架500可鍍覆有例如金之其它金屬。各該外引腳124被框件502及攔壩桿(dam bar)504所支撐。該攔壩桿504被連結桿(tie bar)506所支撐。
該攔壩桿504在第1圖之該模壓基底126形成期間係作用為用以密封注入模具(圖中未顯示)的阻障物。該攔壩桿504之位置界定該模壓基底126之範圍。於完成該模壓製程後，該攔壩桿504、該連結桿506以及該框件502係自該導線架中介層122中移除。
現參考第6圖，其中係顯示於本發明之替代實施例中用於層疊封裝件堆疊系統之偏移中介層(offset interposer)600之俯視圖。該偏移中介層600之俯視圖繪示了成陣列的該訊號接點202，該偏移中介層600具有由該模壓基底126所支撐的外引腳124。斷面線7－7指出該偏移中介層600顯示於第7圖中之部份。所顯示的組構為該訊號接點202之二乘四陣列。但這僅是範例而已，且陣列中實際的接點數目可能會不同。
現參考第7圖，其中係顯示第6圖之偏移中介層600沿著斷面線7－7之剖面圖。該偏移中介層600之剖面圖繪示了已被彎曲來支撐第1圖之該基底封裝體116之向上堆疊高度702之該外引腳124，其目的係供組構之用。延伸基底704係形成於該外引腳124上。該延伸基底704之彎曲位置決定該模壓基底126之向上堆疊高度702，並提供用於連接至第1圖之該基底積體電路件102之接觸表面。
現參考第8圖，其中係顯示於本發明之替代實施例中積體電路層疊封裝件堆疊系統800之剖面圖。該積體電路層疊封裝件堆疊系統800之剖面圖繪示了基底積體電路封裝件802(例如球柵陣列封裝件或接點柵格陣列封裝件)，其包括具有基底頂部表面806與基底底部表面808之基底基板804。第一積體電路810係用黏著劑112(例如晶粒黏接材料)安裝於該基底頂部表面806上。該第一積體電路810係藉由電性互連件114(例如銲線、銲錫凸塊、銲錫柱或栓球凸塊)耦接至該基底頂部表面806。基底封裝體816(例如模壓化合物)係模壓注入圍繞該第一積體電路810、該電性互連件114、以及該基底頂表面806之一部分。系統互連件118(例如銲錫球、銲錫柱中介層或栓球凸塊)係黏接至該基底底部表面808，以用於黏接下一層的系統(圖中未顯示)。接觸墊820之陣列係分佈於該基底封裝體116附近的區域。
該偏移中介層600包括由在該基底封裝體816上的模壓基底126所支撐的外引腳124。包括具有頂部表面832與底部表面834之上層基板830的上層積體電路封裝件828(例如四方扁平無引腳(quad flatpack no－lead,QFN)、球柵陣列、或接點柵格陣列封裝件)係安裝於該偏移中介層600上之偏移位置。該上層積體電路封裝件828具有用黏著劑112安裝於該頂部表面832上之第二積體電路836。該第二積體電路836藉由該電性互連件114耦接到該頂部表面832。上層封裝體838(例如該模壓化合物)係模壓注入於該第二積體電路836、該頂部表面832以及該電性互連件114之上。該系統互連件118係黏接至該上層基板830之底部表面834。該上層積體電路封裝件828係安裝於該基底積體電路封裝件802上，使得該上層基板830之基底表面834置放於該偏移中介層600與該系統互連件118上。該偏移中介層600提供該上層基板830與該基底基板804間之額外互連路徑。
現參考第9圖，其中係顯示於本發明之另一替代實施例中積體電路層疊封裝件堆疊系統900之剖面圖。該積體電路層疊封裝件堆疊系統900之剖面圖繪示了具有安裝於該基底封裝體816上之延伸中介層902的基底積體電路封裝件802。該上層積體電路封裝件828由該延伸中介層902及該系統互連件118所支撐，並且電性連接至該延伸中介層902及該系統互連件118。該延伸中介層902具有可用來安裝積體電路封裝件906(例如QFN封裝件、接點柵格陣列封裝件、或者是具鷗翼型(gull－wing)或J型引腳之雙列直插封裝(dual－in－line package))之額外接觸墊904。
現參考第10圖，其中係顯示本發明之又另一替代實施例中積體電路層疊封裝件堆疊系統1000之剖面圖。該積體電路層疊封裝件堆疊系統1000之剖面圖繪示了具有安裝於該基底封裝體816上之延伸中介層1002的基底積體電路封裝件802。該上層積體電路封裝件828由該延伸中介層1002及該系統互連件118所支撐，並且電性連接至該延伸中介層1002及該系統互連接件118。該延伸中介層1002具有可用來安裝覆晶(flipchip)積體電路1006之額外接觸墊1004。底部填膠(underfill)材料1008係用來保護晶粒互連件1010(例如銲錫球、栓球凸塊、或銲錫柱)。
現參考第11圖，其中係顯示於本發明之再又另一替代實施例中積體電路層疊封裝件堆疊系統1100之剖面圖。該積體電路層疊封裝件堆疊系統1100之剖面圖繪示了具有安裝於該基底封裝體816上之延伸中介層1102的基底積體電路封裝件802。該上層積體電路封裝件828被該延伸中介層1102及該系統互連件118所支撐，並且電性連接至該延伸中介層1102及該系統互連件118。該延伸中介層1102具有可用來安裝離散元件(discrete component)1106(例如被動元件或主動元件)之額外接觸墊1104。
現參考第12圖，其中係顯示於本發明之實施例中用於製造積體電路層疊封裝件堆疊系統100之積體電路層疊封裝件堆疊系統1200之流程圖。該系統1200包括形成導線架中介層，形成該導線架中介層包括形成導線架、形成模壓基底於該導線架上、以及將該導線架中介層自該導線架單顆化分離出來(於方塊1202中)；於方塊1204中，設置基底積體電路封裝件，使該導線架安裝於其上；於方塊1206中，設置上層積體電路封裝件於該導線架中介層上。
已發現本發明因此具有數個態樣。
已意外發現的一種主要態樣係本發明提供用於接點之訊號再分佈層(於積體電路封裝件堆疊中)，該等接點係在下層積體電路之覆蓋物之上。以歷史觀點，這些接點必須移到外部周邊(outer perimeter)，造成該封裝件之增加的接點密度及較大面積(foot print)。
另一態樣係該導線架中介層允許較短之訊號路徑，此舉可對關鍵訊號有益。
本發明之另一重要態樣係本發明有價值支持及提供降低成本、簡化系統、以及增加效能之歷史趨勢。
本發明之這些及其它有價值態樣因此促進技術之狀態進到至少下一層次。
因此，已發現本發明之積體電路層疊封裝件堆疊系統提供用於開發及製造層疊封裝件堆疊之解決方案之重要與迄今未知和無法得到之解決方案、能力、以及功能態樣。所產生之製程及組構係直接的、具成本效益的、不複雜的、高度通用性及有效的，能藉由改變已知的技術而意外地且非顯而易知地實施，且因此容易適用於有效率地及經濟地製造完全與習知製造程序與技術相容的層疊封裝件堆疊裝置。所產生之製程及組構係直接的、具成本效益的、不複雜的、高度通用性的、準確的、敏感的、以及有效的，且能藉由改造已知的元件來實施，以用於立即的、有效率的、及經濟的製造、應用、以及利用。
雖然本發明已結合特定最佳模式來描述，應該瞭解鑑於先前說明，許多替代、修改以及變化對在此技術領域具有通常技藝者會是顯而易見的。因此，本發明係欲包含所有落於附加的申請權利範圍之範疇內的所有此種替代、修改、以及變化。本文中迄今所述及或示出於附加的圖式中之所有標的均以說明且非限制的意義來詮釋。
100、800、900、1000、1100、1200．．．積體電路層疊封裝件堆疊系統
104、804．．．基底基板
106、806．．．基底頂部表面
108、808．．．基底底部表面
110、810．．．第一積體電路
112．．．黏著劑
114、1010．．．互連件
116、816．．．基底封裝體
118．．．系統互連件
120．．．接觸墊、電性連接點
122．．．導線架中介層
124．．．外引腳
126．．．模壓基底
128、828．．．上層積體電路封裝件
130、830．．．上層基板
132、832．．．頂部表面
134、834．．．底部表面
136、836．．．第二積體電路
202．．．訊號接點
402、702．．．向上堆疊高度
500．．．導線架
502．．．框件
504．．．攔壩桿
506．．．連結桿
600．．．偏移中介層
704．．．延伸基底
802．．．基底積體電路封裝件
820、1104．．．接觸墊
838．．．上層封裝體
902、1002、1102．．．延伸中介層
904．．．額外接點
906．．．積體電路封裝件
1004．．．額外接觸墊
1006．．．積體電路晶粒
1008．．．底部填膠材料
1106．．．離散元件
1202、1204、1206．．．方塊
第1圖係於本發明之實施例中積體電路層疊封裝件堆疊系統之剖面圖；第2圖係於本發明之實施例中用於層疊封裝件堆疊系統之導線架中介層之俯視圖；第3圖係第2圖之導線架中介層在引腳彎曲前沿著斷面線3－3之剖面圖；第4圖係第2圖之導線架中介層在引腳彎曲後沿著斷面線3－3之剖面圖；第5圖係於本發明之實施例中用於層疊封裝件堆疊系統之導線架的俯視圖；第6圖係於本發明之替代實施例中用於層疊封裝件堆疊系統之偏移中介層之俯視圖；第7圖係第6圖之偏移中介層沿著斷面線7－7之剖面圖；第8圖係於本發明之替代實施例中積體電路層疊封裝件堆疊系統之剖面圖；第9圖係於本發明之另一替代實施例中積體電路層疊封裝件堆疊系統之剖面圖；第10圖係於本發明之又另一替代實施例中積體電路層疊封裝件堆疊系統之剖面圖；第11圖係於本發明之再又另一替代實施例中積體電路層疊封裝件堆疊系統之剖面圖；以及第12圖係於本發明之實施例中用於製造層疊封裝件堆疊系統之層疊封裝件堆疊系統之流程圖。
1200．．．積體電路層疊封裝件堆疊系統
1202、1204、1206．．．方塊

Claims (8)

  1. 一種形成積體電路層疊封裝件堆疊系統(1200)之方法，包括：形成基底基板(104)；形成導線架中介層(122)及在該基底基板(104)上的至少一系統互連件(118)，該導線架中介層(122)包含：形成組構在該導線架中介層(122)之頂面上的訊號接點(202)；形成具有引腳之導線架(500)；形成模壓基底(126)於該導線架(500)上；將該導線架中介層(122)自該導線架(500)單顆化分離出來；以及彎曲該引腳以支撐向上堆疊高度，其中，該等訊號接點與該引腳之一部分係在共平面位置；以及在該導線架中介層(122)及該至少一系統互連件(118)上形成上層積體電路封裝件(128)，其中，該上層積體電路封裝件(128)直接且電性連接於該導線架中介層(122)的該訊號接點(202)及該至少一系統互連件(118)，以及該引腳及該至少一系統互連件(118)直接且電性連接於該基底基板(104)。
  2. 如申請專利範圍第1項之方法，其中，將該導線架中介層(122)自該導線架(500)單顆化分離出來包含：自該導線架(500)切割攔壩桿(504)；以及 藉由彎曲該引腳(124)而調整該向上堆疊高度(402)。
  3. 如申請專利範圍第1項之方法，進一步包括：形成延伸基底(404)於該導線架中介層(122)上。
  4. 如申請專利範圍第1項之方法，進一步包括：設置額外接點(904)於延伸中介層(902)上，用於黏接離散元件(1106)、積體電路封裝件(906)、積體電路晶粒(1006)、或其組合。
  5. 一種積體電路層疊封裝件堆疊系統(100)，包括：基底基板(104)；導線架中介層(122)及至少一系統互連件(118)形成於該基底基板(104)上，該導線架中介層(122)包含：組構在該導線架中介層(122)之頂面上的訊號接點(202)；具有引腳之導線架(500)；該導線架(500)上之模壓基底(126)；以及自該導線架(500)單顆化分離出來之該導線架中介層(122)，其中，該引腳被彎曲以支撐向上堆疊高度，其中，該等訊號接點與該引腳之一部分係在共平面位置；以及上層積體電路封裝件(128)形成在該導線架中介層(122)及該至少一系統互連件(118)上，其中，該上層積體電路封裝件(128)直接且電性連接於該導線架中介層(122)的該訊號接點(202)及該至少一系統互連件(118)，以及該引腳及該至少一系統互連件(118)直接且電性連接於該基底基板(104)。
  6. 如申請專利範圍第5項之系統(100)，其中，自該導線架 (500)單顆化分離出來之該導線架中介層(122)包含：自該導線架(500)切割之攔壩桿(504)，其中，該向上堆疊高度(402)係藉由該引腳(124)之彎曲所調整。
  7. 如申請專利範圍第5項之系統(100)，進一步包括：形成於該導線架中介層(122)上之延伸基底(404)。
  8. 如申請專利範圍第5項之系統100，進一步包括：延伸中介層(902)上之額外接點(904)，用於離散元件(1106)、積體電路封裝件(906)、積體電路晶粒(1006)、或其組合。
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US20090179312A1 (en) 2009-07-16
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