TWI475606B - 非均勻真空分佈晶粒附著尖端 - Google Patents

非均勻真空分佈晶粒附著尖端 Download PDF

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TWI475606B
TWI475606B TW101106338A TW101106338A TWI475606B TW I475606 B TWI475606 B TW I475606B TW 101106338 A TW101106338 A TW 101106338A TW 101106338 A TW101106338 A TW 101106338A TW I475606 B TWI475606 B TW I475606B
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vacuum
force
semiconductor die
die
vacuum holes
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TW201250808A (en
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Pradeep Kumar Rai
Kl Bock
Li Wang
Jinxiang Huang
Enyong Tai
Jianhua Wang
Kh Ong
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Sandisk Semiconductor Shanghai Co Ltd
Sandisk Information Technology Shanghai Co Ltd
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Description

非均勻真空分佈晶粒附著尖端
實施例係關於用於使經切割之半導體晶粒與膠帶分離之系統。
對於攜帶型消費型電子裝置之需求的猛烈增長正推動對於高容量儲存裝置之需要。諸如快閃記憶體儲存卡之非揮發性半導體記憶體裝置被日益廣泛使用,以滿足對數位資訊儲存及交換之不斷增長之需求。非揮發性半導體記憶體裝置之可攜帶性、通用性及耐用設計連同其高可靠性及大容量已使該等記憶體裝置理想地用於包括(例如)數位相機、數位音樂播放器、視訊遊戲機、PDA及蜂巢式電話之廣泛多種電子裝置中。
雖然已知廣泛多種封裝組態,但可通常將快閃記憶體儲存卡製造為系統級封裝(SiP)或多晶片模組(MCM),其中以所謂的三維堆疊組態將複數個晶粒安裝於基板上。在先前技術圖1中展示習知半導體封裝20(無模製化合物)之邊視圖。典型封裝包括安裝至基板26之複數個半導體晶粒22、24。儘管圖1中未展示,但半導體晶粒在該晶粒之上表面上形成有焊線墊。基板26可由包夾於上部導電層與下部導電層之間的電絕緣核心形成。可蝕刻上部導電層及/或下部導電層以形成包括電導線及接觸墊之傳導圖案。焊線30連接於半導體晶粒22、24之焊線墊與基板26之電導線之間以將半導體晶粒電耦合至基板。基板上之接觸墊又提供晶 粒與主機裝置之間的電路徑。一旦形成了晶粒與基板之間的電連接,則通常接著以模製化合物來圍封該總成,以提供保護性封裝。
為了形成半導體封裝,執行晶粒結合製程,其中自晶圓切割半導體晶粒、自膠帶拾取半導體晶粒且將半導體晶粒結合至基板。先前技術圖2展示晶圓40,晶圓40包括複數個半導體晶粒,例如晶粒22(在圖2中僅對其中一些編號)。晶圓40上之每一半導體晶粒22已經處理而包括如此項技術中已知的能夠執行指定電子功能的積體電路。在測試晶粒22以發現不良晶粒之後,可將晶圓置放於被稱為晶粒附著膜(DAF)帶之黏著膜44上,且接著(例如)用鋸子或雷射切割。DAF帶可由黏著至一帶之晶粒附著膜形成,且在晶粒與該帶分離之後,膜可保持貼附至晶粒之底表面。切割製程將晶圓分離為保持貼附至DAF帶的個別半導體晶粒22。圖2展示貼附至DAF帶44之晶圓40。
為了拆下個別晶粒,將晶圓及DAF帶放在製程工具中,在圖3中展示製程工具之部分。圖3展示晶粒脫離器工具50,其包括一真空夾盤52,晶圓40及DAF帶44支撐於該真空夾盤52上。為了從DAF帶44提起晶粒,提供包括真空尖端62之拾取工具60。拾取工具60降至待自DAF帶44移除之晶粒22之上,將真空施加至尖端62,且將自帶44拔起晶粒22。拾取工具接著輸送晶粒22以用於附著至基板或用於輸送至別處。
圖4展示習知真空尖端62之仰視圖。該尖端包括用於將 負壓力傳達至真空尖端62之表面的複數個真空孔64(在圖4中對其中一些編號)。真空孔64處之負壓力將晶粒22保持在拾取工具60上。在習知真空尖端中,例如,如圖4中所展示,真空孔64跨越尖端之表面均勻地分佈。
習知真空尖端之一缺點在於,當真空孔64跨越待自DAF帶提起之晶粒的表面施加均勻壓力時,並不藉由均勻壓力自DAF帶剝離該晶粒。詳言之,在用刀片切割晶圓期間,刀片在晶粒的邊緣(晶粒在邊緣處被切割)附近引起剪切力及法線力。剪切力及法線力增大了在晶粒之邊緣附近晶粒與DAF帶之間的黏著力。此等黏著力為距晶粒之邊緣之距離x的函數,且隨著遠離晶粒之邊緣之距離的平方而減小。在一實例中,由DAF帶施加至晶粒之黏著力F(x)與某一常數K除以距晶粒之邊緣之距離x的平方成比例:F(x):K/(1+x2 )。
該常數K為由於不同黏著機制而產生之不同常數的總和。舉例而言,化學結合發生於膠帶與切割帶之間,該等化學結合可在由用刀片或雷射切割引起的加熱之後得以增強。另外,靜電力亦可由於切割而產生於晶粒邊緣附近。另外,凡得瓦爾力形成於DAF及切割帶之分子內。
先前技術圖5展示由於真空尖端62而產生之在晶粒22上的向上力Fu ,及由於晶粒22與DAF帶44之間的黏著而產生之在晶粒22上的向下力Fd 。如以上所述,在真空尖端之向上力均勻的情況下,向下力隨著遠離邊緣之距離之平方而變化。先前技術圖5展示由於向上力Fu 及向下力Fd 而產生 之在晶粒上的淨合力Fn 。如圖6中所見,晶粒22上之淨力朝向晶粒之中間比在邊緣處大。
此不均勻力分佈之最終結果為,在習知晶粒脫離器工具中藉由真空尖端62自DAF帶拾取晶粒22時,晶粒22可能會彎曲。在先前技術圖7中展示此情境。晶粒之彎曲可能有若干有害效果。晶粒可能不會緊固於真空尖端62上,且可能自尖端62掉落。此外,晶粒可能在其彎曲時破裂,及/或形成於半導體晶粒22之表面上的導電跡線在晶粒彎曲或偏移時可能受到損壞,以致於與鄰近導電跡線電短路。在半導體晶粒之厚度已減少(一些實例中,減少至40微米(μm)至50微米)的現今,尤為如此。
即使在對晶粒未發生該損壞的情況下,當將彎曲晶粒安裝於基板(諸如,先前技術圖8中所展示之基板70)上時,另外的問題仍可能發生。考慮到晶粒22相對於基板70之表面的凹入形狀,氣泡72可形成於晶粒與基板之間。舉例而言,當在囊封製程中加熱晶粒及基板時,歸因於氣泡之膨脹,此等氣泡可使晶粒與基板分層。
現將參照圖9至圖26來描述實施例,實施例係關於使用非均勻真空力分佈使晶粒與膠帶脫離之系統及方法。在實施例中,在真空尖端處產生非均勻真空力分佈,以使得當真空尖端自膠帶拔起半導體晶粒時,沿著該晶粒之周邊施加相對較高之拾取力(pickup force)。應理解,本發明可以許多不同形式來體現,且不應被解釋為限於本文中所闡述 之實施例。實情為,提供此等實施例以使得本發明將為透徹且完整的,且將向熟習此項技術者完全傳達本發明。實際上,本發明意欲涵蓋此等實施之替代例、修改及等效物,該等替代例、修改及等效物包括於由附加申請專利範圍所界定之本發明之範疇及精神內。另外,在本發明之以下詳細描述中,闡述眾多特定細節以便提供對本發明之透徹理解。然而,一般熟習此項技術者應清楚,可在無該等特定細節之情況下實踐本發明。
本文中對術語「頂部」及「底部」及「上部」及「下部」以及此等術語之衍生變化的任何引用在本文中僅為了便利及說明性目的而使用,且不意謂限制對半導體裝置之描述,此係因為提及項目之位置可互換。
大體而言,實施例係關於在晶粒脫離工具中所使用之拾取工具的真空尖端。提供晶粒脫離工具以用於自膠帶總成(經切割晶圓支撐於該膠帶總成上)移除晶粒,及輸送晶粒而遠離晶圓。雖然膠帶總成可為DAF帶,但應理解,可使用在脫離器工具中用以將經切割半導體晶圓保持在一起的多種不同帶及帶總成。
現將參照圖9之流程圖及圖10至圖26之視圖來描述本發明之實施例的操作。在步驟100中,在晶圓上形成半導體晶粒且測試半導體晶粒。在步驟102中,晶圓之被動側可經受背面研磨製程且接著可將其安裝於膠帶(諸如具有已知設計之DAF帶)上。在步驟104中,可接著將晶圓切割為個別半導體晶粒。圖10展示半導體晶圓200,其包括安裝 於膠帶206上之複數個經切割晶粒204。在一實例中,可自晶圓200切割晶粒204以使其具有12.96 mm之長度、9.28 mm之寬度及46 μm之厚度。應理解,此等尺寸僅以實例說明且在替代實施例中可變化。
膠帶206可為具有已知構造之DAF帶,且可含有由(例如)聚酯或其類似者形成的帶層,該帶層與黏著性晶粒附著膜層疊。可使用之DAF帶的一實例為來自Nitto Denko公司(其總部位於日本大阪)之EM-310VJ-P WEF。在將晶圓貼附至DAF帶之後,可使用諸如鋸切或雷射切割之各種已知切割技術將晶圓切割為個別半導體晶粒。典型切割製程在已經安裝於帶上之鄰近晶粒之間留下小的鋸口。
在步驟108中,可接著將帶及晶圓傳送至脫離器工具220(圖11)以移除個別晶粒。脫離器工具220可類似於[先前技術]段落中所描述之脫離器工具,或類似於用於自膠帶移除經切割半導體晶粒的任何其他已知工具,只是該工具包括新穎之真空尖端230。將晶圓200及帶206定位於支撐台222上,其中帶206抵靠著支撐台222之上表面。支撐台222可包括用於將帶206及晶圓200緊固地保持在支撐台222上的一真空夾盤。
脫離器工具220可進一步包括一拾取工具224,該拾取工具224包括一真空尖端230。該拾取工具安裝於一機器人臂上,該機器人臂經控制以自經切割晶圓200拾取各別晶粒204,且將經拾取晶粒輸送至別處,諸如,輸送至如以下所闡釋之基板上。真空尖端230可由貼附至拾取工具224之 一層橡膠形成,但在另外實施例中,真空尖端230可由其他材料形成。
如圖12中所展示,真空尖端230可包括形成於其中之複數個真空孔234(在圖12中對其中一些編號)。根據本發明技術之態樣,真空孔234可跨越真空尖端230之表面不均勻地分佈。詳言之,孔234可朝向真空尖端230之邊緣較為密集,且朝向真空尖端230之中間較為稀疏。朝向真空尖端230之邊緣具有真空孔234之較高密度的此組態導致朝向真空尖端230之邊緣的較大真空拾取力。
圖12A為列出了例示性尺寸的圖12之真空尖端230的視圖。在一非限制性實例中,圖12A上之尺寸a至l可如下:a.=523 μm
b.=386 μm
c.=494 μm
d.=469 μm
e.=2230 μm
f.=4000 μm
g.=2368 μm
h.=823 μm
i.=4237 μm
j.=3490 μm
k.=12371 μm
l.=9407 μm
如所指示,此等尺寸中之每一者僅以實例說明,且每一者 在另外實施例中可彼此成比例地或不成比例地變化。
藉由真空孔234施加於晶粒上之拾取力等於在真空孔234處之在晶粒之對置側上的壓力差乘以該真空孔之面積。抵靠著真空孔之晶粒204之第一側上的壓力可為真空孔234中的壓力,其可約為或接近於零大氣壓。晶粒之與第一側對置之第二側上的壓力可為大氣壓。因此,在一實例中,在真空孔234處之壓力差可約為大氣壓。
由πr2給出真空孔之面積。使用真空孔234之直徑(2r)為823 μm之以上實例,真空孔234之面積為0.532 mm2 或0.000824 in2
自此等值,可計算一實例中之單一真空孔234的拾取力。使用上述壓力差約為大氣壓(14.7 lbs/in2 )且面積為0.000824 in2 的實例,則單一真空孔之拾取力可為0.012 lbs。此值為大致估計,且僅以實例說明。每一真空孔234皆提供此拾取力。考慮到在圖12A上展示之尺寸,可計算藉由所有真空孔234施加於晶粒204上之力。如所見,考慮到真空孔234在邊緣處之較高密度,拾取力在晶粒204之邊緣處比在中心處高。
該等孔234各自連接至一真空源(未圖示)。因此,當啟動真空力時,將負壓力傳達至孔234。真空尖端230上具有真空孔之較大密度的區域能夠將較大提取力施加於保持在真空尖端230上之半導體晶粒204上。
如圖13中所展示,提供真空孔之圖案以便產生通過晶粒204之橫截面的向上力分佈Fu 。力分佈Fu 大體上與歸因於 晶粒204與帶206之間的黏著力而通過晶粒204之同一橫截面的向下力分佈Fd 成比例。可經由通過晶粒204、與晶粒204之主要平坦表面(上表面及下表面)垂直的任何橫截面獲得圖13中所展示之向上力分佈及向下力分佈。
如在[先前技術]段落中所述,晶粒204上之向下力Fd 大體上隨著遠離邊緣之距離x之平方而變化:F(x):K/(1+x2 )(或者可使用其他等式來描述歸因於黏著之向下力)。在實施例中,真空孔可朝向邊緣具備較大密度,以使得向上力Fu 亦可隨著遠離邊緣之距離x之平方而變化。此導致圖14中所展示之淨力分佈Fn ,其沿著晶粒204之橫截面為均勻的。以此方式,可避免晶粒之彎曲以及隨之而來的問題。
在實施例中,向上力分佈與黏著力為反向力且成比例。然而,雖然黏著力分佈大體上為連續的,但向上力分佈大體上為不連續的。亦即,藉由真空孔234將向上力施加於半導體晶粒204上,但在真空孔234之間不施加向上力。因此,將向上力分佈描述為與黏著力為反向力且成比例的實施例可藉由使真空孔之間的不連續性得到平衡而將向上力分佈視為連續的。
在實施例中,淨力Fn 沿著晶粒204之各橫截面中之任一者為均勻的,諸如,沿著晶粒204之長度方向、跨越晶粒204之寬度尺寸,及沿著晶粒204之對角線(corner-to-corner diagonal)。在另外實施例中,淨力可沿著橫截面略微變化而非淨力Fn 跨越晶粒204始終均勻,但淨力變化可維持在不會引起晶粒204之彎曲的程度內。
考慮到跨越晶粒204之均勻淨力Fn ,可將晶粒平直地吸在真空尖端230上,如圖15中所展示。此外,當藉由真空尖端230將晶粒輸送至如圖16中所展示之基板250時,可將晶粒204平直地安裝在基板250上,而不會在晶粒204與基板250之間截留氣泡。可接著(例如)經由一層晶粒附著膜(DAF)將晶粒平直地安裝在基板上,在晶粒與帶206分離之後,該層DAF留在晶粒上。或者,可使用一層環氧樹脂將晶粒附著至基板。
再次參照圖12及圖13,應理解,可提供多種真空孔組態以便大致估計向上力分佈Fu ,其中力Fu 與遠離邊緣之距離成比例地減小。以下參照圖20至圖25解釋此等替代實施例中之一些。在實施例中,可根據經驗來判定及測試針對真空孔234之給定組態的向上力Fu 以確認其提供所要之向上力分佈(隨著遠離邊緣之距離之平方而變化)。在發現給定真空孔組態在晶粒(或測試組件)之邊緣處不導致足夠高之向上力的情況下,可增大在真空尖端之邊緣處的孔密度(或可減小在中心處之孔密度)。
可基於估計將大致與歸因於晶粒204與帶206之間的黏著之向下力Fd 成比例之組態而提供愈接近於真空尖端230之邊緣就愈密集之真空孔組態。
在另外實施例中,可能發生的是,向下力Fd 不隨著遠離晶粒204之邊緣之距離的平方而變化。在該等實施例中,可以提供成比例地匹配或幾乎匹配向下力分佈Fd 之向上力分佈Fu 的組態來配置真空孔234。此等力分佈可按各種函 數f(x)隨著距晶粒201之邊緣的距離x而變化。
在以上所描述之實施例中,真空孔234經配置以便提供沿著橫截面大體上均勻之淨力分佈Fn 。然而,在一替代實施例中,真空孔234可經組態以便提供在晶粒204之邊緣處的向上力大於朝向晶粒204之中心區域的向上力之淨力分佈Fn 。現參照圖17至圖20描述此實施例。
在圖17至圖20之實施例中,以一方式配置真空孔234以使得在晶粒204之邊緣處相對於晶粒之中心的向上力差大於在圖13至圖16之實施例中跨越晶粒的向上力差。亦即,在圖17至圖20中在晶粒204之邊緣處的向上力可高於在圖13至圖16中在晶粒204之邊緣處的向上力。或者,在圖17至圖20中在晶粒204之中心處的向上力可高於在圖13至圖16中在晶粒204之中心處的向上力。結果為如圖18中所展示之淨向上力分佈Fn ,與在晶粒之中心處的淨向上力相比較,該淨向上力分佈Fn 在晶粒204之邊緣處具有較高的淨向上力。
如圖19中所展示,此可導致晶粒當被吸在真空尖端230上時略微彎曲。在實施例中,該彎曲為略微的以致於不會危及晶粒204在真空尖端230上之保持且不會有晶粒破裂的風險。可將具有諸如圖19中所展示之略微彎曲的晶粒輸送至如以上所描述之基板250上。此實施例中之晶粒可具有相對於基板略微凸起之形狀,以使得當晶粒204被平直地按在基板上(如在圖20之下部分中所展示)時,可順暢地自晶粒204之邊緣排出可能存在於晶粒與基板之間的任何氣泡252。
如以上所述,可提供不同真空孔組態。圖21至圖23說明 幾個替代組態。此等說明並不意欲為詳盡的,且可提供真空孔234之許多其他組態,其中在真空尖端230之邊緣處的所得向上力高於在真空尖端之中心處所得的向上力。
在以上所描述之實施例中,藉由增大較接近於邊緣之真空孔234之密度而達成在邊緣處較高的壓力差。應理解,在另外實施例中可以其他方式產生跨越真空尖端230之表面的所要壓力差。舉例而言,圖24展示具有真空孔之均勻分佈(諸如,在先前技術(圖4)中所發現)之真空尖端230的一實施例。然而,在此實施例中,不同真空孔234連接至不同真空源。在所展示之實例中,圍繞真空尖端230之外部周邊的真空孔234之第一群組連接至一將壓力P1傳達至真空孔之真空源。較接近於真空尖端230之中心的真空孔234之第二群組連接至一將壓力P2傳達至真空孔之真空源。且更接近於真空尖端230之中心的真空孔234之第三群組連接至一將壓力P3傳達至真空孔之真空源。在此實例中,可提供真空源以使得P1>P2>P3。可控制真空源之相對強度以便產生與向下力分佈Fd 成比例之向上力分佈Fu ,使得跨越晶粒204所施加之淨力分佈Fn 為均勻的。
圖25說明另一實例,其同樣具有真空孔234之均勻分佈(諸如,在先前技術(圖4)中所發現)。然而,在此實施例中,不同真空孔234具有不同大小。接近於外部周邊之孔可具有比在真空尖端230之中心處之孔大的直徑。相比於中心處之較小孔,外部周邊處之較大孔可能能夠將較大向上力施加於晶粒上。此可產生一向上力分佈Fu ,其在晶粒 之邊緣處具有較高的力以使得跨越晶粒204所施加之淨力分佈為均勻的。
再次參照圖9之流程圖,在使真空尖端230靠著待移除之晶粒之前或之後,可在步驟112中啟動真空源,且可在步驟116中移除及輸送晶粒。在將經輸送晶粒於別處放下之後,如在步驟120中所指示,拾取工具224可返回至晶圓以拾取下一晶粒204。
圖26說明使用藉由上述系統而脫離之半導體晶粒組裝而成之半導體封裝170。半導體封裝170包括晶粒204中之一或多者。此等晶粒可(例如)為與控制器晶粒174(諸如,ASIC)耦合之非揮發性記憶體。考量其他類型之晶粒。晶粒(例如)經由焊線178電耦合至基板150。可進一步將被動組件(未圖示)安裝於基板150上。封裝170可(例如)為平台柵格陣列(LGA)封裝,其可以可移除方式***至主機裝置中及自主機裝置移除。在此實施例中,基板可包括在封裝之下表面上的接觸指180,其用於與主機裝置中之端子配對。可將封裝囊封於模製化合物182中以保護半導體晶粒及其他組件以對抗衝擊及濕氣。
使用上述系統及方法,可使藉由真空尖端所施加之力相對於黏著力得以平衡,且可提供均勻的淨力分佈。此情形又可減少歸因於晶粒破裂、導電跡線損壞及短路及/或基板上之晶粒分層的良率減退。
大體而言,本發明技術可關於一種用於使一半導體晶粒與一帶總成分離之工具,該工具包含:一真空尖端,在該 真空尖端之一表面中具有複數個真空孔,該複數個真空孔用於將一力施加於該半導體晶粒之一表面上,該表面對置於該半導體晶粒之由帶接合之一表面,該複數個真空孔具有跨越該真空尖端之該表面的一非均勻分佈。
在另一實例中,本發明技術關於一種用於使一半導體晶粒與一帶總成分離之工具,該工具包含:一真空尖端,在該真空尖端之一表面中具有複數個真空孔,該複數個真空孔用於將一力施加於該半導體晶粒之一表面上,該表面對置於該半導體晶粒之由帶接合之一表面,該複數個真空孔將一力施加於該半導體晶粒上,該力在該半導體晶粒之邊緣處比在該半導體晶粒之一中心處大。
在另一實例中,本發明技術關於一種用於使一半導體晶粒與一帶總成分離之工具,該帶總成將非均勻力施加於該半導體晶粒上,該等非均勻力在該半導體晶粒之邊緣處比在該半導體晶粒之一中心處大,該工具包含:用於支撐該半導體晶粒之一支撐表面,該半導體晶粒之一第一表面包括面向該支撐表面之帶;及一真空尖端,在該真空尖端之一表面中具有複數個真空孔,該複數個真空孔用於接收一低壓力,該低壓力將一力施加於該半導體晶粒之一第二表面上,該第二表面對置於該半導體晶粒之由帶接合之該第一表面,該複數個真空孔將一力施加於該半導體晶粒上以抵銷該帶總成在該半導體晶粒上之該等非均勻力。
已出於說明及描述目的而呈現以上詳細描述。其不意欲為詳盡的或將該描述限於所揭示之精確形式。依據以上教
示,許多修改及變化係可能的。選擇所描述之實施例以便最佳解釋所主張之系統之原理及其實務應用,藉此使熟習此項技術者能夠在各種實施例中且以如適合於所考量之特定用途的各種修改來最佳利用所主張之系統。希望方法之範疇由附加於此之申請專利範圍來界定。
20‧‧‧習知半導體封裝
22‧‧‧半導體晶粒
24‧‧‧半導體晶粒
26‧‧‧基板
30‧‧‧焊線
40‧‧‧晶圓
44‧‧‧黏著膜/晶粒附著膜(DAF)帶
50‧‧‧晶粒脫離器工具
52‧‧‧真空夾盤
60‧‧‧拾取工具
62‧‧‧真空尖端
64‧‧‧真空孔
70‧‧‧基板
72‧‧‧氣泡
150‧‧‧基板
170‧‧‧半導體封裝
174‧‧‧控制器晶粒
178‧‧‧焊線
180‧‧‧接觸指
182‧‧‧模製化合物
200‧‧‧半導體晶圓
204‧‧‧晶粒
206‧‧‧膠帶
220‧‧‧脫離器工具
222‧‧‧支撐台
224‧‧‧提取工具
230‧‧‧真空尖端
234‧‧‧真空孔
250‧‧‧基板
252‧‧‧氣泡
圖1為習知半導體晶粒之先前技術邊視圖。
圖2為安裝於DAF帶上之半導體晶圓的先前技術視圖。
圖3為用於使晶圓上之半導體晶粒與DAF帶分離之習知脫離器工具的先前技術側視圖。
圖4為圖3之拾取工具中之習知真空尖端的先前技術仰視圖。
圖5說明歸因於拾取工具之真空力而通過晶粒之橫截面的向上力分佈,及歸因於DAF帶上之晶粒之黏著力而通過晶粒之同一橫截面的向下力分佈。
圖6說明由於圖5之向上力及向下力而產生之淨力。
圖7展示具有習知真空尖端之拾取工具上的彎曲晶粒。
圖8展示安裝於基板上之藉由習知真空尖端拾取的彎曲晶粒。
圖9為展示本發明技術之一實施例之操作的流程圖。
圖10為根據本發明系統之實施例之安裝於膠帶上之半導體晶圓的俯視圖。
圖11為根據本發明技術之實施例之脫離器工具的視圖。
圖12為根據本發明之一實施例之真空尖端的仰視圖。
圖12A為具有例示性尺寸之圖12之真空尖端的仰視圖。
圖13說明歸因於拾取工具之一實施例之真空力而通過晶粒之橫截面的向上力分佈,及歸因於膠帶上之晶粒之黏著力而通過晶粒之同一橫截面的向下力分佈。
圖14說明由於圖13之向上力及向下力而產生之淨力。
圖15展示支撐於本發明技術之拾取工具上的平直晶粒。
圖16展示根據本發明技術之安裝於基板上的平直晶粒。
圖17說明歸因於拾取臂之一替代實施例之真空力而通過晶粒之橫截面的向上力分佈,及歸因於膠帶上之晶粒之黏著力而通過晶粒之同一橫截面的向下力分佈。
圖18說明由於圖17之向上力及向下力而產生之淨力。
圖19展示支撐於本發明技術之拾取臂上的平直晶粒。
圖20展示根據本發明技術之安裝於基板上的平直晶粒。
圖21至圖25為根據本發明系統之另外實施例之真空尖端之替代組態的仰視圖。
圖26為包括藉由本發明系統形成之半導體晶粒之已完成半導體封裝的側視圖。
230‧‧‧真空尖端
234‧‧‧真空孔

Claims (10)

  1. 一種用於使一半導體晶粒與一帶總成(tape assembly)分離之工具,該帶總成施加在圍繞該半導體晶粒之外部周邊處之力大於其施加至該半導體晶粒之一中心之力,該工具包含:一真空尖端,在該真空尖端之一表面之一中心區域中具有一第一複數個真空孔,該第一複數個真空孔用於在該半導體晶粒之一表面上將一第一力施加至該半導體晶粒之該中心,該表面對置於該半導體晶粒之由該帶總成接合之一表面,且該真空尖端在比該中心區域更靠近該表面邊緣之一外部周邊區域處具有一第二複數個真空孔,該第二複數個真空孔用於將一第二力施加至該半導體晶粒之該表面上圍繞該半導體晶粒之外部周邊處,該第二複數個真空孔彼此間比該第一複數個真空孔更加緊密間隔俾使該第二力大於該第一力,該第二力抵消該帶總成施加在圍繞該半導體晶粒之外部周邊處之較大力,該第一力抵消該帶總成施加至該半導體晶粒之該中心之較小力,俾使當該真空尖端自該帶總成將該半導體晶粒提起時該半導體晶粒實質上保持平直(flat)。
  2. 如請求項1之工具,其中該複數個真空孔係以該等真空孔在該真空尖端之一外部周邊處比朝向該真空尖端之一中心密集地提供的一組態予以提供。
  3. 如請求項1之工具,其中該複數個真空孔係以該等真空孔在該晶粒上提供與遠離一邊緣之距離的一平方成比例 地減小之一真空力的一組態予以提供。
  4. 如請求項1之工具,其中該半導體晶粒與該帶總成之間的黏著力界定跨越該半導體晶粒之一表面的一第一力分佈,傳達至該複數個真空孔之一低壓力界定在與該第一力分佈相反之一方向上的一第二力分佈,該第一力分佈與該第二力分佈之間的淨力分佈導致跨越該半導體晶粒之該表面的一均勻力分佈。
  5. 如請求項4之工具,該第一分佈及該第二分佈與距該半導體晶粒之一邊緣之該距離之一平方成比例地變化。
  6. 如請求項1之工具,其中該半導體晶粒與該帶總成之間的黏著力界定跨越該半導體晶粒之一表面的一第一力分佈,傳達至該複數個真空孔之一低壓力界定在與該第一力分佈相反之一方向上的一第二力分佈,該第一力分佈與該第二力分佈之間的該淨力分佈導致一在該半導體晶粒之邊緣處比在該半導體晶粒之一中心處大的力分佈。
  7. 一種用於使一半導體晶粒與一帶總成分離之工具,該帶總成將非均勻力施加於該半導體晶粒上,該等非均勻力在該半導體晶粒之邊緣處比在該半導體晶粒之一中心處大,該工具包含:用於支撐該半導體晶粒之一支撐表面,該半導體晶粒之一第一表面包括面向該支撐表面之該帶總成;及一真空尖端,在該真空尖端之一表面之一中心區域中具有一第一複數個真空孔,該第一複數個真空孔用於接收一低壓力,該低壓力在該半導體晶粒之一第二表面上 將一第一力施加至該半導體晶粒之該中心,該第二表面對置於該半導體晶粒之由該帶總成接合之該第一表面,且該真空尖端在比該中心區域更靠近該表面邊緣之一外部周邊區域處具有一第二複數個真空孔,該第二複數個真空孔用於將一第二力施加至該半導體晶粒之該表面上圍繞該半導體晶粒之外部周邊處,該第二複數個真空孔彼此間比該第一複數個真空孔更加緊密間隔俾使該第二力大於該第一力,該第二力抵消該帶總成施加在圍繞該半導體晶粒之外部周邊處之較大力,該第一力抵消該帶總成施加至該半導體晶粒之該中心之較小力,俾使當該真空尖端自該帶總成將該半導體晶粒提起時該半導體晶粒實質上保持平直。
  8. 如請求項7之工具,其中由該帶總成及該複數個真空孔產生於該半導體晶粒上之淨力為一淨均勻向上力。
  9. 如請求項7之工具,其中該複數個真空孔係以該等真空孔在該真空尖端之一外部周邊處比朝向該真空尖端之一中心密集地提供的一組態予以提供。
  10. 如請求項7之工具,其中該複數個真空孔係以該等真空孔在該晶粒上提供與遠離一邊緣之距離的一平方成比例地減小之一真空力的一組態予以提供。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102881587B (zh) * 2012-10-17 2015-03-25 如皋市大昌电子有限公司 一种叠片二极管制造工艺及其芯片筛盘
US11023606B2 (en) * 2016-10-02 2021-06-01 Vmware, Inc. Systems and methods for dynamically applying information rights management policies to documents
CN106736528B (zh) * 2016-12-30 2019-02-22 湖南先步信息股份有限公司 高效智能标准装配平台
DE102019112318B3 (de) * 2019-05-10 2020-07-23 Witrins S.R.O. Vakuumspannvorrichtung
KR102189274B1 (ko) * 2019-07-02 2020-12-09 세메스 주식회사 다이 픽업 방법 및 다이 픽업 장치

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI283906B (en) * 2001-12-21 2007-07-11 Esec Trading Sa Pick-up tool for mounting semiconductor chips
TW200946427A (en) * 2008-05-07 2009-11-16 Shinkawa Kk Semiconductor die pickup device and pickup metho
TW201001614A (en) * 2008-06-30 2010-01-01 Shinkawa Kk Semiconductor die pickup apparatus and semiconductor die pickup method
TW201033100A (en) * 2009-03-05 2010-09-16 Shinkawa Kk Apparatus and method for picking up semiconductor die

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69133413D1 (de) * 1990-05-07 2004-10-21 Canon Kk Substratträger des Vakuumtyps
US5660380A (en) * 1995-08-15 1997-08-26 W. L. Gore & Associates, Inc. Vacuum fixture and method for dimensioning and manipulating materials
JP2003059955A (ja) * 2001-08-08 2003-02-28 Matsushita Electric Ind Co Ltd 電子部品実装装置および電子部品実装方法
JP4266106B2 (ja) 2001-09-27 2009-05-20 株式会社東芝 粘着性テープの剥離装置、粘着性テープの剥離方法、半導体チップのピックアップ装置、半導体チップのピックアップ方法及び半導体装置の製造方法
US6889427B2 (en) * 2002-02-15 2005-05-10 Freescale Semiconductor, Inc. Process for disengaging semiconductor die from an adhesive film
TWI225279B (en) * 2002-03-11 2004-12-11 Hitachi Ltd Semiconductor device and its manufacturing method
EP1535312B1 (en) 2002-07-17 2007-09-26 Matsushita Electric Industrial Co., Ltd. Method and apparatus for picking up semiconductor chip and suction and exfoliation tool up therefor
KR100480628B1 (ko) * 2002-11-11 2005-03-31 삼성전자주식회사 에어 블로잉을 이용한 칩 픽업 방법 및 장치
US7306695B2 (en) 2003-04-10 2007-12-11 Matsushita Electric Industrial Co., Ltd. Apparatus and method for picking up semiconductor chip
US7028396B2 (en) 2003-04-14 2006-04-18 Texas Instruments Incorporated Semiconductor chip pick and place process and equipment
US7650688B2 (en) * 2003-12-31 2010-01-26 Chippac, Inc. Bonding tool for mounting semiconductor chips
US20050274457A1 (en) * 2004-05-28 2005-12-15 Asm Assembly Automation Ltd. Peeling device for chip detachment
JP4541807B2 (ja) * 2004-09-03 2010-09-08 Okiセミコンダクタ株式会社 半導体素子保持装置および半導体素子の搬送方法
US7238258B2 (en) * 2005-04-22 2007-07-03 Stats Chippac Ltd. System for peeling semiconductor chips from tape
KR100834837B1 (ko) * 2006-12-29 2008-06-03 삼성전자주식회사 반도체 다이 픽업 장치와 이를 이용한 반도체 다이 픽업방법
US7607647B2 (en) * 2007-03-20 2009-10-27 Kla-Tencor Technologies Corporation Stabilizing a substrate using a vacuum preload air bearing chuck
JP2008290170A (ja) 2007-05-23 2008-12-04 Renesas Technology Corp 半導体装置の製造方法
US8141612B2 (en) * 2009-04-02 2012-03-27 Asm Assembly Automation Ltd Device for thin die detachment and pick-up

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI283906B (en) * 2001-12-21 2007-07-11 Esec Trading Sa Pick-up tool for mounting semiconductor chips
TW200946427A (en) * 2008-05-07 2009-11-16 Shinkawa Kk Semiconductor die pickup device and pickup metho
TW201001614A (en) * 2008-06-30 2010-01-01 Shinkawa Kk Semiconductor die pickup apparatus and semiconductor die pickup method
TW201033100A (en) * 2009-03-05 2010-09-16 Shinkawa Kk Apparatus and method for picking up semiconductor die

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