TWI467731B - 半導體封裝件及其製法 - Google Patents
半導體封裝件及其製法 Download PDFInfo
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Description
本發明係有關一種半導體封裝件,尤指一種具堆疊晶片之半導體封裝件及其製法。
早期多晶片封裝結構係採用並排式(side-by-side),其因具有封裝成本太高及結構尺寸太大等缺點,故近年來係使用垂直式之堆疊方法增加晶片之數量以節省基板使用空間;堆疊的方式係依晶片之設計而定,且其打線(wire bonding)製程係依堆疊之方式而有所不同,例如:電子裝置中之記憶卡所設之快閃記憶體晶片(flash memory chip)或動態隨機存取記憶體晶片(Dynamic Random Access Memory,DRAM)等。
如第1A圖所示,習知半導體封裝件1(省略封裝膠體之繪示)係堆疊複數記憶體晶片11於一承載板10上,且各該記憶體晶片11係呈階梯狀堆疊,並透過複數銲線12將該些記憶體晶片11之電極墊110電性連接至該承載板10之電性連接墊100。
然而,階狀堆疊係以偏移一距離後進行堆疊,故當堆疊愈多晶片時,最上方之記憶體晶片11所涵蓋該承載板10之面積愈大,而會增加該承載板10之使用面積,亦即增加無作用區域L,而不利於封裝件微小化之需求。
再者,各該記憶體晶片11均須進行打線製程,故當堆疊該記憶體晶片11之數量越多時,打線處之數量亦越多,使該銲線12之佈設更加密集,致使該半導體封裝件1需更多的銲線12佈設空間,而不利於該半導體封裝件1之體積的縮減,導致該半導體封裝件1之尺寸難以符合微小化之需求。
因此,遂發展出一種應用於堆疊結構之電性連接技術,如第20090068790號美國專利,其係於各晶片上利用重佈線路層(Redistribution layer,RDL)製程形成複數向外凸出之信號端,由晶片內部之線路作為傳導路徑,以於各晶片垂直堆疊於一基板上後,能以點膠方式由複數導電膠體電性連接各信號端至該基板,使所需之佈設空間小於以銲線為電性連接介質之習知封裝件所需之佈設空間,故可縮減該基板之尺寸,使該半導體封裝件符合封裝件微小化之需求。
再者,藉由上述方式,可形成如第1B圖所示之半導體封裝件1’(省略封裝膠體之繪示),即各該記憶體晶片11所構成之階梯狀堆疊結構係透過複數導電膠體12’電性連接該承載板10。
惟,上述兩種應用導電膠體12’之習知技術中,該導電膠體12’之寬度較習知銲線12之寬度大,故該承載板10上之任二相鄰之電性連接墊100之間距D需夠大(如第1B’圖所示,該間距D約大於200um),以避免各該導電膠體12’相接觸而造成短路,致使該承載板10需具有較大的承載面積以佈設該些電性連接墊100,導致該承載板10仍需維持一定尺寸而難以再縮小,以致於無法進一步微小化封裝件。
再者,形成該導電膠體12’之製程,需在每一層記憶體晶片11上形成RDL,故相較於習用之打線製程,不僅成本較高,且因技術尚未成熟而造成產品生產之產能(Unit Per Hour,UPH)較低;若為了省成本,僅增加信號端而未於記憶體晶片11上形成RDL,堆疊晶片之數量則將受限。
又,於後續製程中,設置一控制晶片(未圖示)於最上層之記憶體晶片11上時,若該控制晶片為不良品,則會直接影響產品整體電性良率。
另外,晶片研磨技術已達瓶頸,使其晶片薄化有其限度,且該半導體封裝件之整體厚度需加上該控制晶片之厚度,故難以進一步薄化製成之半導體封裝件。
因此,如何克服上述習知技術中之種種問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失,本發明係提供一種半導體封裝件,係包括:封裝膠體,係具有相對之第一表面與第二表面,且於該封裝膠體之第一表面上形成有至少一開孔;複數第一半導體元件,係相互堆疊且封埋於該封裝膠體中;導電層,係形成於該些第一半導體元件所堆疊成之結構表面,以電性導通各該第一半導體元件,且至少一該第一半導體元件上之部分導電層外露出該開孔;以及第一線路層,係形成於該封裝膠體之第一表面上,以經該開孔電性連接該導電層。
前述之半導體封裝件中,復包括設於該封裝膠體之第二表面上的散熱結構。
本發明復提供一種半導體封裝件之製法,係包括:堆疊複數第一半導體元件於一承載板上;於該些第一半導體元件所堆疊成之結構表面上形成導電層,以電性導通各該第一半導體元件;形成封裝膠體於該承載板上,以包覆各該第一半導體元件與導電層,且該封裝膠體具有相對之第一表面與第二表面,該第二表面係結合至該承載板;形成至少一開孔於至少一該封裝膠體之第一表面上,以令該第一半導體元件上之部分導電層外露出該開孔;以及形成第一線路層於該封裝膠體之第一表面上,且該第一線路層經該開孔電性連接該導電層。
前述之製法中,係以雷射方式形成該開孔。
前述之製法中,該承載板係為散熱結構。
前述之半導體封裝件及其製法中,該些第一半導體元件之堆疊方式係為階梯狀堆疊。
前述之半導體封裝件及其製法中,復包括形成絕緣層於該些第一半導體元件之表面上,且該絕緣層露出該第一半導體元件之部分表面,令該導電層復形成於該絕緣層上。
前述之半導體封裝件及其製法中,係移除該承載板,以露出該第一半導體元件與該封裝膠體之第二表面。因此,係形成第二線路層於該封裝膠體之第二表面上,使該第二線路層電性連接該第一半導體元件,且置放至少一第二半導體元件於該第二線路層上,以電性連接該第二線路層。
前述之半導體封裝件及其製法中,該承載板上復設置有至少一第二半導體元件,令該封裝膠體復包覆該第二半導體元件,且該第二半導體元件係電性連接該第一半導體元件。例如,該導電層復延伸形成於該承載板之表面與該第二半導體元件之表面,使該第二半導體元件電性連接該第一半導體元件。
另外,該承載板上復具有線路增層結構,該些第一與第二半導體元件係設於該線路增層結構上並電性連接該線路增層結構,且該封裝膠體之第二表面係結合該線路增層結構。該線路增層結構具有至少一介電層與形成於該介電層上之第二線路層,該第二線路層係電性連接該第一與第二半導體元件。
由上可知,本發明之半導體封裝件及製法中,係藉由該導電層之設計、封裝膠體形成開孔之技術、及於該封裝膠體上進行RDL製程,減少製程步驟,以降低成本,並可達到產品微小化之目的。
再者,相較於打線製程,本發明無需考量弧線之高度,故可降低該封裝膠體之高度,以利於產品微小化之需求。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“下”、“底”、“側”、“第一”、“第二”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。例如,本發明中,第一半導體元件之“第一”係指堆疊於承載板上之半導體元件,而非限定所有第一半導體元件皆為相同之元件或晶片。
請參閱第2A至2F圖,係為本發明之半導體封裝件2之製法之第一實施例之剖面示意圖。
如第2A圖所示,以階梯狀堆疊方式堆疊複數第一半導體元件21於一承載板20上。
於本實施例中,該承載板20之種類可依需求作選擇,例如,僅具承載功能、具散熱功能、具電性功能等,而於本實施例中係僅作承載之用,因而選擇石英板。
再者,該承載板20乃藉由一固著層200結合最下層之第一半導體元件21,且該固著層200之種類繁多,例如:光學膜(如UV film)、膠層、離型膜(release film)等,並無特別限制,而於本實施例中係以光學膜(如UV film)為例。
又,該些第一半導體元件21係為記憶體晶片並具有複數電極墊210,且該些第一半導體元件21之間亦係利用黏著層211結合。
另外,有關堆疊該些第一半導體元件21之方式繁多,例如垂直對齊堆疊,並不限於上述。
如第2B圖所示,形成一導電層22於該些第一半導體元件21之表面上,以藉由該導電層22電性連接該電極墊210,使各該第一半導體元件21之間相互電性導通。
於本實施例中,該導電層22為金屬層,例如,藉由奈米金屬(如奈米銀)噴印技術形成該導電層22,使該導電層22沿該些第一半導體元件21所構成之階梯狀結構佈設,亦即形成於該電極墊210與該些第一半導體元件21之側面上。
再者,亦可依需求,先噴印一絕緣層(圖未示)於該些第一半導體元件21之表面上,再於該絕緣層上形成複數開口以露出欲電性導通之電極墊210,再於該絕緣層上形成該導電層22,以選擇該些第一半導體元件21彼此之間電性導通的對象;例如,令第2B圖所示之最上層與最下層的第一半導體元件21兩者電性導通,而中間兩第一半導體元件21電性導通。
如第2C圖所示,接續第2B圖之製程,形成封裝膠體23於該承載板20上,以包覆各該第一半導體元件21與導電層22,且該封裝膠體23具有相對之第一表面23a(圖式中之上表面)與第二表面23b(圖式中之下表面),且該第二表面23b係結合該承載板20之固著層200。
接著,以雷射形成複數開孔230於該封裝膠體23之第一表面23a上,以令至少一該第一半導體元件21上之部分導電層22外露出該些開孔230。
於本實施例中,係藉由紫外光雷射剝離(UV laser ablation)技術將該封裝膠體23之第一表面23a燒蝕出該些開孔230。再者,該些開孔230係對應外露出最上層之第一半導體元件21之電極墊210上之導電層22。
再者,相較於打線製程,本發明因無需考量銲線線弧(wireloop)之高度,故可降低該封裝膠體23之高度,而利於製成品微小化之需求。
如第2D圖所示,以重佈線路層(Redistribution layer,RDL)製程,形成一第一線路層24於該封裝膠體23之第一表面23a上,且該第一線路層24經該些開孔230電性連接該電極墊210與該導電層22。
於本實施例中,該第一線路層24上係結合複數導電元件240,如銲球,以電性連接其他半導體封裝件(圖略)或如電路板之電子裝置(圖略)。
如第2E圖所示,移除該承載板20,以露出該第一半導體元件21與該封裝膠體23之第二表面23b,使該第一半導體元件21之底部能直接向外散熱。
於本實施例中,係利用紫外光雷射曝光脫膜技術,將該承載板20移除,且該固著層200可選擇留在該封裝膠體23之第二表面23b上供保護晶片之用或隨該承載板20一併移除。
再者,如第2E’圖所示,於第2B圖所示之製作該導電層22之製程中,該導電層22’係可延伸至該承載板20之表面上;故當移除該承載板20之後,可利用重佈線路層(RDL)製程,形成一第二線路層25於該封裝膠體23之第二表面23b與該第一半導體元件21上,使該第二線路層25電性連接該第一半導體元件21。
又,本發明藉由移除該承載板20與固著層200,可大幅降低製成品之整體厚度,以利於達到薄化之需求。
另外,於其它實施例中,若該承載板20具散熱功能(如作為散熱結構)或其它功能,則不需移除該承載板20。
如第2F或2F’圖所示,接續第2E或2E’圖之製程,係沿如第2E圖之切割路徑Y進行切單製程,以形成複數個半導體封裝件2,2’。
本發明藉由奈米金屬噴印技術製作該導電層22,相較於習知技術,不僅成本低,且因技術成熟而能提高產品生產之產能(Unit Per Hour,UPH)。
再者,藉由紫外光雷射剝離技術形成該些開孔230,亦可使成本較低,且能提高產品生產之產能。
又,僅需於該封裝膠體23之第一表面23a上進行RDL製程以形成該第一線路層24,而不需如習知技術於每一層記憶體晶片11進行RDL製程,故不僅能有效降低成本及提高產能,且堆疊晶片之數量不會受到限制。
另外,若接續第2E’圖之製程,可置放一具有複數電極墊260之第二半導體元件26於該封裝膠體23之第二表面23b上,且該第二半導體元件26電性連接該第二線路層25,以形成堆疊封裝結構(Package on Packge,POP),如第2F’圖所示。此外,亦先經測試後,再將該半導體封裝件2’與第二半導體元件26進行堆疊,以確保良率。
於本實施例中,該第二半導體元件26係為邏輯控制晶片,因該第二半導體元件26先經測試後再堆疊於矽晶片上,故可降低後端熱製程所產生的製程問題,如熱膨脹係數(Coefficient of thermal expansion,CTE)影響較低,以避免影響製成品之整體電性良率。
請參閱第3A至3C圖,係為本發明之半導體封裝件3之製法之第二實施例之剖面示意圖。本實施例與第一實施例之差異在於第二半導體元件36之設置方式與電性連接方式,而其它相關製程均大致相同,故不再贅述相同製程。
如第3A圖所示,於堆疊該些第一半導體元件21時,亦置放至少一具有複數電極墊360之第二半導體元件36於該承載板20上,且該第二半導體元件36位於該些第一半導體元件21所構成之階梯狀結構的側方。
接著,形成一導電層32於該些第一半導體元件21之表面、該承載板20之表面與該第二半導體元件36之表面上,使該第二半導體元件36藉由該導電層32電性連接該第一半導體元件21。
其中,有關該第一與第二半導體元件21,36兩者間之電性連接之方式繁多,並不限於上述,亦可以打線方式或如第2E’圖之第二線路層25製程。
如第3B圖所示,進行如第2C至2D圖所示之封裝製程與RDL製程。
如第3C圖所示,移除該承載板20,以露出該封裝膠體23之第二表面23b、部分導電層32、該第一及第二半導體元件21,36,再進行切單製程。
再者,亦可於該封裝膠體23之第二表面23b上進行重佈線路層(RDL)製程,使該第二線路層(圖未示)電性連接該第一與第二半導體元件21,36,且該第二線路層可外接其它電子元件(圖未示)。
又,本發明藉由將該第二半導體元件36設於該些第一半導體元件21所構成之階梯狀結構的側方,可降低整體結構之高度,以克服晶片研磨技術呈現瓶頸所造成的影響,故此設計有利於產品薄化之需求。
另外,即使以打線方式電性連接該第一與第二半導體元件21,36,其弧線高度仍不會影響整體結構高度,故可達到薄化之需求。
請參閱第4A至4B圖,係為本發明之半導體封裝件4之製法之第三實施例之剖面示意圖。本實施例與第二實施例之差異在於第二半導體元件46之位置、第二線路層45之製程及第一線路層44之態樣,而其它相關製程大致相同,故不再贅述相同製程。
如第4A及4A’圖所示,先於該承載板40上形成線路增層結構,該線路增層結構具有至少一介電層40a及設於該介電層40a上之第二線路層45。
於本實施例中,該第二線路層45具有複數電性連接墊45a,45b,且該電性連接墊45a,45b可為打線墊、覆晶銲墊或其它類型。
再者,該線路增層結構之態樣繁多,並不限於圖式中之態樣,特此述明。
如第4B圖所示,於後續製程中,該第二半導體元件46係設於該些第一半導體元件21所構成之階梯狀結構的下方的收納空間S,且該些第一半導體元件21係以該導電層42電性連接該電性連接墊45a,而該第二半導體元件46之電極墊460係以銲線47電性連接該電性連接墊45b。
之後,再移除該承載板40。若該承載板40為金屬材質,因可作為散熱板,故可不需移除該承載板40。
於本實施例中,該第一線路層44係嵌埋於該封裝膠體23之第一表面23a中,而該第二半導體元件46係為控制晶片。
再者,因該導電層42之寬度遠小於習知技術之導電膠體,故該承載板40上之各該電性連接墊45a之間的距離能大幅縮小,使該承載板40之尺寸可依需求縮小,進而縮小該封裝膠體23之尺寸,因而有利於製成品微小化之需求。
又,當階狀堆疊愈多晶片時,可利用該階梯狀結構的下方的收納空間S放置該第二半導體元件46,以有效利用該承載板40上之區域,而避免形成習知技術中之無作用區域。
另外,將該第二半導體元件46放置於該收納空間S,可縮小該承載板40之使用面積(即該介電層40a之使用面積),且降低整體結構之高度,以克服晶片研磨技術呈現瓶頸所造成的影響,故此設計有利於製成品微小化之需求。
本發明復提供一種半導體封裝件2,2’,3,4,係包括:具有相對之第一表面23a與第二表面23b的封裝膠體23、相互堆疊且封埋於該封裝膠體23中之複數第一半導體元件21、埋設於該封裝膠體23中之導電層22,22’,32,42、以及形成於該封裝膠體22之第一表面23a上的第一線路層24,44。
所述之封裝膠體23之第一表面23a上形成有複數開孔230。
所述之第一半導體元件21之堆疊方式係為階梯狀堆疊。
所述之導電層22,22’,32,42係形成於該些第一半導體元件21之表面上,以電性導通各該第一半導體元件21,且令該最上層之第一半導體元件21上之部分導電層22,22’,32,42外露於該開孔230。又該第一半導體元件21之表面上復可具有絕緣層(圖略),且該絕緣層露出該第一半導體元件之部分表面,令該導電層22,22’,32,42形成於該絕緣層與該第一半導體元件21之外露表面。
所述之第一線路層24,44係經該些開孔230電性連接該第一半導體元件21與該導電層22,22’,32,42,且該第一線路層44可選擇性嵌埋於該封裝膠體23之第一表面23a中。
於其中一半導體封裝件2,2’之實施例中,該第一半導體元件21係外露於該封裝膠體23之第二表面23b。
於其中一半導體封裝件2’之實施例中,復包括一第二線路層25,係設於該封裝膠體23之第二表面23b上以供結合一第二半導體元件26,且該第二半導體元件26可藉由該第二線路層25電性連接該第一半導體元件21。
於其中一半導體封裝件3之實施例中,所述之第二半導體元件36係嵌埋於該封裝膠體23之第二表面23b中,且電性連接該第一半導體元件21,例如:該導電層32復延伸於該封裝膠體23之第二表面23b與該第二半導體元件36之表面上,使該第二半導體元件36藉由該導電層32電性連接該第一半導體元件21。再者,亦可令該第二線路層25電性連接該第二半導體元件36。
於其中一半導體封裝件4之實施例中,復包括線路增層結構,係形成於該封裝膠體23之第二表面23b上,且電性連接該第一與第二半導體元件21,46。
所述之線路增層結構具有至少一介電層40a及設於該介電層40a上之第二線路層45,該第二線路層45係電性連接該第一與第二半導體元件21,46。
另外,該嵌埋式之第二半導體元件36,46可位於該些第一半導體元件21所構成之階梯狀結構的側方、或者該階梯狀結構的下方的收納空間S。
綜上所述,本發明半導體封裝件及製法,主要藉由該導電層之設計、封裝膠體形成開孔之技術、及於該封裝膠體上進行RDL製程,以降低成本而提升與打線結構之產品的競爭力,且避免因邏輯控制晶片良率問題而影響產品整體良率,並可達到產品微小化之目的。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
1,1’,2,2’,3,4...半導體封裝件
10,20,40...承載板
100,45a,45b...電性連接墊
11...記憶體晶片
110,210,260,360,460...電極墊
12,47...銲線
12’...導電膠體
200...固著層
21...第一半導體元件
211...黏著層
22,22’,32,42...導電層
23...封裝膠體
23a...第一表面
23b...第二表面
230...開孔
24,44...第一線路層
240...導電元件
25,45...第二線路層
26,36,46...第二半導體元件
40a...介電層
D...間距
L...無作用區域
S...收納空間
Y...切割路徑
第1A及1B圖係為習知半導體封裝件之不同實施例之剖視示意圖;其中,第1B’圖係為第1B圖之承載板之上視示意圖;
第2A至2F圖係為本發明半導體封裝件之製法之第一實施例之剖面示意圖;其中,第2E’及2F’圖係為第2E及2F圖之另一實施例;
第3A至3C圖係為本發明半導體封裝件之製法之第二實施例之剖面示意圖;以及
第4A至4B圖係為本發明半導體封裝件之製法之第三實施例之剖面示意圖;其中,第4A’圖係為第4A圖之上視示意圖。
2...半導體封裝件
21...第一半導體元件
22...導電層
23...封裝膠體
23a...第一表面
23b...第二表面
230...開孔
24...第一線路層
Claims (27)
- 一種半導體封裝件,係包括:封裝膠體,係具有相對之第一表面與第二表面,且於該封裝膠體之第一表面上形成有至少一開孔;複數第一半導體元件,係相互堆疊且封埋於該封裝膠體中,各該第一半導體元件具有複數電極墊,堆疊之該等第一半導體元件係外露該複數電極墊;導電層,係形成於該些第一半導體元件所堆疊成之結構表面與電極墊表面,以電性導通各該第一半導體元件,且至少一該第一半導體元件上之部分導電層外露出該開孔;以及第一線路層,係形成於該封裝膠體之第一表面上,以經該開孔電性連接該導電層。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該些第一半導體元件之堆疊方式係為階梯狀堆疊。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該第一半導體元件之表面上具有絕緣層,且該絕緣層露出該第一半導體元件之部分表面,令該導電層形成於該絕緣層上且電性連接該第一半導體元件之外露表面。
- 如申請專利範圍第1項所述之半導體封裝件,其中,該第一半導體元件係外露於該封裝膠體之第二表面。
- 如申請專利範圍第1項所述之半導體封裝件,復包括第二線路層,係設於該封裝膠體之第二表面上,且電 性連接該第一半導體元件。
- 如申請專利範圍第5項所述之半導體封裝件,復包括至少一第二半導體元件,係設於該第二線路層上,且電性連接該第二線路層。
- 如申請專利範圍第1項所述之半導體封裝件,復包括至少一第二半導體元件,係嵌埋於該封裝膠體之第二表面中。
- 如申請專利範圍第7項所述之半導體封裝件,其中,該第二半導體元件電性連接該第一半導體元件。
- 如申請專利範圍第8項所述之半導體封裝件,其中,該導電層復形成於該封裝膠體之第二表面與該第二半導體元件之表面上,使該第二半導體元件電性連接該第一半導體元件。
- 如申請專利範圍第7項所述之半導體封裝件,復包括線路增層結構,係形成於該封裝膠體之第二表面上,且電性連接該第一與第二半導體元件。
- 如申請專利範圍第10項所述之半導體封裝件,其中,該線路增層結構具有至少一介電層及設於該介電層上之第二線路層,該第二線路層係電性連接該第一與第二半導體元件。
- 如申請專利範圍第10項所述之半導體封裝件,復包括散熱結構,係設於該線路增層結構上。
- 如申請專利範圍第1項所述之半導體封裝件,復包括散熱結構,係設於該封裝膠體之第二表面上。
- 一種半導體封裝件之製法,係包括:堆疊複數第一半導體元件於一承載板上,各該第一半導體元件具有複數電極墊,堆疊之該等第一半導體元件係外露該複數電極墊;於該些第一半導體元件所堆疊成之結構表面與電極墊表面上形成導電層,以電性導通各該第一半導體元件;形成封裝膠體於該承載板上,以包覆各該第一半導體元件與導電層,且該封裝膠體具有相對之第一表面與第二表面,該第二表面係結合至該承載板;形成至少一開孔於該封裝膠體之第一表面上,以令至少一該第一半導體元件上之部分導電層外露出該開孔;以及形成第一線路層於該封裝膠體之第一表面上,且該第一線路層經該開孔電性連接該導電層。
- 如申請專利範圍第14項所述之半導體封裝件之製法,其中,該些第一半導體元件之堆疊方式係為階梯狀堆疊。
- 如申請專利範圍第14項所述之半導體封裝件之製法,復包括形成該導電層之前,形成絕緣層於該些第一半導體元件之表面上,且該絕緣層露出該第一半導體元件之部分表面,令該導電層復形成於該絕緣層上。
- 如申請專利範圍第14項所述之半導體封裝件之製法,復包括移除該承載板。
- 如申請專利範圍第17項所述之半導體封裝件之製法,復包括形成第二線路層於該封裝膠體之第二表面上,且該第二線路層係電性連接該第一半導體元件。
- 如申請專利範圍第18項所述之半導體封裝件之製法,復包括置放至少一第二半導體元件於該第二線路層上,且該第二半導體元件電性連接該第二線路層。
- 如申請專利範圍第14項所述之半導體封裝件之製法,其中,該承載板上復設置有至少一第二半導體元件,令該封裝膠體復包覆該第二半導體元件。
- 如申請專利範圍第20項所述之半導體封裝件之製法,其中,該第二半導體元件電性連接該第一半導體元件。
- 如申請專利範圍第21項所述之半導體封裝件之製法,其中,該導電層復延伸形成於該承載板之表面與該第二半導體元件之表面,使該第二半導體元件電性連接該第一半導體元件。
- 如申請專利範圍第20項所述之半導體封裝件之製法,其中,該承載板上復具有線路增層結構,該些第一與第二半導體元件係設於該線路增層結構上並電性連接該線路增層結構,且該封裝膠體之第二表面係結合該線路增層結構。
- 如申請專利範圍第23項所述之半導體封裝件之製法,其中,該線路增層結構具有至少一介電層與形成於該介電層上之第二線路層,該第二線路層係電性連接該第一與第二半導體元件。
- 如申請專利範圍第23項所述之半導體封裝件之製法,其中,該承載板係為散熱結構。
- 如申請專利範圍第14項所述之半導體封裝件之製法,其中,該承載板係為散熱結構。
- 如申請專利範圍第14項所述之半導體封裝件之製法,其中,係以雷射方式形成該開孔。
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