TWI452957B - Circuit substrate having multi-layered structure and routing method thereof - Google Patents
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本發明係有關於一種多層電路基板，尤指一種具匯流排之多層電路基板結構及其佈線方法。The present invention relates to a multilayer circuit substrate, and more particularly to a multilayer circuit substrate structure having a bus bar and a wiring method thereof.
近年來，隨著電子產品之小型化、輕量化及高機能化，於是搭載電子零件的電路基板即由單面佈線基板演變成為多層佈線基板，且進行可將更多電路集成於佈線基板上之高密度多層電路基板結構之開發。In recent years, with the miniaturization, weight reduction, and high performance of electronic products, the circuit board on which electronic components are mounted has evolved from a single-sided wiring substrate to a multilayer wiring substrate, and more circuits can be integrated on the wiring substrate. Development of high-density multilayer circuit substrate structures.
在電路系統中，不同的電子裝置間會以匯流排來互相交換資訊，舉例來說，主控晶片會經由匯流排向附屬晶片組發送訊息，或是接收由附屬晶片組所傳遞的訊息，以使各電子裝置間能夠協調運作，並進一步將各自的功能進行整合，以達成電子系統的整體功能。In a circuit system, information is exchanged between different electronic devices by busbars. For example, the master chip sends a message to the attached chipset via the busbar or receives the message transmitted by the attached chipset. The electronic devices can be coordinated to operate, and the respective functions are further integrated to achieve the overall function of the electronic system.
習知的多層電路基板結構中，匯流排的電路佈局通常係利用設置在主控晶片及各附屬晶片一側的區間調整匯流排中整體傳輸線的長度以滿足電路時序的要求，當調整任一區間的傳輸線時，亦必須同時調整其他區間的傳輸線。故這樣的作業方式往往造成佈線的複雜度高，且較耗費時間及材料成本，並可能導致電子產品的效能不穩定。In a conventional multilayer circuit substrate structure, the circuit layout of the bus bar usually adjusts the length of the entire transmission line in the bus bar to meet the circuit timing requirement by using an interval disposed on one side of the main control chip and each auxiliary chip, and adjusts any interval. When the transmission line is used, it is also necessary to adjust the transmission lines of other intervals at the same time. Therefore, such operation methods often result in high wiring complexity, time consuming and material cost, and may result in unstable performance of electronic products.
此外，根據電路設計的電氣特性需求，匯流排中的多條傳輸線需佈設於一電路基板的完整金屬參考面上，以四層電路基板為例，多條傳輸線只能分別設於第一、三層或第二、四層，以避免傳輸線上的訊號受到干擾或破壞，進而導致電子產品的效能衰減，因此為確保電子產品的效能，習知的佈線方式必須使用到較多層數電路基板結構。In addition, according to the electrical characteristic requirements of the circuit design, a plurality of transmission lines in the bus bar need to be disposed on a complete metal reference surface of a circuit substrate. Taking a four-layer circuit substrate as an example, a plurality of transmission lines can only be respectively set in the first and third lines. The layers or the second and fourth layers are used to avoid interference or damage to the signals on the transmission line, thereby causing the performance degradation of the electronic products. Therefore, in order to ensure the performance of the electronic products, the conventional wiring method must use a larger number of circuit substrate structures. .
緣是，本發明人有感於上述缺失之可改善，乃特潛心研究並配合學理之運用，終於提出一種設計合理且有效改善上述缺失之本發明。The reason is that the present inventors have felt that the above-mentioned defects can be improved, and the research and the use of the theory have been painstakingly studied, and finally the present invention which is reasonable in design and effective in improving the above-mentioned defects is proposed.
為了能夠減少匯流排之佈線面積，本發明提供一種多層電路基板結構及其佈線方法，特別是只需要調整一延遲線調整區內的傳輸線，進而降低線路佈局的複雜度及減少作業的時間。In order to reduce the wiring area of the bus bar, the present invention provides a multi-layer circuit substrate structure and a wiring method thereof, and in particular, only needs to adjust a transmission line in a delay line adjustment area, thereby reducing the complexity of the line layout and reducing the operation time.
本發明提供一種多層電路基板結構，其中每一電路基板上設有多數個貫孔，用於提供該些電路基板之間的電性導通，所述多層電路基板結構包括一主控單元、一延遲線調整區、至少一分歧區、至少二附屬單元及一匯流排，該延遲線調整區設置於該主控單元與該分歧區之間，且該至少一分歧區包含有多數個中央節點；該至少二附屬單元設置於該分歧區的二側且對稱該些中央節點。The present invention provides a multi-layer circuit substrate structure, wherein each of the circuit substrates is provided with a plurality of through holes for providing electrical conduction between the circuit substrates, the multi-layer circuit substrate structure including a main control unit and a delay a line adjustment area, at least one divergence area, at least two auxiliary units, and a bus bar, the delay line adjustment area is disposed between the main control unit and the divergent area, and the at least one divergent area includes a plurality of central nodes; At least two accessory units are disposed on two sides of the divergent zone and symmetrically the central nodes.
再者，該匯流排具有多數條第一傳輸線、多數條第二傳輸線及多數條第三傳輸線，其中，該些第一傳輸線自該主控單元延伸通過該延遲線調整區連接該些中央節點，該些第二傳輸線及該些第三傳輸線分別自該至少二附屬單元連接至該些中央節點，且該些第二傳輸線與該些第三傳輸線的長度大致相等。Furthermore, the bus bar has a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of third transmission lines, wherein the first transmission lines extend from the main control unit through the delay line adjustment area to connect the central nodes, The second transmission lines and the third transmission lines are respectively connected to the central nodes from the at least two accessory units, and the second transmission lines are substantially equal in length to the third transmission lines.
本發明另提供一種多層電路基板結構之佈線方法，其包括以下之步驟：首先，在一主控單元的一側設置一延遲線調整區，且該延遲線調整區位於該主控單元與一分歧區之間，以及將至少二附屬單元對稱設置在一分歧區的二側；接著，將多數條傳輸線分別自每一附屬單元以一滿足設計需求之最短路徑連接至該分歧區內的多數個中央節點，其中該些中央節點大致呈一條狀分佈；隨後，將多數條傳輸線分別自該些中央節點連接至該主控單元；最後，於該延遲線調整區內進行延遲線佈局以將各傳輸線的長度調整至可容許的誤差範圍內。The present invention further provides a wiring method for a multi-layer circuit substrate structure, which includes the following steps: First, a delay line adjustment area is disposed on one side of a main control unit, and the delay line adjustment area is located at a different portion of the main control unit Between the zones, and at least two accessory units are symmetrically disposed on two sides of a divergent zone; then, a plurality of transmission lines are respectively connected from each of the accessory cells to a plurality of centrals in the divergent zone with a shortest path satisfying design requirements a node, wherein the central nodes are substantially in a strip shape; subsequently, a plurality of transmission lines are respectively connected to the main control unit from the central nodes; and finally, a delay line layout is performed in the delay line adjustment area to The length is adjusted to within the allowable error range.
綜上所述，本發明之多層電路基板結構中，主控單元與每一附屬單元之間的所有傳輸線的長度大致相等，因此主控單元與每一附屬單元之間的通道電氣特性亦大致相同，以確保匯流排之訊號完整度及訊號的時序要求，降低誤碼的機率。In summary, in the multilayer circuit substrate structure of the present invention, the lengths of all the transmission lines between the main control unit and each of the auxiliary units are substantially equal, so that the electrical characteristics of the channels between the main control unit and each of the auxiliary units are substantially the same. In order to ensure the signal integrity and signal timing requirements of the bus, reduce the probability of bit errors.
又，本發明之佈線方法只需要在延遲線調整區內繞線，以調整各附屬單元與主控單元之間的傳輸路徑長度，因此可大幅減少佈線的複雜度及時間。再者，本發明之佈線方法可提升多層電路基板結構中每一電路基板之空間的利用率，因此能夠使用較少層數的電路基板。Moreover, the wiring method of the present invention only needs to be wound in the delay line adjustment region to adjust the length of the transmission path between each accessory unit and the main control unit, thereby greatly reducing wiring complexity and time. Furthermore, the wiring method of the present invention can improve the utilization of the space of each circuit substrate in the multilayer circuit substrate structure, and thus it is possible to use a circuit board having a small number of layers.
為使能更進一步瞭解本發明之特徵及技術內容，請參閱以下有關本發明之詳細說明與附圖，但是此等說明與所附圖式僅係用來說明本發明，而非對本發明的權利範圍作任何的限制。The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.
請參閱圖1，其顯示本發明多層電路基板結構之較佳實施例之示意圖，所述多層電路基板結構1包括一主控單元10、一延遲線調整區20、至少一分歧區30、至少二附屬單元40及一匯流排50，舉例來說，主控單元10可以為一主控晶片，附屬單元40可以為附屬晶片或DDR系列的記憶體，但此僅為一實施例，本發明並不以此為限，舉凡自一單元傳輸資訊至複數個單元者，均為本發明可應用之範疇。1 is a schematic diagram showing a preferred embodiment of a multi-layer circuit substrate structure of the present invention. The multi-layer circuit substrate structure 1 includes a main control unit 10, a delay line adjustment area 20, at least one divergent area 30, and at least two. The auxiliary unit 40 and the bus bar 50, for example, the main control unit 10 can be a main control chip, and the auxiliary unit 40 can be an auxiliary chip or a DDR series memory, but this is only an embodiment, and the present invention is not To the extent that the information is transmitted from one unit to a plurality of units, the scope of application of the present invention is applicable.
其中，該延遲線調整區20設置在主控單元10與分歧區30之間，至少一分歧區30包含有多數個中央節點31，至少二附屬單元40分別設置在分歧區30的二側並對稱於中央節點31。The delay line adjustment area 20 is disposed between the main control unit 10 and the divergent area 30. The at least one divergence area 30 includes a plurality of central nodes 31, and at least two auxiliary units 40 are respectively disposed on two sides of the divergent area 30 and are symmetric. At the central node 31.
匯流排50具有多數條第一傳輸線51、第二傳輸線52及第三傳輸線53，其中，第一傳輸線51自該主控單元10延伸通過延遲線調整區20，並分別由分歧區30的二側連接到中央節點31，第二傳輸線52及該些第三傳輸線53則分別自該至每一附屬單元40連接到中央節點31。The bus bar 50 has a plurality of first transmission lines 51, a second transmission line 52, and a third transmission line 53, wherein the first transmission line 51 extends from the main control unit 10 through the delay line adjustment area 20 and is respectively disposed on two sides of the divergent area 30. Connected to the central node 31, the second transmission line 52 and the third transmission lines 53 are respectively connected to the central node 31 from the attachment unit 40.
復參閱圖1，首先必須提及，本發明之多層電路基板結構1中疊構有複數層電路基板(圖未示)，但疊構的層數並不限定，每一電路基板具有完整的金屬面(圖未示)，以滿足鄰近的電路基板走線所需，且每一電路基板上還設置有多數個貫孔，以提供複數層電路基板之間的電性導通。具體而言，電路基板可以是一玻璃纖維基板、一陶瓷基板、一金屬氧化基板等介電材料基板，但不以此為限，第一傳輸線51、第二傳輸線52及第三傳輸線53可以是銅線路、銀線路或任何導電材料。Referring to FIG. 1, it must first be mentioned that the multilayer circuit substrate structure 1 of the present invention has a plurality of circuit substrates (not shown) stacked thereon, but the number of layers is not limited, and each circuit substrate has a complete metal. A surface (not shown) is required to meet adjacent circuit substrate traces, and a plurality of through holes are disposed on each circuit substrate to provide electrical conduction between the plurality of circuit boards. Specifically, the circuit substrate may be a substrate of a dielectric material such as a glass fiber substrate, a ceramic substrate, or a metal oxide substrate. However, the first transmission line 51, the second transmission line 52, and the third transmission line 53 may be Copper wire, silver wire or any conductive material.
在本具體實施例中，多層電路基板結構1包含有四層 電路基板，另外，為使能更為了解本發明之多層電路基板結構1的技術特徵，因此將匯流排50之多數條第一傳輸線51分別以51a、51b、51c、51d標示，將多數條第二傳輸線52分別以52a、52b、52c、52d標示，將多數條第三傳輸線53分別以53a、53b、53c、53d標示。In this embodiment, the multilayer circuit substrate structure 1 includes four layers. In addition, in order to enable a better understanding of the technical features of the multilayer circuit substrate structure 1 of the present invention, a plurality of first transmission lines 51 of the bus bar 50 are denoted by 51a, 51b, 51c, 51d, respectively, and a plurality of strips The two transmission lines 52 are denoted by 52a, 52b, 52c, 52d, respectively, and the plurality of third transmission lines 53 are denoted by 53a, 53b, 53c, 53d, respectively.
更詳細地說，第一傳輸線51a、51b係由分歧區30的左側連接到分歧區30內的中央節點31，第一傳輸線51c、51d係由分歧區30的右側連接到分歧區30內的中央節點31，第一傳輸線51a、51b及第一傳輸線51c、51d可採不同層進行佈線，以提升每一電路基板上的面積利用效率，例如第一傳輸線51a、51b係佈設於多層電路基板結構1中的第一層，第一傳輸線51c、51d則佈設於多層電路基板結構1中的第四層，再者，第二傳輸線52a、52b、52c、52d皆佈設在多層電路基板結構1中的第三層，而第三傳輸線53a、53b、53c、53d皆佈設在多層電路基板結構1中的第二層，如此鄰近於第一傳輸線51a、51b、第一傳輸線51c、51d、第二傳輸線52a、52b、52c、52d及第三傳輸線53a、53b、53c、53d之電路基板的相對金屬面為一完整參考面。上述匯流排50於各層的佈線僅為一實施例，舉凡利用兩側於不同層佈線技術達到相對金屬面為完整參考面之目的者，均為本發明之範疇。In more detail, the first transmission lines 51a, 51b are connected to the central node 31 in the divergent region 30 by the left side of the divergent region 30, and the first transmission lines 51c, 51d are connected to the center in the divergent region 30 by the right side of the divergent region 30. The node 31, the first transmission lines 51a, 51b and the first transmission lines 51c, 51d may be wired in different layers to improve the area utilization efficiency on each circuit substrate. For example, the first transmission lines 51a, 51b are disposed on the multilayer circuit substrate structure 1 In the first layer, the first transmission lines 51c, 51d are disposed in the fourth layer of the multilayer circuit substrate structure 1, and the second transmission lines 52a, 52b, 52c, 52d are all disposed in the multilayer circuit substrate structure 1. Three layers, and the third transmission lines 53a, 53b, 53c, 53d are all disposed in the second layer in the multilayer circuit substrate structure 1, so as to be adjacent to the first transmission lines 51a, 51b, the first transmission lines 51c, 51d, the second transmission line 52a, The opposite metal faces of the circuit boards 52b, 52c, 52d and the third transmission lines 53a, 53b, 53c, 53d are a complete reference plane. The wiring of the bus bar 50 in each layer is only an embodiment, and the use of the two-layer different layer wiring technology to achieve the relative metal surface as the complete reference surface is within the scope of the present invention.
此外，當第一附屬單元41、第二附屬單元42與中央節點31電性導通之後，但匯流排50的整體長度仍需進行補償時，由於附屬單元對稱於分歧區30，如此一來第二傳輸線52a的長度便近似於第三傳輸線53a，同理第二傳輸線52b的長度亦近似於第三傳輸線53b，以此類推，故第二傳輸線52與第三傳輸線53不需額外進行繞線補償之動作，只需要透過調整連接中央節點31與主控單元10的第一傳輸線51a、51b、51c、51d來作一補償動作(即於延遲線調整區20內進行佈局作一延長傳輸線的動作，使得各匯流排自主控單元10至附屬單元40的傳輸路徑長度接近或相等)，以大幅減少傳輸線的佈局面積、複雜度及作業的時間。In addition, after the first auxiliary unit 41 and the second auxiliary unit 42 are electrically connected to the central node 31, but the overall length of the bus bar 50 still needs to be compensated, since the auxiliary unit is symmetric to the divergent area 30, the second The length of the transmission line 52a is similar to that of the third transmission line 53a, and the length of the second transmission line 52b is similar to the third transmission line 53b, and so on, so that the second transmission line 52 and the third transmission line 53 do not need additional winding compensation. For the action, only the first transmission line 51a, 51b, 51c, 51d connecting the central node 31 and the main control unit 10 is adjusted to perform a compensation action (ie, the layout in the delay line adjustment area 20 is performed to extend the transmission line, so that The lengths of the transmission paths of the busbar autonomous control unit 10 to the accessory unit 40 are close to or equal to each other to greatly reduce the layout area, complexity, and operation time of the transmission line.
在一變化實施例中，考量應用於不同之系統架構(如記憶體晶片)，本發明之多層電路基板結構1可加入多數個終端電阻60，將其分別設置於中央節點31的二側。具體而言，第一傳輸線51a、51b係由分歧區30的左側連結至中央節點31，故可在與第一傳輸線51a、51b同層右側及底層兩側的電路基板上加入終端電阻60；第一傳輸線51c、51d係由分歧區30的右側連結至中央節點31，故可在與第一傳輸線51c、51d同層左側及頂層兩側的電路基板上加入終端電阻60。據此，本發明之多層電路基板結構1可有效減化終端電阻60佈局的複雜度，並可縮減每一終端電阻60到其所對應的中央節點31的距離，以達到匹配的效果。In a variant embodiment, the application is applied to different system architectures (such as memory chips). The multilayer circuit substrate structure 1 of the present invention can incorporate a plurality of termination resistors 60, which are respectively disposed on two sides of the central node 31. Specifically, the first transmission lines 51a, 51b are connected to the central node 31 by the left side of the divergent region 30, so that the terminating resistor 60 can be added to the circuit substrate on both sides of the right side and the bottom layer of the same layer of the first transmission line 51a, 51b; A transmission line 51c, 51d is connected to the central node 31 by the right side of the branch region 30, so that the terminating resistor 60 can be added to the circuit board on the left side and the top layer of the same layer as the first transmission lines 51c, 51d. Accordingly, the multilayer circuit substrate structure 1 of the present invention can effectively reduce the complexity of the layout of the termination resistor 60, and can reduce the distance of each termination resistor 60 to its corresponding central node 31 to achieve a matching effect.
請參閱圖2，為實現上述之多層電路基板結構1，本發明另提供一種多層電路基板結構1之佈線方法S100，其包括以下之步驟：主要流程步驟包括開始步驟S102，在一主控單元10的一側設置一遲線調整區20，且該遲線調整區20位於該主控單元10與一分歧區30之間，以及將至少二附屬單元40對稱設置於該分歧區30的二側；之後如步驟S104，將第二傳輸線52、53分別自第一附屬單元41及第二附屬單元42以一滿足設計需求之最短路徑連接至該分歧區30的中央節點31，值得一提的是，該些中央節點以長條分佈為擺設原則，且透過左右些微錯開的排列方式，可縮短其條狀分佈的長度。Referring to FIG. 2, in order to realize the above-mentioned multilayer circuit substrate structure 1, the present invention further provides a wiring method S100 for a multilayer circuit substrate structure 1, which comprises the following steps: The main process steps include starting step S102, in a main control unit 10 One side of the delay line adjustment area 20 is disposed, and the late line adjustment area 20 is located between the main control unit 10 and a divergent area 30, and at least two auxiliary units 40 are symmetrically disposed on two sides of the divergent area 30; Then, in step S104, the second transmission lines 52, 53 are respectively connected from the first auxiliary unit 41 and the second auxiliary unit 42 to the central node 31 of the divergent area 30 with a shortest path satisfying the design requirement. It is worth mentioning that The central nodes are arranged in a strip shape, and the length of the strip distribution can be shortened by a slight misalignment arrangement.
如步驟S106，將第一傳輸線51分別自中央節點31的左、右二側連接到主控單元10；之後如步驟S108，在延遲線調整區20內進行延遲線佈局，即作一延長第一傳輸線51的動作，使主控單元10至各附屬單元40之各傳輸線的傳輸路徑長度為接近或相等，並調整長度至可容許的誤差範圍內。In step S106, the first transmission line 51 is respectively connected to the main control unit 10 from the left and right sides of the central node 31; then, in step S108, the delay line layout is performed in the delay line adjustment area 20, that is, an extension first. The operation of the transmission line 51 causes the transmission path lengths of the transmission lines of the main control unit 10 to each of the accessory units 40 to be close or equal, and adjusts the length to within an allowable error range.
額外提及的是，使用本發明之佈線方法只需使用到4層電路基板，而完成佈線後所耗費的總面積約為5000.5mm2 ；一般常用的佈線方法則需使用到6層電路基板，而完成佈線後所耗費的總面積約為9892.97mm2 。Additionally mentioned that, using the wiring method of the invention only to the use of 4-layer circuit board, and the wiring is completed after consuming total area of about 5000.5mm 2; commonly used method of wiring is required to use 6-layer circuit board, The total area consumed after wiring is approximately 9892.97mm 2 .
請參閱圖3，其顯示本發明多層電路基板結構1的第二實施例，其與前一實施例的不同之處在於，根據電路的設計需求，第一附屬單元41及第二附屬單元42能夠以任意角度(例如45度)設置於電路基板上，而第一附屬單元41及第二附屬單元42同樣係對稱於分歧區30內的多數個長條狀分佈的中央節點31，據此，第二傳輸線52的長度同樣接近或相等於第三傳輸線53。因此，本實施例除包含有前一實施例的優點之外，更可廣泛應用於各種平台上。Please refer to FIG. 3, which shows a second embodiment of the multilayer circuit substrate structure 1 of the present invention, which is different from the previous embodiment in that the first auxiliary unit 41 and the second auxiliary unit 42 can be configured according to the design requirements of the circuit. The first auxiliary unit 41 and the second auxiliary unit 42 are symmetrical to the plurality of elongated central nodes 31 in the branching area 30, and the first auxiliary unit 41 and the second auxiliary unit 42 are also symmetrically arranged at any angle (for example, 45 degrees). The length of the second transmission line 52 is also close to or equal to the third transmission line 53. Therefore, the present embodiment can be widely applied to various platforms in addition to the advantages of the previous embodiment.
請參閱圖4，其顯示本發明多層電路基板結構1’的第三實施例，其與前述實施例的不同之處在於，根據電路的效能需求，所述多層電路基板結構1’中包含有一第一附屬單元組41’及一第二附屬單元組42’，即主控單元10係經由匯流排50同時向第一附屬單元組41’及第二附屬單元組42’發送訊息，或係接收由第一附屬單元組41’及第二附屬單元組42’傳遞之訊息。Referring to FIG. 4, there is shown a third embodiment of the multilayer circuit substrate structure 1' of the present invention, which differs from the previous embodiment in that the multilayer circuit substrate structure 1' includes a first An auxiliary unit group 41' and a second auxiliary unit group 42', that is, the main control unit 10 simultaneously sends a message to the first auxiliary unit group 41' and the second auxiliary unit group 42' via the bus bar 50, or is received by The message transmitted by the first subsidiary unit group 41' and the second subsidiary unit group 42'.
所述第一附屬單元組41’與第二附屬單元組42’係對稱設置於第一分歧區30a的二側，具體而言，第一附屬單元組41’具有第一子單元411’及第二子單元412’，且第一子單元411’與第二子單元412’係對稱設置於第二分歧區30b的二側；第二附屬單元組42’具有第三子單元421’及第四子單元422’，且第三子單元421’與第四子單元422’係對稱設置於第三分歧區30c的二側，更詳細地說，第二分歧區30b與第三分歧區30c位於第一分歧區30a的二側且相互對稱。The first auxiliary unit group 41' and the second auxiliary unit group 42' are symmetrically disposed on two sides of the first branching area 30a. Specifically, the first auxiliary unit group 41' has a first sub-unit 411' and a first Two subunits 412', and the first subunit 411' and the second subunit 412' are symmetrically disposed on two sides of the second divergent area 30b; the second subunit unit 42' has the third subunit 421' and the fourth The sub-unit 422', and the third sub-unit 421' and the fourth sub-unit 422' are symmetrically disposed on two sides of the third divergent region 30c. In more detail, the second divergent region 30b and the third divergent region 30c are located at the The two sides of a divergent zone 30a are symmetrical to each other.
據此，當第一附屬單元組41’及第二附屬單元組42’通過第一分歧區30a的中央節點31與主控單元10電性導通後，但匯流排50的整體長度仍需進行補償時，只需要透過調第一傳輸線51來作一補償動作，並於延遲線調整區20內進行佈局，作一繞設第一傳輸線51的動作，使得各第一傳輸線51的傳輸路徑接近或相等，以大幅減少傳輸線的佈局面積、複雜度及作業的時間，並同時提升電子產品的效能。Accordingly, when the first auxiliary unit group 41' and the second auxiliary unit group 42' are electrically connected to the main control unit 10 through the central node 31 of the first branching area 30a, the overall length of the bus bar 50 still needs to be compensated. In this case, only the first transmission line 51 is adjusted to perform a compensation operation, and the layout is performed in the delay line adjustment area 20 to perform an action of winding the first transmission line 51 so that the transmission paths of the first transmission lines 51 are close or equal. To significantly reduce the layout area, complexity and time of the transmission line, while improving the performance of electronic products.
綜上所述，本發明之多層電路基板結構中，主控單元與每一附屬單元之間的通道電氣特性亦大致相同，以確保匯流排之訊號完整度及訊號的時序要求，並降低誤碼的機率。In summary, in the multi-layer circuit substrate structure of the present invention, the electrical characteristics of the channel between the main control unit and each of the auxiliary units are also substantially the same to ensure the signal integrity and signal timing requirements of the bus, and reduce the error. The chance.
又，本發明之佈線方法只需要在延遲線調整區內繞線，以調整主控單元至每一附屬單元之間的傳輸路徑長度，因此可大幅減少佈線的複雜度及時間。再者，本發明之佈線方法可提升多層電路基板結構中每一電路基板之空間的利用率，因此能夠使用較少層數的電路基板。Moreover, the wiring method of the present invention only needs to be wound in the delay line adjustment region to adjust the length of the transmission path between the main control unit and each of the auxiliary units, thereby greatly reducing wiring complexity and time. Furthermore, the wiring method of the present invention can improve the utilization of the space of each circuit substrate in the multilayer circuit substrate structure, and thus it is possible to use a circuit board having a small number of layers.
1、1’．．．多層電路基板結構1, 1’. . . Multilayer circuit substrate structure
10．．．主控單元10. . . Master unit
20．．．延遲線調整區20. . . Delay line adjustment zone
30‧‧‧分歧區30‧‧‧Differs
31‧‧‧中央節點31‧‧‧Central node
30a‧‧‧第一分歧區30a‧‧‧First divergent area
30b‧‧‧第二分歧區30b‧‧‧Second divergence zone
30c‧‧‧第三分歧區30c‧‧‧ Third divergence zone
40‧‧‧附屬單元40‧‧‧Subsidiary unit
41‧‧‧第一附屬單元41‧‧‧First Affiliated Unit
42‧‧‧第二附屬單元42‧‧‧Second subsidiary unit
41’‧‧‧第一附屬單元組41’‧‧‧First Auxiliary Unit Group
411’‧‧‧第一子單元411’‧‧‧ first subunit
412’‧‧‧第二子單元412’‧‧‧Second subunit
42’‧‧‧第二附屬單元組42’‧‧‧Second subsidiary unit
421’‧‧‧第三子單元421’‧‧‧ third subunit
422’‧‧‧第四子單元422’‧‧‧ fourth subunit
50‧‧‧匯流排50‧‧‧ busbar
51、51a、51b、51c、51d‧‧‧第一傳輸線51, 51a, 51b, 51c, 51d‧‧‧ first transmission line
52、52a、52b、52c、52d‧‧‧第二傳輸線52, 52a, 52b, 52c, 52d‧‧‧ second transmission line
53、53a、53b、53c、53d‧‧‧第三傳輸線53, 53a, 53b, 53c, 53d‧‧‧ third transmission line
60‧‧‧終端電阻60‧‧‧ terminating resistor
圖1為本發明之多層電路基板結構之第一實施例之示意圖；1 is a schematic view showing a first embodiment of a multilayer circuit substrate structure of the present invention;
圖2為本發明之多層電路基板結構之佈線方法之流程示意圖；2 is a schematic flow chart of a wiring method of a multilayer circuit substrate structure according to the present invention;
圖3為本發明之多層電路基板結構之第二實施例之示意圖；以及3 is a schematic view showing a second embodiment of the structure of the multilayer circuit substrate of the present invention;
圖4為本發明之多層電路基板結構之第三實施例之示意圖。4 is a schematic view showing a third embodiment of the structure of the multilayer circuit substrate of the present invention.
1．．．多層電路基板結構1. . . Multilayer circuit substrate structure
10．．．主控單元10. . . Master unit
20．．．延遲線調整區20. . . Delay line adjustment zone
30．．．分歧區30. . . Divergent area
31．．．中央節點31. . . Central node
40．．．附屬單元40. . . Affiliated unit
41．．．第一附屬單元41. . . First subsidiary unit
42．．．第二附屬單元42. . . Second subsidiary unit
50．．．匯流排50. . . Busbar
51、51a、51b、51c、51d．．．第一傳輸線51, 51a, 51b, 51c, 51d. . . First transmission line
52、52a、52b、52c、52d．．．第二傳輸線52, 52a, 52b, 52c, 52d. . . Second transmission line
53、53a、53b、53c、53d．．．第三傳輸線53, 53a, 53b, 53c, 53d. . . Third transmission line
60．．．終端電阻60. . . Terminating resistor
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