TW202406421A - Printed circuit board and electronic device including same - Google Patents
Printed circuit board and electronic device including same Download PDFInfo
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- TW202406421A TW202406421A TW112128243A TW112128243A TW202406421A TW 202406421 A TW202406421 A TW 202406421A TW 112128243 A TW112128243 A TW 112128243A TW 112128243 A TW112128243 A TW 112128243A TW 202406421 A TW202406421 A TW 202406421A
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- 239000003990 capacitor Substances 0.000 claims description 28
- 238000000034 method Methods 0.000 description 25
- 230000008054 signal transmission Effects 0.000 description 14
- 238000002955 isolation Methods 0.000 description 8
- 238000009413 insulation Methods 0.000 description 5
- 230000001629 suppression Effects 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0215—Grounding of printed circuits by connection to external grounding means
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0262—Arrangements for regulating voltages or for using plural voltages
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- Structure Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
本發明係關於電子電路技術領域，具體而言，關於一種印刷電路板和包括該印刷電路板的電子設備。The present invention relates to the technical field of electronic circuits, and specifically to a printed circuit board and electronic equipment including the printed circuit board.
得益於半導體技術和電子技術的快速發展，積體電路晶片的積體度亦越來越高。相應地，積體電路晶片包括數量越來越多的電路模組，此等相異的電路模組通常具有各自獨立的功能，上述的電路模組亦稱為IP核。為使得積體電路晶片內的各個電路模組正常運行實現相應的功能，需要向電路模組提供相應的電源電壓。因此，積體電路晶片設置在印刷電路板上，積體電路晶片的電源引腳與印刷電路板中的電源走線電連接，從而積體電路晶片可以藉由印刷電路板接收相應的電源電壓。Thanks to the rapid development of semiconductor technology and electronic technology, integrated circuit chips are becoming more and more integrated. Accordingly, integrated circuit chips include an increasing number of circuit modules. These different circuit modules usually have independent functions. The above-mentioned circuit modules are also called IP cores. In order for each circuit module in the integrated circuit chip to operate normally and achieve corresponding functions, it is necessary to provide corresponding power supply voltage to the circuit module. Therefore, the integrated circuit chip is disposed on the printed circuit board, and the power pins of the integrated circuit chip are electrically connected to the power traces in the printed circuit board, so that the integrated circuit chip can receive the corresponding power voltage through the printed circuit board.
本發明的部分實施例提供一種印刷電路板，利用該印刷電路板，至少可以降低積體電路晶片運行時積體電路晶片中相異電路模組之間的雜訊干擾，即使此等相異的電路模組接收到的電源訊號相同。Some embodiments of the present invention provide a printed circuit board, which can at least reduce noise interference between different circuit modules in the integrated circuit chip when the integrated circuit chip is running, even if these different circuit modules The power signals received by the circuit modules are the same.
如本發明的實施例提供的印刷電路板包括：複數個導電層；以及至少一個絕緣層，前述至少一個絕緣層中的各個絕緣層分別位於前述複數個導電層中相鄰的導電層之間。前述複數個導電層包括用於連接積體電路晶片的複數個引腳的頂導電層，前述頂導電層包括第一導電部分和第二導電部分，前述第一導電部分和前述第二電部分分別用於連接前述積體電路晶片的前述複數個引腳中的第一電源引腳和第二電源引腳。前述複數個導電層包括向前述積體電路晶片傳輸電源訊號的電源走線，前述印刷電路板包括第一電源訊號導通路徑和第二電源訊號導通路徑，前述第一電源訊號導通路徑和前述第二電源訊號導通路徑分別將前述第一導電部分和前述第二導電部分電連接至前述電源走線，以使得前述第一導電部分和前述第二導電部分接收同一電源訊號。前述第一電源訊號導通路徑和前述第二電源訊號導通路徑中的每個至少穿過前述至少一個絕緣層中最靠近前述頂導電層的第一絕緣層。A printed circuit board provided by an embodiment of the present invention includes: a plurality of conductive layers; and at least one insulating layer, each of the at least one insulating layer being located between adjacent conductive layers of the plurality of conductive layers. The plurality of conductive layers include a top conductive layer for connecting a plurality of pins of the integrated circuit chip. The top conductive layer includes a first conductive part and a second conductive part. The first conductive part and the second conductive part are respectively For connecting the first power pin and the second power pin among the plurality of pins of the integrated circuit chip. The plurality of conductive layers include power traces that transmit power signals to the integrated circuit chip. The printed circuit board includes a first power signal conduction path and a second power signal conduction path. The first power signal conduction path and the second power signal conduction path are included in the printed circuit board. The power signal conduction path electrically connects the first conductive part and the second conductive part to the power trace respectively, so that the first conductive part and the second conductive part receive the same power signal. Each of the first power signal conduction path and the second power signal conduction path passes through at least the first insulating layer of the at least one insulating layer closest to the top conductive layer.
在部分實施例中，前述複數個導電層進一步包括底導電層和至少一個中間導電層，前述底導電層、至少前述一個中間導電層和前述頂導電層沿著前述印刷電路板的厚度方向依次層疊，前述至少一個中間導電層包括前述電源走線，前述第一電源訊號導通路徑和前述第二電源訊號導通路徑分別從前述第一導電部分和前述第二導電部分延伸至前述電源走線。In some embodiments, the plurality of conductive layers further include a bottom conductive layer and at least one middle conductive layer, and the bottom conductive layer, at least one middle conductive layer and the top conductive layer are sequentially stacked along the thickness direction of the printed circuit board. The at least one intermediate conductive layer includes the power trace, and the first power signal conduction path and the second power signal conduction path respectively extend from the first conductive part and the second conductive part to the power trace.
在部分實施例中，前述印刷電路板包括分別從前述第一導電部分和前述第二導電部分延伸至前述電源走線的第一盲孔和第二盲孔，前述第一到路徑和前述第二電源訊號導通路徑分別包括前述第一盲孔和前述第二盲孔。In some embodiments, the printed circuit board includes first blind holes and second blind holes respectively extending from the first conductive part and the second conductive part to the power traces, and the first path and the second blind hole extend from the first conductive part to the power trace. The power signal conduction paths respectively include the aforementioned first blind holes and the aforementioned second blind holes.
在部分實施例中，前述複數個導電層進一步包括底導電層和至少一個中間導電層，前述底導電層、至少前述一個中間導電層和前述頂導電層沿著前述印刷電路板的厚度方向依次層疊，前述底導電層包括前述電源走線，前述第一電源訊號導通路徑和前述第二電源訊號導通路徑分別從前述第一導電部分和前述第二導電部分延伸至前述電源走線。In some embodiments, the plurality of conductive layers further include a bottom conductive layer and at least one middle conductive layer, and the bottom conductive layer, at least one middle conductive layer and the top conductive layer are sequentially stacked along the thickness direction of the printed circuit board. , the aforementioned bottom conductive layer includes the aforementioned power trace, and the aforementioned first power signal conduction path and the aforementioned second power signal conduction path extend from the aforementioned first conductive portion and the aforementioned second conductive portion to the aforementioned power trace.
在部分實施例中，前述印刷電路板包括分別從前述第一導電部分和前述第二導電部分延伸至前述電源走線的第一通孔和第二通孔，前述第一電源訊號導通路徑和前述第二電源訊號導通路徑分別包括前述第一通孔和前述第二通孔。In some embodiments, the printed circuit board includes first through holes and second through holes respectively extending from the first conductive part and the second conductive part to the power traces, the first power signal conduction path and the The second power signal conduction paths respectively include the aforementioned first through holes and the aforementioned second through holes.
在部分實施例中，前述頂導電層進一步包括第三導電部分，前述第三導電部分用於連接前述積體電路晶片的前述複數個引腳中的第三電源引腳，前述印刷電路板進一步包括第三電源訊號導通路徑，前述第三電源訊號導通路徑將前述第三部分電連接至前述電源走線，以使前述第一導電部分、前述第二導電部分和前述第三導電部分接收同一電源訊號。In some embodiments, the aforementioned top conductive layer further includes a third conductive portion, the aforementioned third conductive portion is used to connect the third power pin among the aforementioned plurality of pins of the aforementioned integrated circuit chip, and the aforementioned printed circuit board further includes A third power signal conduction path. The third power signal conduction path electrically connects the third part to the power trace, so that the first conductive part, the second conductive part and the third conductive part receive the same power signal. .
本發明的另一實施例提供一種電子設備，包括如前述實施例中任一實施例前述的印刷電路板和積體電路晶片，前述積體電路晶片包括用於接收相同電壓水準的電源訊號的第一電源引腳和第二電源引腳，前述第一電源引腳和前述第二電源引腳分別連接至前述印刷電路板的頂導電層中的第一導電部分和第二導電部分。Another embodiment of the present invention provides an electronic device, including the printed circuit board as described in any of the preceding embodiments and an integrated circuit chip. The integrated circuit chip includes a third circuit breaker for receiving power signals of the same voltage level. A power pin and a second power pin, the first power pin and the second power pin are respectively connected to the first conductive part and the second conductive part in the top conductive layer of the printed circuit board.
在部分實施例中，前述印刷電路板的前述複數個導電層包括接地走線，前述電子設備進一步包括並聯在前述接地走線和前述電源走線之間的至少一個電容器。In some embodiments, the plurality of conductive layers of the printed circuit board include ground traces, and the electronic device further includes at least one capacitor connected in parallel between the ground traces and the power traces.
在部分實施例中，前述積體電路晶片佈置在前述印刷電路板的第一側，前述至少一個電容器佈置在前述印刷電路板的與前述第一側正對的第二側。In some embodiments, the integrated circuit chip is arranged on the first side of the printed circuit board, and the at least one capacitor is arranged on the second side of the printed circuit board that is opposite to the first side.
在部分實施例中，前述積體電路晶片進一步包括第一接地引腳和第二接地引腳，前述印刷電路板進一步包括第一接地訊號導通路徑和第二接地訊號導通路徑，前述第一電源訊號導通路徑、前述第二電源訊號導通路徑、前述第一接地訊號導通路徑和前述第二接地訊號導通路徑分別從前述第一電源引腳、前述第二電源引腳、前述第一接地引腳和前述第二接地引腳沿著前述印刷電路板的厚度方向延伸至前述印刷電路板的第二側，前述至少一個電容器包括連接在前述第一電源訊號導通路徑和前述第一接地訊號導通路徑之間的第一電容器、以及連接在前述第二電源訊號導通路徑和前述第二接地訊號導通路徑之間的第二電容器。In some embodiments, the integrated circuit chip further includes a first ground pin and a second ground pin, the printed circuit board further includes a first ground signal conduction path and a second ground signal conduction path, and the first power signal The conduction path, the aforementioned second power signal conduction path, the aforementioned first ground signal conduction path and the aforementioned second ground signal conduction path are respectively connected from the aforementioned first power pin, the aforementioned second power pin, the aforementioned first ground pin and the aforementioned The second ground pin extends along the thickness direction of the printed circuit board to the second side of the printed circuit board, and the at least one capacitor includes a capacitor connected between the first power signal conduction path and the first ground signal conduction path. A first capacitor, and a second capacitor connected between the second power signal conduction path and the second ground signal conduction path.
在部分實施例中，電子設備進一步包括電壓變換器，前述電壓變換器的電壓輸出端電連接至前述印刷電路板中的前述電源走線。In some embodiments, the electronic device further includes a voltage converter, and the voltage output end of the voltage converter is electrically connected to the power trace in the printed circuit board.
在部分實施例中，前述電壓變換器佈置在前述印刷電路板的前述第一側。In some embodiments, the voltage converter is arranged on the first side of the printed circuit board.
以上概述本發明的部分實施例，基於部分實施例的組合以及相異實施例中特徵的組合可以獲得另外的相異實施例，此等相異實施例同樣屬於本發明的保護範圍。The above summarizes some embodiments of the present invention. Based on the combination of some embodiments and the combination of features in different embodiments, other different embodiments can be obtained. These different embodiments also belong to the protection scope of the present invention.
下述提供本發明的各種實施例的特定細節，以便所屬技術領域中具有通常知識者能夠充分理解和實施本發明的各種實施例。在某些情況下，本發明並沒有示出或詳細描述部分本領域熟知的結構或功能，以避免此等不必要的描述使對本發明的實施例的描述模糊不清。本發明的技術手段可以體現為許多相異的形式和目的，並且不應侷限於本說明書所闡述的實施例。提供此等實施例是為使得本發明的技術手段清楚完整，但前述實施例並不限定本專利申請的保護範圍。The following provides specific details of various embodiments of the invention to enable those of ordinary skill in the art to fully understand and practice the various embodiments of the invention. In some cases, some well-known structures or functions in the art are not shown or described in detail in order to avoid unnecessary description and obscuring the description of the embodiments of the invention. The technical means of the present invention can be embodied in many different forms and purposes, and should not be limited to the embodiments set forth in this specification. These embodiments are provided to make the technical means of the present invention clear and complete, but the aforementioned embodiments do not limit the protection scope of this patent application.
在此，首先對本發明實施例中關於之部分用語進行說明，以便於所屬技術領域中具有通常知識者理解。Here, some terms related to the embodiments of the present invention are first described to facilitate understanding by those with ordinary knowledge in the technical field.
本說明書提到的「電子設備」至少包括印刷電路板和連接在印刷電路板上的積體電路晶片，亦就是說，「電子設備」包括印刷電路板和積體電路晶片的組合體，電子設備亦可以包括另外的機械部件或電氣元件。電子設備的示例包括但不限於主機板、顯卡、電腦、平板電腦、行動通訊裝置等。The "electronic equipment" mentioned in this manual at least includes printed circuit boards and integrated circuit chips connected to the printed circuit board. In other words, "electronic equipment" includes the combination of printed circuit boards and integrated circuit chips. Electronic equipment Additional mechanical components or electrical components may also be included. Examples of electronic devices include, but are not limited to, motherboards, graphics cards, computers, tablets, mobile communication devices, etc.
積體電路晶片中的各個電路模組（IP核）需要相應的電源電壓以實現相應的功能。本發明的發明人認識到，相異電路模組對電源訊號的雜訊有相異的要求。例如，即使兩個相異的電路模組所需要的電源電壓（工作電壓）的電壓值相同，對電源訊號中的紋波訊號的要求亦相異。同時，相異電路模組運行時產生的電源雜訊訊號亦可能存在較大差異。因此，即使在相異電路模組所需的工作電壓的電壓值相同的情況下，亦期望相異電路模組的電源訊號之間較低的耦合度。Each circuit module (IP core) in the integrated circuit chip requires a corresponding power supply voltage to achieve the corresponding function. The inventor of the present invention realized that different circuit modules have different requirements on the noise of the power signal. For example, even if the voltage value of the power supply voltage (working voltage) required by two different circuit modules is the same, the requirements for the ripple signal in the power signal are also different. At the same time, there may also be large differences in the power supply noise signals generated when different circuit modules operate. Therefore, even when the voltage values of the operating voltages required by different circuit modules are the same, a lower degree of coupling between the power signals of different circuit modules is expected.
如本發明的一個實施例，降低積體電路晶片相異電路模組的電源訊號之間較低的耦合度的技術手段是針對積體電路晶片中的相異電路模組在印刷電路板上設計彼此獨立的複數個電源走線。圖1示出該技術手段的示例。如圖1所示，至少採用兩個電源（例如，第一電壓變換器10、第二電壓變換器20）向印刷電路板PB提供輸出電壓。相應地，印刷電路板PB中至少存在彼此獨立的第一電源走線和第二電源走線，分別接收兩個電源輸出的電壓。圖1中的圓點用於示意性地表示印刷電路板PB與積體電路晶片的引腳連接的區域，即圓點可對應於積體電路晶片的引腳。第一電源10的輸出端和積體電路晶片的一部分引腳與印刷電路板PB中的第一電源走線（圖1中未示出）電連接，從而形成第一電源訊號傳輸路徑，第二電源20的輸出端和積體電路晶片的另一部分引腳與印刷電路板PB中的第二電源走線（圖1中未示出）電連接，從而形成第二電源訊號傳輸路徑。在圖1中，第一電源訊號傳輸路徑和第二電源訊號傳輸路徑分別被標識為100和200。因採用兩個獨立的電源向印刷電路板和積體電路晶片供電，印刷電路板中的第一電源走線和第二電源走線亦彼此獨立和隔離，故向積體電路晶片的各個電路模組供電的各電源訊號傳輸路徑彼此之間的干擾雜訊較小。然而，為積體電路晶片中工作電壓相同的各個電路模組仍分別設置對應的獨立電源，這導致電子設備成本的增加。而且，在印刷電路板中設置彼此隔離和獨立的複數個電源走線，這可能限制印刷電路板內的佈線空間，導致包括電源走線在內的部分訊號走線的通流能力較弱。為增強訊號走線的通流能力，需要增加印刷電路板內的導電層的數量，但這進一步導致印刷電路板的製作成本的增加。As one embodiment of the present invention, the technical means to reduce the low coupling degree between the power signals of different circuit modules in the integrated circuit chip is to design the different circuit modules in the integrated circuit chip on the printed circuit board. Multiple power supply traces that are independent of each other. Figure 1 shows an example of this technical means. As shown in FIG. 1 , at least two power supplies (for example, a first voltage converter 10 and a second voltage converter 20 ) are used to provide output voltages to the printed circuit board PB. Correspondingly, there are at least first power traces and second power traces independent of each other in the printed circuit board PB, which respectively receive the voltages output by the two power supplies. The dots in FIG. 1 are used to schematically represent the area where the printed circuit board PB is connected to the pins of the integrated circuit chip, that is, the dots may correspond to the pins of the integrated circuit chip. The output end of the first power supply 10 and part of the pins of the integrated circuit chip are electrically connected to the first power trace (not shown in FIG. 1 ) on the printed circuit board PB, thereby forming a first power signal transmission path, and a second The output end of the power supply 20 and another part of the pins of the integrated circuit chip are electrically connected to the second power trace (not shown in FIG. 1 ) on the printed circuit board PB, thereby forming a second power signal transmission path. In FIG. 1 , the first power signal transmission path and the second power signal transmission path are identified as 100 and 200 respectively. Since two independent power supplies are used to supply power to the printed circuit board and the integrated circuit chip, the first power trace and the second power trace in the printed circuit board are also independent and isolated from each other. Therefore, each circuit module of the integrated circuit chip is supplied with power. The interference noise between each power signal transmission path of the group power supply is small. However, corresponding independent power supplies are still provided for each circuit module with the same operating voltage in the integrated circuit chip, which leads to an increase in the cost of the electronic equipment. Moreover, arranging a plurality of power traces that are isolated and independent from each other in the printed circuit board may limit the wiring space in the printed circuit board, resulting in weak flow capabilities of some signal traces, including the power traces. In order to enhance the flow capacity of signal traces, it is necessary to increase the number of conductive layers in the printed circuit board, but this further leads to an increase in the production cost of the printed circuit board.
圖2圖示如本發明的另一實施例的技術手段，與圖1所示的技術手段相比，圖2的技術手段只採用單個的電源10為印刷電路板上的積體電路晶片內工作電壓相同的電路模組供電。如圖2所示，電源10的電壓輸出路徑上設置有雜訊抑制器件30，利用雜訊抑制器件30可以基於電源10的輸出形成兩路電源訊號。圖2中所示的印刷電路板PB與圖1中所示的印刷電路板相同，第一電源訊號傳輸路徑和第二電源訊號傳輸路徑同樣分別被標識為100和200。雜訊抑制器件30的示例包括但不限於磁珠、零歐姆電阻等。雖然第一電源訊號傳輸路徑和第二電源訊號傳輸路徑傳輸的電源訊號的電壓水準相同，但是，印刷電路板PB中仍需要設置彼此隔離和獨立的複數個電源走線，這同樣不能緩解增加印刷電路板內的訊號走線的通流能力和控制印刷電路板的製作成本之間的矛盾。Figure 2 illustrates a technical means according to another embodiment of the present invention. Compared with the technical means shown in Figure 1, the technical means in Figure 2 only uses a single power supply 10 to operate the integrated circuit chip on the printed circuit board. Circuit modules with the same voltage supply power. As shown in FIG. 2 , a noise suppression device 30 is provided on the voltage output path of the power supply 10 . The noise suppression device 30 can be used to form two power supply signals based on the output of the power supply 10 . The printed circuit board PB shown in FIG. 2 is the same as the printed circuit board shown in FIG. 1 , and the first power signal transmission path and the second power signal transmission path are also marked as 100 and 200 respectively. Examples of the noise suppression device 30 include, but are not limited to, magnetic beads, zero-ohm resistors, and the like. Although the voltage levels of the power signals transmitted by the first power signal transmission path and the second power signal transmission path are the same, a plurality of power traces that are isolated from each other and independent of each other still need to be provided in the printed circuit board PB, which also cannot alleviate the increase in the number of printed circuit boards. There is a conflict between the flow capacity of the signal traces in the circuit board and the manufacturing cost of the printed circuit board.
在本說明書中，以上結合圖1和圖2所說明的為積體電路晶片供電的技術手段可以被稱為第一類技術手段（手段一）。在第一類技術手段中，在印刷電路板內設置彼此獨立和隔離的多條電源走線，當積體電路晶片運行時，該情形等同於印刷電路板內包括複數個彼此獨立的電源訊號，分別向積體電路晶片的相異電源引腳提供電壓，這有利於降低積體電路晶片在運行時相異電源引腳之間的雜訊干擾，進而提升積體電路晶片的工作性能。然而，如前述，這類技術手段導致印刷電路板中的部分訊號走線的通流能力較弱，需要增加印刷電路板的導電層的層數才能提升訊號走線的通流能力，這導致印刷電路板的成本的增加。In this specification, the technical means for supplying power to the integrated circuit chip described above with reference to FIGS. 1 and 2 can be called the first type of technical means (means 1). In the first type of technical means, multiple independent and isolated power traces are provided in the printed circuit board. When the integrated circuit chip is running, the situation is equivalent to the printed circuit board including a plurality of independent power signals. Providing voltages to different power supply pins of the integrated circuit chip respectively can help reduce noise interference between different power supply pins of the integrated circuit chip during operation, thereby improving the operating performance of the integrated circuit chip. However, as mentioned above, this kind of technical means results in weak flow capacity of some signal traces in the printed circuit board. It is necessary to increase the number of conductive layers of the printed circuit board to improve the flow capacity of the signal traces. This results in printed circuit board The cost of circuit boards increases.
一種不增加印刷電路板的成本的解決手段是讓積體電路晶片中可以接收相同電壓水準的相異電源引腳在印刷電路板的表層導電層相互連接，在此的「表層導電層」指的是積體電路晶片安裝至印刷電路板時印刷電路板中距離積體電路晶片最近的導電層，其亦可以理解成下文中提到的「頂導電層」。印刷電路板內不針對接收相同電壓水準的相異電源引腳設置彼此獨立和隔離的複數個電源走線，這時，可以採用單個的電源10為積體電路晶片供電。可以借助圖3來說明該技術手段的示例。在該技術手段中，針對積體電路晶片的接收相同電壓水準的複數個電源引腳，印刷電路板實際上只包括單個的電源訊號傳輸路徑。如圖3所示，電源10的輸出端為積體電路晶片的相異電源引腳供電，與電源10的輸出端連接的各個電源引腳實際上是藉由同一電源訊號傳輸路徑100彼此連通的。在本段結合圖3說明的技術手段可被稱為手段二，在該情形中，印刷電路板中包括電源走線在內的訊號走線的佈線空間受到的限制相對較小，因此有利於增強印刷電路板的訊號走線的通流能力，但是積體電路晶片在運行時相異電源引腳之間的雜訊干擾較明顯，可能導致積體電路晶片運行性能的降低。A solution that does not increase the cost of the printed circuit board is to connect different power pins in the integrated circuit chip that can receive the same voltage level to each other on the surface conductive layer of the printed circuit board. The "surface conductive layer" here refers to It is the conductive layer in the printed circuit board closest to the integrated circuit chip when the integrated circuit chip is installed on the printed circuit board. It can also be understood as the "top conductive layer" mentioned below. Instead of providing a plurality of independent and isolated power traces in the printed circuit board for different power pins receiving the same voltage level, a single power supply 10 can be used to power the integrated circuit chip. An example of this technical approach can be explained with the help of Figure 3 . In this technical approach, the printed circuit board actually only includes a single power signal transmission path for multiple power pins of the integrated circuit chip that receive the same voltage level. As shown in FIG. 3 , the output terminal of the power supply 10 supplies power to different power pins of the integrated circuit chip. Each power pin connected to the output terminal of the power supply 10 is actually connected to each other through the same power signal transmission path 100 . The technical means described in this paragraph in conjunction with Figure 3 can be called means two. In this case, the wiring space for signal traces, including power traces, in the printed circuit board is relatively small, so it is conducive to enhancing The flow capacity of the signal traces on the printed circuit board, but the noise interference between different power pins of the integrated circuit chip is more obvious during operation, which may lead to a reduction in the operating performance of the integrated circuit chip.
本發明的另一實施例提供一種印刷電路板，試圖降低積體電路晶片在運行時相異電源引腳之間的雜訊干擾，同時實現印刷電路板的製作成本的控制和保證印刷電路板中的訊號走線的較強的通流能力。Another embodiment of the present invention provides a printed circuit board that attempts to reduce noise interference between different power supply pins of an integrated circuit chip during operation, while controlling the manufacturing cost of the printed circuit board and ensuring that the printed circuit board The signal routing has strong flow capacity.
如該實施例提供的印刷電路板包括複數個導電層以及至少一個絕緣層，前述至少一個絕緣層中的各個絕緣層分別位於前述複數個導電層中相鄰的導電層之間。圖4示意性地示出印刷電路板的局部截面圖，如圖4所示，印刷電路板包括複數個導電層401、402、403、404、以及位於各導電層中相鄰的導電層之間的絕緣層。印刷電路板的複數個導電層包括用於連接積體電路晶片的複數個引腳的頂導電層401，頂導電層401包括第一導電部分401a和第二導電部分401b，第一導電部分401a和第二電部分401b分別用於連接積體電路晶片的前述複數個引腳中的第一電源引腳和第二電源引腳（圖4中未示出）。前述複數個導電層包括向積體電路晶片傳輸電源訊號的電源走線402，印刷電路板包括第一電源訊號導通路徑d1和第二電源訊號導通路徑d2，第一電源訊號導通路徑d2和第二電源訊號導通路徑d2分別將第一導電部分401a和第二導電部分401b電連接至電源走線402，以使得前述第一導電部分401a和第二導電部分401b接收同一電源訊號。如圖4所示，第一電源訊號導通路徑d1和第二電源訊號導通路徑d2中的每個至少穿過前述至少一個絕緣層中最靠近前述頂導電層的第一絕緣層410。The printed circuit board provided in this embodiment includes a plurality of conductive layers and at least one insulating layer, and each insulating layer of the at least one insulating layer is respectively located between adjacent conductive layers of the plurality of conductive layers. Figure 4 schematically shows a partial cross-sectional view of a printed circuit board. As shown in Figure 4, the printed circuit board includes a plurality of conductive layers 401, 402, 403, 404, and is located between adjacent conductive layers in each conductive layer. of insulation layer. The plurality of conductive layers of the printed circuit board include a top conductive layer 401 for connecting a plurality of pins of the integrated circuit chip. The top conductive layer 401 includes a first conductive portion 401a and a second conductive portion 401b. The first conductive portion 401a and The second electrical part 401b is respectively used to connect the first power pin and the second power pin among the aforementioned plurality of pins of the integrated circuit chip (not shown in FIG. 4 ). The aforementioned plurality of conductive layers include power traces 402 that transmit power signals to the integrated circuit chip. The printed circuit board includes a first power signal conduction path d1 and a second power signal conduction path d2. The first power signal conduction path d2 and the second power signal conduction path d2 are included in the printed circuit board. The power signal conduction path d2 electrically connects the first conductive part 401a and the second conductive part 401b to the power trace 402 respectively, so that the first conductive part 401a and the second conductive part 401b receive the same power signal. As shown in FIG. 4 , each of the first power signal conduction path d1 and the second power signal conduction path d2 at least passes through the first insulating layer 410 of the at least one insulating layer that is closest to the top conductive layer.
能夠理解到的是，圖4所示的截面圖僅用於示意性地表示印刷電路板中與本發明上述實施例關於之技術特徵，而省略其它的與上述實施例中的技術特徵無關的部件或結構。例如，印刷電路板的進一步可包括位於頂導電層401上的阻焊層以及位於底導電層404下方的阻焊層。圖4雖然示出包括四個導電層的印刷電路板，但是，印刷電路板所包含的導電層的數目並不受此限制。又，圖4所示的各個導電層結構並不代表實際的印刷電路板的產品中的導電層，部分導電層可以是連續的板狀結構，亦可以是斷續的圖案化結構。It can be understood that the cross-sectional view shown in FIG. 4 is only used to schematically represent the technical features of the printed circuit board related to the above-mentioned embodiments of the present invention, and other components irrelevant to the technical features of the above-mentioned embodiments are omitted. or structure. For example, the printed circuit board may further include a solder mask layer on the top conductive layer 401 and a solder mask layer below the bottom conductive layer 404 . Although FIG. 4 shows a printed circuit board including four conductive layers, the number of conductive layers included in the printed circuit board is not limited thereto. In addition, the conductive layer structures shown in FIG. 4 do not represent the conductive layers in actual printed circuit board products. Some conductive layers may have a continuous plate-like structure or an intermittent patterned structure.
當積體電路晶片連接於圖4所示的印刷電路板時，頂導電層401中的第一導電部分401a和第二電部分401b可分別與積體電路晶片用於接收相同電壓水準的兩個相異電源引腳（例如，第一電源引腳和第二電源引腳）焊接。積體電路晶片的第一電源引腳和第二電源引腳分別藉由穿過第一絕緣層410的第一電源訊號導通路徑d1和第二電源訊號導通路徑d2與電源走線402電連接。亦就是說，第一電源引腳和第二電源引腳電連接至同一電源走線402，但是，第一電源訊號導通路徑d1和第二電源訊號導通路徑d2的等效電感可以抑制至少一部分雜訊訊號，降低積體電路晶片中與第一電源引腳和第二電源引腳連接的相異電路模組之間的訊號干擾。同時，針對接收相同電壓水準的兩個相異電源引腳，並沒有設置在物理上彼此隔離的複數個電源走線，即相對於前述的手段一，印刷電路板內包括電源走線的訊號走線的空間佈局受到的約束較小，有利於保證訊號走線較強的通流能力。When the integrated circuit chip is connected to the printed circuit board shown in FIG. 4, the first conductive portion 401a and the second electrical portion 401b in the top conductive layer 401 can be used to receive the same voltage level as the integrated circuit chip. Solder dissimilar power pins (eg, first power pin and second power pin). The first power pin and the second power pin of the integrated circuit chip are electrically connected to the power trace 402 through the first power signal conduction path d1 and the second power signal conduction path d2 passing through the first insulating layer 410 respectively. That is to say, the first power pin and the second power pin are electrically connected to the same power trace 402, but the equivalent inductance of the first power signal conduction path d1 and the second power signal conduction path d2 can suppress at least part of the noise. signal to reduce signal interference between different circuit modules connected to the first power pin and the second power pin in the integrated circuit chip. At the same time, for two different power pins receiving the same voltage level, a plurality of power traces that are physically isolated from each other are not provided. That is, compared to the aforementioned method 1, the signal traces including the power traces in the printed circuit board The spatial layout of the lines is less constrained, which is beneficial to ensuring strong flow capacity of the signal traces.
圖5示意性地示出如本發明的另一實施例的印刷電路板的局部截面圖。圖5所示的實施例與圖4所示的實施例大致相同，二者主要的差異在於印刷電路板所包括的導電層的數目以及第一電源訊號導通路徑的長度、第二電源訊號導通路徑的長度方面的差別。在圖4和圖5所示的實施例中，印刷電路板的複數個導電層包括底導電層404/505、和至少一個中間導電層，前述底導電層404/505、前述至少一個中間導電層和前述頂導電層401/501沿著印刷電路板的厚度方向依次層疊，電源走線設402/504設置在前述至少一個中間導電層中，第一電源訊號導通路徑d1和第二電源訊號導通路徑d2分別從前述第一導電部分401a/501a和前述第二導電部分401b/501b延伸至前述電源走線402/504。與圖4所示的實施例相比，圖5所示的印刷電路板中的第一電源訊號導通路徑d1和第二電源訊號導通路徑d2具有更長的長度。當積體電路晶片連接於圖5所示的印刷電路板時，頂導電層501中的第一導電部分501a和第二導電部分501b可分別與積體電路晶片用於接收相同電壓水準的兩個相異電源引腳（例如，第一電源引腳和第二電源引腳）焊接，第一電源引腳和第二電源引腳之間的訊號導通路徑更長，從而能夠進一步降低積體電路晶片中與第一電源引腳和第二電源引腳連接的相異電路模組之間的訊號干擾。Figure 5 schematically shows a partial cross-sectional view of a printed circuit board according to another embodiment of the invention. The embodiment shown in FIG. 5 is substantially the same as the embodiment shown in FIG. 4 . The main difference between the two lies in the number of conductive layers included in the printed circuit board and the lengths of the first power signal conduction path and the second power signal conduction path. difference in length. In the embodiment shown in FIGS. 4 and 5 , the plurality of conductive layers of the printed circuit board include a bottom conductive layer 404/505 and at least one intermediate conductive layer. The aforementioned bottom conductive layer 404/505 and the aforementioned at least one intermediate conductive layer and the aforementioned top conductive layer 401/501 are stacked sequentially along the thickness direction of the printed circuit board. The power trace device 402/504 is provided in the aforementioned at least one middle conductive layer. The first power signal conduction path d1 and the second power signal conduction path d2 extends from the aforementioned first conductive portion 401a/501a and the aforementioned second conductive portion 401b/501b to the aforementioned power trace 402/504 respectively. Compared with the embodiment shown in FIG. 4 , the first power signal conduction path d1 and the second power signal conduction path d2 in the printed circuit board shown in FIG. 5 have a longer length. When the integrated circuit chip is connected to the printed circuit board shown in FIG. 5, the first conductive portion 501a and the second conductive portion 501b in the top conductive layer 501 can be used to receive the same voltage level as the integrated circuit chip. By welding different power pins (for example, the first power pin and the second power pin), the signal conduction path between the first power pin and the second power pin is longer, which can further reduce the cost of the integrated circuit chip. signal interference between different circuit modules connected to the first power pin and the second power pin.
如圖4或圖5所示，第一電源訊號導通路徑d1和第二電源訊號導通路徑d2並沒有穿透印刷電路板的整個厚度，因此，前述印刷電路板包括分別從前述第一導電部分和前述第二導電部分延伸至前述電源走線的第一盲孔和第二盲孔，前述第一電源訊號導通路徑d1和前述第二電源訊號導通路徑d2分別包括前述第一盲孔和前述第二盲孔。第一盲孔和第二盲孔的內壁可塗覆有導電材料。As shown in Figure 4 or Figure 5, the first power signal conduction path d1 and the second power signal conduction path d2 do not penetrate the entire thickness of the printed circuit board. Therefore, the aforementioned printed circuit board includes components from the aforementioned first conductive portion and The second conductive part extends to the first blind hole and the second blind hole of the power trace, and the first power signal conduction path d1 and the second power signal conduction path d2 respectively include the first blind hole and the second blind hole. Blind hole. The inner walls of the first blind hole and the second blind hole may be coated with conductive material.
如本發明的另外的實施例，如圖6所示，印刷電路板的複數個導電層包括頂導電層601、中間導電層602、603、604和底導電層605，底導電層605、中間導電層604、603、602和頂導電層601沿著印刷電路板的厚度方向依次層疊，底導電層605包括電源走線，第一電源訊號導通路徑和第二電源訊號導通路徑分別從頂導電層的第一導電部分601a和第二導電部分601b延伸至電源走線。在該實施例中，第一電源訊號導通路徑d1和第二電源訊號導通路徑d2穿過第一絕緣層610、各個中間導電層之間的絕緣層並與底導電層605的電源走線連接。與圖5所示的實施例類似，第一電源訊號導通路徑d1和第二電源訊號導通路徑d2與各中間導電層之間是絕緣的。相比於圖5所示的實施例，因第一電源訊號導通路徑和第二電源訊號導通路徑分別從頂導電層的第一導電部分601a和第二導電部分601b延伸至底導電層的電源走線，當積體電路晶片的相異電源引腳連接至第一導電部分601a和第二導電部分601b時，上述相異電源引腳之間的訊號導通路徑更長，積體電路晶片中與上述相異電源引腳連接的相異電路模組之間的訊號干擾可以進一步得到抑制。As another embodiment of the present invention, as shown in Figure 6, the plurality of conductive layers of the printed circuit board include a top conductive layer 601, middle conductive layers 602, 603, 604 and a bottom conductive layer 605. The bottom conductive layer 605, the middle conductive layer Layers 604, 603, 602 and the top conductive layer 601 are stacked in sequence along the thickness direction of the printed circuit board. The bottom conductive layer 605 includes power traces. The first power signal conduction path and the second power signal conduction path are respectively formed from the top conductive layer. The first conductive portion 601a and the second conductive portion 601b extend to the power traces. In this embodiment, the first power signal conduction path d1 and the second power signal conduction path d2 pass through the first insulating layer 610 and the insulating layer between the respective intermediate conductive layers and are connected to the power traces of the bottom conductive layer 605 . Similar to the embodiment shown in FIG. 5 , the first power signal conduction path d1 and the second power signal conduction path d2 are insulated from each intermediate conductive layer. Compared with the embodiment shown in FIG. 5, the first power signal conduction path and the second power signal conduction path respectively extend from the first conductive portion 601a and the second conductive portion 601b of the top conductive layer to the power trace of the bottom conductive layer. lines, when different power supply pins of the integrated circuit chip are connected to the first conductive part 601a and the second conductive part 601b, the signal conduction paths between the different power supply pins are longer, and the integrated circuit chip is different from the above-mentioned Signal interference between different circuit modules connected to different power pins can be further suppressed.
在圖6的實施例中，印刷電路板包括分別從第一導電部分601a和第二導電部分601b延伸至底導電層605的電源走線的第一通孔和第二通孔，第一電源訊號導通路徑d1和第二電源訊號導通路徑d2分別包括前述第一通孔和前述第二通孔。第一通孔和第二通孔的內壁可塗覆有導電材料。In the embodiment of FIG. 6 , the printed circuit board includes first and second vias respectively extending from the first conductive portion 601 a and the second conductive portion 601 b to the power traces of the bottom conductive layer 605 , the first power signal The conductive path d1 and the second power signal conductive path d2 respectively include the aforementioned first through hole and the aforementioned second through hole. Inner walls of the first through hole and the second through hole may be coated with conductive material.
在以上結合圖4至圖6描述的印刷電路板的實施例中，僅提到位於某一導電層中的電源走線，但是，這並不意味著印刷電路板的電源走線只能分布於單個的導電層中。如印刷電路板的設計需求，電源走線可以分布於相異的導電層，同一電源走線位於相異導電層中的相異部分可以藉由絕緣層中的過孔相互連接。而且，圖4至圖6實施例中提到的單個單元走線是針對積體電路晶片中接收相同電壓水準的電源引腳設置的。在積體電路晶片包括接收相異電壓水準的複數個電源引腳的情形中，印刷電路板可包括彼此隔離和獨立的多條電源走線。In the embodiments of the printed circuit board described above in conjunction with FIGS. 4 to 6 , only power traces located in a certain conductive layer are mentioned. However, this does not mean that the power traces of the printed circuit board can only be distributed in in a single conductive layer. For example, according to the design requirements of printed circuit boards, power traces can be distributed in different conductive layers, and different parts of the same power trace located in different conductive layers can be connected to each other through vias in the insulating layer. Moreover, the individual cell traces mentioned in the embodiments of FIGS. 4 to 6 are provided for power pins in the integrated circuit chip that receive the same voltage level. In the case where the integrated circuit die includes a plurality of power pins receiving different voltage levels, the printed circuit board may include multiple power traces that are isolated and independent from each other.
圖4至圖6示意性地示出頂導電層的第一導電部分和第二導電部分分別藉由第一電源訊號導通路徑和第二電源訊號導通路徑連接至電源走線。在其他實施例中，頂導電層進一步包括第三導電部分，第三導電部分用於連接前述積體電路晶片的前述複數個引腳中的第三電源引腳，印刷電路板進一步包括第三電源訊號導通路徑，前述第三電源訊號導通路徑將前述第三部分電連接至前述電源走線，以使前述第一導電部分、前述第二導電部分和前述第三導電部分接收同一電源訊號。頂導電層可以包括彼此獨立的任意數量的導電部分，分別用於連接積體電路晶片接收同一電壓水準的電源訊號的相異電源引腳。4 to 6 schematically show that the first conductive portion and the second conductive portion of the top conductive layer are connected to the power traces through the first power signal conduction path and the second power signal conduction path. In other embodiments, the top conductive layer further includes a third conductive portion, the third conductive portion is used to connect the third power supply pin among the plurality of pins of the aforementioned integrated circuit chip, and the printed circuit board further includes a third power supply pin. The signal conduction path, the third power signal conduction path electrically connects the third part to the power trace, so that the first conductive part, the second conductive part and the third conductive part receive the same power signal. The top conductive layer may include any number of conductive portions that are independent of each other and are respectively used to connect different power pins of the integrated circuit chip that receive power signals of the same voltage level.
本發明的另外的實施例提供一種電子設備，該電子設備包括如前述實施例中任一實施例前述的印刷電路板和積體電路晶片，前述積體電路晶片包括用於接收相同電壓水準的電源訊號的第一電源引腳和第二電源引腳，前述第一電源引腳和前述第二電源引腳分別連接至前述印刷電路板的頂導電層中的第一導電部分和第二導電部分。Another embodiment of the present invention provides an electronic device. The electronic device includes a printed circuit board as described in any of the preceding embodiments and an integrated circuit chip. The integrated circuit chip includes a power supply for receiving the same voltage level. The first power pin and the second power pin of the signal are respectively connected to the first conductive part and the second conductive part in the top conductive layer of the printed circuit board.
在該電子設備中，積體電路晶片的第一電源引腳和第二電源引腳分別藉由至少穿過印刷電路板的第一絕緣層的第一電源訊號導通路徑和第二電源訊號導通路徑與電源走線電連接。第一電源訊號導通路徑和第二電源訊號導通路徑增加第一電源引腳和第二電源引腳之間的訊號傳輸路徑的等效電感值，從而可以抑制至少一部分雜訊訊號，降低積體電路晶片中與第一電源引腳和第二電源引腳連接的相異電路模組之間的干擾。同時，不必在印刷電路板中設置用於接收相同電壓水準而在物理上彼此隔離的多條電源走線，相應地，印刷電路板內包括電源走線的訊號走線的空間佈局受到的約束較小，有利於保證較強訊號走線較強的通流能力。同時，僅需要一個電壓源（例如，電壓變換器）向積體電路晶片的第一電源引腳和第二電源引腳供電，避免電子設備元器件成本的增加。In the electronic device, the first power pin and the second power pin of the integrated circuit chip are respectively through a first power signal conduction path and a second power signal conduction path that pass through at least the first insulating layer of the printed circuit board. Electrically connected to power traces. The first power signal conduction path and the second power signal conduction path increase the equivalent inductance value of the signal transmission path between the first power pin and the second power pin, thereby suppressing at least part of the noise signal and reducing the integrated circuit Interference between different circuit modules in the chip connected to the first power pin and the second power pin. At the same time, there is no need to provide multiple power traces in the printed circuit board that are physically isolated from each other for receiving the same voltage level. Correspondingly, the spatial layout of the signal traces including the power traces in the printed circuit board is less constrained. Small, it is helpful to ensure the strong flow capacity of strong signal wiring. At the same time, only one voltage source (eg, voltage converter) is required to supply power to the first power pin and the second power pin of the integrated circuit chip, thereby avoiding an increase in the cost of electronic equipment components.
圖7示意性地示出如本發明的一個實施例提供的電子設備的局部截面圖。該電子設備中的印刷電路板的結構與參照圖3說明的手段二的印刷電路板的結構的主要差異在於接收相同電壓水準的相異電源引腳在印刷電路板中與電源走線相互連接的位置相異，圖3所示的印刷電路板的俯視圖亦可以用來示意性地表示該電子設備中的印刷電路板的俯視圖。圖7所示的局部截面圖可以視為沿著圖3中的線A1-A2獲得的。Figure 7 schematically shows a partial cross-sectional view of an electronic device as provided in one embodiment of the present invention. The main difference between the structure of the printed circuit board in this electronic device and the structure of the printed circuit board of the second method explained with reference to FIG. 3 is that different power supply pins receiving the same voltage level are connected to the power traces in the printed circuit board. Depending on the position, the top view of the printed circuit board shown in FIG. 3 can also be used to schematically represent the top view of the printed circuit board in the electronic device. The partial cross-sectional view shown in Figure 7 can be considered as being taken along line A1-A2 in Figure 3.
圖7示意性地示出佈置在印刷電路板上的積體電路晶片IC，並圖示頂導電層701中的複數個導電部分，包括第一導電部分P1、第二導電部分P2、第三導電部分P3、第四導電部分G1、第五導電部分G2和第六導電部分G3。第一導電部分P1、第二導電部分P2和第三導電部分P3分別與積體電路晶片IC的用於接收相同電壓水準的第一電源引腳、第二電源引腳和第三電源引腳連接，第四導電部分G1、第五導電部分G2和第六導電部分G3分別與積體電路晶片IC的用於接收參考地電壓的第一接地引腳、第二接地引腳和第三接地引腳連接。如圖7所示，印刷電路板包括第一絕緣層710、中間導電層702、703、704以及底導電層704。印刷電路板的複數個導電層包括接地走線和電源走線，接地走線位於中間導電層704中，電源走線位於底導電層705中，積體電路晶片IC的第一接地引腳、第二接地引腳和第三接地引腳均與接地走線電連接，積體電路晶片IC的第一電源引腳、第二電源引腳和第三電源引腳均與電源走線電連接。亦就是說，圖7所示的印刷電路板包括第一電源訊號導通路徑d1、第二電源訊號導通路徑d2和第三電源訊號導通路徑d3，其等分別將第一導電部分P1、第二導電部分P2、第三導電部分P3連接至電源走線，且第一電源訊號導通路徑d1、第二電源訊號導通路徑d2和第三電源訊號導通路徑d3中的每個沿著延伸電路板的厚度方向延伸至底導電層705，從而可以減少積體電路晶片IC中與第一電源引腳、第二電源引腳和第三電源引腳連接的相異電路模組之間的雜訊干擾。第一電源訊號導通路徑d1、第二電源訊號導通路徑d2和第三電源訊號導通路徑d3與底導電層705電連接，而與各個中間導電層相互絕緣。如本發明的該實施例，電子設備進一步包括並聯在接地走線和前述電源走線之間的至少一個電容器。圖7示意性地示出三個電容器C1、C2和C3。7 schematically shows an integrated circuit chip IC arranged on a printed circuit board, and illustrates a plurality of conductive parts in the top conductive layer 701, including a first conductive part P1, a second conductive part P2, a third conductive part Portion P3, fourth conductive portion G1, fifth conductive portion G2 and sixth conductive portion G3. The first conductive part P1, the second conductive part P2 and the third conductive part P3 are respectively connected to the first power pin, the second power pin and the third power pin of the integrated circuit chip IC for receiving the same voltage level. , the fourth conductive part G1, the fifth conductive part G2 and the sixth conductive part G3 are respectively connected with the first ground pin, the second ground pin and the third ground pin of the integrated circuit chip IC for receiving the reference ground voltage. connection. As shown in FIG. 7 , the printed circuit board includes a first insulating layer 710 , intermediate conductive layers 702 , 703 , 704 and a bottom conductive layer 704 . The plurality of conductive layers of the printed circuit board include ground traces and power traces. The ground traces are located in the middle conductive layer 704, and the power traces are located in the bottom conductive layer 705. The first ground pin and the first ground pin of the integrated circuit chip IC The second ground pin and the third ground pin are both electrically connected to the ground trace, and the first power pin, the second power pin and the third power pin of the integrated circuit chip IC are all electrically connected to the power trace. That is to say, the printed circuit board shown in FIG. 7 includes a first power signal conduction path d1, a second power signal conduction path d2 and a third power signal conduction path d3, which respectively connect the first conductive part P1 and the second conductive part P1. The portion P2 and the third conductive portion P3 are connected to the power traces, and each of the first power signal conduction path d1, the second power signal conduction path d2 and the third power signal conduction path d3 extends along the thickness direction of the circuit board Extending to the bottom conductive layer 705 can reduce noise interference between different circuit modules connected to the first power pin, the second power pin and the third power pin in the integrated circuit chip IC. The first power signal conduction path d1, the second power signal conduction path d2 and the third power signal conduction path d3 are electrically connected to the bottom conductive layer 705 and are insulated from each other between the intermediate conductive layers. According to this embodiment of the present invention, the electronic device further includes at least one capacitor connected in parallel between the ground trace and the aforementioned power trace. Figure 7 schematically shows three capacitors C1, C2 and C3.
積體電路晶片與印刷電路板的第一導電部分、第二導電部分和第三導電部分連接的第一電源引腳、第二電源引腳和第三電源引腳連接可分別視為向積體電路晶片內部的相異電路模組供電的三個電壓節點，積體電路晶片的第一電源引腳、第二電源引腳和第三電源引腳分別藉由第一電源訊號導通路徑d1、第二電源訊號導通路徑d2和第三電源訊號導通路徑d3與電源走線電連接，故，並聯在接地走線和電源走線之間的電容器的濾波效果實際上可以為前述的三個電壓節點共享，並降低每個電壓節點處的阻抗。The first power pin, the second power pin and the third power pin connecting the integrated circuit chip to the first conductive part, the second conductive part and the third conductive part of the printed circuit board can be regarded as connected to the integrated circuit chip respectively. Three voltage nodes powered by different circuit modules inside the circuit chip, the first power pin, the second power pin and the third power pin of the integrated circuit chip are respectively through the first power signal conduction path d1, the third power pin The second power signal conduction path d2 and the third power signal conduction path d3 are electrically connected to the power traces. Therefore, the filtering effect of the capacitors connected in parallel between the ground traces and the power traces can actually be shared by the aforementioned three voltage nodes. , and reduce the impedance at each voltage node.
在部分實施例中，積體電路晶片IC佈置在印刷電路板的第一側，前述至少一個電容器佈置在前述印刷電路板的與前述第一側正對的第二側。在圖7所示的實施例中，第一側即為靠近印刷電路板的頂導電層701的一側。當然，圖7中沒有示出印刷電路板與本發明的技術手段不太相關的其它結構，例如阻焊層等。In some embodiments, the integrated circuit chip IC is arranged on a first side of the printed circuit board, and the at least one capacitor is arranged on a second side of the printed circuit board that is opposite to the first side. In the embodiment shown in FIG. 7 , the first side is the side close to the top conductive layer 701 of the printed circuit board. Of course, FIG. 7 does not show other structures of the printed circuit board that are less relevant to the technical means of the present invention, such as solder resist layers.
如本發明的部分實施例，積體電路晶片包括第一接地引腳和第二接地引腳，前述印刷電路板進一步包括第一接地訊號導通路徑和第二接地訊號導通路徑，前述第一電源訊號導通路徑、前述第二電源訊號導通路徑、前述第一接地訊號導通路徑和前述第二接地訊號導通路徑分別從前述第一電源引腳、前述第二電源引腳、前述第一接地引腳和前述第二接地引腳沿著前述印刷電路板的厚度方向延伸至前述印刷電路板的第二側，前述至少一個電容器包括連接在前述第一電源訊號導通路徑和前述第一接地訊號導通路徑之間的第一電容器、以及連接在前述第二電源訊號導通路徑和前述第二接地訊號導通路徑之間的第二電容器。當然，印刷電路板可以包括更多的接到引腳和更多的接地訊號導通路徑。例如，圖7示出第一接地訊號導通路徑e1、第二接地訊號導通路徑e2和、第三接地訊號導通路徑e3。第一電源訊號導通路徑d1、第二電源訊號導通路徑d2、第三電源訊號導通路徑d3、第一接地訊號導通路徑e1、第二接地訊號導通路徑e2和第三接地訊號導通路徑e3分別從第一電源引腳、第二電源引腳、第三電源引腳、第一接地引腳、第二接地引腳和第三接地引腳沿著印刷電路板的厚度方向延伸至印刷電路板的第二側。並聯在電壓走線和接地走線之間的至少一個電容器包括連接在第一電源訊號導通路徑d1和第一接地訊號導通路徑e1之間的第一電容器C1、連接在第二電源訊號導通路徑d2和第二接地訊號導通路徑e2之間的第二電容器C2、以及連接在第三電源訊號導通路徑d3和第三接地訊號導通路徑e3之間的第三電容器C3。As in some embodiments of the present invention, the integrated circuit chip includes a first ground pin and a second ground pin, the printed circuit board further includes a first ground signal conduction path and a second ground signal conduction path, and the first power signal The conduction path, the aforementioned second power signal conduction path, the aforementioned first ground signal conduction path and the aforementioned second ground signal conduction path are respectively connected from the aforementioned first power pin, the aforementioned second power pin, the aforementioned first ground pin and the aforementioned The second ground pin extends along the thickness direction of the printed circuit board to the second side of the printed circuit board, and the at least one capacitor includes a capacitor connected between the first power signal conduction path and the first ground signal conduction path. A first capacitor, and a second capacitor connected between the second power signal conduction path and the second ground signal conduction path. Of course, a printed circuit board can include more pins and more ground signal conduction paths. For example, FIG. 7 shows a first ground signal conduction path e1, a second ground signal conduction path e2, and a third ground signal conduction path e3. The first power signal conduction path d1, the second power signal conduction path d2, the third power signal conduction path d3, the first ground signal conduction path e1, the second ground signal conduction path e2 and the third ground signal conduction path e3 are respectively connected from the A power pin, a second power pin, a third power pin, a first ground pin, a second ground pin and a third ground pin extend along the thickness direction of the printed circuit board to the second side of the printed circuit board. side. At least one capacitor connected in parallel between the voltage trace and the ground trace includes a first capacitor C1 connected between the first power signal conduction path d1 and the first ground signal conduction path e1, a first capacitor C1 connected between the second power signal conduction path d2 and the second capacitor C2 between the second ground signal conduction path e2, and the third capacitor C3 connected between the third power signal conduction path d3 and the third ground signal conduction path e3.
在部分實施例中，電子設備進一步包括電壓變換器，前述電壓變換器的電壓輸出端電連接至前述印刷電路板中的前述電源走線。電壓變換器的示例包括但不限於整流器、直流斬波器以及整流器和直流斬波器的組合。電壓變換器可以將電子設備的外部電源電壓變換為適於積體電路晶片工作所需要的適當電壓。In some embodiments, the electronic device further includes a voltage converter, and the voltage output end of the voltage converter is electrically connected to the power trace in the printed circuit board. Examples of voltage converters include, but are not limited to, rectifiers, DC choppers, and combinations of rectifiers and DC choppers. The voltage converter can convert the external power supply voltage of the electronic device into the appropriate voltage required for the operation of the integrated circuit chip.
在部分實施例中，電壓變換器佈置在前述印刷電路板的前述第一側。亦就是說，與積體電路晶片一樣，電壓變換器亦安裝（例如，藉由焊接）在印刷電路板的第一側。In some embodiments, the voltage converter is arranged on the first side of the printed circuit board. That is, like the integrated circuit chip, the voltage converter is mounted (eg, by soldering) on the first side of the printed circuit board.
圖4至圖7中所示的印刷電路板的各個導電層並不代表實際的印刷電路板產品的結構，而只是用於示意性地表示各導電層與電源訊號導通路徑和接地訊號導通路徑之間的關聯。如本發明的一個實施例，電子設備的印刷電路板包括依次層疊佈置的12層導電層，前述的各個電源訊號導通路徑均延伸至底導電層（第12層導電層）。如前述，積體電路晶片的電源引腳可視為向積體電路晶片供電的電壓節點。圖8圖示在應用本說明書描述的相異技術手段為積體電路晶片供電時電壓節點處的阻抗曲線。上述電壓節點處的阻抗在數值上可以理解為在不向其它電壓節點提供電流而僅在上述電壓節點處注入單位電流時該電壓節點處的電壓。該阻抗在本說明書中亦可稱為電壓節點的自阻抗。圖8圖示電子設備分別應用本說明書中描述的手段一、手段二以及圖7所圖示的實施例的技術手段（在本說明書中稱為手段三）時一個電壓節點處的阻抗曲線。具體而言，圖8中的曲線8a、8b和8c分別表示在應用手段一、手段二和手段三的情況下某一電壓節點的相異頻率下的阻抗。圖9圖示電子設備分別應用本說明書中描述的手段一、手段二以及手段三時另一電壓節點處的阻抗曲線。具體而言，圖9中的曲線9a、9b和9c分別表示在應用手段一、手段二和手段三的情況下該另一電壓節點的相異訊號頻率下的阻抗。The various conductive layers of the printed circuit board shown in Figures 4 to 7 do not represent the structure of the actual printed circuit board product, but are only used to schematically represent the conductive paths between each conductive layer and the power signal conduction path and the ground signal conduction path. connections between. According to one embodiment of the present invention, the printed circuit board of the electronic device includes 12 conductive layers arranged in a stacked manner, and each of the aforementioned power signal conductive paths extends to the bottom conductive layer (the 12th conductive layer). As mentioned above, the power pin of the integrated circuit chip can be regarded as a voltage node that supplies power to the integrated circuit chip. Figure 8 illustrates the impedance curve at the voltage node when applying the different techniques described in this specification to power an integrated circuit chip. The impedance at the above-mentioned voltage node can be understood numerically as the voltage at the voltage node when no current is provided to other voltage nodes and only unit current is injected at the above-mentioned voltage node. This impedance may also be referred to as the self-impedance of the voltage node in this specification. FIG. 8 illustrates the impedance curve at a voltage node when the electronic device applies means 1 and 2 described in this specification and the technical means of the embodiment illustrated in FIG. 7 (referred to as means 3 in this specification) respectively. Specifically, curves 8a, 8b and 8c in Figure 8 respectively represent the impedances at different frequencies of a certain voltage node when applying means one, two and three. Figure 9 illustrates the impedance curve at another voltage node when the electronic device applies method one, method two and method three described in this specification respectively. Specifically, curves 9a, 9b, and 9c in FIG. 9 respectively represent the impedance of the other voltage node at different signal frequencies when the method 1, the method 2, and the method 3 are applied.
在圖8和圖9中，曲線8b和8c彼此近似重合，曲線9b和9c彼此近似重合，為區分起見，曲線8c和9c均以虛線形式示出。從圖8和圖9可以看出，在應用手段二和手段三的情況下，電子設備的電壓節點的阻抗特性基本接近，但是，電子設備的電壓節點的阻抗在採用手段一的情況下變得較大，數值接近於應用手段二和手段三情況下的兩倍。因此，這表明採用本說明書提供的手段三的印刷電路板中的電源走線具有較強的通流能力。In Figures 8 and 9, the curves 8b and 8c approximately coincide with each other, and the curves 9b and 9c approximately coincide with each other. For the sake of distinction, the curves 8c and 9c are both shown in the form of dotted lines. It can be seen from Figure 8 and Figure 9 that when method two and method three are applied, the impedance characteristics of the voltage node of the electronic device are basically close. However, the impedance of the voltage node of the electronic device becomes different when method one is used. Larger, the value is close to twice that of the case of applying method 2 and method 3. Therefore, this shows that the power traces in the printed circuit board using method three provided in this specification have strong current flow capabilities.
圖10圖示分別採用手段一、手段二和手段三的情況下上述的相異電壓節點之間的隔離度，在此的隔離度用於表徵相異電壓節點（即，積體電路晶片的相異電源引腳）之間的雜訊隔離能力。在一個實施例中，兩個電壓節點隔離度L可以表示為L=20*lg(V2/V1)。V1表示在兩個電壓節點中的第一電壓節點處施加的交流訊號的幅值，V2表示因在第一電壓節點處施加的交流訊號而在兩個電壓節點中的第二電壓節點處產生的交流訊號的幅值。因此，隔離度L的值越小意味著兩個電壓節點的隔離度越好。具體而言，圖10中的曲線10a、10b和10c分別表示在應用手段一、手段二和手段三的情況下兩個電壓節點之間的隔離度。從圖10可以看出，採用手段一和手段三的電子設備可以實現相異電壓節點之間高頻雜訊的良好抑制。因此，採用手段三的電子設備能夠保證印刷電路板中的電源走線較強的通流能力，同時可以較好地抑制相異電壓節點（積體電路晶片的相異電源引腳）之間的雜訊干擾。Figure 10 illustrates the isolation between the above-mentioned different voltage nodes when using method 1, method 2 and method 3 respectively. The isolation here is used to characterize the different voltage nodes (ie, the phase of the integrated circuit chip). Noise isolation capability between different power supply pins). In one embodiment, the isolation L of two voltage nodes can be expressed as L=20*lg(V2/V1). V1 represents the amplitude of the AC signal applied at the first voltage node of the two voltage nodes, and V2 represents the amplitude of the AC signal applied at the first voltage node at the second voltage node of the two voltage nodes. Amplitude of AC signal. Therefore, a smaller value of isolation L means better isolation between two voltage nodes. Specifically, curves 10a, 10b and 10c in Figure 10 respectively represent the isolation between two voltage nodes when means one, two and three are applied. It can be seen from Figure 10 that electronic equipment using means 1 and 3 can achieve good suppression of high-frequency noise between nodes with different voltages. Therefore, electronic equipment using method 3 can ensure the strong flow capacity of the power traces in the printed circuit board, and at the same time can better suppress the interference between different voltage nodes (different power pins of integrated circuit chips). Noise interference.
以上描述本發明的部分實施例，「第一」、「第二」、「第三」等術語在本說明書中可以用來描述各種設備、元件、部件或部分，但是此等設備、元件、部件或部分不應當由此等術語限制，僅表示名稱方面的區分。此外，本說明書提到的「電連接」包括「直接連接」或「間接連接」。以上已經結合部分實施例描述本發明的技術手段，但是本發明的保護範圍並不限於在本說明書中所闡述的實施例的特定形式，本發明的範圍由所附申請專利範圍來定義。Some embodiments of the present invention are described above. Terms such as "first", "second" and "third" may be used to describe various devices, components, components or parts in this specification. However, these devices, components, components or part shall not be limited by such terms and shall only indicate a distinction in name. In addition, the "electrical connection" mentioned in this manual includes "direct connection" or "indirect connection". The technical means of the present invention have been described above in conjunction with some embodiments. However, the protection scope of the present invention is not limited to the specific forms of the embodiments described in this specification. The scope of the present invention is defined by the appended patent application scope.
10:第一電壓變換器、第一電源 20:第二電壓變換器、第二電源 100:第一電源訊號傳輸路徑 200:第二電源訊號傳輸路徑 PB:印刷電路板 30:雜訊抑制器件 A1,A2:線 401:頂導電層 401a:第一導電部分 401b:第二導電部分 402:電源走線 403:導電層 404:底導電層 410:第一絕緣層 d1:第一電源訊號導通路徑 d2:第二電源訊號導通路徑 501:頂導電層 501a:第一導電部分 501b:第二導電部分 504:電源走線 505:底導電層 601:頂導電層 601a:第一導電部分 601b:第二導電部分 602,603,604:中間導電層 605:底導電層 610:第一絕緣層 701:頂導電層 702,703:中間導電層 704:中間導電層、底導電層 705:底導電層 710:第一絕緣層 d3:第三電源訊號導通路徑 e1:第一接地訊號導通路徑 e2:第二接地訊號導通路徑 e3:第三接地訊號導通路徑 C1:第一電容器 C2:第二電容器 C3:第三電容器 P1:第一導電部分 P2:第二導電部分 P3:第三導電部分 G1:第四導電部分 G2:第五導電部分 G3:第六導電部分 IC:積體電路晶片 8a,8b,8c:曲線 9a,9b,9c:曲線 10a,10b,10c:曲線 10: First voltage converter, first power supply 20: Second voltage converter, second power supply 100: First power signal transmission path 200: Second power signal transmission path PB: Printed circuit board 30:Noise suppression device A1,A2: line 401:Top conductive layer 401a: First conductive part 401b: Second conductive part 402:Power wiring 403: Conductive layer 404: Bottom conductive layer 410: First insulation layer d1: first power signal conduction path d2: Second power signal conduction path 501:Top conductive layer 501a: First conductive part 501b: Second conductive part 504:Power wiring 505: Bottom conductive layer 601:Top conductive layer 601a: First conductive part 601b: Second conductive part 602,603,604: Intermediate conductive layer 605: Bottom conductive layer 610: First insulation layer 701:Top conductive layer 702,703: Intermediate conductive layer 704: Middle conductive layer, bottom conductive layer 705: Bottom conductive layer 710: First insulation layer d3: The third power signal conduction path e1: first ground signal conduction path e2: The second ground signal conduction path e3: The third ground signal conduction path C1: first capacitor C2: Second capacitor C3: The third capacitor P1: first conductive part P2: The second conductive part P3: The third conductive part G1: The fourth conductive part G2: The fifth conductive part G3: The sixth conductive part IC: integrated circuit chip 8a,8b,8c: Curve 9a,9b,9c: Curve 10a,10b,10c: Curve
現在將更詳細並且參考圖式來描述本發明的實施例。能夠理解到的是，圖式中示出的印刷電路板和包括該印刷電路板的電子設備的截面圖或俯視圖僅示意性地表示印刷電路板或電子設備的與本發明實施例所描述的技術手段相關的部分結構或部分元件，並不代表實際的產品結構。 〔圖1〕示意性地圖示如本發明的一個實施例的印刷電路板的局部俯視圖、以及印刷電路板和向印刷電路板供電的電源之間的電連接。 〔圖2〕示意性地圖示如本發明的另一實施例的印刷電路板的局部俯視圖、以及印刷電路板和向印刷電路板供電的電源之間的電連接。 〔圖3〕示意性地圖示如本發明的另一實施例的印刷電路板的局部俯視圖、以及印刷電路板和向印刷電路板供電的電源之間的電連接。 〔圖4〕圖示如本發明的又一實施例的印刷電路板的示意性局部截面圖。 〔圖5〕圖示如本發明的又一實施例的印刷電路板的示意性局部截面圖。 〔圖6〕圖示如本發明的又一實施例的印刷電路板的示意性局部截面圖。 〔圖7〕圖示如本發明的又一實施例的電子設備的示意性局部截面圖。 〔圖8及圖9〕分別圖示電子設備分別應用本說明書描述的手段一、手段二以及手段三時兩個電壓節點處的阻抗曲線。 〔圖10〕圖示電子設備分別應用分別採用手段一、手段二和手段三的情況下的相異電壓節點之間的隔離度。 Embodiments of the invention will now be described in greater detail and with reference to the drawings. It can be understood that the cross-sectional or top views of the printed circuit board and the electronic device including the printed circuit board shown in the drawings only schematically represent the technology described in the embodiments of the present invention. The partial structures or components related to the means do not represent the actual product structure. [Fig. 1] schematically illustrates a partial top view of a printed circuit board according to one embodiment of the present invention, and electrical connections between the printed circuit board and a power source that supplies power to the printed circuit board. [Fig. 2] schematically illustrates a partial top view of a printed circuit board according to another embodiment of the present invention, and electrical connections between the printed circuit board and a power supply that supplies power to the printed circuit board. [Fig. 3] schematically illustrates a partial top view of a printed circuit board according to another embodiment of the present invention, and an electrical connection between the printed circuit board and a power supply that supplies power to the printed circuit board. [Fig. 4] illustrates a schematic partial cross-sectional view of a printed circuit board according to yet another embodiment of the present invention. [Fig. 5] illustrates a schematic partial cross-sectional view of a printed circuit board according to yet another embodiment of the present invention. [Fig. 6] illustrates a schematic partial cross-sectional view of a printed circuit board according to yet another embodiment of the present invention. [Fig. 7] illustrates a schematic partial cross-sectional view of an electronic device according to yet another embodiment of the present invention. [Figure 8 and Figure 9] respectively illustrate the impedance curves at two voltage nodes when the electronic device applies method one, method two and method three described in this specification. [Figure 10] The diagram shows the isolation between nodes with different voltages when the electronic equipment uses method one, method two and method three respectively.
601:頂導電層 601:Top conductive layer
601a:第一導電部分 601a: First conductive part
601b:第二導電部分 601b: Second conductive part
602,603,604:中間導電層 602,603,604: Intermediate conductive layer
605:底導電層 605: Bottom conductive layer
610:第一絕緣層 610: First insulation layer
d1:第一電源訊號導通路徑 d1: first power signal conduction path
d2:第二電源訊號導通路徑 d2: Second power signal conduction path
Claims (12)
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| CN202210892660X | 2022-07-27 | ||
| CN202210892660.XA CN115209613A (en) | 2022-07-27 | 2022-07-27 | Printed circuit board and electronic device including the same |
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| TW202406421A true TW202406421A (en) | 2024-02-01 |
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| WO2024022449A1 (en) * | 2022-07-27 | 2024-02-01 | 摩尔线程智能科技(北京)有限责任公司 | Printed circuit board and electronic device comprising same |
| WO2024138558A1 (en) * | 2022-12-29 | 2024-07-04 | Beijing Baidu Netcom Science Technology Co., Ltd. | High speed camera interface pcb floor plan for autonomous vehicles |
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