TWI730489B - Circuit board and electronic device using same - Google Patents

Circuit board and electronic device using same Download PDF

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Publication number
TWI730489B
TWI730489B TW108139821A TW108139821A TWI730489B TW I730489 B TWI730489 B TW I730489B TW 108139821 A TW108139821 A TW 108139821A TW 108139821 A TW108139821 A TW 108139821A TW I730489 B TWI730489 B TW I730489B
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Taiwan
Prior art keywords
circuit board
substrate layer
traces
wiring
trace
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TW108139821A
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Chinese (zh)
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TW202118364A (en
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張登琦
林柏榮
謝樺岳
姜丞鴻
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大陸商業成科技（成都）有限公司
大陸商業成光電（深圳）有限公司
英特盛科技股份有限公司
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0268—Marks, test patterns or identification means for electrical inspection or testing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

A circuit board and an electronic device using the circuit board are disclosed. The circuit board includes a first substrate layer, a plurality of first traces, a plurality of second traces, an electrical conductor, and a plurality of test pads. The first substrate layer has opposing first and second surfaces. The circuit board defines a plurality of vias extending through the first substrate layer. The first traces are on the first surface. The second traces are on the second surface. The electrical conductor is in each via to electrically connect one first trace to one second trace. Each test pad covers and electrically connects the electrical conductor in one via. Since each test pad of the circuit board is on a via, each test pad no longer occupies an area of the circuit board, thereby increasing an integration of the circuit board.

Description

電路板及應用其的電子裝置 Circuit board and electronic device using the same

本發明涉及印刷電路技術領域，尤其涉及一種電路板及應用該電路板的電子裝置。 The invention relates to the technical field of printed circuits, in particular to a circuit board and an electronic device using the circuit board.

隨著電子產品集成度的增加，電路板上單位面積內的電子元件以及佈線越來越密集，同時對訊號品質的要求亦越發嚴格。通常會在電路板上設置測試墊，以完成對電路板上各電子元件訊號的測量。 With the increase in the integration of electronic products, the electronic components and wiring per unit area on the circuit board are becoming more and more dense, and the requirements for signal quality are becoming more stringent. Test pads are usually set on the circuit board to complete the measurement of the signals of the various electronic components on the circuit board.

習知設置測試墊的方式為在原走線上設置一個焊墊(pad)進行測試或者額外拉一條走線進行測試。然，由於每個焊墊或測試走線均會佔用一定的電路板面積，而電路板的面積有限，故，存在電路板沒有足夠空間做測試墊的問題。 The conventional method for setting the test pad is to set a pad on the original trace for testing or to pull an additional trace for testing. However, since each solder pad or test trace occupies a certain area of the circuit board, and the area of the circuit board is limited, there is a problem that the circuit board does not have enough space as a test pad.

本發明一方面提供一種電路板，其包括：第一基材層，具有相對的第一表面與第二表面，所述電路板定義有過孔，所述過孔沿所述第一表面至所述第二表面的方向貫穿所述第一基材層；複數第一走線，位於所述第一表面； 複數第二走線，位於所述第二表面；導電體，位於所述過孔內，以電性連接一條所述第一走線與一條所述第二走線；以及測試墊，覆蓋並電性連接所述導電體。 One aspect of the present invention provides a circuit board comprising: a first substrate layer having a first surface and a second surface opposite to each other, the circuit board is defined with a via hole, and the via hole extends along the first surface to the The direction of the second surface penetrates the first substrate layer; a plurality of first traces are located on the first surface; A plurality of second traces are located on the second surface; an electrical conductor is located in the via hole to electrically connect one of the first traces and one of the second traces; and a test pad covering the parallel connection Sexually connect the conductor.

本發明實施例中，藉由將電路板的測試墊設置在過孔處，使得每個測試墊不再單獨佔用電路板的面積，且過孔的位置處，既能夠實現位於不同走線層的第一走線與第二走線的換層，又兼具測試墊的功能。藉此，節省了電路板的空間，提高了電路板的集成度。 In the embodiment of the present invention, by arranging the test pads of the circuit board at the via hole, each test pad no longer separately occupies the area of the circuit board, and the via hole position can achieve The layer change between the first trace and the second trace also functions as a test pad. Thereby, the space of the circuit board is saved, and the integration degree of the circuit board is improved.

本發明另一方面還提供一種電子裝置，其包括第一電子元件、第二電子元件以及電性連接所述第一電子元件與所述第二電子元件的電路板，所述電路板為上述的電路板，所述第一電子元件電性連接所述第一走線，所述第二電子元件電性連接所述第二走線。 Another aspect of the present invention also provides an electronic device, which includes a first electronic component, a second electronic component, and a circuit board electrically connecting the first electronic component and the second electronic component, the circuit board being the above On the circuit board, the first electronic component is electrically connected to the first wiring, and the second electronic component is electrically connected to the second wiring.

由於上述電路板具有集成度高的優點，使得應用該電路板的電子裝置的結構更緊湊。 Because the above-mentioned circuit board has the advantage of high integration, the structure of the electronic device using the circuit board is more compact.

100、200、300:電路板 100, 200, 300: circuit board

10:第一基材層 10: The first substrate layer

10a:第一表面 10a: first surface

10b:第二表面 10b: second surface

11:過孔 11: Via

12:第一走線 12: The first trace

13:第二走線 13: Second trace

14:其他走線 14: Other routing

15:導電體 15: Conductor

16:測試墊 16: test pad

20:第一阻焊層 20: The first solder mask

30:第二基材層 30: The second substrate layer

40:第三基材層 40: The third substrate layer

50:第二阻焊層 50: The second solder mask

D1:第一方向 D1: First direction

D2:第二方向 D2: second direction

A1:訊號輸入區 A1: Signal input area

17:輸入引腳 17: Input pin

172:第一輸入引腳 172: The first input pin

174:第二輸入引腳 174: second input pin

A2:測試區 A2: Test area

A3:彎折區 A3: bending area

A4:訊號輸出區 A4: Signal output area

18:輸出引腳 18: output pin

182:第一輸出引腳 182: The first output pin

184:第二輸出引腳 184: second output pin

80:電子裝置 80: electronic device

60:第一電子元件 60: The first electronic component

70:第二電子元件 70: second electronic component

圖1為本發明電路板的第一實施例的示意圖。 FIG. 1 is a schematic diagram of the first embodiment of the circuit board of the present invention.

圖2為沿圖1中線II-II方向的剖面示意圖。 Fig. 2 is a schematic cross-sectional view taken along the line II-II in Fig. 1.

圖3、圖4及圖5分別為本發明電路板的變更實施例的導電體在第一基材層上的投影圖。 3, 4, and 5 are projection views of the conductor on the first substrate layer of the modified embodiment of the circuit board of the present invention.

圖6與圖7分別為本發明電路板的變更實施例的第一走線、第二走線及測試墊的示意圖。 6 and 7 are schematic diagrams of the first wiring, the second wiring and the test pad of the modified embodiment of the circuit board of the present invention.

圖8為本發明電路板的第二實施例的剖視圖。 Fig. 8 is a cross-sectional view of the second embodiment of the circuit board of the present invention.

圖9為本發明電路板的第三實施例的剖視圖。 Fig. 9 is a cross-sectional view of the third embodiment of the circuit board of the present invention.

圖10為本發明一實施例提供的電子裝置的方框結構示意圖。 FIG. 10 is a schematic block diagram of an electronic device provided by an embodiment of the present invention.

如圖1所示，本發明第一實施例的電路板100包括第一基材層10、複數第一走線12、複數第二走線13、複數過孔11以及複數測試墊16。 As shown in FIG. 1, the circuit board 100 of the first embodiment of the present invention includes a first substrate layer 10, a plurality of first traces 12, a plurality of second traces 13, a plurality of via holes 11 and a plurality of test pads 16.

如圖2所示，第一基材層10具有相對的第一表面10a與第二表面10b。第一表面10a與第二表面10b為大致平行相背的兩個表面。 As shown in FIG. 2, the first substrate layer 10 has a first surface 10a and a second surface 10b opposite to each other. The first surface 10a and the second surface 10b are two surfaces that are substantially parallel and opposite to each other.

於一實施例中，電路板100為柔性電路板，例如整合柔性電路板(Flexible Printed Circuit+Assembly，FPCA)。第一基材層10由柔性的有機材料製成，例如聚醯亞胺(Polyimide，PI)或聚對苯二甲酸乙二醇酯(Polyethylene glycol terephthalate，PET)等。於其他實施例中，電路板100可為硬質電路板，例如，整合印刷電路板(Printed Circuit Board+Assembly，PCBA)。 In one embodiment, the circuit board 100 is a flexible circuit board, such as an integrated flexible circuit board (Flexible Printed Circuit+Assembly, FPCA). The first substrate layer 10 is made of a flexible organic material, such as polyimide (PI) or polyethylene glycol terephthalate (PET). In other embodiments, the circuit board 100 may be a rigid circuit board, for example, an integrated printed circuit board (PCBA).

請結合參閱圖1與圖2，複數第一走線12位於所述第一表面10a。複數第二走線13位於所述第二表面10b。每一過孔11沿所述第一表面10a至所述第二表面10b的方向貫穿所述第一基材層10。電路板100還包括位於過孔11內的導電體15。每個過孔11藉由位於其內的導電體15電性連接一條第一走線12與一條第二走線13，以使位於不同膜層的第一走線12與第二走線13實現電性導通。測試墊16覆蓋並電性連接過孔11內的導電體15。 Please refer to FIG. 1 and FIG. 2 in combination, a plurality of first traces 12 are located on the first surface 10a. A plurality of second traces 13 are located on the second surface 10b. Each via hole 11 penetrates the first substrate layer 10 along the direction from the first surface 10 a to the second surface 10 b. The circuit board 100 further includes a conductor 15 located in the via hole 11. Each via 11 is electrically connected to a first trace 12 and a second trace 13 through a conductor 15 located in it, so that the first trace 12 and the second trace 13 in different layers are realized Electrical conduction. The test pad 16 covers and electrically connects the conductor 15 in the via 11.

於一實施例中，每一條第一走線12用於電性連接第一電子元件60(標記在圖10中)，每一條第二走線13用於電性連接第二電子元件70(標記 在圖10中)。一條第一走線12與一條第二走線13電性連接以實現第一電子元件60與第二電子元件70之間訊號的傳輸。 In one embodiment, each of the first traces 12 is used to electrically connect to the first electronic component 60 (marked in FIG. 10), and each of the second traces 13 is used to electrically connect to the second electronic component 70 (marked In Figure 10). A first wiring 12 and a second wiring 13 are electrically connected to realize signal transmission between the first electronic component 60 and the second electronic component 70.

當電路板100出現故障需要檢測時，可以將測試儀器的探針連接至測試墊16，以獲得第一走線12與第二走線13之間傳輸的訊號。根據測試儀器獲得的第一走線12與第二走線13之間傳輸的訊號是否符合規範，進而可以確定電路板100出現故障的位置。 When the circuit board 100 has a fault and needs to be detected, the probe of the test instrument can be connected to the test pad 16 to obtain the signal transmitted between the first wire 12 and the second wire 13. According to whether the signal transmitted between the first wire 12 and the second wire 13 obtained by the test instrument meets the specification, the location of the circuit board 100 can be determined.

藉由將測試墊16設置在過孔11處，使得每個測試墊16不再單獨佔用電路板100的面積，且過孔11的位置處，既能夠實現位於不同走線層的第一走線12與第二走線13的換層，又兼具測試墊16的功能。相較於現有技術中過孔與測試墊分開設置，並過孔與測試墊分別佔用電路板100面積的方式，節省了電路板100的空間，提高了電路板100的集成度。 By arranging the test pad 16 at the via hole 11, each test pad 16 no longer occupies the area of the circuit board 100 separately, and the position of the via hole 11 can realize the first wiring in different wiring layers. The layer change between 12 and the second wiring 13 also has the function of the test pad 16. Compared with the method in the prior art that the via holes and the test pads are separately arranged, and the via holes and the test pad occupy the area of the circuit board 100 respectively, the space of the circuit board 100 is saved and the integration degree of the circuit board 100 is improved.

請繼續參閱圖1，所述第一基材層10定義有沿第一方向D1上順次連接的訊號輸入區A1、測試區A2、彎折區A3以及訊號輸出區A4。訊號輸入區A1與測試區A2沿第二方向D2上的寬度大致相同。彎折區A3與訊號輸出區A4沿第二方向D2上的寬度大致相同。第二方向D2與第一方向D1交叉。 Please continue to refer to FIG. 1, the first substrate layer 10 defines a signal input area A1, a test area A2, a bending area A3, and a signal output area A4 that are sequentially connected along the first direction D1. The signal input area A1 and the test area A2 have approximately the same width along the second direction D2. The widths of the bending area A3 and the signal output area A4 along the second direction D2 are approximately the same. The second direction D2 crosses the first direction D1.

訊號輸入區A1設置有複數輸入引腳17。所述測試墊16位於所述測試區A2。彎折區A3沿第一方向D1上大致為長條狀，以利於彎折。各第二走線13在彎折區A3內沿第一方向D1延伸。所述訊號輸出區A4設置有複數輸出引腳18。 The signal input area A1 is provided with multiple input pins 17. The test pad 16 is located in the test area A2. The bending area A3 is substantially elongated along the first direction D1 to facilitate bending. Each second wire 13 extends along the first direction D1 in the bending area A3. The signal output area A4 is provided with a plurality of output pins 18.

每一第一走線12大致沿第一方向D1延伸，複數第一走線12沿第二方向D2間隔排列。每一第二走線13藉由一個過孔11內設置的導電體15電性連接一條第一走線12。每一第一走線12與一條第二走線13的連接處設置有 一個測試墊16。即，測試墊16的數量等於過孔11的數量。對應每一過孔11的位置設置一測試墊16。於其他實施例中，電路板100上可以僅對應部分過孔11的位置設置測試墊16。即，電路板100上並非所有的過孔11位置處均設置有測試墊16，仍有部分過孔11僅作為位於不同膜層的走線換層使用。 Each first trace 12 extends substantially along the first direction D1, and the plurality of first traces 12 are arranged at intervals along the second direction D2. Each second wiring 13 is electrically connected to a first wiring 12 through a conductive body 15 disposed in a via hole 11. The connection between each first wire 12 and a second wire 13 is provided with One test pad 16. That is, the number of test pads 16 is equal to the number of via holes 11. A test pad 16 is provided corresponding to the position of each via hole 11. In other embodiments, the circuit board 100 may only be provided with a test pad 16 corresponding to a portion of the via hole 11. That is, not all via holes 11 on the circuit board 100 are provided with test pads 16 and there are still some via holes 11 that are only used for layer exchange in different film layers.

每一第二走線13大致沿第一方向D1延伸，複數第二走線13沿第二方向D2間隔排列。每一第一走線12電性連接一個測試墊16後，自測試區A2延伸至所述訊號輸入區A1，並在訊號輸入區A1電性連接一個輸入引腳17。每一第二走線13電性連接一個測試墊16後，自測試區A2延伸跨越彎折區A3，並在訊號輸出區A4電性連接一個輸出引腳18。每一第一走線12可以藉由一個輸入引腳17電性連接至第一電子元件60，每一第二走線13可以藉由一個輸出引腳18電性連接至第二電子元件70。 Each second trace 13 extends substantially along the first direction D1, and the plurality of second traces 13 are arranged at intervals along the second direction D2. After each first trace 12 is electrically connected to a test pad 16, it extends from the test area A2 to the signal input area A1, and is electrically connected to an input pin 17 in the signal input area A1. After each second trace 13 is electrically connected to a test pad 16, it extends from the test area A2 across the bending area A3, and is electrically connected to an output pin 18 in the signal output area A4. Each first wiring 12 can be electrically connected to the first electronic component 60 through an input pin 17, and each second wiring 13 can be electrically connected to the second electronic component 70 through an output pin 18.

於一實施例中，輸入引腳17包括第一輸入引腳172與第二輸入引腳174。第二輸入引腳174相較於第一輸入引腳172更遠離測試區A2。每一個第一輸入引腳172和一個第二輸入引腳174間隔排列。藉此，使得各第一走線12在訊號輸入區A1內的排列可以更加緊密，以減小電路板100的訊號輸入區A1在第二方向D2上的寬度，提高電路板100的集成度。 In one embodiment, the input pin 17 includes a first input pin 172 and a second input pin 174. The second input pin 174 is farther away from the test area A2 than the first input pin 172. Each first input pin 172 and one second input pin 174 are arranged at intervals. Thereby, the arrangement of the first wires 12 in the signal input area A1 can be more compact, so as to reduce the width of the signal input area A1 of the circuit board 100 in the second direction D2, and improve the integration of the circuit board 100.

於一實施例中，測試區A2內，每一第一走線12、每一第二走線13電性連接一個測試墊16後均向第一基材層10沿第二方向D2上的中間區域靠近。藉此，使得各第一走線12與各第二走線13在測試區A2內的排列可以更加緊密，以減小電路板100的測試區A2在第二方向D2上的寬度，提高電路板100的集成度。 In one embodiment, in the test area A2, each of the first traces 12 and each of the second traces 13 is electrically connected to a test pad 16 and then all go to the middle of the first substrate layer 10 along the second direction D2. The area is close. Thereby, the arrangement of each first wiring 12 and each second wiring 13 in the test area A2 can be closer, so as to reduce the width of the test area A2 of the circuit board 100 in the second direction D2, and improve the circuit board. 100 degree of integration.

於一實施例中，第一基材層10沿第二方向D2上呈軸對稱，各測試墊16的分佈可以關於第一基材層10的對稱軸呈對稱分佈。各測試墊16可以分為多組(圖1中除去中間的測試墊16，剩餘的各測試墊16三個為一組)，每一組內的測試墊16的排佈呈斜直線狀。即，每一組內的各測試墊16的連線為直線或曲線，且與第二方向D2(或第一方向D1)呈一定的夾角。可以理解，夾角的範圍大小與各測試墊16的分組情況以電路板100方便佈線為准，不限於圖1所示的情形。 In an embodiment, the first substrate layer 10 is axisymmetric along the second direction D2, and the distribution of the test pads 16 may be symmetrically distributed with respect to the symmetry axis of the first substrate layer 10. Each test pad 16 can be divided into multiple groups (in FIG. 1, the middle test pad 16 is removed, and the remaining three test pads 16 are a group), and the test pads 16 in each group are arranged in an oblique straight line. That is, the connecting line of the test pads 16 in each group is a straight line or a curve, and forms a certain angle with the second direction D2 (or the first direction D1). It can be understood that the range of the angle and the grouping of the test pads 16 are based on the convenient wiring of the circuit board 100, and is not limited to the situation shown in FIG. 1.

於一實施例中，輸出引腳18包括第一輸出引腳182與第二輸出引腳184。第一輸出引腳182相較於第二輸出引腳184更遠離彎折區A3。每一個第一輸出引腳182與一個第二輸出引腳184間隔排列。藉此，使得各第二走線13在訊號輸出區A4內的排列可以更加緊密，以減小電路板100的訊號輸出區A4在第二方向D2上的寬度，提高電路板100的集成度。 In one embodiment, the output pin 18 includes a first output pin 182 and a second output pin 184. The first output pin 182 is farther away from the bending area A3 than the second output pin 184. Each first output pin 182 and a second output pin 184 are arranged at intervals. Thereby, the arrangement of the second wirings 13 in the signal output area A4 can be closer, so as to reduce the width of the signal output area A4 of the circuit board 100 in the second direction D2, and improve the integration of the circuit board 100.

請參閱圖2，電路板100為雙層電路板。即，電路板100包括兩層走線層。過孔11為大致沿垂直於第一表面10a與第二表面10b的方向貫穿第一基材層10的通孔。導電體15大致呈中空柱狀。導電體15嵌在過孔11的內壁上，並部分延伸至第一基材的第一表面10a與第二表面10b上。導電體15的一端與位於第一表面10a上的第一走線12電性連接，另一端與位於第二表面10b上的第二走線13電性連接，從而實現第一走線12與第二走線13之間的訊號傳遞。導電體15的材料可為銅箔。該實施例中，過孔11為圓孔。導電體15在第一基材層10上的投影為一圓環。 Please refer to FIG. 2, the circuit board 100 is a double-layer circuit board. That is, the circuit board 100 includes two wiring layers. The via hole 11 is a through hole that penetrates the first substrate layer 10 substantially in a direction perpendicular to the first surface 10 a and the second surface 10 b. The conductor 15 has a substantially hollow cylindrical shape. The conductor 15 is embedded on the inner wall of the via hole 11 and partially extends to the first surface 10a and the second surface 10b of the first substrate. One end of the conductor 15 is electrically connected to the first trace 12 on the first surface 10a, and the other end is electrically connected to the second trace 13 on the second surface 10b, so as to realize the first trace 12 and the second trace 12 Signal transmission between the two traces 13. The material of the conductor 15 may be copper foil. In this embodiment, the via hole 11 is a round hole. The projection of the conductor 15 on the first substrate layer 10 is a circular ring.

如圖3至圖5所示，於其他實施例中，過孔11可為橢圓孔或多邊形孔等。如圖3所示，當過孔11為橢圓孔時，導電體15在第一基材層10上的 投影為一橢圓環。如圖4所示，當過孔11為一梯形孔時，導電體15在第一基材層10上的投影為兩個大小不同的梯形構成的環。如圖5所示，當過孔11為十四邊形孔時，導電體15在第一基材層10上的投影為兩個大小不同的十四邊形構成的環。 As shown in FIGS. 3 to 5, in other embodiments, the via hole 11 may be an elliptical hole or a polygonal hole. As shown in FIG. 3, when the via hole 11 is an elliptical hole, the conductor 15 is on the first substrate layer 10 The projection is an ellipse ring. As shown in FIG. 4, when the via hole 11 is a trapezoidal hole, the projection of the conductor 15 on the first substrate layer 10 is a ring composed of two trapezoids of different sizes. As shown in FIG. 5, when the via hole 11 is a tetragonal hole, the projection of the conductor 15 on the first substrate layer 10 is a ring composed of two tetragons of different sizes.

請繼續參閱圖2，第一基材層10的第一表面10a上還設置有不同於第一走線12的其他走線14。導電體15與第一表面10a上的其他走線14間隔且絕緣設置。第一基材層10的第二表面10b上還設置有不同於第二走線13的其他走線14。導電體15與第二表面10b上的其他走線14間隔且絕緣設置。測試墊16覆蓋並電性連接導電體15。測試墊16部分延伸至導電體15圍繞而成的中空位置。測試墊16的材質可為錫膏或銅錫合金等。 Please continue to refer to FIG. 2, the first surface 10 a of the first substrate layer 10 is further provided with other wires 14 different from the first wires 12. The conductor 15 is spaced apart from and insulated from other traces 14 on the first surface 10a. The second surface 10b of the first substrate layer 10 is further provided with other wires 14 different from the second wires 13. The conductor 15 is spaced apart from and insulated from the other traces 14 on the second surface 10b. The test pad 16 covers and is electrically connected to the conductor 15. The test pad 16 partially extends to the hollow position surrounded by the conductor 15. The material of the test pad 16 can be solder paste, copper-tin alloy, or the like.

請繼續參閱圖2，電路板100還包括第一阻焊層20與第二阻焊層50。第一阻焊層20與第二阻焊層50均為電路板100的最外層。第一阻焊層20覆蓋第一走線12與位於第一表面10a上的其他走線14，並暴露各測試墊16。第二阻焊層50覆蓋第二走線13與位於第二表面10b上的其他走線14。第一阻焊層20與第二阻焊層50用於防止其覆蓋的各走線暴露在空氣中而被氧化。第一阻焊層20與第二阻焊層50的材質可為保護漆或三防膠等。 Please continue to refer to FIG. 2, the circuit board 100 further includes a first solder resist layer 20 and a second solder resist layer 50. Both the first solder resist layer 20 and the second solder resist layer 50 are the outermost layers of the circuit board 100. The first solder resist layer 20 covers the first trace 12 and other traces 14 on the first surface 10 a, and exposes the test pads 16. The second solder resist layer 50 covers the second trace 13 and other traces 14 located on the second surface 10b. The first solder resist layer 20 and the second solder resist layer 50 are used to prevent the traces covered by them from being exposed to air and oxidized. The material of the first solder resist layer 20 and the second solder resist layer 50 may be protective paint or three-proof glue.

如圖1所示，第一實施例中，一個輸入引腳17與一個輸出引腳18之間僅需要一條第一走線12與一條第二走線13即可實現電性連接。即，一個輸入引腳17與一個輸出引腳18之間僅設置有一個過孔11以及對應該過孔11的一個測試墊16。於一變更實施例中，一個輸入引腳17與一個輸出引腳18之間可以設置兩個以上的過孔11以及兩個以上的測試墊16。 As shown in FIG. 1, in the first embodiment, only one first wire 12 and one second wire 13 are needed between one input pin 17 and one output pin 18 to achieve electrical connection. That is, only one via hole 11 and one test pad 16 corresponding to the via hole 11 are provided between one input pin 17 and one output pin 18. In a modified embodiment, more than two vias 11 and more than two test pads 16 can be provided between one input pin 17 and one output pin 18.

如圖6所示，一個輸入引腳17與一個輸出引腳18之間可以設置兩個過孔11、兩個測試墊16、兩條第一走線12與一條第二走線13。其中，一條第一走線12電性連接一個輸入引腳17，另一條第一走線12電性連接一個輸出引腳18。第一走線12與第二走線13之間藉由過孔11(測試墊16)實現不同層的走線之間的換線。 As shown in FIG. 6, two via holes 11, two test pads 16, two first wires 12 and one second wire 13 can be provided between one input pin 17 and one output pin 18. Among them, one first wiring 12 is electrically connected to an input pin 17, and the other first wiring 12 is electrically connected to an output pin 18. The first wire 12 and the second wire 13 are exchanged between wires of different layers through the via 11 (test pad 16).

如圖7所示，一個輸入引腳17與一個輸出引腳18之間可以設置兩個過孔11、兩個測試墊16、兩條第二走線13與一條第一走線12。其中，一條第二走線13電性連接一個輸入引腳17，另一條第二走線13電性連接一個輸出引腳18。第一走線12與第二走線13之間藉由過孔11(測試墊16)實現不同層的走線之間的換線。 As shown in FIG. 7, two via holes 11, two test pads 16, two second traces 13 and one first trace 12 can be provided between one input pin 17 and one output pin 18. Among them, one second wiring 13 is electrically connected to an input pin 17, and the other second wiring 13 is electrically connected to an output pin 18. The first wire 12 and the second wire 13 are exchanged between wires of different layers through the via 11 (test pad 16).

如圖8所示，本發明第二實施例的電路板200與第一實施例的電路板100的結構基本相同，其區別在於：第一實施例中，電路板100為雙層電路板，其包括一層基材層與兩層走線層；第二實施例中，電路板200為多層電路板，其還包括位於所述第二走線13遠離所述第一基材層10一側的至少一層第二基材層30以及位於第二基材層30的表面上的其他走線14。即，第二實施例中，電路板200包括至少兩層基材層及至少三層走線層。 As shown in FIG. 8, the circuit board 200 of the second embodiment of the present invention has basically the same structure as the circuit board 100 of the first embodiment. The difference is that: in the first embodiment, the circuit board 100 is a double-layer circuit board. It includes a substrate layer and two wiring layers. In the second embodiment, the circuit board 200 is a multi-layer circuit board, which further includes at least one side of the second wiring 13 away from the first substrate layer 10. A second substrate layer 30 and other traces 14 located on the surface of the second substrate layer 30. That is, in the second embodiment, the circuit board 200 includes at least two substrate layers and at least three wiring layers.

第一實施例中，過孔11為貫穿電路板100所有基材層(第一基材層10)的通孔。第二實施例中，過孔11為未貫穿電路板200所有基材層的盲孔。如圖8所示，過孔11僅貫穿第一基材層10而未貫穿第二基材層30。藉此設計，可以防止水汽等從測試墊16的一側進入導電體15而導致的第一走線12與第二走線13之間電性連接的可靠性較差的現象。 In the first embodiment, the via hole 11 is a through hole that penetrates all the substrate layers (the first substrate layer 10) of the circuit board 100. In the second embodiment, the via 11 is a blind hole that does not penetrate through all the substrate layers of the circuit board 200. As shown in FIG. 8, the via hole 11 only penetrates the first substrate layer 10 and does not penetrate the second substrate layer 30. With this design, it is possible to prevent the poor reliability of the electrical connection between the first trace 12 and the second trace 13 caused by moisture and the like entering the conductor 15 from one side of the test pad 16.

第一實施例中，導電體15嵌在過孔11的內壁上，呈中空柱狀；第二實施例中，導電體15完全填充過孔11。 In the first embodiment, the conductive body 15 is embedded on the inner wall of the via hole 11 in a hollow column shape; in the second embodiment, the conductive body 15 completely fills the via hole 11.

可以理解，電路板200還可為包括三層基材層與四層走線層的四層電路板。具體結構可為圖8所示的電路板200中，在第二走線13與第二阻焊層50之間依次設置第二基材層30、其他走線14、第二基材層30以及其他走線14。即，在第二走線13與第二阻焊層50之間設置兩層基材層與兩層走線層。 It can be understood that the circuit board 200 may also be a four-layer circuit board including three substrate layers and four wiring layers. The specific structure may be that in the circuit board 200 shown in FIG. 8, a second substrate layer 30, other traces 14, a second substrate layer 30, and a second substrate layer 30 are sequentially arranged between the second trace 13 and the second solder resist layer 50. Other routing 14. That is, two substrate layers and two wiring layers are provided between the second wiring 13 and the second solder resist layer 50.

如圖9所示，本發明第三實施例中的電路板300與第一實施例的電路板100的結構基本相同，其區別在於：第一實施例中，電路板100為雙層電路板，其包括一層基材層與兩層走線層；而第三實施例中的電路板300為大於兩層的多層電路板，其還包括位於所述第一走線12遠離所述第一基材層10一側的至少一層第三基材層40以及位於第三基材層40的表面上的其他走線14。即，第三實施例中，電路板300包括至少兩層基材層及至少三層走線層。 As shown in FIG. 9, the circuit board 300 in the third embodiment of the present invention has basically the same structure as the circuit board 100 in the first embodiment. The difference is that: in the first embodiment, the circuit board 100 is a double-layer circuit board. It includes a substrate layer and two wiring layers; and the circuit board 300 in the third embodiment is a multi-layer circuit board with more than two layers, and it also includes a substrate located at the first wiring 12 away from the first substrate. At least one third substrate layer 40 on one side of the layer 10 and other traces 14 located on the surface of the third substrate layer 40. That is, in the third embodiment, the circuit board 300 includes at least two substrate layers and at least three wiring layers.

如圖9所示，電路板300為四層電路板，其還包括位於第一走線12遠離第一基材層10一側的兩層第三基材層40、位於兩層第三基材層40之間的其他走線14以及位於第一阻焊層20與第三基材層40之間的其他走線14。過孔11為貫穿電路板所有基材層(第一基材層10以及兩層第三基材層40)的通孔。其他走線14與同層設置的第一走線12、同層設置的第二走線13或同層設置的其他走線14之間在過孔11位置處間隔且絕緣設置。 As shown in FIG. 9, the circuit board 300 is a four-layer circuit board, which further includes two third substrate layers 40 located on the side of the first trace 12 away from the first substrate layer 10, and two third substrate layers located on the two layers. Other traces 14 between the layers 40 and other traces 14 between the first solder resist layer 20 and the third substrate layer 40. The via hole 11 is a through hole that penetrates all the substrate layers (the first substrate layer 10 and the two third substrate layers 40) of the circuit board. The other wires 14 are spaced apart and insulated from the first wires 12 provided on the same layer, the second wires 13 provided on the same layer, or other wires 14 provided on the same layer at the positions of the via holes 11.

可以理解，電路板300還可為包括兩層基材層與三層走線層的三層電路板。具體結構可為圖9所示的電路板300中，在第一走線12與第一阻焊層20之間減少一層第三基材層40與一層其他走線14。即，在第一走線12與第一阻焊層20之間僅設置一層基材層與一層走線層。 It can be understood that the circuit board 300 may also be a three-layer circuit board including two substrate layers and three wiring layers. The specific structure may be that in the circuit board 300 shown in FIG. 9, a third substrate layer 40 and a layer of other wirings 14 are reduced between the first wiring 12 and the first solder resist layer 20. That is, only one substrate layer and one wiring layer are provided between the first wiring 12 and the first solder resist layer 20.

本發明實施例中，藉由將測試墊16設置在過孔11中，使得每個測試墊16不再單獨佔用電路板100的面積，且對應過孔11的位置處，既能夠實現不同走線層的走線的換層，又兼具測試墊16的功能。藉此，節省了電路板100的空間，提高了電路板100的集成度。 In the embodiment of the present invention, by arranging the test pads 16 in the via holes 11, each test pad 16 no longer occupies the area of the circuit board 100 separately, and the position corresponding to the via hole 11 can realize different wiring. The layer change of the routing of the layers also has the function of the test pad 16. Thereby, the space of the circuit board 100 is saved, and the integration degree of the circuit board 100 is improved.

本發明再一實施例還提供一種電子裝置80。電子裝置80包括第一電子元件60與第二電子元件70以及上述的電路板100(200、300)。第一電子元件60藉由輸入引腳17電性連接第一走線12。第二電子元件70藉由輸出引腳18電性連接所述第二走線13。由於上述電路板100(200、300)具有集成度高的優點，使得應用該電路板100(200、300)的電子裝置80的結構更緊湊。 Another embodiment of the present invention also provides an electronic device 80. The electronic device 80 includes a first electronic component 60 and a second electronic component 70 and the aforementioned circuit board 100 (200, 300). The first electronic component 60 is electrically connected to the first wiring 12 through the input pin 17. The second electronic component 70 is electrically connected to the second wiring 13 through the output pin 18. Since the above-mentioned circuit board 100 (200, 300) has the advantage of high integration, the structure of the electronic device 80 using the circuit board 100 (200, 300) is more compact.

於一實施例中，電子裝置80可為顯示面板，第一電子元件60可為顯示驅動晶片，第二電子元件70可為接收顯示驅動晶片上的訊號的顯示電極。 In one embodiment, the electronic device 80 can be a display panel, the first electronic component 60 can be a display driver chip, and the second electronic component 70 can be a display electrode that receives signals from the display driver chip.

於另一實施例中，電子裝置80可為觸控面板，第一電子元件60可為觸控驅動晶片，第二電子元件70可為接收觸控驅動晶片上的訊號的觸控驅動電極。 In another embodiment, the electronic device 80 may be a touch panel, the first electronic element 60 may be a touch drive chip, and the second electronic element 70 may be a touch drive electrode that receives signals on the touch drive chip.

以上實施方式僅用以說明本發明的技術方案而非限制，儘管參照較佳實施方式對本發明進行了詳細說明，本領域的普通技術人員應當理解，可以對本發明的技術方案進行修改或等同替換，而不脫離本發明技術方案的精神及範圍。 The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced. Without departing from the spirit and scope of the technical solution of the present invention.

100:電路板 100: circuit board

10:第一基材層 10: The first substrate layer

10a:第一表面 10a: first surface

10b:第二表面 10b: second surface

11:過孔 11: Via

12:第一走線 12: The first trace

13:第二走線 13: Second trace

14:其他走線 14: Other routing

15:導電體 15: Conductor

16:測試墊 16: test pad

20:第一阻焊層 20: The first solder mask

50:第二阻焊層 50: The second solder mask

Claims (10)

一種電路板，其改良在於，包括：第一基材層，具有相對的第一表面與第二表面，所述電路板定義有過孔，所述過孔沿所述第一表面至所述第二表面的方向貫穿所述第一基材層；複數第一走線，位於所述第一表面；複數第二走線，位於所述第二表面；導電體，位於所述過孔內，以電性連接一條所述第一走線與一條所述第二走線；以及測試墊，覆蓋並電性連接所述導電體；其中，所述第一基材層的所述第一表面上還設置有不同於所述第一走線的其他走線，所述導電體與所述其他走線間隔且絕緣設置；所述電路板還包括第一阻焊層，所述第一阻焊層位於所述第一走線遠離所述第一基材層一側，所述第一阻焊層覆蓋所述第一走線與所述其他走線，且所述第一阻焊層至少部分覆蓋所述導電體。 A circuit board is improved in that it comprises: a first substrate layer having a first surface and a second surface opposite to each other, the circuit board is defined with a via hole, and the via hole extends from the first surface to the second surface. The directions of the two surfaces pass through the first substrate layer; a plurality of first traces are located on the first surface; a plurality of second traces are located on the second surface; a conductor is located in the via hole to Electrically connected to one of the first wiring and one of the second wiring; and a test pad, covering and electrically connecting the conductor; wherein, the first surface of the first substrate layer is also Other traces different from the first trace are provided, and the conductor is spaced apart from the other traces and insulated from the other traces; the circuit board further includes a first solder resist layer, where the first solder resist layer is located The first trace is away from the side of the first substrate layer, the first solder resist layer covers the first trace and the other traces, and the first solder resist layer at least partially covers all the traces.述conductive body. 如請求項1所述的電路板，其中，所述導電體設置於所述過孔的內壁上。 The circuit board according to claim 1, wherein the conductor is provided on the inner wall of the via hole. 如請求項1所述的電路板，其中，所述導電體完全填充所述過孔。 The circuit board according to claim 1, wherein the conductive body completely fills the via hole. 如請求項1所述的電路板，其中，所述第一阻焊層暴露所述測試墊。 The circuit board according to claim 1, wherein the first solder resist layer exposes the test pad. 如請求項4所述的電路板，其中，所述電路板還包括至少一第二基材層，所述第二基材層位於所述第二走線遠離所述第一基材層一側，所述過孔未貫穿所述第二基材層。 The circuit board according to claim 4, wherein the circuit board further includes at least one second substrate layer, and the second substrate layer is located on a side of the second trace away from the first substrate layer , The via hole does not penetrate the second substrate layer. 如請求項4所述的電路板，其中，所述電路板還包括至少一第三基材層，所述第三基材層位於所述第一走線與所述阻焊層之間，所述過孔貫穿所述第一基材層與所述第三基材層。 The circuit board according to claim 4, wherein the circuit board further includes at least one third substrate layer, and the third substrate layer is located between the first trace and the solder resist layer, so The via hole penetrates the first substrate layer and the third substrate layer. 如請求項6所述的電路板，其中，所述電路板還包括第二阻焊層，所述第二阻焊層覆蓋所述第二走線的表面。 The circuit board according to claim 6, wherein the circuit board further includes a second solder resist layer, and the second solder resist layer covers the surface of the second trace. 如請求項1所述的電路板，其中，所述電路板還包括用於輸入訊號的輸入引腳與用於輸出訊號的輸出引腳，所述輸入引腳與所述輸出引腳藉由所述第一走線與所述第二走線實現電性連接。 The circuit board according to claim 1, wherein the circuit board further includes an input pin for inputting a signal and an output pin for outputting a signal, and the input pin and the output pin are The first wiring and the second wiring are electrically connected. 如請求項8所述的電路板，其中，所述輸入引腳與所述輸出引腳之間的所述測試墊的數量為一個或兩個。 The circuit board according to claim 8, wherein the number of the test pads between the input pin and the output pin is one or two. 一種電子裝置，包括第一電子元件、第二電子元件以及電性連接所述第一電子元件與所述第二電子元件的電路板，其中，所述電路板為如請求項1至9中任一項所述的電路板，所述第一電子元件電性連接所述第一走線，所述第二電子元件電性連接所述第二走線。 An electronic device, comprising a first electronic element, a second electronic element, and a circuit board electrically connecting the first electronic element and the second electronic element, wherein the circuit board is any of claims 1 to 9 In the circuit board of item 1, the first electronic component is electrically connected to the first wiring, and the second electronic component is electrically connected to the second wiring.
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