CN111027057B - Method and device for detecting hidden hardware of chip and storage medium - Google Patents
Method and device for detecting hidden hardware of chip and storage medium Download PDFInfo
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- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
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- G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The embodiment of the invention discloses a method and a device for detecting hidden hardware of a chip and a storage medium, which relate to the technical field of chip safety and can effectively judge whether the hidden hardware exists in the chip. The method comprises the following steps: setting scan-related configuration parameters, including: address range of scanning, operation type of scanning; scanning the address space of the tested SoC based on the configuration parameters; capturing and analyzing the internal state of the tested SoC in the scanning process; the internal states include: the hardware resource access state of the system environment and the related variable value or register value; capturing and analyzing the external state of the tested SoC in the scanning process; the external state includes: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
Description
Technical Field
The present invention relates to the field of chip security technologies, and in particular, to a method and apparatus for detecting hidden hardware of a chip, and a storage medium.
Background
With the development of microelectronic technology, the number of transistors on a single chip of an integrated circuit has been billions or more, and the chip functions and logic complexity are also very high. For chips with certain scale and complexity, the workload of designing, verifying and manufacturing is often finished by cooperation of multiple companies at the upstream and downstream of the whole industry. From an information security perspective, integrated circuit chips may be tampered with maliciously, for example, by implanting malicious logic circuits to alter circuit functions under certain subtle conditions, or to reveal information under certain triggering conditions, at various links of design and manufacture. As a highly complex system, malicious logic has high concealment, and detection and recognition are very difficult.
Disclosure of Invention
In view of this, the embodiments of the present invention provide a method, an apparatus, and a storage medium for detecting hidden hardware of a chip, which perform a large-scale scan operation on an address space of a SoC under test, and further observe an internal state and an external state of the SoC, so as to finally and effectively determine whether hardware hidden logic exists.
In a first aspect, an embodiment of the present invention provides a method for detecting hidden hardware of a chip, including:
setting scan-related configuration parameters, including: address range of scanning, operation type of scanning;
scanning the address space of the tested SoC based on the configuration parameters;
capturing and analyzing the internal state of the tested SoC in the scanning process; the internal states include: the hardware resource access state of the system environment and the related variable value or register value;
capturing and analyzing the external state of the tested SoC in the scanning process; the external state includes: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to a specific implementation manner of the embodiment of the invention, the operation types of the scanning include: a read operation, a write operation, or a read-write combination operation.
According to a specific implementation manner of the embodiment of the present invention, the scan operation is performed on the address space of the SoC under test based on the configuration parameters, specifically: and performing fuzzy test operation on the address space of the tested SoC based on the configuration parameters.
In a second aspect, an embodiment of the present invention provides a device for detecting hardware hidden in a chip, including:
the configuration generating module is used for setting configuration parameters related to scanning, and comprises the following steps: address range of scanning, operation type of scanning;
the upper computer control module is deployed on the upper computer and is used for loading configuration parameters to the bus operation execution module;
the bus operation execution module is positioned inside the tested SoC and is used for carrying out scanning operation on the address space of the tested SoC based on the configuration parameters;
the internal state capturing and analyzing module is used for capturing and analyzing the internal state of the tested SoC in the scanning process; the internal states include: the hardware resource access state of the system environment and the related variable value or register value;
the external state capturing and analyzing module is used for capturing and analyzing the external state of the tested SoC in the scanning process; the external state includes: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to a specific implementation manner of the embodiment of the invention, the operation types of the scanning include: a read operation, a write operation, or a read-write combination operation.
According to a specific implementation manner of the embodiment of the invention, the bus operation execution module is specifically a tested SoC processor and an embedded software module thereon.
According to a specific implementation manner of the embodiment of the present invention, the internal state capture analysis module is an embedded software module on the SoC processor under test, and is configured to perform a local analysis operation on an internal state in the SoC under test.
According to a specific implementation manner of the embodiment of the invention, the bus operation execution module is specifically a bus master device controlled by JTAG.
According to a specific implementation manner of the embodiment of the present invention, the internal state capturing and analyzing module is a software module running on an upper computer, and is configured to perform internal state analysis operation according to original captured data returned by the bus operation executing module; wherein the raw captured data comprises: the internal states captured by the operational process and the Fuzzing process.
In a third aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs executable by one or more processors to implement the method of any of the preceding implementations.
According to the method, the device and the storage medium for detecting the hidden hardware of the chip, provided by the embodiment of the invention, the address space of the tested SoC is scanned based on the configuration parameters, and the internal state and the external state of the chip in the scanning process are captured, so that whether the hidden hardware exists in the current chip or not is comprehensively analyzed and judged. The embodiment of the invention can avoid data leakage possibly caused by using an unsafe chip, and even avoid other more serious consequences.
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In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an address bus and various device modules thereon according to the present invention;
FIG. 2 is a flowchart of an embodiment of a method for detecting hidden hardware of a chip according to the present invention;
FIG. 3 is a schematic diagram of an embodiment 1 of a device for detecting hidden hardware of a chip according to the present invention;
FIG. 4 is a schematic diagram of an embodiment 2 of a device for detecting hidden hardware of a chip according to the present invention;
fig. 5 is a schematic structural diagram of an embodiment 3 of a detection device with hardware hidden in a chip according to the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
There is often a large reserved area in the chip processor memory address space. The system will not access the address space during normal operation. These reserved address spaces are hidden from view and the user cannot learn about the address space or what functional logic is present. These hidden spaces may have embedded Trojan logical access portals that implement a prefetch or attack behavior in some cases outside of the normal functioning of the system.
In terms of hardware, as shown in fig. 1, each device module connected on the bus decodes the bus address of a certain section, and enables its chip select signal when the read-write address hits its range on the bus; if the hidden malicious logic hardware of the system is connected to the bus, the address of a certain section is decoded, and when the address hits the range of the bus, the chip selection signal is enabled, so that the function of the functional module is activated. Therefore, when the scan hits in the hidden logical address range, the result is different from the result of the common reserved address during read-write, and the power consumption or the chip heat change may be caused by activating the additional hardware circuit. These internal and external state characteristic changes can be used as clues to discover hidden logic. Based on this, the present invention proposes the following embodiments for efficiently identifying and discovering hidden hardware logic of a chip.
In a first aspect, an embodiment of the present invention provides a method for detecting hidden hardware of a chip, which can effectively determine whether hidden hardware exists in the chip.
Fig. 2 is a flowchart of an embodiment of a method for detecting hidden hardware of a chip according to the present invention, including:
s101: setting configuration parameters related to scanning; the configuration parameters include, but are not limited to: address range of scan, operation type of scan.
Wherein, the operation types of the scanning include: a read operation, a write operation, or a read-write combination operation. More specifically, the write operation also requires determining the data content of the write operation, and the read-write combination operation also requires determining the pattern in which the operations are repeated and alternately combined.
S102: and scanning the address space of the tested SoC based on the configuration parameters.
More preferably, the scan operation is performed on the address space of the SoC under test based on the configuration parameters, specifically: and performing fuzzy test operation on the address space of the tested SoC based on the configuration parameters.
Step S102 may be performed by the SoC processor under test and the embedded software thereon, or may be performed by a bus master device controlled by JTAG.
S103: and capturing and analyzing the internal state of the tested SoC in the scanning process. The internal states include: the hardware resource access status of the system environment, and the associated variable values or register values. Wherein the relevant variable value refers to a variable involved in the interaction with hardware; the register value refers to an internal register resource of the SoC, and is used for completing the functions of configuration, communication, data exchange and the like of an application layer and hardware resources.
The step S103 may be implemented by embedded software on the SoC processor to be tested or software on an upper computer.
S104: and capturing and analyzing the external state of the tested SoC in the scanning process. The external state includes: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to the embodiment, the internal state and the external state of the tested SoC chip are obtained in real time by performing a large-scale scanning operation on the tested SoC, and whether the hardware Trojan exists in the current chip or not is finally judged based on the internal state and the external state, so that serious consequences such as data leakage possibly caused by using the chip with the abnormality are avoided.
In a second aspect, an embodiment of the present invention provides a device for detecting hidden hardware of a chip, which can effectively determine whether the hidden hardware exists in the chip.
Fig. 3 is a schematic structural diagram of an embodiment 1 of a detection device for hiding hardware of a chip according to the present invention, where the device of the embodiment may include:
the configuration generating module 301 is configured to set scan-related configuration parameters, including: address range of scan, operation type of scan. Wherein, the operation types of the scanning include: a read operation, a write operation, or a read-write combination operation.
The upper computer control module 302 is disposed on the upper computer and is configured to load configuration parameters into the bus operation execution module 303;
the bus operation execution module 303 is located inside the SoC to be tested, and is configured to perform a scan operation on an address space of the SoC to be tested based on the configuration parameters;
the internal state capturing and analyzing module 304 is configured to capture and analyze an internal state of the SoC under test during the scanning process; the internal states include: the hardware resource access state of the system environment and the related variable value or register value;
the external state capturing and analyzing module 305 is configured to capture and analyze an external state of the SoC under test during the scanning process; the external state includes: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
According to the embodiment, the internal state and the external state of the tested SoC are obtained in real time by performing a large-scale scanning operation on the tested SoC, and the hardware Trojan of the chip is finally detected based on the internal state and the external state, so that serious consequences such as data leakage possibly caused by using the chip with abnormality are avoided.
Fig. 4 is a schematic structural diagram of an embodiment 2 of a detection device with hardware hidden in a chip, which is applicable to a situation that an on-chip processor is controllable and a scanning operation does not interfere with execution of the processor, where the device of the embodiment may include:
the configuration generating module is used for setting configuration parameters related to scanning, and comprises the following steps: address range of scan, operation type of scan. Wherein, the operation types of the scanning include: a read operation, a write operation, or a read-write combination operation.
The upper computer control module is deployed on the upper computer and is used for loading configuration parameters to the bus operation execution module. The upper computer control module is also used for loading the configuration parameters, the test execution program and the software program of the internal state capture analysis module into the tested SoC processor.
The bus operation execution module is a tested SoC processor and an embedded software module on the tested SoC processor and is used for carrying out scanning operation on an address space of the tested SoC based on configuration parameters. The bus operation execution module is used as a master device on the bus and can initiate read-write operation on any address space on the bus.
The internal state capturing and analyzing module is an embedded software module on the tested SoC processor and is used for capturing and analyzing the internal state of the tested SoC in the scanning process; the internal states include: the hardware resource access status of the system environment, and the associated variable values or register values.
The external state capturing and analyzing module is used for capturing and analyzing the external state of the tested SoC in the scanning process; the external state includes: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
The embodiment is suitable for the condition that the on-chip processor is controllable and the scanning operation does not interfere with the execution of the processor. In the embodiment, the SoC processor to be tested and the embedded software module on the SoC processor to be tested are used for executing scanning operation and capturing and analyzing of the internal state, and meanwhile, the external state capturing and analyzing module is used for capturing and analyzing the external state. Finally, judging whether hidden hardware exists in the tested SoC according to the analysis results of the internal state and the external state.
Fig. 5 is a schematic structural diagram of an embodiment 3 of a detection device for hiding hardware of a chip, which is suitable for a situation that a processor on the chip is unavailable or a scan test process affects a normal execution program of the processor, the device of the embodiment may include:
the configuration generating module is used for setting configuration parameters related to scanning, and comprises the following steps: address range of scanning, operation type of scanning; the operation types of the scanning include: a read operation, a write operation, or a read-write combination operation.
The upper computer control module is deployed on the upper computer and is used for loading configuration parameters to the bus operation execution module;
the bus operation execution module is positioned inside the tested SoC, specifically is a JTAG controlled bus master device and is used for carrying out scanning operation on the address space of the tested SoC based on the configuration parameters; the bus operation execution module is used as a master device on the bus and has the capability of initiating read-write operation on any address space on the bus, can perform the read-write operation according to the configuration parameters issued by the upper computer control module, and returns the original captured data in the scanning operation process to the upper computer control module.
The internal state capturing and analyzing module is in particular a software module running on the upper computer and is used for carrying out internal state analyzing operation according to the original captured data returned by the bus operation executing module; the internal states include: the hardware resource access state of the system environment and the related variable value or register value; wherein the raw captured data comprises: the internal states captured by the operational process and the Fuzzing process.
The external state capturing and analyzing module is used for capturing and analyzing the external state of the tested SoC in the scanning process; the external state includes: the state of the chip output signal, the chip power consumption, or the chip thermal characteristics.
This embodiment is applicable in cases where the on-chip processor is not controllable, or where the scanning operation may interfere with the processor execution. In the embodiment, the DAP controller controlled by the JTAG test interface on the tested SoC specifically executes the scan test operation, and feeds back the data of the internal state change in the scan test to the upper computer, and the internal state capture analysis module located on the upper computer performs the analysis operation of the internal state data, and simultaneously, the external state capture analysis module realizes the capture and analysis of the external state. Finally, judging whether hidden hardware exists in the tested SoC according to the analysis results of the internal state and the external state.
In a third aspect, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs executable by one or more processors to implement the method of any of the preceding implementations.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
For convenience of description, the above apparatus is described as being functionally divided into various units/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention.
Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (9)
1. The method for detecting the hidden hardware of the chip is characterized by comprising the following steps of:
setting scan-related configuration parameters, including: address range of scanning, operation type of scanning;
scanning the address space of the tested SoC based on the configuration parameters;
capturing and analyzing the internal state of the tested SoC in the scanning process; the internal states include: the hardware resource access state of the system environment and the related variable value or register value; the related variable value refers to a variable involved in the interaction with hardware;
capturing and analyzing the external state of the tested SoC in the scanning process; the external state includes: the state of the chip output signal, the chip power consumption or the chip thermal characteristics;
the scan operation is performed on the address space of the SoC to be tested based on the configuration parameters, specifically: and performing fuzzy test operation on the address space of the tested SoC based on the configuration parameters.
2. The method of detection of claim 1, wherein the type of operation of the scanning comprises: a read operation, a write operation, or a read-write combination operation.
3. A chip hidden hardware detection device, comprising:
the configuration generating module is used for setting configuration parameters related to scanning, and comprises the following steps: address range of scanning, operation type of scanning;
the upper computer control module is deployed on the upper computer and is used for loading configuration parameters to the bus operation execution module;
the bus operation execution module is positioned inside the tested SoC and is used for carrying out scanning operation on the address space of the tested SoC based on the configuration parameters;
the internal state capturing and analyzing module is used for capturing and analyzing the internal state of the tested SoC in the scanning process; the internal states include: the hardware resource access state of the system environment and the related variable value or register value;
the external state capturing and analyzing module is used for capturing and analyzing the external state of the tested SoC in the scanning process; the external state includes: the state of the chip output signal, the chip power consumption or the chip thermal characteristics;
the bus operation execution module scans the address space of the tested SoC based on the configuration parameters, and specifically comprises the following steps: and performing fuzzy test operation on the address space of the tested SoC based on the configuration parameters.
4. A detection apparatus according to claim 3, wherein the type of operation of the scanning comprises: a read operation, a write operation, or a read-write combination operation.
5. The test device of claim 3, wherein the bus operation execution module is embodied as a SoC processor under test and an embedded software module thereon.
6. The detection apparatus of claim 5, wherein the internal state capture analysis module is an embedded software module on a SoC processor under test for performing local analysis operations on internal states within the SoC under test.
7. The test apparatus of claim 3, wherein the bus operation execution module is embodied as a JTAG-controlled bus master.
8. The detecting device according to claim 7, wherein the internal state capturing and analyzing module is a software module running on a host computer, and is configured to perform an internal state analyzing operation according to the original captured data returned by the bus operation executing module; wherein the raw captured data comprises: the internal states captured by the operational process and the Fuzzing process.
9. A computer readable storage medium storing one or more programs executable by one or more processors to implement the method of any preceding claim.
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