KR20120031644A - Boundary scan testing apparatus for embedded-type substrate and method thereof - Google Patents

Boundary scan testing apparatus for embedded-type substrate and method thereof Download PDF

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KR20120031644A
KR20120031644A KR1020100093133A KR20100093133A KR20120031644A KR 20120031644 A KR20120031644 A KR 20120031644A KR 1020100093133 A KR1020100093133 A KR 1020100093133A KR 20100093133 A KR20100093133 A KR 20100093133A KR 20120031644 A KR20120031644 A KR 20120031644A
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test
chip
embedded
semiconductor chip
boundary scan
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KR1020100093133A
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KR101222737B1 (en
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김현호
정원근
정율교
정태성
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삼성전기주식회사
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Priority to KR1020100093133A priority Critical patent/KR101222737B1/en
Priority to TW100131886A priority patent/TWI443355B/en
Priority to DE201110113305 priority patent/DE102011113305A1/en
Publication of KR20120031644A publication Critical patent/KR20120031644A/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: A boundary scan test apparatus and method of an embedded substrate are provided to improve reliability of function test about the embedded substrate by processing a boundary scan test about a semiconductor chip included in the embedded substrate. CONSTITUTION: A boundary scan test arrangement of an embedded substrate comprises a plurality of embedded substrates(1), a plurality of test chips(2), and a test controller(3). The embedded substrate includes a semiconductor chip which becomes an object for test. The test chip processes a boundary scan test about the semiconductor chip included in the embedded substrate. The test controller controls the test chip. The plurality of test chips is formed into a chain shape in which a test input terminal is connected to a test output terminal. A first probe is connected to a contact point of one side of the embedded substrate. A second probe is connected to a contact point of the other side of the embedded substrate.

Description

Boundary scan testing apparatus for embedded-type substrate and method

The present invention relates to an apparatus and method for scanning boundary scan of an embedded substrate.

In general, Surface Mounting Technology (SMT) of electronic components refers to a technology for placing components on a substrate. In the semiconductor field, which occupies almost all electronic products such as home appliances, computers, communication devices, and aerospace industries, It is a core technology.

In recent years, in order to meet the demand for miniaturization of the size of a board, an embedded board having a semiconductor chip or the like embedded therein has been developed in order to increase the mounting density of components on the same board.

After completing the surface mounting process in the embedded board, in order to check whether each component is well mounted on the board, the short circuit / disruption test through the resistance measurement is mainly performed.

The short circuit / break test according to the related art is not a main purpose of the functional test of the semiconductor chip of the embedded board, and the short circuit / break test of the circuit pattern of the board is mainly used, so it is difficult to be applied to the functional test of the embedded board. There was this.

Therefore, the present invention has been proposed to solve the above-described problems of the prior art, and can perform a boundary scan test on a semiconductor chip embedded in a substrate by using a chip having a boundary scan test function. It is an object of the present invention to provide an apparatus and method for performing a boundary scan test of an embedded substrate, which enables functional tests to proceed quickly and reliably.

An apparatus of the present invention for achieving the above object is an embedded substrate containing a semiconductor chip to be tested; A test chip for performing a boundary scan test on the semiconductor chip embedded in the embedded substrate; And a test controller controlling the test chip to control a boundary scan test on a semiconductor chip embedded in an embedded substrate.

In addition, the present invention is characterized in that a plurality of the test chip corresponding to the case of a plurality of the embedded substrate, the plurality of test chips are connected to each other test input terminal and the test output terminal to form a chain.

In addition, the test chip of the present invention, the first probe connected to the contact point on one surface for the boundary scan test of the embedded substrate; And a second probe connected to a contact point on the other surface for the boundary scan test of the embedded substrate.

In addition, when there are a plurality of semiconductor chips embedded in the embedded substrate of the present invention, an input terminal and an output terminal are connected to each other to form a chain.

In addition, the test chip of the present invention is characterized in that it is embedded in the embedded substrate.

The test controller of the present invention applies test data to the test chip while the test chip controls the semiconductor chip so that the input / output terminal and the internal core logic are separated from each other. To test the connection state of the board.

In addition, the test controller of the present invention is characterized by performing a function test of the semiconductor chip by receiving a result of executing the semiconductor chip according to the applied function execution command by applying a function execution command to the test chip.

In addition, the method includes: (A) electrically connecting a semiconductor chip, a test chip, and a test controller embedded in an embedded substrate to establish a boundary scan test environment; (B) testing a substrate connection state by applying test data to the test chip in the test controller in a state where the input / output terminal and the internal core logic of the semiconductor chip are separated; And (C) the test controller applying a function execution command to the test chip to perform a function test of the semiconductor chip.

In the method of the present invention, the test chip is embedded in the semiconductor chip.

Further, in the method of the present invention, the step (B) may include: (B-1) the test controller applying an outer boundary scan test mode selection signal to the test chip; (B-2) controlling the semiconductor chip to separate the input / output terminal and the internal core logic by the test chip; (B-3) the test controller applying test data to the test chip; (B-4) the test chip applying test data to the semiconductor chip, receiving the response signal and transmitting the test signal to the test controller; And (B-5) comparing the test data applied to the semiconductor chip with the response signal to test the board connection state.

Further, in the step (B-4) of the method of the present invention, when there are a plurality of semiconductor chips embedded in the embedded substrate and connected in a chain, the test data is transmitted as a response signal to the test chip via the plurality of semiconductor chips. It is characterized in that the output.

Also, in the method of the present invention, the step (C) may include: (C-1) the test controller applying an inner boundary scan test mode selection signal to the test chip; (C-2) the test controller applying a function execution command to the test chip; (C-3) the test chip applying a function execution command to the semiconductor chip, receiving the execution result and transmitting the result to the test controller; And (C-4) performing a function test by comparing a function execution command applied to the semiconductor chip with an execution result by the test chip.

Further, in the step (C-3) of the method of the present invention, when there are a plurality of semiconductor chips embedded in the embedded substrate and connected in a chain, the function execution command is executed as the test chip via the plurality of semiconductor chips. It is characterized in that the output.

Prior to this, the terms or words used in this specification and claims are not to be interpreted in a conventional and dictionary sense, and the inventors may appropriately define the concept of terms in order to best describe their own invention. It should be interpreted as meaning and concept corresponding to the technical idea of the present invention based on the principle that the present invention.

According to the present invention as described above, it is possible to improve the reliability of the performance of the semiconductor chip by enabling the functional test through the boundary scan test for the semiconductor chip embedded in the substrate.

In addition, according to the present invention, a boundary scan test for a plurality of embedded substrates is performed through a chain of test chips to enable a quick and efficient test on a plurality of embedded substrates.

1 is a block diagram of a boundary scan test apparatus for an embedded substrate according to a first exemplary embodiment of the present invention.
2 is an exemplary view of the embedded substrate of FIG. 1.
3 is a block diagram illustrating an internal block of the test chip of FIG. 1.
4 is an exemplary diagram illustrating a coupling relationship between an embedded substrate and a test chip of FIG. 1.
5 is an exemplary view illustrating a state in which a test chip is embedded in the embedded substrate of FIG. 1.
6 is a flowchart of a boundary scan test method of an embedded substrate according to a first exemplary embodiment of the present invention.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components as possible, even if displayed on different drawings have the same number as possible. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a boundary scan test apparatus for an embedded substrate according to a first exemplary embodiment of the present invention.

As shown in FIG. 1, an apparatus for scanning a boundary scan of an embedded substrate according to the present invention includes a plurality of embedded substrates 1 including a semiconductor chip to be tested and a semiconductor chip embedded in the embedded substrate 1. A test controller which controls a plurality of test chips 2 performing a boundary scan test and a plurality of test chips 2 to control a boundary scan test on a semiconductor chip embedded in the plurality of embedded substrates 1. 3) is included.

Here, the embedded substrate 1 includes a plurality of semiconductor chips embedded therein, and the embedded semiconductor chip includes a semiconductor chip having no boundary scan test function.

An example of such an embedded substrate 1 is illustrated in FIG. 2, which is formed of an insulating material, has a plurality of semiconductor chips 20a-20c embedded therein, and a plurality of via holes 12. Stacked on both sides of the first insulating layer 10 including the first insulating layer 10, the first circuit layers 11a and 11b formed on both sides of the first insulating layer 10, and the first circuit layers 11a and 11b. Second insulating layers 13a and 13b having a plurality of via holes 15a and 15b therein, and second circuit layers 14a and 14b formed on both sides of the second insulating layers 13a and 13b. And third insulating layers 16a and 16b stacked on both sides of the second circuit layers 14a and 14b and having a plurality of via holes 18a and 18b therein, and third insulating layers 16a and 16b. And the solder resist layers 19a and 19b covering the third circuit layers 17a and 17b and the third circuit layers 17a and 17b.

In the embedded substrate 1, six networks are formed as indicated by a dotted line in FIG. 2. Herein, since the networks 1, 2, and 4 have no connection relationship with the embedded semiconductor chips 20a to 20c, even if the disconnection / short test is performed according to the related art, a test result for a desired board connection state can be obtained.

However, in the case of the networks 3, 5, and 6, since the semiconductor chips 20a to 20c are connected to each other, the disconnection / short test according to the prior art cannot obtain a test result for a desired board connection state, and the test according to the present invention. The chip may be used to check the board connection state by performing a boundary scan test. In addition, a functional test of the semiconductor chips 20a to 20c may be performed.

To this end, when there are a plurality of semiconductor chips 20a to 20c, they must be connected to each other in a chain. Referring to FIG. 2, the semiconductor chip 20a and the semiconductor chip 20b are connected to each other by a network 5 to form a chain. The semiconductor chip 20b and the semiconductor chip 20c are connected to each other by a network 6 to form a chain.

Therefore, if the input signal of the test chip is applied to the semiconductor chip 20a and the response signal of the input signal of the test chip 20b is analyzed and outputted, the connection state of the semiconductor chips can be checked or the function is performed. You can check whether it is smooth.

Meanwhile, the plurality of test chips 2 may be contact points for testing the upper probe 2-1 and the lower surface of the embedded substrate 1, which may contact the contact points for testing the upper surface of the embedded substrate 1. The lower probe 2-2 which can contact is provided.

In addition, the plurality of test chips 2 have a boundary scan test function, and are connected to the semiconductor chip embedded in the embedded substrate 1 through the provided upper probe 2-1 and the lower probe 2-2. Perform a boundary scan test.

An example of such a test chip 2 is illustrated in FIG. 3, in which a plurality of boundary scan cells 22 are bundled together for a test between a core logic 21 for unique operation and an input / output terminal. ). During a typical boundary scan test operation, data may pass through the boundary scan cell 22 between the core logic 21 and the signal pin unaffected by the core logic 21.

During the boundary scan test operation, the test data enters the test chip 2 through the TDI (Test Data In) pin, passes through the chain of the boundary scan cell 22, and outputs the TDO (test data). It is output from the test chip 2 through the; Test Data Out) pin.

Many such test chips 2 are tied together by coupling the TDO output to the TDI input as shown in FIG.

As shown in FIG. 4, the test chip 2 is located outside the embedded substrate 30 in which the semiconductor chips 32a and 32b are embedded in the insulating layer 31 and the circuit layers 31a and 31b are formed on both sides thereof. can do. Here, the semiconductor chip of reference numeral 32a has an output terminal connected to the input terminal of the semiconductor chip of reference numeral 32b to form a chain, and the test chip 2 applies a signal to the semiconductor chip of reference numeral 32a, and The result can be received from the semiconductor chip at 32b. Of course, the opposite is also possible.

On the other hand, as shown in FIG. 5, the test chip 2 has an embedded substrate 30 in which semiconductor chips 32a and 32b are embedded in the insulating layer 31 and circuit layers 31a and 31b are formed on both sides thereof. It can be built inside of.

Next, the test controller 3 performs a test on a plurality of embedded substrates while performing control on the plurality of test chips 2.

The test controller 3 provides a TMS (Test Mode Select) signal to the test chip 2 to put the test chips 2 into the test mode, and the TCK to shift data through the scan chain. Provide a (test clock).

Looking at the operation of the boundary scan test device of the embedded substrate is configured as follows.

First, the test controller 3 provides a test mode select (TMS) signal to the test chip 2 to put the test chips 2 into the test mode, and to shift the data through the scan chain. Provides a TCK (test clock). The test controller 3 applies data for test or diagnosis to the TDI pin of the test chip 2.

Each test chip 2 then acts as a shift register to shift the data bits from one test chip 2 to the next test chip 2.

The state of each test chip 2 can be monitored during the scan shift through those signal pins related to the output or bidirectional signal.

For example, during the boundary scan test, the state of each test chip 2 can be monitored by the test controller 3 through the associated signal pins as the data bits are shifted through the boundary scan path.

During the shift of data through the boundary scan path, generally each test chip 2 will make a lot of transitions between the logic high level and the logic low level. If a fault exists (such as an unconnected signal pin), the test controller 3 may not detect the foreseeable state for that cell at a given time, thereby causing a test failure. In this way, a defective signal connection can be detected.

In the input signal, the test data can be driven into the test chip 2 via its associated signal pins and monitored via TDO (test data output) after a shift through the connected test chip 2. In this manner, the semiconductor chip embedded in the embedded substrate 1 is tested in cooperation with the test controller 3 and the test chip 2.

In more detail, the embedded controller 2 is subjected to a board connection test and a functional test by the test controller 3.

In the board connection state test, the test controller 3 selects the boundary scan test mode as the external boundary stand test (EXTEST) mode, so that the internal core logic of the semiconductor chip embedded in the embedded substrate 1 is connected to the test chip 2. It is isolated from the input / output terminal by control of

When the test controller 3 inputs predetermined test data to the test chip 2 to test the board connection state through the test data input terminal in the state of selecting the outer boundary scan test mode, the test data is stored in the embedded substrate 1. After being loaded into a semiconductor chip, the test chip (via a plurality of semiconductor chips embedded in the case where a plurality of semiconductor chips are embedded in the embedded substrate 1 and chained together) 2) is output.

Accordingly, the test chip 2 outputs the received response signal to the test controller 3 through the test data output terminal.

Then, the test controller 3 compares the test data inputted to the semiconductor chip embedded in the embedded substrate 1 through the test chip 2 and the test data output from the semiconductor chip embedded in the embedded substrate 1. The connection state between the semiconductor chip and the semiconductor is examined.

Next, for the functional test, the test controller 3 selects the boundary scan test mode as the internal boundary scan test mode, so that the internal core logic of the semiconductor chip embedded in the embedded substrate 1 is connected to the input / output terminal. Keep it.

In the state selected as the internal boundary scan test mode, the test controller 3 inputs test data, that is, a test function execution command for a predetermined function test, to the test chip 2 through the test data input terminal. The command transmits a function execution command to the internal core logic of the semiconductor chip through an input terminal of the semiconductor chip embedded in the embedded substrate 1.

Accordingly, the internal core logic of the semiconductor chip performs the corresponding function according to the input test function execution command and outputs the result to the test chip 2 through the output terminal, and the test chip 2 receiving the execution result is The result is transmitted to the test controller 3. At this time, in the case where a plurality of semiconductor chips are connected in a chain form inside the embedded substrate 1 and the functions are organically combined, the above-described process is repeated and the last semiconductor chip is a test chip through an output terminal. The execution result is transmitted to (2).

The test controller 3 then determines whether a result suitable for the input function execution command has been obtained to determine whether the semiconductor chip embedded in the embedded substrate 1 is in normal operation.

6 is a flowchart of a boundary scan test method of an embedded substrate according to a first exemplary embodiment of the present invention.

Referring to FIG. 6, in the boundary scan test method of the embedded substrate according to the first embodiment of the present invention, an upper probe and a lower probe of a test chip having a boundary scan test function are first positioned at a corresponding contact point of the embedded substrate, thereby forming an integrated substrate. The semiconductor chip and the test chip are electrically connected to each other, and the test environment is established by electrically connecting the test chip and the test controller through the connector (S100).

In this case, when there are a plurality of embedded substrates, a plurality of test chips are connected in a chain to enable a boundary scan test on a plurality of embedded substrates.

 When the embedded test target board, the test chip, and the test controller are connected, the test controller inputs the test clock, the test mode selection signal, and the test data for the boundary scan test to the test chip. The test clock, the control signal, and the test data are applied to the substrate connection state test (S200) and the function test (S300).

In more detail, for the board connection test (S200), the test controller first applies a test mode selection signal for selecting the boundary scan test mode as the external boundary scan test (EXTEST) mode to the test chip (S202).

Then, the test chip transmits a control signal according to the outer boundary scan test mode to the semiconductor chip of the embedded substrate to control the internal core logic of the semiconductor chip to be isolated from the input and output terminals of the semiconductor chip (S204). In this state, the test controller inputs test data for testing the board connection state through the test data input terminal (S206).

Accordingly, the test chip inputs the received test data through the input terminal of the semiconductor chip (S208). When the test chip receives the test data from the test chip through the input terminal, the test chip is isolated from the internal core logic. The response signal is output through the output terminal.

In this case, when a plurality of semiconductor chips are connected in a chain form inside the embedded substrate, the above-described process is repeated to transmit the response signal to the test chip through the output terminal.

The test chip which receives the response signal according to the test data applied through the process from the semiconductor chip transmits the response signal to the test controller through the test data output terminal (S210).

Then, the test controller compares the test data input to the test chip with the response signal output from the test data output terminal of the test chip, thereby connecting the semiconductor chip mounted on the embedded substrate and the plurality of semiconductor chips, that is, the lead inside the substrate. (lead) state, disconnection / short-circuit state between the patterns, and check the connection state of the board, such as Struck-at-zero, Struck-at-one-fault (S212).

Next, for the functional test (S300), the test controller applies a test mode selection signal for selecting the boundary scan test mode as the internal boundary scan test (INTEST) mode to the test chip (S302).

Then, the test chip transmits a control signal according to the inner boundary scan test mode to the semiconductor chip of the embedded substrate to maintain the internal core logic of the semiconductor chip connected to the input / output terminals of the semiconductor chip. In this state, the test controller inputs test data for a function test, that is, a function execution command for a predetermined function test, to the test chip through the test data input terminal (S304). The internal core logic of the semiconductor chip is loaded through pins such as GPO and GPI (S306).

When the test function execution command is input to the internal core logic of the embedded semiconductor chip, the internal core logic of the chip executes a function according to the input test function execution command and outputs the execution result to the outside through the output terminal. (S308).

At this time, when a plurality of semiconductor chips are connected in a chain form inside the embedded substrate and the functions are organically coupled, the above process is repeated, and the last semiconductor chip is executed as a test chip through the output terminal. Will be sent.

The test chip receiving the execution result according to the test data applied through the process from the semiconductor chip transmits the execution result transmitted to the test controller through the test data output terminal (S310).

Then, the test controller compares the test data input to the test chip with the execution result output from the test data output terminal to determine the function performance state of the semiconductor chip mounted on the embedded substrate and the plurality of semiconductor chips to perform the function. It is determined whether this is smooth (S312).

Although the above has been illustrated and described with respect to the preferred embodiments of the present invention, the present invention is not limited to the above-described specific embodiments, it is common in the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1: embedded substrate 2: test chip
2-1, 2-2: Probe 3: Test Controller
10, 13a, 13b, 16a, 16b: insulating layer
11a, 11b, 14a, 14b, 17a, 17b: circuit layer
12, 15a, 15b, 18a, 18b: via hole
19a, 19b: Solder resist 20a-20c: semiconductor chip
21: core logic 22: boundary scan cell

Claims (13)

An embedded substrate containing a semiconductor chip to be tested;
A test chip for performing a boundary scan test on the semiconductor chip embedded in the embedded substrate; And
And a test controller configured to control the test chip so that a boundary scan test is performed on the semiconductor chip embedded in the embedded substrate. The method according to claim 1,
In the case of a plurality of embedded substrates, there are also a plurality of test chips corresponding to the plurality of embedded substrates, and the plurality of test chips have a test input terminal and a test output terminal connected to each other to form a chain scan test. Device. The method according to claim 1,
The test chip,
A first probe connected to a contact point on one surface of the boundary scan test of the embedded substrate; And
And a second probe connected to a contact point on the other surface for a boundary scan test of the embedded substrate. The method according to claim 1,
And a plurality of semiconductor chips embedded in the embedded substrate, wherein an input terminal and an output terminal are connected to each other to form a chain. The method according to claim 1,
And the test chip is embedded in the embedded substrate. The method according to claim 1,
The test controller applies test data to the test chip while the test chip controls the semiconductor chip to separate the input / output terminal and the internal core logic so that the applied test data is output through the semiconductor chip. Edge scan test device of the embedded substrate, characterized in that for testing the connection state. The method according to claim 1,
The test controller applies a function execution command to the test chip, receives a result of execution of the semiconductor chip according to the applied function execution command, and performs a functional test of the semiconductor chip. . (A) electrically connecting a semiconductor chip, a test chip, and a test controller embedded in the embedded substrate to establish a boundary scan test environment;
(B) testing a substrate connection state by applying test data to the test chip in the test controller in a state where the input / output terminal and the internal core logic of the semiconductor chip are separated; And
(C) the test controller applying a function execution command to the test chip to perform a function test of the semiconductor chip. The method according to claim 8,
And the test chip is embedded in the semiconductor chip. The method according to claim 8,
Step (B) is,
(B-1) the test controller applying an outer boundary scan test mode selection signal to the test chip;
(B-2) controlling the semiconductor chip to separate the input / output terminal and the internal core logic by the test chip;
(B-3) the test controller applying test data to the test chip;
(B-4) the test chip applying test data to the semiconductor chip, receiving the response signal and transmitting the test signal to the test controller; And
(B-5) The test chip boundary scan test method comprising the step of comparing the test data applied to the semiconductor chip with the response signal to test the substrate connection state. 12. The method of claim 10,
In the step (B-4),
And a plurality of semiconductor chips embedded in the embedded substrate and connected in a chain, wherein the test data is output as a response signal to the test chip via the plurality of semiconductor chips. The method according to claim 8,
Step (C) is
(C-1) the test controller applying an inner boundary scan test mode selection signal to the test chip;
(C-2) the test controller applying a function execution command to the test chip;
(C-3) the test chip applying a function execution command to the semiconductor chip, receiving the execution result and transmitting the result to the test controller; And
(C-5) comparing the execution command and the execution result of the function applied to the semiconductor chip by the test chip to perform a function test. The method of claim 12,
In the step (C-3),
And when the plurality of semiconductor chips embedded in the embedded substrate are connected in a chain, the execution command is output to the test chip via a plurality of semiconductor chips.
KR1020100093133A 2010-09-27 2010-09-27 Boundary scan testing apparatus for embedded-type substrate and method thereof KR101222737B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020100093133A KR101222737B1 (en) 2010-09-27 2010-09-27 Boundary scan testing apparatus for embedded-type substrate and method thereof
TW100131886A TWI443355B (en) 2010-09-27 2011-09-05 Boundary scan test apparatus and method for embedded substrate
DE201110113305 DE102011113305A1 (en) 2010-09-27 2011-09-14 Boundary scan test device for embedded substrate, has test controller that controls test chip to perform boundary scan test at semiconductor chip embedded into embedded substrate

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TWI453442B (en) * 2012-10-18 2014-09-21 Inventec Corp Detecting system for chip connection based on boundary scan and method thereof
CN111027057B (en) * 2019-01-31 2023-12-26 安天科技集团股份有限公司 Method and device for detecting hidden hardware of chip and storage medium

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KR100213230B1 (en) * 1997-01-29 1999-08-02 윤종용 Test method for core and embedded memory circuit
US5793778A (en) * 1997-04-11 1998-08-11 National Semiconductor Corporation Method and apparatus for testing analog and digital circuitry within a larger circuit
AU2001232778A1 (en) * 2000-01-21 2001-07-31 Sun Microsystems, Inc. A printed circuit assembly with configurable boundary scan paths
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