TWI436436B - 金屬-陶瓷複合基板及其製造方法 - Google Patents

金屬-陶瓷複合基板及其製造方法 Download PDF

Info

Publication number
TWI436436B
TWI436436B TW095116195A TW95116195A TWI436436B TW I436436 B TWI436436 B TW I436436B TW 095116195 A TW095116195 A TW 095116195A TW 95116195 A TW95116195 A TW 95116195A TW I436436 B TWI436436 B TW I436436B
Authority
TW
Taiwan
Prior art keywords
layer
ceramic
metal
solder
substrate
Prior art date
Application number
TW095116195A
Other languages
English (en)
Other versions
TW200701375A (en
Inventor
Yoshikazu Oshika
Original Assignee
Dowa Electronics Materials Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dowa Electronics Materials Co filed Critical Dowa Electronics Materials Co
Publication of TW200701375A publication Critical patent/TW200701375A/zh
Application granted granted Critical
Publication of TWI436436B publication Critical patent/TWI436436B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/053Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an inorganic insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85417Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/85424Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/8546Iron (Fe) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85466Titanium (Ti) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85469Platinum (Pt) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85463Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/85484Tungsten (W) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15Ceramic or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/022Mountings; Housings
    • H01S5/0235Method for mounting laser chips
    • H01S5/02355Fixing laser chips on mounts
    • H01S5/0237Fixing laser chips on mounts by soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/024Arrangements for thermal management
    • H01S5/02476Heat spreaders, i.e. improving heat flow between laser chip and heat dissipating elements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0179Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Ceramic Products (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

金屬-陶瓷複合基板及其製造方法
本發明係有關一種用於電子電路用基板之金屬-陶瓷複合基板及其製造方法。
通常,各種電子零件係搭載於形成在印刷基板上之銅配線圖案上的預定部位,且予以焊接以進行電子電路之結線。然而,由於使用紙酚醛樹脂、環氧樹脂、玻璃環氧樹脂等各種樹脂作為印刷基板之材料,雖然低成本,但放熱性並不好。
專利文獻1中,揭示有為了半導體搭載用電路基板之高密度安裝化,以在Al、Cu等經圖案化的金屬基材基板上流入絕緣填充物而形成電路之方式作成之半導體搭載用電路基板。該文獻中,作為絕緣填充物,形成有厚度100μm之含氧化矽之環氧樹脂,與在該樹脂上面由鋁及銅構成之箔作為配線層。
專利文獻2中,揭示有透過黏貼等手段而在由AlN構成之陶瓷基板上設置Cu等導電層,藉由將該導電層圖案化以形成電路而能使用於IC封裝體等之金屬薄膜積層陶瓷基板。
[專利文獻1]日本專利第3156798號[專利文獻2]日本專利第2762007號
然而,上述專利文獻1之半導體搭載用電路基板中,係因使用金屬基材基板,而放熱性係變得比印刷基板要好,但因配線層形成在0.1mm之厚的含氧化矽之環氧樹脂上,而有放熱性變得低之課題。此外,雖較印刷基板昂貴,但能以相對較低的成本加以製造。
專利文獻2之陶瓷基板中,使用AlN之熱傳導率較高的陶瓷基板時,放熱性係較印刷基板及專利文獻1之金屬基材基板更為良好。然而,陶瓷基板本身需要進行燒結製程等,製程較複雜,並且良品率差,而有成本將變得比印刷基板及專利文獻1之金屬基材基板要高之課題。
又,電路構造作成微細化時,結果,熱傳導率較小的陶瓷基板之每一體積的熱阻將變得比以Cu及Al作為基板之金屬基板大。因而,搭載半導體元件之微小電路,例如於次載具(sub mount)中,次載具整體中的AlN基板之熱阻為90%以上,而使放熱性不佳,故在放熱性方面並不一定適合。
相對於此,作為電子元件之半導體元件搭載用之電路基板中,雖有低成本之要求,但以放熱性為最優先。因此進一步的期望有熱阻較小的基板。
本發明之一目的係在提供一種具有良好放熱性之金屬-陶瓷複合基板。
本發明之另一目的係在提供一種能以低成本製造上述金屬-陶瓷複合基板之方法。
為達成上述之目的,本發明係由金屬基板、形成在金屬基板上的陶瓷層、形成在陶瓷層上的電極層以及形成在電極層上的銲料層(在本文中亦稱「銲錫層」,惟不以包含錫為限)所構成之金屬-陶瓷複合基板,其特徵為,陶瓷層係由陶瓷薄膜所構成。
上述構成中,在陶瓷層上進一步直接形成有與上述銲錫層不同的另一銲錫層為佳。再者,在陶瓷層與電極層之間***陶瓷層保護膜亦可。
金屬基板係最好由銅或鋁構成。陶瓷層係最好由氮化物系陶瓷構成。該氮化物系陶瓷係最好為氮化鋁。
根據本發明,作為金屬基板,最好係使用銅、鋁等金屬,並且在該金屬基板表面形成由陶瓷薄膜,最好係氮化物系陶瓷,尤其由氮化鋁構成之薄的陶瓷層,藉此陶瓷薄膜本身之熱阻將變小,且可將金屬基板表面的熱阻減低。因而,金屬基板表面的熱阻減低,且金屬-陶瓷複合基板之放熱性提高。如上所述,由於將熱傳導率較大的金屬基板之體積加大,並且可形成電路,因此能提供一種熱阻比陶瓷基板要小的金屬-陶瓷複合基板。
為達成上述另一目的,本發明係由金屬基板、形成在金屬基板上的陶瓷層、形成在陶瓷上的電極層以及形成在電極層上的銲錫層所構成之金屬-陶瓷複合基板之製造方法,其特徵為包含:在金屬基板表面,形成陶瓷薄膜以作為陶瓷層製程;以及在陶瓷層形成預定圖案的電極層之製程。
本發明之製造方法中,亦可包含在陶瓷層上進一步直接形成另一銲錫層之製程。此外,亦可包含在形成陶瓷層後,用以形成陶瓷層保護膜之製程。陶瓷層係由氮化物系陶瓷構成為佳,尤其以氮化鋁為佳。
根據本發明,藉由使用金屬作為基板,並且在該金屬基板表面形成陶瓷薄膜,由於將熱傳導率較大的金屬基板之體積加大,並且可形成電路,因此能製造一種熱阻比陶瓷基板要小的金屬-陶瓷複合基板。再者,金屬基板與金屬基材基板之情況大致相同地,能以低成本製造,並且作為陶瓷層之陶瓷薄膜係可藉由例如PVD法等方法形成,因此陶瓷薄膜並不需要進行燒結製程等複雜的製程,而整體能以比較低的成本加以製造。
根據本發明之金屬-陶瓷複合基板,例如搭載半導體裝置時,來自半導體裝置之熱在透過熱阻較低的陶瓷薄膜之後,進一步的通過金屬基板而加以放熱,因放熱性提升,故能獲得熱阻較小的金屬-陶瓷複合基板。因而,使用本發明之金屬-陶瓷複合基板之半導體裝置中的溫度上升變小,而能使半導體裝置之性能及壽命提升。
又,根據本發明,由於在金屬基板及該金屬基板表面使用陶瓷薄膜,因此整體能以低成本製造。
以下藉由圖式詳細說明本發明之實施形態。各圖中對相同或相對應之構件使用相同符號。
第1圖及第2圖係以示意方式顯示本發明金屬-陶瓷複合基板之構造的剖視圖。第1圖中,金屬-陶瓷複合基板10係由金屬基板11、在該金屬基板11之單面以覆蓋該金屬基板11全體之方式形成之陶瓷層12、以覆蓋該陶瓷層12之一部分或全面之方式形成在陶瓷層12表面之電極層13、以及形成在該電極層13表面的預定部位13A之銲錫層14所構成。
此處,以電極層13之預定部位13A來說,當發光二極體等之情況時,為全面亦可。存在未形成有銲錫層之電極層13B亦可。在該電極層13B形成圖案亦可,又,在電極層13B之一部分連接金線,形成電性電路亦可。
在金屬基板11之背面側設置電極層13及銲錫層14亦可。在金屬基板11之背面側、電極層13以及銲錫層14之間***陶瓷層12亦可。在第2圖所示之金屬-陶瓷複合基板10A之情況時,係顯示在金屬基板11之背面側,將陶瓷層12、電極層13以及銲錫層14依序積層之例。
以上述金屬基板11來說,可使用由銅、鋁等金屬構成之金屬基材基板。如上所述之金屬基材基板係具有例如200W/mK以上之熱傳導率為佳。
以上述陶瓷層12來說,係使用與金屬基板11之密接性良好的陶瓷薄膜,最好係熱阻較小的氮化鋁(AlN)等氮化物系陶瓷薄膜。
以電極層13來說係金屬為佳,尤其可使用金(Au)、鉑(Pt)、銀(Ag)、銅(Cu)、鐵(Fe)、鋁(Al)、鈦(Ti)以及鎢(W)之任一者。亦可為包含該等金屬之任一者之合金。
銲錫層14則不使用鉛(Pb),亦即以無鉛銲錫為佳。進一步的,使用包含銀、金、銅、鋅(Zn)、鎳(Ni)、銦(In)、鎵(Ga)、鉍(Bi)、鋁以及錫(Sn)之中兩種以上之元素之銲錫為佳。
此外,在上述金屬基板11與陶瓷層12之間以及/或上述電極層13與銲錫層14之間,為提高成膜時之密接性而配置密接層亦可。以密接層來說,可適當使用鈦。
接著,說明本發明金屬-陶瓷複合基板之半導體裝置的安裝例。
第3圖係以示意方式顯示於本發明之金屬-陶瓷複合基板搭載半導體裝置之構造的剖視圖。如第3圖所示,本發明之金屬-陶瓷複合基板10中,半導體裝置15之下部電極15A係可透過銲錫層14對金屬-陶瓷複合基板10進行銲錫接合。又,當使用由Au-Sn合金構成之銲錫層14時,半導體裝置15係能以無助焊劑的方式來進行銲錫接合。
另一方面,如圖所示,與右側之電極層13A係為絕緣狀態,並且可將半導體裝置15之上部電極15A藉由Au線16等,進行打線接合而連接在未形成有銲錫層之左側的電極層13B上。
此處,半導體裝置15意指如雷射二極體或發光二極體之發光元件、二極體、如使用於高頻放大或切換之電晶體及閘流晶體管之主動元件、積體電路等。第3圖中,雖顯示半導體裝置15作為搭載之電子零件,但亦可為包含被動元件或各種主動元件之電子電路。
接著,說明搭載有半導體裝置之金屬-陶瓷複合基板10之熱阻。金屬基板11之背面側搭載於封裝體或放熱體,當金屬-陶瓷複合基板10為能搭載半導體裝置15之程度的面積時,金屬-陶瓷複合基板10之熱阻RT 係能以下述數式(1)來計算。
此處,第1項係金屬-陶瓷複合基板10之熱阻成分。tM 、tC 、tE 、tS 以及κM 、κC 、κE 、κS 係分別為金屬基板11、陶瓷層12、電極層13A、銲錫層14之厚度以及熱傳導率,而A係半導體裝置15之面積。第2項係半導體裝置15之熱阻成分,接合深度為tD ,熱傳導率為κD 。第3項係熱傳導率為 κh 之封裝體或放熱體之熱阻成分。
金屬基板11之厚度係,若考量其操作之容易度等則為100μ m至1mm程度,而陶瓷層12、電極層13A以及銲錫層14之任一者之厚度皆大約為10μ m程度以下。因而,上述(1)式係近似於下述(2)式所示。
例如,金屬基板11由銅(κM =300W/mK)構成,且將其厚度tM 設為500μ m。陶瓷層12係由氮化鋁(κC =200W/mK)構成,且將其厚度tC 設為10μ m。電極層13A係由Au(κE =315W/mK)構成,且將其厚度tE 設為0.1μ m。而且,銲錫層14由Au-Sn(κS =50W/mK)構成,且將其厚度tS 設為5μ m。
此時,在上述(1)式之第1項所表示之金屬-陶瓷複合基板10中,若將金屬基板11之熱阻設為1,則陶瓷層12、電極層13A以及銲錫層14之熱阻係分別為0.03、0.0002、0.06程度。該等之各層中,熱阻係依銲錫層14、陶瓷層12、電極層13A之順序而遞增。即使如此,該等各層之熱阻的總合係為金屬基板11之熱阻之約1/15,則可知本發明之金屬-陶瓷複合基板10之熱阻係可以上述(2)式近似。
接著,說明金屬-陶瓷複合基板10A之熱阻。此時,亦在金屬基板11之背面,與其表面側同樣地設置陶瓷層12、電極層13A以及銲錫層14,金屬基板11之背面側的各層之材質與厚度作成與表面側之值相同。金屬-陶瓷複合基板10A之熱阻RT ’係能以在上述(1)式,進一步的加上設在金屬基板11之背面側之陶瓷層12、電極層13A以及銲錫14層之熱阻成分之下述(3)式來計算。
熱阻RT ’係與在金屬-陶瓷複合基板10說明時同樣地,相較於金屬基板11之熱阻,設在金屬基板11之兩面側的陶瓷層12、電極層13A以及銲錫層14之熱阻成分非常地小。因而,在金屬基板11之表面及背面設有陶瓷層12、電極層13A以及銲錫層14之金屬-陶瓷複合基板10A的熱阻RT ’,亦能以上述(2)式近似。
藉此,根據本發明之金屬-陶瓷複合基板10及10A,若將作為絕緣物之陶瓷層12的厚度,作的比金屬基板11更充分地薄,則熱阻係藉由更厚的金屬基板11來決定。因而,本發明之金屬-陶瓷複合基板10之熱阻係成為與金屬基板11大致相同程度之值。
說明本發明之金屬-陶瓷複合基板之變形例。
第4圖及第5圖係以示意方式顯示本發明金屬-陶瓷複合基板的變形例之構造的剖視圖。第4圖所示之金屬-陶瓷複合基板20與第1圖所示之金屬-陶瓷複合基板10相異之點,係直接在陶瓷層12上形成與上述銲錫層14不同的銲錫層22。該銲錫層22係與電極層13連接構成電性電路亦可。亦可作成用以搭載其他電子電路零件之配線圖案。銲錫層22係可在形成設於電極層13上之銲錫層14時同時地形成。
在金屬基板11之背面側亦可設置電極層13及銲錫層14。在金屬基板11之背面側、電極層13以及銲錫層14之間***陶瓷層12亦可。在第5圖所示之金屬-陶瓷複合基板20A之情況,顯示在金屬基板11之背面側,將陶瓷層12、電極層13以及銲錫層14依序積層之例。
說明本發明金屬-陶瓷複合基板之另一變形例30。
第6圖及第7圖係以示意方式顯示本發明金屬-陶瓷複合基板的另一變形例之構造的剖視圖。第6圖所示之金屬-陶瓷複合基板30與第1圖所示之金屬-陶瓷複合基板10相異之點,係在陶瓷層12與電極層13A之間***有陶瓷層保護膜24。
陶瓷層保護膜24係為於製造本發明之金屬-陶瓷複合基板30時,最初被覆於陶瓷層12全面之層,且在形成電極層13A及銲錫層14之圖案時之製程中,藉由蝕刻等將陶瓷層12予以蝕刻,及用以防止其表面粗度變大而設。該陶瓷層保護膜24係在形成銲錫層14後,可藉由去除不必要的區域,進行與形成在金屬-陶瓷複合基板30上之電極層13A之絕緣分離。
此處,陶瓷層保護膜24係為與陶瓷層12之密接性良好,且與電極層13為不同的金屬為佳,而可使用鈦、鉑、鎳、鎢、鉬(Mo)、銀、銅、鐵、鋁以及金之任一者。亦可包含該等金屬兩種以上。例如,亦可在陶瓷層12上積層鈦而形成。
在金屬基板11之背面側亦可設置電極層13及銲錫層14。在金屬基板11之背面側、電極層13以及銲錫層14之間***陶瓷層12亦可。在第7圖所示之金屬-陶瓷複合基板30A之情況,顯示在金屬基板11之背面側,將陶瓷層12、電極層13以及銲錫層14依序積層之例。
本發明之金屬-陶瓷複合基板10、20、30中,上述陶瓷層12係亦可形成在金屬基板11之表面全體。因應必要,亦可僅形成在金屬基板11之表面的預定部分。此種情況,在沈積陶瓷層12之前,利用光微影法(photolithography)施行圖案化之後,沈積陶瓷層12,之後利用所謂將圖案化所使用之阻劑膜進行蝕刻之舉離法(lift-off method),可僅在預定區域形成陶瓷層12。在將預定部分經開口之金屬遮罩載置於金屬基板11上之狀態下,沈積陶瓷層12亦可。此時僅在金屬遮罩之開口部形成有陶瓷層12。
如本發明之金屬-陶瓷複合基板10A、20A、30A所示,不僅在金屬基板11之表面側的單面,在背面側,亦即在兩面設置陶瓷層12、電極層13以及銲錫層14亦可。因應必要,在陶瓷層12與電極層13之間***陶瓷層保護膜24亦可。
本發明之金屬-陶瓷複合基板10、10A、20、20A、30、30A之特徵在於,在低成本之金屬基板11表面形成放熱性良好的陶瓷薄膜之陶瓷層12。根據本發明之金屬-陶瓷複合基板10、10A、20、20A、30、30A,由於能形成熱阻小的接合,因此使用金屬-陶瓷複合基板10、10A、20、20A、30、30A之半導體裝置中的熱阻將變小,而能使半導體裝置之性能及壽命提升。
接著,說明本發明之金屬-陶瓷複合基板之製造方法。
首先,準備金屬基板11,將其兩面研磨之後,將研磨完之金屬基板11洗淨,進行表面清潔化,以在金屬基板11之表面形成作為陶瓷層12之AlN薄膜。該陶瓷層12係可藉由例如PVD法(物理蒸鍍法:physical vapor deposition)及CVD法(化學氣相反應法:chemical vapor deposition)形成。
繼之,藉由光微影法進行圖案化。具體而言,將金屬基板11之表面全體使用旋轉塗佈機均勻塗佈阻劑之後,藉由烘焙機進行預定的烘烤,再使用遮罩對準裝置(mask aligner)進行γ線接觸曝光。
曝光後,藉由四甲基胺系之顯影液,將成為電極層13之部分的阻劑溶解,而使陶瓷層12露出。
接著,藉由舉離製程,在陶瓷層12上面進行電極層13之形成。具體而言,藉由阻劑剝離液,將於上述圖案化製程中形成之阻劑膜,與蒸鍍在阻劑膜上之金屬層一起利用阻劑膜之膨潤來進行去除。藉此,可在陶瓷層12上形成具有預定圖案之電極層13。以阻劑剝離液來說,可使用丙酮、異丙酮以及其他之阻劑剝離液。
與上述電極層13同樣地,進行使用光微影法及真空蒸鍍裝置之舉離製程,在形成於金屬基板11表面的電極層13之一部分形成銲錫層14。
將所得之金屬基板11,使用切割裝置等分割成預定之次載具10的尺寸。以上,即完成金屬-陶瓷複合基板10。
上述金屬-陶瓷複合基板20之情況,在形成電極層13上之銲錫層14的同時,形成欲形成於陶瓷層12上之銲錫層22即可。
上述金屬-陶瓷複合基板30之情況,在形成陶瓷層12後,於陶瓷層12表面之全面形成成為陶瓷層保護膜24之金屬膜。其後的製程係可與金屬-陶瓷複合基板10之情況同樣地進行。形成銲錫層14後,因應必要,藉由蝕刻將不要的陶瓷層保護膜24去除即可。
又,在本發明之金屬-陶瓷複合基板10A、20A、30A之情況中,不僅限於在基板表面側,更可進一步的藉由以與金屬基板11之表面側同樣的製程設置陶瓷層12、電極層13及銲錫層14來在其背面側進行製造。因應必要,在陶瓷層12與電極層13之間***陶瓷層保護膜24亦可。
本發明金屬-陶瓷複合基板10、10A、20、20A、30、30A之製造方法的特徵在於,在Cu、Al等之金屬基板11之表面,或表面及背面,亦即在兩面形成AlN等之陶瓷薄膜12。根據本發明之金屬-陶瓷複合基板10、10A、20、20A、30、30A之製造方法,可以低成本、良率佳地製造與半導體裝置15之熱阻小,而放熱性良好的金屬-陶瓷複合基板。
[實施例]
以下根據實施例,更詳細說明本發明。
首先,說明實施例之金屬-陶瓷複合基板30A之製造方法。
將由大小50mm×50mm、厚度300μ m、熱傳導率為300W/mK由Cu構成之金屬基板11兩面洗淨,進行表面清潔化,在該金屬基板11之表面及背面全體,藉由PVD法形成由厚度10μ m之AlN構成之陶瓷層12。以PVD法來說,使用了濺鍍法。使用Al作為靶材(tavget),進一步的,同時供應氮氣藉此沈積AlN薄膜。該AlN薄膜之熱傳導率係為200W/mK。
接著,在AlN薄膜12之表面及背面之全面,藉由真空蒸鍍裝置,將熱傳導率為20W/mK之Ti沈積0.05μ m而成為陶瓷層保護膜24。
因藉由光微影法進行圖案化,將形成有AlN薄膜12及陶瓷層保護膜24之金屬基板11之表面全體,使用旋轉塗佈機均勻塗佈阻劑後,藉由烘焙機進行預定的烘烤,再使用遮罩對準裝置進行γ線接觸曝光。曝光用之遮罩係以同時能圖案化1mm見方之次載具尺寸、2500個份之方式設計遮罩。
曝光後,藉由四甲基胺系液顯影液,將成為電極層13之部分的阻劑溶解,使陶瓷層保護膜24露出。此時,在金屬基板11之背面側之陶瓷層保護膜24並未施行圖案化。
藉由真空蒸鍍裝置在金屬基板11之表面及背面側形成之陶瓷層保護膜24,蒸鍍熱傳導率為315W/mK之金,且對形成在金屬基板11之表面側之陶瓷層保護膜24之阻劑圖案施行舉離製程。具體而言,藉由使用丙酮溶解全體阻劑,將電極層13以外之Au去除,而形成預定之電極層13。電極層13之厚度係為0.1μ m,其尺寸係兩面皆為800μ m見方。
與電極層13同樣地使用光微影法及真空蒸鍍裝置,形成在金屬基板11表面之電極層13的一部分,藉由舉離製程形成厚度5μ m之銲錫層14。以銲錫層14來說,使用了熱傳導率為50W/mK之Au0 . 8 Sn0 . 2 (元素比)。銲錫層14之尺寸係半導體元件接合面為500μ m見方、次載具接合面為800μ m見方。此時,在設於金屬基板11之背面側之Au層上的銲錫層14並未施行圖案化。
將所獲得之金屬基板11,使用切割裝置切斷成1mm見方,即製造出實施例之金屬-陶瓷複合基板30A。
接著說明比較例。
(比較例1)
如第8圖所示,在由熱傳導率為200W/mK、厚度為520μ m之AlN構成之陶瓷基板51之表面及背面,藉由蒸鍍法形成由厚度0.05μ m之Ti及厚度0.1μ m之Au構成之電極層52,以及由厚度5μ m之Au0 . 8 Sn0 . 2 (元素比)構成之銲錫層53,而製造出陶瓷基板之電路基板50。陶瓷基板51之大小與設於其表面側之電極層52及銲錫層53之圖案尺寸,係作成與實施例相同。
(比較例2)
如第9圖所示,在由熱傳導率為300W/mK、厚度為500μ m之Cu構成之金屬基板61之兩面,形成厚度10μ m之填充物(10W/mK)之絕緣層62,在其上藉由蒸鍍法,形成由厚度0.05μ m之Ti及厚度0.1μ m之Au構成之電極層63,以及由厚度5μ m之Au0 . 8 Sn0 . 2 (元素比)構成之銲錫層64,而製造出電路基板60。金屬基板61之大小與設於其表面側之電極層63及銲錫層64之圖案尺寸,係作成與實施例相同。
以下,說明實施例之金屬-陶瓷複合基板30A以及比較例1、2之電路基板50、60之諸特性。
相對於以實施例製造之金屬-陶瓷複合基板30A,以及以比較例1、2製造之電路基板50、60,分別對銲錫層接合發光二極體,測定其通電後之溫度上升及熱阻(參照表1)。
實施例之金屬-陶瓷複合基板30A中,熱阻係為2.0℃/W,晶片側溫度與放熱側溫度之溫度差為3.0℃。相對於此,比較例1之電路基板50中,熱阻係為2.8℃/W,晶片側溫度與放熱側溫度之溫度差為4.2℃。比較例2之電路基板60中,熱阻係為3.9℃/W,晶片側溫度與放熱側溫度之溫度差為5.8℃。
根據上述實施例及比較例,用以搭載實施例之半導體裝置15之金屬-陶瓷複合基板30A中,藉由在金屬基板11表面形成由陶瓷薄膜構成之陶瓷層12,而獲得低成本,且熱阻小的金屬-陶瓷複合基板30A。
本發明並非限定於上述實施例記載之發光二極體者,只要係為具有背面電極之半導體裝置及電路零件即能適用,在申請專利範圍記載之發明之範圍內能做各種變形,該等當然亦包含在本發明之範圍。例如,半導體裝置並未限定於發光二極體等。作為金屬基板11,雖已說明使用Cu、Al之情況,但並非限定於此,金屬基板11係由其他金屬構成亦可。
上述之實施形態中,陶瓷層12係由AlN構成,但並非限定於此,由其他陶瓷材料構成亦可。電極層13及銲錫層14之圖案係以成為目的之電路構成之方式適當設計即可。
10、10A、20、20A、30、30A...金屬-陶瓷複合基板
11、61...金屬基板
12...陶瓷層(陶瓷薄膜)
13、52、63...電極層
13A...預定部位
13B...未形成有銲錫層之電極層
14、53、64...銲錫層
15...半導體裝置
15A...下部電極
15B...上部電極
16...Au線
22...銲錫層(形成在陶瓷層上之銲錫層)
24...陶瓷層保護膜
50、60...電路基板
51...陶瓷基板
62...絕緣層
第1圖係以示意方式顯示本發明金屬-陶瓷複合基板之構造的剖視圖。
第2圖係以示意方式顯示本發明金屬-陶瓷複合基板之構造的剖視圖。
第3圖係以示意方式顯示於本發明金屬-陶瓷複合基板搭載半導體裝置之構造的剖視圖。
第4圖係以示意方式顯示本發明金屬-陶瓷複合基板之變形例之構造的剖視圖。
第5圖係以示意方式顯示本發明金屬-陶瓷複合基板之變形例之構造的剖視圖。
第6圖係以示意方式顯示本發明金屬-陶瓷複合基板之另一變形例之構造的剖視圖。
第7圖係以示意方式顯示本發明金屬-陶瓷複合基板之另一變形例之構造的剖視圖。
第8圖係以示意方式顯示比較例1之構成的剖視圖。
第9圖係以示意方式顯示比較例2之構成的剖視圖。
10...金屬-陶瓷複合基板
11...金屬基板
12...陶瓷層(陶瓷薄膜)
13...電極層
13A...預定部位
13B...未形成有銲錫層之電極層
14...銲錫層

Claims (7)

  1. 一種金屬-陶瓷複合基板,係具備金屬基板、形成在該金屬基板上之陶瓷層、形成在該陶瓷層上之陶瓷層保護膜、形成在該陶瓷層保護膜上之電極層以及形成在該電極層上之銲料層,其中上述陶瓷層係由使用氮化鋁之陶瓷薄膜所構成,上述陶瓷層保護膜係含有與上述電極層為不同的鈦、鉑、鎳、鎢、鉬、銀、銅、鐵、鋁以及金之任一者或此等金屬之二種以上,在形成上述電極層及上述銲料層之圖案時,使上述陶瓷層不會被蝕刻製程所蝕刻,且防止該陶瓷層之表面粗度變大,上述銲料層係可用無助焊劑的方式來進行銲料接合之不使用鉛的銲料層。
  2. 如申請專利範圍第1項之金屬-陶瓷複合基板,其中,在前述陶瓷層上未形成前述陶瓷層保護膜之區域,進一步直接形成另外的銲料層。
  3. 如申請專利範圍第1項之金屬-陶瓷複合基板,其中,前述陶瓷層、前述陶瓷層保護膜、前述電極層及前述銲料層,係分別積層於前述金屬基板的背面與表面兩面。
  4. 如申請專利範圍第1項之金屬-陶瓷複合基板,其中,前述金屬基板由銅或鋁構成。
  5. 如申請專利範圍第1項至第3項中任一項之金屬-陶瓷複合基板,其中,前述銲料層係包含銀、金、銅、鋅、鎳、銦、鎵、鉍、鋁以及錫之中兩種以上之元素。
  6. 如申請專利範圍第5項之金屬-陶瓷複合基板,其中, 前述銲料層係包含金及錫。
  7. 一種金屬-陶瓷複合基板之製造方法,該金屬-陶瓷複合基板係由金屬基板、形成在該金屬基板上之陶瓷層、形成在該陶瓷層上之陶瓷層保護膜、形成在該陶瓷層保護膜上之電極層以及形成在該電極層上之銲料層所構成,該製造方法包含:研磨上述金屬基板之表面,進行該金屬基板之表面清潔化之製程;在上述進行過表面清潔化之金屬基板表面,形成使用氮化鋁之陶瓷薄膜作為上述陶瓷層之製程;在上述陶瓷薄膜上之全面,藉由物理蒸鍍法形成陶瓷層保護膜之製程;藉由舉離法,在上述陶瓷層保護膜上形成預定圖案之上述電極層以及上述銲料層的製程;以及形成上述特定圖案之上述電極層以及上述銲料層後,將在未形成該特定圖案之區域的不要的陶瓷層保護膜除去之製程,其中,上述陶瓷層保護膜係含有與上述電極層為不同的鈦、鉑、鎳、鎢、鉬、銀、銅、鐵、鋁以及金之任一者或此等金屬之二種以上,在形成上述電極層及上述銲料層之圖案時,使上述陶瓷層不會被蝕刻製程所蝕刻,且防止該陶瓷層表面粗度變大,上述銲料層係可用無助焊劑的方式來進行銲料接合之不使用鉛的銲料層。
TW095116195A 2005-06-06 2006-05-08 金屬-陶瓷複合基板及其製造方法 TWI436436B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005166162A JP5413707B2 (ja) 2005-06-06 2005-06-06 金属−セラミック複合基板及びその製造方法

Publications (2)

Publication Number Publication Date
TW200701375A TW200701375A (en) 2007-01-01
TWI436436B true TWI436436B (zh) 2014-05-01

Family

ID=37498290

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095116195A TWI436436B (zh) 2005-06-06 2006-05-08 金屬-陶瓷複合基板及其製造方法

Country Status (7)

Country Link
US (1) US20090151982A1 (zh)
EP (2) EP2224479B1 (zh)
JP (1) JP5413707B2 (zh)
KR (1) KR100913762B1 (zh)
CN (1) CN101233612B (zh)
TW (1) TWI436436B (zh)
WO (1) WO2006132087A1 (zh)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101298659B (zh) * 2007-04-30 2010-12-01 汉达精密电子(昆山)有限公司 绝缘导热金属基板的制造方法
CN101573001B (zh) * 2008-04-29 2012-07-04 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
CN101572996B (zh) * 2008-04-29 2011-12-07 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
CN101572998B (zh) * 2008-04-29 2012-07-18 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
CN101572993B (zh) * 2008-04-29 2012-10-03 汉达精密电子(昆山)有限公司 绝缘导热金属基板上真空溅镀形成导电线路的方法
US9387532B2 (en) * 2009-02-13 2016-07-12 Denka Company Limited Composite substrate for LED light emitting element, method of production of same, and LED light emitting element
DE102009014993B4 (de) * 2009-03-26 2011-07-14 Continental Automotive GmbH, 30165 Verfahren zum elektrischen Kontaktieren eines elektronischen Bauelements
DE102009017434A1 (de) * 2009-04-15 2010-10-28 Continental Automotive Gmbh Elektronisches Bauelement und Verfahren zum elektrischen Kontaktieren eines elektronischen Bauelements als Stapel
KR101039771B1 (ko) 2009-05-20 2011-06-09 권오국 고방열 금속판을 이용한 피씨비 제조방법
KR101045847B1 (ko) * 2009-06-12 2011-07-01 (주)솔라원 열 계면층을 갖는 메탈 인쇄회로기판
KR101167425B1 (ko) * 2010-09-16 2012-07-23 삼성전기주식회사 방열기판 및 그 제조방법
CN102054713A (zh) * 2010-09-26 2011-05-11 浙江大学 金属基氮化铝板绝缘基板制备方法
US8803183B2 (en) 2010-10-13 2014-08-12 Ho Cheng Industrial Co., Ltd. LED heat-conducting substrate and its thermal module
CN103114261A (zh) * 2011-11-16 2013-05-22 和淞科技股份有限公司 复合式金属陶瓷基板的制法及其结构
CN103117335A (zh) * 2011-11-16 2013-05-22 和淞科技股份有限公司 具有电路的复合式金属陶瓷基板的制法及其结构
WO2014073038A1 (ja) * 2012-11-06 2014-05-15 日本碍子株式会社 発光ダイオード用基板
EP2919287B1 (en) * 2012-11-06 2019-12-25 NGK Insulators, Ltd. Substrate for light emitting diodes
WO2014122971A1 (ja) * 2013-02-06 2014-08-14 シャープ株式会社 発光装置、および、発光装置の製造方法
CN103166103A (zh) * 2013-03-18 2013-06-19 中国工程物理研究院应用电子学研究所 一种水电绝缘的半导体激光器线阵的封装方法
DE102014116529A1 (de) * 2014-11-12 2016-05-12 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
JP6311887B2 (ja) * 2015-05-15 2018-04-18 豊田合成株式会社 発光素子用基板および発光装置
CN109863835B (zh) 2016-09-27 2022-04-05 奥特斯奥地利科技与***技术有限公司 部件承载件及其组成件的制造方法
JP2018142569A (ja) * 2017-02-27 2018-09-13 株式会社アカネ 放熱基板
CN107708296A (zh) * 2017-10-19 2018-02-16 深圳职业技术学院 一种高导热的金属基电路板及其制作方法
TWI656231B (zh) * 2017-12-05 2019-04-11 國家中山科學研究院 Method for preparing polycrystalline aluminum nitride high reflection mirror
DE102018104521B4 (de) 2018-02-28 2022-11-17 Rogers Germany Gmbh Metall-Keramik-Substrate
CN109390843A (zh) * 2018-12-10 2019-02-26 业成科技(成都)有限公司 发射模组及其制作方法
CN111490018A (zh) * 2019-01-29 2020-08-04 瑷司柏电子股份有限公司 具有金属导热凸块接垫的陶瓷基板元件、组件及制法
CN114727504B (zh) * 2022-03-16 2024-07-05 景旺电子科技(龙川)有限公司 金属陶瓷复合基板及其制作方法
TWI822346B (zh) * 2022-09-20 2023-11-11 健策精密工業股份有限公司 電子裝置及其製造方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57122592A (en) * 1981-01-23 1982-07-30 Tokyo Shibaura Electric Co Method of producing hybrid integrated circuit
JPH0697663B2 (ja) * 1986-01-10 1994-11-30 沖電気工業株式会社 半導体素子の製造方法
JP2664744B2 (ja) * 1988-11-02 1997-10-22 株式会社東芝 窒化アルミニウム薄膜回路基板
JP3156798B2 (ja) 1991-07-24 2001-04-16 電気化学工業株式会社 半導体搭載用回路基板
JP2762007B2 (ja) 1992-12-04 1998-06-04 住友金属工業株式会社 金属薄膜積層セラミックス基板
US5965193A (en) * 1994-04-11 1999-10-12 Dowa Mining Co., Ltd. Process for preparing a ceramic electronic circuit board and process for preparing aluminum or aluminum alloy bonded ceramic material
JP2000077583A (ja) * 1998-09-03 2000-03-14 Sumitomo Metal Electronics Devices Inc 電子部品用パッケージおよびその製造方法
JP3092603B2 (ja) * 1998-11-02 2000-09-25 日本電気株式会社 半導体素子実装基板又は放熱板とその製造方法及び該基板又は放熱板と半導体素子との接合体
JP3648189B2 (ja) * 2001-09-28 2005-05-18 同和鉱業株式会社 金属−セラミックス回路基板
JP2004031485A (ja) * 2002-06-24 2004-01-29 Nissan Motor Co Ltd 半導体装置
JP2004119515A (ja) * 2002-09-24 2004-04-15 Neo Led Technology Co Ltd 高い放熱性を有する発光ダイオード表示モジュール及びその基板
US6854636B2 (en) * 2002-12-06 2005-02-15 International Business Machines Corporation Structure and method for lead free solder electronic package interconnections
JP4132038B2 (ja) * 2003-03-24 2008-08-13 京セラ株式会社 発光装置
KR101097075B1 (ko) * 2003-04-15 2011-12-22 덴끼 가가꾸 고교 가부시키가이샤 금속 베이스 회로 기판과 그 제조 방법
JP2005116621A (ja) * 2003-10-03 2005-04-28 Nissan Motor Co Ltd 半導体装置
US7193838B2 (en) * 2003-12-23 2007-03-20 Motorola, Inc. Printed circuit dielectric foil and embedded capacitors
JP2006269966A (ja) * 2005-03-25 2006-10-05 Toyota Industries Corp 配線基板およびその製造方法

Also Published As

Publication number Publication date
KR100913762B1 (ko) 2009-08-25
EP1909321A1 (en) 2008-04-09
EP2224479A3 (en) 2010-10-06
JP5413707B2 (ja) 2014-02-12
US20090151982A1 (en) 2009-06-18
EP2224479A2 (en) 2010-09-01
TW200701375A (en) 2007-01-01
KR20080014033A (ko) 2008-02-13
WO2006132087A1 (ja) 2006-12-14
JP2006339611A (ja) 2006-12-14
CN101233612B (zh) 2013-09-25
EP2224479B1 (en) 2016-05-11
CN101233612A (zh) 2008-07-30
EP1909321B1 (en) 2011-08-17
EP1909321A4 (en) 2009-09-23

Similar Documents

Publication Publication Date Title
TWI436436B (zh) 金屬-陶瓷複合基板及其製造方法
US7838410B2 (en) Method of electrically connecting element to wiring, method of producing light-emitting element assembly, and light-emitting element assembly
TW583722B (en) Circuit board and method for manufacturing same
US20060198162A1 (en) Light emitting element mounting member, and semiconductor device using the same
JP2006261569A (ja) サブマウントおよびその製造方法
JPH0722435A (ja) 半導体装置およびその製造方法
TW554417B (en) Circuit board, method for manufacturing same, and high-output module
JP4822155B2 (ja) サブマウント及びその製造方法
US20170125651A1 (en) Light emitting device and method of manufacturing light emitting module
EP0460785B1 (en) Semiconductor device having a heat sink
JP2012074591A (ja) 回路基板および電子装置
WO2003069743A1 (fr) Embase et dispositif a semiconducteur
EP1274125A2 (en) Circuit board, method for manufacturing same, and high-output module
JP2006286944A (ja) サブマウント及びその製造方法
JP2013098481A (ja) 半導体装置
JP7237687B2 (ja) 配線基板、電子装置及び電子モジュール
JP2007109829A (ja) 半田接合形成方法
KR102496718B1 (ko) 복층구조를 가지는 금속기판 및 그 제조방법
US20230138349A1 (en) Embedded packaging structure
KR100708604B1 (ko) 저융점의 금속범프를 이용한 플립칩 발광소자 및 그의제조방법
EP4099375A1 (en) Electronic component mounting package and electronic device
JP2024003845A (ja) セラミックス薄膜メタライズ基板の製造方法、チップオンサブマウントの製造方法、および、半導体モジュールの製造方法
JP6258635B2 (ja) 回路基板および電子装置
JP2016032032A (ja) 回路基板、および電子装置
JP2011100897A (ja) 回路基板の製造方法及び回路基板

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees