TWI435395B - 堆疊及對位複數積體電路的方法及系統、以及製造具有對位及堆疊裝置類型之積體電路的方法 - Google Patents

堆疊及對位複數積體電路的方法及系統、以及製造具有對位及堆疊裝置類型之積體電路的方法 Download PDF

Info

Publication number
TWI435395B
TWI435395B TW98144940A TW98144940A TWI435395B TW I435395 B TWI435395 B TW I435395B TW 98144940 A TW98144940 A TW 98144940A TW 98144940 A TW98144940 A TW 98144940A TW I435395 B TWI435395 B TW I435395B
Authority
TW
Taiwan
Prior art keywords
stacking
funnel
integrated circuits
aligning
integrated circuit
Prior art date
Application number
TW98144940A
Other languages
English (en)
Other versions
TW201029074A (en
Inventor
Kai Ming Ching
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Publication of TW201029074A publication Critical patent/TW201029074A/zh
Application granted granted Critical
Publication of TWI435395B publication Critical patent/TWI435395B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02123—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body inside the bonding area
    • H01L2224/02125—Reinforcing structures
    • H01L2224/02126—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13009—Bump connector integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13575—Plural coating layers
    • H01L2224/1358—Plural coating layers being stacked
    • H01L2224/13582—Two-layer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605—Shape
    • H01L2224/16057—Shape in side view
    • H01L2224/16059—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16147—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/811—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01002—Helium [He]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

堆疊及對位複數積體電路的方法及系統、以及製造具有對位及堆疊裝置類型之積體電路的方法
本發明係有關於積體電路，且特別是有關於堆疊及對位複數積體電路的方法及系統。
在半導體製程中，經常需要精確堆疊及結合二或以上之積體電路晶片或晶圓。進行對位及堆疊時必需在具有高度精準度的狀況下被施行，以避免損傷該晶片或晶圓。如第1圖所示，在傳統使用“凸塊對凸塊”的結合製程中，在第一晶片或晶圓之一系列凸塊或突出部係與第二晶片或晶圓對應之一系列凸塊或突出部進行對位及結合。請參照第1圖，該傳統製程不具有任何可確保兩晶片或晶圓進行合適之機械對位的手段，因此需要一具有高度精確的結合工具。第1圖所示之狀況下，係顯示一高度錯位的對位結果。即使少量的對位錯誤也會對所得之結構的電及機械性質產生不良影響。
因此，目前極需一用來對晶片或晶圓提供機械對位之積體電路堆疊及結合之系統及方法，以降低積體電路在進行對位時造成損害的風險。
在一較佳實施例中，本發明包含一種堆疊及對位複數積體電路的方法。該方法包含以下步驟：提供一具有至少一漏斗形插槽之第一積體電路，提供一具有至少一突出部之第二積體電路，將該至少一突出部與該至少一漏斗形插槽進行對位，以及將該第一積體電路與該第二積體電路進行結合。
在另一較佳實施例中，本發明包含一種堆疊及對位複數積體電路的系統。該系統包含具有至少一漏斗形插槽之第一積體電路，金屬化擴散阻障層配置於該漏斗形插槽之內部，以及一第二積體電路，其中該至少一漏斗形插槽係用以承接該第二積體電路之一突出部。
在另一較佳實施例中，本發明包含製造具有一對位及堆疊裝置類型之積體電路的方法。該方法包含形成複數蝕刻停止層於一介電材料，該介電材料包含複數金屬層，該蝕刻停止層係定義出一被蝕刻區域之邊界，形成一光阻層於該介電材料之一表面，蝕刻該介電材料至一預定深度以形成一漏斗形插槽，以及形成一金屬化擴散阻障層於該漏斗形插槽之內部。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。各特定實施例中的組成及配置將會在以下作描述以簡化本發明。這些為實施例並非用於限定本發明。
首先，請參照第2圖，係顯示本發明一實施例。如第2圖所示，提供一下晶片或晶圓12，其具有至少一插槽14配置於一上表面16。該插槽14可以為任何適當的形狀，一般來說可具有一圓形開口。該插槽14之側壁向內延伸至該下晶片或晶圓12的本體以形成具有漏斗形狀之插槽。此外，配置於該上表面16之插槽14可為任何數量。在一實施例中，第2圖顯示該晶片或晶圓12具有十二個插槽。如所繪示之插槽14係分佈於該下晶片或晶圓12之上表面16，一熟知此技藝之人士將可了解本發明亦可以其他習知配置的方式來加以實施，其中插槽14係與該下晶片或晶圓12之周圍對齊，形成於該上表面16之中心區域，或者是其他的變化。
仍請參照第2圖，顯示一上晶片或晶圓18，其具有複數凸塊或突出部20配置於一下表面22之上。相似於該下晶片或晶圓12，該上晶片或晶圓18可具有任何數量之凸塊或突出部20配置於其上。然而，配置於該上晶片或晶圓18之下表面22之該凸塊或突出部的數量較佳係對應配置於該下晶片或晶圓12之上表面之插槽14的數量。因此，該上晶片或晶圓18可例如具有12個凸塊或突出部20配置於其上。
請參照第3圖，係顯示該上晶片或晶圓18與該下晶片或晶圓12進行堆疊及結合。該插槽14配置於該下晶片或晶圓12之上表面16用以承接配置於該上晶片或晶圓18之下表面的該凸塊或突出部20。由於該插槽14具有漏斗形狀允許該上晶片或晶圓18及該下晶片或晶圓12進行主動對位，符合所需之精確度，因此降低該上及下晶片或晶圓12及18受損的風險以及該堆疊及結合程序的所有成本。
請參照第4A-4D圖，係顯示製造如第2圖及第3圖所示之具有插槽的積體電路的流程。如第4A圖所示，該下晶片或晶圓12係典型地由一介電材料40所構成。該介電材料40可為任何適合的材料，例如SiN、SiO2、或SiC。該介電材料40典型地僅包含數個膜層42。數個金屬層M1-M7、接觸栓V1-V6、及金屬蝕刻停止層44係嵌入該介電材料40中。該蝕刻停止層44包含複數個側壁溝槽46。這些側壁溝槽46增加焊料之結合區域。
如第4B、4C、及4D圖所示，該光阻層48係被形成於該介電材料層40之上表面16。該光阻層48可避免該介電材料40在蝕刻過程中受到損害。接著，介於該蝕刻停止層44之介電材料係被一蝕刻步驟加以移除。該蝕刻步驟可為任何合適之製程，較佳係為一乾蝕刻或一溼蝕刻製程。在該蝕刻製程過程中，該光阻層48係避免不需被蝕刻的介電材料40被蝕刻。該蝕刻停止層44係對蝕刻製程具有抵抗能力，因此可確保該插槽14可形成所需之漏斗形結構。當該蝕刻製程完成後，將該光阻層48移除。
請參照第5A-5C圖，係顯示本發明一實施例所述堆疊及結合二個積體電路之方法。一金屬化擴散阻障層50係被形成於該插槽14之內部。該金屬化擴散阻障層50典型地具有一厚度大於2微米，且該金屬化擴散阻障層50可僅由一擴散阻障層(例如鎳)或是焊料潤濕層(例如金)所構成。該金屬化擴散阻障層50之形成具有二個目的。第一，該金屬化擴散阻障層50可加強該插槽14之一底部層52。第二，該金屬化擴散阻障層50可平滑該插槽之側壁54以提供較佳之機械結合對位。
如第5B及5C圖所示，該插槽14係用來承接配置於該上晶片或晶圓18上表面22之一凸塊或突出部20。舉例來說，第5B圖所示之該凸塊或突出部20係為一焊料凸塊。該插槽14之平滑測壁54係用來協助該上晶片或晶圓18以適當安置及對齊於該下晶片或晶圓12。當座落於該插槽14中時，該凸塊係與該側壁54結合，因此使得上下晶片或晶圓12及18組裝完成。
請參照第6圖，係繪示在本發明一較佳實施例中所使用之凸塊或突出部20為一由該上晶片或晶圓18之下表面22所突出之一銅凸塊或一直通矽晶穿孔(Through-Silicon Via、TSV)銅釘。如第6圖所示，該金屬化擴散阻障層50亦可直接形成於該凸塊或突出部20之上，以取代形成於該插槽14之側壁54上。或是，該金屬化擴散阻障層50同時形成於該凸塊或突出部20及該插槽14之側壁54之上。
請參照第7圖，係繪示在本發明一較佳實施例中，一金屬條70嵌入環繞該插槽14之區域內的該介電材料40。該金屬條陣列係作用以強化該介電材料40以及形成一用來結合之堅固結構。
請參照第8圖，係繪示在本發明一較佳實施例中，該上晶片或晶圓18可包含一插槽80，其中該插槽80係對應配置於該下晶片或晶圓12之該插槽14。在使用時，係將一焊料球82配置於該上晶片或晶圓18及下晶片或晶圓12各自的插槽14及80間。該插槽14及80之傾斜的側壁協助該上及下晶片或晶圓18及12在結合時之對位。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
12．．．下晶片或晶圓
14．．．插槽
16．．．上表面
18．．．上晶片或晶圓
20．．．凸塊或突出部
22．．．下表面
40．．．介電材料
42．．．膜層
44．．．金屬蝕刻停止層
46．．．側壁溝槽
48．．．光阻層
50．．．金屬化擴散阻障層
52．．．底部層
54．．．插槽之側壁
70．．．金屬條
80．．．插槽
82．．．焊料球
M1-M7．．．金屬層
V1-V6．．．接觸栓
第1圖係顯示習知堆疊及對位積體電路之方法。
第2圖係一透視圖，顯示一根據本發明原則所述之對位及堆疊積體電路系統。
第3圖係一側視剖面圖，顯示第2圖所述之系統在進行二積體電路的堆疊及結合之配置。
第4A-4D圖係繪示製造本發明所述之具有一對位插槽之積體電路的方法，其各種中間步驟。
第5A-5C圖係為一系列之側視剖面圖，顯示本發明一實施例之操作。
第6圖係一側視剖面圖，顯示本發明另一實施例之操作。
第7圖係一側視剖面圖，顯示本發明一實施例所述之具有一強化金屬條狀陣列之對位插槽。
第8圖係一側視剖面圖，顯示本發明又一實施例之操作。
12．．．下晶片或晶圓
14．．．插槽
16．．．上表面
18．．．上晶片或晶圓
20．．．凸塊或突出部
22．．．下表面

Claims (20)

  1. 一種堆疊及對位複數積體電路的方法，包含：提供一第一積體電路包含複數金屬層，該第一積體電路具有至少一漏斗形插槽，其中該至少一漏斗形插槽係由複數之蝕刻停止層所定義，且該至少一漏斗形插槽具有一階梯狀側壁；提供一第二積體電路，該第二積體電路具有至少一突出部；將該至少一突出部與該至少一漏斗形插槽進行對位；以及將該第一積體電路與該第二積體電路進行結合。
  2. 如申請專利範圍第1項所述之堆疊及對位複數積體電路的方法，其中該漏斗形插槽之一側壁係配置成與該第一積體電路之一上表面構成45度夾角。
  3. 如申請專利範圍第1項所述之堆疊及對位複數積體電路的方法，其中該漏斗形插槽由該第一積體電路之一上表面延伸至該複數金屬層之一中間金屬層。
  4. 如申請專利範圍第3項所述之堆疊及對位複數積體電路的方法，其中該中間金屬層係為該複數金屬層之最下層金屬層。
  5. 如申請專利範圍第1項所述之堆疊及對位複數積體電路的方法，其中該第二積體電路包含該至少一突出部。
  6. 如申請專利範圍第5項所述之堆疊及對位複數積體電路的方法，其中該至少一突出包含一焊料凸塊。
  7. 如申請專利範圍第5項所述之堆疊及對位複數積體電路的方法，其中該至少一突出包含一銅凸塊。
  8. 如申請專利範圍第1項所述之堆疊及對位複數積體電路的方法，其中該第二積體電路包含一第二漏斗形插槽。
  9. 一種堆疊及對位複數積體電路的系統，包含：一具有至少一漏斗形插槽之第一積體電路，其中該至少一漏斗形插槽係由複數之蝕刻停止層所定義，且該至少一漏斗形插槽具有一階梯狀側壁；一金屬化擴散阻障層配置於該漏斗形插槽之內部；一第二積體電路；以及其中該至少一漏斗形插槽係用以承接該第二積體電路之一突出部。
  10. 如申請專利範圍第9項所述之堆疊及對位複數積體電路的系統，其中該漏斗形插槽之一側壁係配置成與該第一積體電路之一上表面構成45度夾角。
  11. 如申請專利範圍第9項所述之堆疊及對位複數積體電路的系統，其中該漏斗形插槽由該第一積體電路之一上表面延伸至該複數金屬層之一中間金屬層。
  12. 如申請專利範圍第11項所述之堆疊及對位複數積體電路的系統，其中該中間金屬層係為該複數金屬層之最下層金屬層。
  13. 如申請專利範圍第9項所述之堆疊及對位複數積體電路的系統，其中該第二積體電路包含至少一突出部。
  14. 如申請專利範圍第13項所述之堆疊及對位複數 積體電路的系統，其中該至少一突出包含一焊料凸塊。
  15. 如申請專利範圍第13項所述之堆疊及對位複數積體電路的系統，其中該至少一突出包含一銅凸塊。
  16. 如申請專利範圍第9項所述之堆疊及對位複數積體電路的系統，其中該金屬化擴散阻障層係用以加強該該漏斗形插槽之一側壁。
  17. 如申請專利範圍第9項所述之堆疊及對位複數積體電路的系統，更包含一金屬陣列配置於該第一積體電路之一區域內，該區域環繞該漏斗形插槽，且該金屬陣列係用以強化該第一積體電路之環繞該漏斗形開口的區域。
  18. 一種製造具有對位及堆疊裝置類型之積體電路的方法，該方法包含：形成複數蝕刻停止層於一介電材料內，該介電材料包含複數金屬層，該蝕刻停止層係定義出一被蝕刻區域之邊界；形成一光阻層於該介電材料之一表面；蝕刻該介電材料至一預定深度以形成一漏斗形插槽；以及形成一金屬化擴散阻障層於該漏斗形插槽之內部。
  19. 如申請專利範圍第18項所述之製造具有對位及堆疊裝置類型之積體電路的方法，其中該漏斗形插槽由該第一積體電路之一上表面延伸至該複數金屬層之一中間金屬層。
  20. 如申請專利範圍第19項所述之製造具有對位及 堆疊裝置類型之積體電路的方法，其中該中間金屬層係為該複數金屬層之最下層金屬層。
TW98144940A 2009-01-26 2009-12-25 堆疊及對位複數積體電路的方法及系統、以及製造具有對位及堆疊裝置類型之積體電路的方法 TWI435395B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14738309P 2009-01-26 2009-01-26
US12/616,920 US8309396B2 (en) 2009-01-26 2009-11-12 System and method for 3D integrated circuit stacking

Publications (2)

Publication Number Publication Date
TW201029074A TW201029074A (en) 2010-08-01
TWI435395B true TWI435395B (zh) 2014-04-21

Family

ID=42353509

Family Applications (1)

Application Number Title Priority Date Filing Date
TW98144940A TWI435395B (zh) 2009-01-26 2009-12-25 堆疊及對位複數積體電路的方法及系統、以及製造具有對位及堆疊裝置類型之積體電路的方法

Country Status (5)

Country Link
US (3) US8309396B2 (zh)
JP (1) JP5300753B2 (zh)
KR (1) KR101159094B1 (zh)
CN (1) CN101853778B (zh)
TW (1) TWI435395B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2273545B1 (en) * 2009-07-08 2016-08-31 Imec Method for insertion bonding and kit of parts for use in said method
KR20160001033A (ko) * 2014-06-26 2016-01-06 에스케이하이닉스 주식회사 반도체 패키지
EP3185290A1 (en) * 2015-12-24 2017-06-28 IMEC vzw Method for self-aligned solder reflow bonding and devices obtained therefrom
JP1593701S (zh) * 2016-12-14 2017-12-25
KR102392856B1 (ko) * 2020-05-29 2022-05-02 엠케이전자 주식회사 핀 그리드 어레이 방식의 반도체 패키지

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100372A (en) * 1979-12-28 1981-08-12 Ibm Movinggtarget detector
US4954875A (en) * 1986-07-17 1990-09-04 Laser Dynamics, Inc. Semiconductor wafer array with electrically conductive compliant material
US6271059B1 (en) * 1999-01-04 2001-08-07 International Business Machines Corporation Chip interconnection structure using stub terminals
DE19907168C1 (de) * 1999-02-19 2000-08-10 Micronas Intermetall Gmbh Schichtanordnung sowie Verfahren zu deren Herstellung
US6222280B1 (en) * 1999-03-22 2001-04-24 Micron Technology, Inc. Test interconnect for semiconductor components having bumped and planar contacts
US7557452B1 (en) * 2000-06-08 2009-07-07 Micron Technology, Inc. Reinforced, self-aligning conductive structures for semiconductor device components and methods for fabricating same
SG115455A1 (en) * 2002-03-04 2005-10-28 Micron Technology Inc Methods for assembly and packaging of flip chip configured dice with interposer
US6891272B1 (en) * 2002-07-31 2005-05-10 Silicon Pipe, Inc. Multi-path via interconnection structures and methods for manufacturing the same
US6756305B1 (en) * 2003-04-01 2004-06-29 Xilinx, Inc. Stacked dice bonded with aluminum posts
US6977435B2 (en) * 2003-09-09 2005-12-20 Intel Corporation Thick metal layer integrated process flow to improve power delivery and mechanical buffering
JP3929966B2 (ja) * 2003-11-25 2007-06-13 新光電気工業株式会社 半導体装置及びその製造方法
JP3953027B2 (ja) * 2003-12-12 2007-08-01 ソニー株式会社 半導体装置およびその製造方法
JP4308797B2 (ja) * 2005-05-02 2009-08-05 株式会社アドバンストシステムズジャパン 半導体パッケージおよびソケット付き回路基板
CN101796636B (zh) * 2005-06-14 2013-02-27 丘费尔资产股份有限公司 芯片连接方法
US7946331B2 (en) * 2005-06-14 2011-05-24 Cufer Asset Ltd. L.L.C. Pin-type chip tooling
JP2007294652A (ja) * 2006-04-25 2007-11-08 Matsushita Electric Ind Co Ltd 半導体集積回路装置及びその製造方法
US7851384B2 (en) * 2006-06-01 2010-12-14 Applied Materials, Inc. Method to mitigate impact of UV and E-beam exposure on semiconductor device film properties by use of a bilayer film
CN101364586B (zh) * 2007-08-10 2010-06-23 全懋精密科技股份有限公司 封装基板结构
KR20090047776A (ko) * 2007-11-08 2009-05-13 삼성전자주식회사 반도체 소자 및 그 형성 방법
US7821107B2 (en) * 2008-04-22 2010-10-26 Micron Technology, Inc. Die stacking with an annular via having a recessed socket
US7867910B2 (en) * 2008-06-10 2011-01-11 International Business Machines Corporation Method of accessing semiconductor circuits from the backside using ion-beam and gas-etch
US8138563B2 (en) * 2008-08-08 2012-03-20 International Business Machines Corporation Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
KR101078737B1 (ko) * 2009-08-10 2011-11-02 주식회사 하이닉스반도체 적층 반도체 패키지

Also Published As

Publication number Publication date
US20130062766A1 (en) 2013-03-14
US20150214166A1 (en) 2015-07-30
TW201029074A (en) 2010-08-01
CN101853778A (zh) 2010-10-06
KR20100087252A (ko) 2010-08-04
US8309396B2 (en) 2012-11-13
JP5300753B2 (ja) 2013-09-25
US9006892B2 (en) 2015-04-14
US20100187684A1 (en) 2010-07-29
CN101853778B (zh) 2012-07-18
JP2010171432A (ja) 2010-08-05
US9236359B2 (en) 2016-01-12
KR101159094B1 (ko) 2012-06-26

Similar Documents

Publication Publication Date Title
TWI746776B (zh) 半導體元件及其製造方法
US10741505B2 (en) Method of manufacturing semiconductor device and semiconductor device
US20240170457A1 (en) Stacked integrated circuits with redistribution lines
US8367472B2 (en) Method of fabricating a 3-D device
TWI458071B (zh) 晶片封裝體及其製造方法
TWI429046B (zh) 半導體裝置及其製造方法
TWI602273B (zh) 半導體裝置
JP2010045371A (ja) 導電性保護膜を有する貫通電極構造体及びその形成方法
TWI435395B (zh) 堆疊及對位複數積體電路的方法及系統、以及製造具有對位及堆疊裝置類型之積體電路的方法
US9343364B2 (en) Semiconductor device and method for manufacturing the same
JP2015041718A (ja) 半導体装置及びその製造方法
CN110223922B (zh) 一种晶圆结构及其制造方法、芯片结构
JP2010087273A (ja) 電子デバイス及びその製造方法
TWI772335B (zh) 半導體裝置及其製造方法
US9478464B2 (en) Method for manufacturing through-hole silicon via
TW202410378A (zh) 具有電感器的半導體裝置及其製造方法
JP2013110255A (ja) 半導体ウェハ、半導体装置及びその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees