KR102392856B1 - 핀 그리드 어레이 방식의 반도체 패키지 - Google Patents

핀 그리드 어레이 방식의 반도체 패키지 Download PDF

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Publication number
KR102392856B1
KR102392856B1 KR1020200065396A KR20200065396A KR102392856B1 KR 102392856 B1 KR102392856 B1 KR 102392856B1 KR 1020200065396 A KR1020200065396 A KR 1020200065396A KR 20200065396 A KR20200065396 A KR 20200065396A KR 102392856 B1 KR102392856 B1 KR 102392856B1
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South Korea
Prior art keywords
core material
solder
metal layer
reverse reflow
metal
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KR1020200065396A
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English (en)
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KR20210147734A (ko
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손재열
문정탁
송재헌
이영우
이슬기
박민수
김휘중
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엠케이전자 주식회사
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Priority to KR1020200065396A priority Critical patent/KR102392856B1/ko
Priority to US17/323,722 priority patent/US20210375811A1/en
Publication of KR20210147734A publication Critical patent/KR20210147734A/ko
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Publication of KR102392856B1 publication Critical patent/KR102392856B1/ko

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Abstract

본 발명의 기술적 사상에 따른 반도체 패키지는, 제1 기판에 배치되는 범프 패드, 제2 기판에 배치되는 금속 소켓, 범프 패드에 배치되는 리버스 리플로우용 심재, 리버스 리플로우용 심재에 솔더층을 형성하며 범프 패드와 맞닿는 솔더 페이스트 또는 솔더 범프를 포함하고, 리버스 리플로우용 심재 및 리버스 리플로우용 심재와 접합된 솔더 페이스트 또는 솔더 범프가 핀의 역할을 수행하여 금속 소켓에 탈부착되고, 범프 패드의 제1 직경은 리버스 리플로우용 심재의 제2 직경보다 작거나 동일하고, 리버스 리플로우용 심재는 코어, 코어의 직접 위에 코팅되고 니켈(Ni) 또는 코발트(Co)인 제1 금속층, 및 제1 금속층의 직접 위에 코팅되고 금(Au) 또는 백금(Pt)인 제2 금속층을 포함한다.

Description

핀 그리드 어레이 방식의 반도체 패키지{PIN GRID ARRAY TYPE SEMICONDUCTOR PACKAGE}
본 발명의 기술분야는 반도체 패키지 및 이의 제조 방법에 관한 것으로, 더욱 상세하게는, 리버스 리플로우용 심재를 핀으로 이용하는 핀 그리드 어레이 방식의 반도체 패키지 및 이의 제조 방법에 관한 것이다.
전자 제품에 사용되는 솔더로는 주석(Sn)-납(Pb) 계열의 합금 제품이 주로 사용되는데, 특히 납은 합금의 젖음성(wetting), 강도, 기계적 특성을 결정하는 성분으로 작용하여 왔으며, 납이 포함됨으로써 융점이 183℃까지 낮춰질 수 있어 반도체 공정의 솔더링에서 발생하는 열적 손상이 방지될 수 있었다. 한편, 납으로 인한 환경 문제와 관련하여 규제가 엄격해짐에 따라, 주석(Sn)-은(Ag)-구리(Cu)의 3원계 무연 솔더 합금이 제안되었으며, 반도체 패키지의 고밀도 실장을 위해 금속 또는 비금속 심재에 니켈(Ni)을 도금한 후, 반도체 패키지의 전기적 신호를 전달하기 위해 주석(Sn)-은(Ag)과 같은 2원계 또는 주석(Sn)-은(Ag)-구리(Cu)와 같은 3원계 도금층이 형성되는 도금볼이 사용되고 있으며, 도금볼의 적용 방식에 대해 다양한 연구가 진행되고 있다.
본 발명의 기술적 사상이 해결하고자 하는 과제는, 리버스 리플로우용 심재를 핀으로 이용함으로써, 정밀도가 높고 접합 강도가 우수한 핀 그리드 어레이 방식의 반도체 패키지를 제공하는 것이다.
본 발명의 기술적 사상이 해결하고자 하는 과제는, 리버스 리플로우용 심재를 핀으로 이용함으로써, 정밀도가 높고 접합 강도가 우수한 핀 그리드 어레이 방식의 반도체 패키지의 제조 방법을 제공하는 것이다.
본 발명의 기술적 사상이 해결하고자 하는 과제는, 리버스 리플로우용 심재를 핀으로 이용함으로써, 정밀도가 높고 접합 강도가 우수한 핀 그리드 어레이 방식의 반도체 패키지를 포함하는 전자 시스템을 제공하는 것이다.
본 발명의 기술적 사상이 해결하고자 하는 과제는, 이상에서 언급한 과제에 제한되지 않으며, 언급되지 않은 또 다른 과제들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.
본 발명의 기술적 사상에 따른 반도체 패키지는, 제1 기판에 배치되는 범프 패드; 제2 기판에 배치되는 금속 소켓; 상기 범프 패드에 배치되는 리버스 리플로우용 심재; 상기 리버스 리플로우용 심재에 솔더층을 형성하며, 상기 범프 패드와 맞닿는 솔더 페이스트 또는 솔더 범프;를 포함하고, 상기 리버스 리플로우용 심재 및 상기 리버스 리플로우용 심재와 접합된 상기 솔더 페이스트 또는 솔더 범프가 핀의 역할을 수행하여, 상기 금속 소켓에 탈부착되고, 상기 범프 패드의 제1 직경은 상기 리버스 리플로우용 심재의 제2 직경보다 작거나 동일하고, 상기 리버스 리플로우용 심재는, 코어; 상기 코어의 직접 위에 코팅되고, 니켈(Ni) 또는 코발트(Co)인 제1 금속층; 및 상기 제1 금속층의 직접 위에 코팅되고, 금(Au) 또는 백금(Pt)인 제2 금속층;을 포함한다.
본 발명의 기술적 사상에 따른 반도체 패키지의 제조 방법은, 범프 패드가 배치되는 제1 기판을 제공하는 단계; 금속 소켓이 배치되는 제2 기판을 제공하는 단계; 상기 범프 패드 상에 솔더 페이스트 또는 솔더 범프를 실장하는 단계; 상기 솔더 페이스트 또는 솔더 범프 상에 리버스 리플로우용 심재를 배치하는 단계; 적어도 상기 리버스 리플로우용 심재의 측면 상에 솔더층을 형성하도록 상기 솔더 페이스트 또는 솔더 범프를 리플로우시키는 단계; 및 상기 리버스 리플로우용 심재 및 상기 리버스 리플로우용 심재와 접합된 상기 솔더 페이스트 또는 솔더 범프가 핀의 역할을 수행하여, 상기 핀을 상기 금속 소켓에 결합하는 단계;를 포함하고, 상기 리버스 리플로우용 심재는, 코어; 상기 코어의 직접 위에 코팅되고, 니켈(Ni) 또는 코발트(Co)인 제1 금속층; 및 상기 제1 금속층의 직접 위에 코팅되고, 금(Au) 또는 백금(Pt)인 제2 금속층;을 포함한다.
본 발명의 기술적 사상에 따른 반도체 패키지에 따르면, 리버스 리플로우용 심재를 핀으로 이용함으로써, 정밀도가 높고 접합 강도가 우수한 핀 그리드 어레이 방식의 반도체 패키지를 제공하는 효과가 있다.
도 1은 본 발명의 기술적 사상의 실시예에 따른 리버스 리플로우용 심재를 나타내는 단면도이다.
도 2는 본 발명의 기술적 사상의 실시예에 따른 핀 그리드 어레이 방식의 반도체 패키지를 나타내는 단면도이다.
도 3은 본 발명의 기술적 사상의 일 실시예로서, 도 2의 CC로 표시된 부분을 나타내는 부분 확대도이다.
도 4는 본 발명의 기술적 사상의 다른 실시예로서, 도 2의 CC로 표시된 부분을 나타내는 부분 확대도이다.
도 5는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지에서 핀의 강도를 나타내는 그래프이다.
도 6은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지의 제조 방법을 나타내는 순서도이다.
도 7a 내지 도 7e는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지의 제조 방법을 순서에 따라 나타내는 단면도들이다.
도 8은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 메모리 모듈을 나타내는 평면도이다.
도 9는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 메모리 카드를 나타내는 개략도이다.
도 10은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 메모리 장치를 나타내는 블록도이다.
도 11은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 전자 시스템을 나타내는 블록도이다.
도 12는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 서버 시스템에 대한 네트워크를 나타내는 블록도이다.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하기로 한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되는 것으로 해석되는 것은 아니다.
동일한 부호는 동일한 요소를 의미한다. 나아가, 도면에서의 다양한 요소와 영역은 개략적으로 그려진 것이다. 따라서, 본 발명은 첨부한 도면에 그려진 상대적인 크기나 간격에 의해 제한되어지지 않는다.
제1, 제2 등의 용어는 다양한 구성 요소들을 설명하는 데 사용될 수 있지만, 상기 구성 요소들은 상기 용어들에 의해 한정되지 않는다. 상기 용어들은 하나의 구성 요소를 다른 구성 요소로부터 구별하는 목적으로만 사용된다. 예를 들어, 본 발명의 권리 범위를 벗어나지 않으면서 제1 구성 요소는 제2 구성 요소로 명명될 수 있고, 반대로 제2 구성 요소는 제1 구성 요소로 명명될 수 있다.
달리 정의되지 않는 한, 여기에 사용되는 모든 용어들은 기술 용어와 과학 용어를 포함하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 공통적으로 이해하는 바와 동일한 의미를 지닌다. 또한, 통상적으로 사용되는 용어들은 관련되는 기술의 맥락에서 이들이 의미하는 바와 일관되는 의미를 갖는 것으로 해석되어야 하며, 여기에 명시적으로 정의하지 않는 한 과도하게 형식적인 의미로 해석되어서는 아니 될 것임은 이해될 것이다.
도 1은 본 발명의 기술적 사상의 실시예에 따른 리버스 리플로우용 심재를 나타내는 단면도이다.
도 1을 참조하면, 리버스 리플로우용 심재(110)는 코어(111), 상기 코어(111) 위에 코팅된 제1 금속층(113), 및 상기 제1 금속층(113) 위에 코팅된 제2 금속층(115)을 포함할 수 있다.
상기 코어(111)는 일반적인 금속 재료 또는 유기 재료로 이루어질 수도 있고, 유기/유기 복합 재료 또는 유기/무기 복합 재료로 이루어질 수 있다.
상기 유기 재료의 코어(111)는 예를 들어, 플라스틱 재질의 코어(111)일 수 있으며, 상기 플라스틱 재질의 코어(111)는 에폭시계, 멜라민-포름알데히드계, 벤조구아나민-포름알데히드계, 디비닐벤젠, 디비닐에테르, 폴리디아크릴레이트, 알킬렌비스아크릴아미드와 같은 열경화성 수지를 포함하는 플라스틱 코어(111); 폴리염화비닐, 폴리에틸렌, 폴리스틸렌, 나일론, 폴리아세탈과 같은 열가소성 수지를 포함하는 플라스틱 코어(111); 및 천연고무, 합성고무와 같은 탄성체 코어(111);를 포함할 수 있다. 또한, 열경화성 수지와 열가소성 수지를 혼용한 수지로 형성된 플라스틱 코어(111)를 포함할 수도 있다.
한편, 상기 플라스틱 재질의 코어(111)는 중합체 합성 방법을 사용하여 형성될 수 있다. 일부 실시예들에서, 현탁, 유화, 분산중합법 등의 합성 방법을 통하여 상기 플라스틱 재질의 코어(111)는 약 21㎛ 내지 약 500㎛의 직경을 갖도록 형성될 수 있다.
상기 금속 재질의 코어(111)는 예를 들어, 순수 구리(Cu), 니켈(Ni), 알루미늄(Al), 또는 이들의 합금 등으로 구성될 수 있으나, 이에 한정되는 것은 아니다.
도면에서는 코어(111)의 형태가 구형인 것을 예시하였지만, 상기 코어(111)는 원기둥 형태, 사각 기둥 형태, 다각 기둥 형태, 원뿔 형태, 각뿔 형태 등의 다양한 형태를 가질 수 있다.
상기 코어(111)의 위에는 제1 금속층(113)이 제공될 수 있다. 상기 제1 금속층(113)은 상기 코어(111)의 직접 위에 형성될 수도 있고, 다른 물질층을 개재하여 상기 코어(111)의 위에 형성될 수도 있다.
상기 제1 금속층(113)의 성분은 특별히 한정하지 않으나, 금(Au), 은(Ag), 니켈(Ni), 아연(Zn), 주석(Sn), 알루미늄(Al), 크롬(Cr), 코발트(Co), 안티몬(Sb) 등의 금속이 사용될 수 있다. 이들은 단독 또는 2종 이상을 병용하여 사용될 수 있다. 상기 제1 금속층(113)은 도금, 물리 기상 증착, 화학 기상 증착 등의 방법으로 형성될 수 있다. 특히, 상기 제1 금속층(113)을 도금에 의하여 형성하는 경우, 니켈을 이용한 전해 도금 또는 무전해 도금 방법을 수행하여 형성할 수 있다.
상기 제1 금속층(113)을 형성할 때, 상기 제1 금속층(113)의 표면의 조도(roughness)를 향상시키기 위하여 광택제(brightener)가 사용될 수 있다. 즉, 광택제를 사용함으로써 보다 매끈한 표면의 제1 금속층(113)을 얻을 수 있다. 상기 광택제는 예를 들어, 폴리에테르계 화합물과 같은 산소 함유 유기화합물; 3급 아민 화합물, 4급 암모늄 화합물과 같은 질소 함유 유기화합물; 및/또는 술포네이트 기를 갖는 황 함유 유기화합물;일 수 있지만, 이에 한정되는 것은 아니다.
상기 제1 금속층(113)의 두께는 약 1㎛ 내지 약 5㎛일 수 있다. 상기 제1 금속층(113)은 주석(Sn)계 솔더 페이스트와의 반응에 의하여, 예를 들어, (Ni,Cu)3Sn4, (Cu,Ni)6Sn5, Ni3Sn4 등과 같은 금속간 화합물(intermetallic compound)을 형성할 수 있다.
상기 제1 금속층(113)의 표면 위에는 제2 금속층(115)이 형성될 수 있다. 상기 제2 금속층(115)은 약 0.01㎛ 내지 약 0.3㎛의 두께를 가질 수 있다. 상기 제2 금속층(115)의 두께가 너무 얇으면, 상기 리버스 리플로우용 심재(110)가 추후 리플로우에 사용되었을 때 솔더층이 전체 표면에 걸쳐 형성되지 않을 수 있다. 상기 제2 금속층(115)의 두께가 너무 두꺼우면, 경제적으로 불리할 뿐만 아니라 추후 리플로우에 사용되었을 때 주석(Sn)계 솔더와 반응하여 AuSn4와 같이 취약한 강도의 금속간 화합물이 형성될 수 있다.
상기 제2 금속층(115)은 예를 들어, 금(Au), 백금(Pt), 또는 이들의 합금일 수 있다. 상기 제2 금속층(115)은 가열에 의하여 솔더층과 용이하게 혼합될 수 있다. 또한, 상기 제2 금속층(115)은 산화가 잘되지 않는 금속이기 때문에 상기 리버스 리플로우용 심재(110)의 표면이 산화되는 것을 억제할 수 있다.
상기 제2 금속층(115)은 전해 도금, 무전해 도금, 물리 기상 증착, 화학 기상 증착 등의 방법으로 형성될 수 있으나, 이에 한정되는 것은 아니다.
상기 리버스 리플로우용 심재(110)는 그 자체가 핀(100, 도 2 참조)으로 사용되는 것은 아니며, 솔더 페이스트(120, 도 2 참조)와 함께 리플로우 공정을 거침으로써, 핀 그리드 어레이(Pin Grid Array) 방식을 위한 핀(100, 도 2 참조)의 일부를 이룰 수 있다. 이에 관해, 이하에서 보다 상세하게 설명한다.
도 2는 본 발명의 기술적 사상의 실시예에 따른 핀 그리드 어레이 방식의 반도체 패키지를 나타내는 단면도이다.
도 2를 참조하면, 핀(100)으로 사용되는 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)를 포함하는 반도체 패키지(10)를 나타낸다.
리버스 리플로우용 심재(110)는 예를 들어, 코어(111)의 직경이 약 21㎛ 내지 약 500㎛이고, 제1 금속층(113)의 두께가 약 1㎛ 내지 약 5㎛이고, 제2 금속층(115)의 두께가 약 0.01㎛ 내지 약 0.3㎛일 수 있다. 다만, 상기 리버스 리플로우용 심재(110)의 직경이 이에 한정되는 것은 아니다. 상기 리버스 리플로우용 심재(110)에 대해서는 앞서 도 1을 참조하여 상세하게 설명하였으므로, 추가적인 설명을 생략한다.
솔더 페이스트(120)는 상기 리버스 리플로우용 심재(110)를 둘러싸는 솔더층을 의미할 수 있다. 또한, 본 명세서에서 솔더 페이스트(120)는 솔더볼과 같은 솔더 범프를 포함하는 개념으로 사용될 수 있다. 여기서, 솔더 페이스트 또는 솔더 범프를 편의상 솔더 페이스트(120)로 통칭하도록 한다.
상기 솔더 페이스트(120)에 사용되는 도전성의 금속 분말은 예를 들어, 주석(Sn), 금(Au), 은(Ag), 백금(Pt), 구리(Cu), 비스무트(Bi), 팔라듐(Pd), 크롬(Cr), 칼슘(Ca), 니켈(Ni), 저머늄(Ge), 아연(Zn), 망간(Mn), 코발트(Co), 텅스텐(W), 안티몬(Sb), 납(Pb), 및 이들의 임의의 합금으로부터 선택되는 하나 이상일 수 있다.
일부 실시예들에서, 상기 솔더 페이스트(120)는 납 함유 솔더 합금(예를 들어, Sn-Pb계 또는 Sn-Pb-Ag계) 또는 무연 솔더 합금(예를 들어, Sn-Ag계 합금, Sn-Bi계 합금, Sn-Zn계 합금, Sn-Sb계 합금, 또는 Sn-Ag-Cu 합금)을 포함할 수 있다. 상기 솔더 페이스트(120)는 전체 금속 중량에 대해 Sn을 50% 이상, 60% 이상, 또는 90% 이상 함유할 수 있다. 상기 금속 분말이 둘 이상의 금속 성분을 갖는 경우, 이들은 합금을 통하여 형성될 수 있다. 상기 금속 분말이 합금을 통하여 얻어지는 경우, 상기 금속 분말은 유기 물질을 실질적으로 포함하지 않을 수 있다.
상기 솔더 페이스트(120)는 도전성의 금속 분말이 액상의 플럭스와 혼합되어 있는 혼합물일 수 있다. 상기 플럭스는 용제, 로진, 틱소트로피제, 및 활성제 등의 각 성분을 혼합하여 조제될 수 있다.
구체적으로, 상기 용제는, 디에틸렌글리콜모노헥실에테르, 디에틸렌글리콜모노부틸에테르, 디에틸렌글리콜모노부틸에테르아세테이트, 테트라에틸렌글리콜, 2-에틸-1,3-헥산디올, α-테르피네올 등의 비점이 180℃ 이상인 유기 용제를 들 수 있다. 또한, 상기 로진은, 검 로진, 수첨 로진, 중합 로진, 에스테르 로진일 수 있다. 또한, 상기 틱소트로피제는, 경화 피마자유, 지방산 아마이드, 천연 유지, 합성 유지, N,N'-에틸렌비스-12-하이드록시스테아릴아미드, 12-하이드록시스테아르산, 1,2,3,4-디벤질리덴-D-소르비톨, 및 그 유도체일 수 있다. 또한, 상기 활성제는, 할로겐화수소산아민염일 수 있다. 다만, 상기 용제, 로진, 틱소트로피제, 및 활성제가 이에 한정되는 것은 아니다.
상기 솔더 페이스트(120)의 실장량은 상기 솔더 페이스트(120)의 점도, 범프 패드(132)의 크기, 상기 솔더 페이스트(120)에 배치될 상기 리버스 리플로우용 심재(110)의 크기 등을 고려하여 당 업자가 적절히 선택할 수 있다.
반도체 장치(130)의 범프 패드(132)에 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)가 배치될 수 있다. 상기 반도체 장치(130)는 범프 패드(132)가 배치되는 제1 기판(134) 및 상기 제1 기판(134)에 형성된 반도체 소자들(미도시)을 포함할 수 있다.
상기 제1 기판(134)은 반도체 소자들이 배치되는 활성면 및 이와 마주보는 비활성면을 포함할 수 있다.
상기 제1 기판(134)은 반도체 기판일 수 있고, 구체적으로, 실리콘(Si) 기판일 수 있다. 또한, 상기 제1 기판(134)은 저머늄(Ge)과 같은 반도체 원소; 또는 SiC(silicon carbide), GaAs(gallium arsenide), InAs(indium arsenide), 및 InP(indium phosphide)와 같은 화합물 반도체;를 포함할 수도 있다.
상기 제1 기판(134)은 SOI(silicon on insulator) 구조를 가질 수 있다. 예를 들어, 상기 제1 기판(134)은 BOX 층(buried oxide layer)을 포함할 수 있다. 일부 실시예들에서, 상기 제1 기판(134)은 도전 영역(예를 들어, 불순물이 도핑된 웰 또는 불순물이 도핑된 구조물)을 포함할 수 있다. 또한, 상기 제1 기판(134)은 STI(shallow trench isolation) 구조와 같은 다양한 소자 분리 구조를 가질 수도 있다.
상기 제1 기판(134)의 활성면에는 다양한 반도체 소자들이 제공될 수 있다. 상기 반도체 소자들은 메모리 소자, 코어 회로 소자, 주변 회로 소자, 로직 회로 소자, 또는 제어 회로 소자를 포함할 수 있다. 상기 메모리 소자는 예를 들어, DRAM, SRAM 등과 같은 휘발성 반도체 메모리 소자;와 플래시 메모리, 상변화 메모리(phase-change RAM, PRAM), 저항 메모리(resistive RAM, RRAM), 강유전체 메모리(ferroelectric RAM, FRAM), 자기 메모리(magnetic RAM, MRAM), EPROM, EEPROM, Flash EEPROM 등과 같은 비휘발성 메모리 소자;를 포함할 수 있다.
또한, 상기 제1 기판(134)의 활성면에는 시스템 LSI, 이미지 센서, MEMS, 능동 소자, 수동 소자 등을 포함할 수 있다.
또한, 상기 제1 기판(134)의 활성면에는 상기 반도체 소자들 상에 배선층이 구비될 수 있다. 상기 배선층은 배선 패턴과 절연층을 포함할 수 있다. 또한, 상기 배선 패턴은 전극 단자인 범프 패드(132)와 전기적으로 연결될 수 있다.
다른 실시예들에서, 상기 제1 기판(134)은 인쇄회로기판(printed circuit board, PCB)을 포함할 수 있다.
일부 실시예들에서, 상기 반도체 장치(130)는 상기 반도체 소자들을 밀봉하는 봉지제(encapsulant)를 더 포함할 수 있다. 상기 봉지제는 예를 들어, 에폭시 몰딩 컴파운드로 형성될 수 있다.
모듈 장치(210)의 금속 소켓(212)에 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)로 구성되는 핀(100)이 결합될 수 있다. 상기 모듈 장치(210)는 제2 기판(214) 및 상기 제2 기판(214)의 상부면에 형성된 금속 소켓(212)을 포함할 수 있다.
제2 기판(214)은 인쇄회로기판일 수 있다. 예를 들어, 상기 제2 기판(214)은 경성 인쇄회로기판(rigid PCB), 연성 인쇄회로기판(flexible PCB), 테이프 기판, 또는 경연성 인쇄회로기판(rigid-flexible PCB)일 수 있다. 다른 실시예들에서, 상기 제2 기판(214)은 상기 제1 기판(134)과 동일한 반도체 기판일 수도 있다.
상기 제2 기판(214)이 인쇄회로기판인 경우, 상기 제2 기판(214)은 몸체부를 중심으로 그의 상면과 하면에 각각 제1 수지층 및 제2 수지층을 포함할 수 있다. 상기 제1 수지층 및 제2 수지층은 각각 다층 구조일 수 있고, 상기 다층 구조 사이에 신호층, 접지층, 또는 전원층이 개재될 수 있으며, 이들은 배선 패턴과 연결될 수 있다. 또한, 상기 배선 패턴은 금속 소켓(212)을 전기적으로 연결할 수 있다.
상기 제1 수지층과 제2 수지층은 예를 들어, 에폭시 수지, 우레탄 수지, 폴리이미드 수지, 아크릴 수지, 폴리올레핀 수지 등으로 형성될 수 있다.
상기 금속 소켓(212)은 전도성의 소켓일 수 있다. 보다 구체적으로, 상기 금속 소켓(212)은 예를 들어, 구리(Cu) 소켓, 니켈(Ni) 소켓, 또는 니켈이 도금된 알루미늄(Al) 소켓일 수 있으나, 이에 한정되는 것은 아니다.
다시, 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)에 대하여 살펴보도록 한다. 상기 범프 패드(132) 및 상기 금속 소켓(212) 사이에 핀(100)이 일정한 높이로 배치될 수 있다. 상기 리버스 리플로우용 심재(110)를 둘러싸는 솔더층을 형성하기 위하여, 상기 솔더 페이스트(120)를 리플로우시킬 수 있다.
상기 솔더 페이스트(120)의 온도를 상승시키면, 상기 솔더 페이스트(120)를 구성하는 물질이 용융되어 상기 리버스 리플로우용 심재(110)의 표면을 코팅하게 된다. 구체적으로, 상기 솔더 페이스트(120)는 용융되어 상기 리버스 리플로우용 심재(110)의 측벽을 타고 이동하여, 결과적으로는 상기 리버스 리플로우용 심재(110)의 적어도 전체 측면을 덮게 된다.
일부 실시예들에서, 상기 리버스 리플로우용 심재(110)보다 상기 솔더 페이스트(120)가 아래쪽에 위치하여도 용융된 솔더 페이스트(120)는 중력의 방향을 역행하여 상기 리버스 리플로우용 심재(110)의 표면을 따라 상승할 수 있다. 용융된 솔더 페이스트(120)의 점도가 상당히 감소하기 때문에, 상기 리버스 리플로우용 심재(110)는 용융되지 않은 솔더 페이스트(120) 위에 처음 배치되었을 때보다 상기 제1 기판(134) 쪽으로 이동할 수 있다.
특정한 이론에 의하여 한정되는 것은 아니지만, 이러한 리버스 리플로우용 심재(110)의 움직임, 그 표면에서의 표면 장력, 및 상기 리버스 리플로우용 심재(110)의 표면을 이루는 제2 금속층과 솔더 페이스트(120) 사이의 친화성에 의하여, 상기 솔더 페이스트(120)가 중력에도 불구하고 상승하는 것으로 추정될 수 있다.
이와 같은 형상으로, 상기 범프 패드(132) 및 상기 금속 소켓(212)의 사이에 리버스 리플로우용 심재(110)와 솔더 페이스트(120)로 구성되는 핀(100)을 형성할 수 있다.
종래의 핀 그리드 어레이(Pin Grid Array) 방식의 반도체 패키지를 제조하기 위하여는, 금속 소켓과 결합하는 다수의 핀을 기판 상에 형성하기 위하여 매우 높은 공정 비용과 제조 시간을 투입하여 필라(pillar)를 먼저 형성해야만 한다. 또한, 상기 필라를 구성하는 물질은 내부식 및 내산화 특성을 모두 만족하면서도, 원하는 형상으로 제조가 가능한 특성까지 만족하여야만 한다. 즉, 상기 필라를 통한 핀의 형성은 제조 효율 및 생산성이 낮다는 문제점이 있다.
이를 해결하기 위하여 본 발명의 기술적 사상에 따르면, 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)를 핀(100)으로 이용함으로써, 리버스 리플로우용 심재(110)의 최외곽층을 구성하는 제2 금속층(115, 도 1 참조)의 물질 특성에 따라, 내부식 및 내산화 특성 그리고 높은 신호 전달 특성을 모두 만족시킬 수 있다. 따라서, 공정 비용과 제조 시간을 절약할 수 있으므로, 궁극적으로 반도체 패키지(10)의 제조 효율 및 생산성을 높일 수 있다.
또한, 본 발명의 기술적 사상에 따르면, 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)를 핀(100)으로 이용함으로써, 상대적으로 정밀도가 높고 접합 강도가 우수한 핀 그리드 어레이 방식의 반도체 패키지(10)를 경제적으로 제공할 수 있는 효과가 있다.
도 3은 본 발명의 기술적 사상의 일 실시예로서, 도 2의 CC로 표시된 부분을 나타내는 부분 확대도이다.
도 3을 참조하면, 리버스 리플로우용 심재(110) 및 상기 리버스 리플로우용 심재(110)의 측면까지만 형성된 솔더 페이스트(120A)를 핀(100A)으로 이용하여 금속 소켓(212)에 결합된 모습을 나타낸다.
리버스 리플로우용 심재(110)의 코어(111)와 제1 금속층(113)은 앞서 도 1에서 설명한 바와 동일할 수 있다. 한편, 제2 금속층(115A)은 솔더층을 형성하는 과정에서 상기 솔더 페이스트(120A)와 합금을 형성할 수 있다. 도면에는, 상기 제2 금속층(115A)의 일부가 상기 솔더 페이스트(120A)로부터 노출된 핀(100A)을 구성하는 반도체 패키지(10A)를 나타낸다.
다시 말해, 상기 제2 금속층(115A)의 일부가 상기 솔더 페이스트(120A)로부터 노출되는 구조이다. 이는 리플로우 공정 조건을 제어함으로써, 상기 리버스 리플로우용 심재(110)의 하단(도면에 도시된 바에 따라)에는 솔더층을 형성하지 않고, 상기 리버스 리플로우용 심재(110)의 측면에만 솔더층을 형성할 수 있다. 노출된 상기 제2 금속층(115A)은 산화에 강하며, 전도성 또한 우수하여, 신호 전달에 안정성을 확보할 수 있다.
일부 실시예들에서, 상기 제2 금속층(115A)은 자신의 일부 두께에 대해서 상기 솔더 페이스트(120A)와 합금을 형성할 수 있다. 상기 제2 금속층(115A)이 상기 솔더 페이스트(120A)와 합금을 형성하는 부분에서, 상기 코어(111)의 표면으로부터 멀어질수록 제2 금속층(115A)을 이루는 성분의 농도는 점차 감소할 수 있다.
또는, 상기 제1 금속층(113)의 일부 또는 전부는 상기 솔더 페이스트(120A)와 금속간 화합물을 형성함으로써 계면층을 형성할 수도 있다. 또는, 상기 금속간 화합물은 상기 코어(111)의 성분을 포함할 수도 있다. 특히, 상기 제1 금속층(113) 전체가 상기 솔더 페이스트(120A)와 금속간 화합물을 형성하는 경우, 상기 제1 금속층(113)은 존재하지 않고 계면층이 직접 코어(111)의 표면에 존재할 수도 있다.
여기서, 상기 금속간 화합물은 예를 들어, (Ni,Cu)3Sn4, (Cu,Ni)6Sn5, 및 Ni3Sn4 로 구성되는 군으로부터 선택된 하나 이상일 수 있지만, 코어(111), 제1 금속층(113), 제2 금속층(115A), 및 상기 솔더 페이스트(120A)의 물질에 따라, 다른 금속간 화합물이 형성될 수도 있다. 상기 계면층 내에는 상기 제1 금속층(113)으로부터 유래한 성분과 상기 솔더 페이스트(120A)로부터 유래한 성분의 금속간 화합물이 존재할 수 있다. 또는, 상기 계면층 내에는 상기 제2 금속층(115A)으로부터 유래한 성분과 상기 솔더 페이스트(120A)로부터 유래한 성분의 합금이 존재할 수 있다.
상기 솔더 페이스트(120A)는 상기 리버스 리플로우용 심재(110)의 측면에서 상기 제2 금속층(115A)과의 혼합에 의해, 상기 제2 금속층(115A)이 없을 때보다 젖음성(wetting)이 향상될 수 있다.
상기 범프 패드(132)의 제1 직경(132R)은 상기 리버스 리플로우용 심재(110)의 제2 직경(110R)보다 작거나, 실질적으로 동일할 수 있다. 즉, 상기 범프 패드(132)의 상면은 상기 리버스 리플로우용 심재(110)와 전부 오버랩될 수 있다.
상기 금속 소켓(212)은 상기 리버스 리플로우용 심재(110)의 제2 금속층(115A)과 직접 접촉할 수 있다. 즉, 상기 금속 소켓(212)은 상기 솔더 페이스트(120A)와 접촉하지 않을 수 있다. 상기 제2 금속층(115A)을 이루는 물질은 높은 신호 전달 특성을 가지므로, 더욱 빠른 신호 전달이 가능할 수 있다.
또한, 후술하겠지만, 상기 제2 금속층(115A)의 일부가 상기 솔더 페이스트(120A)로부터 노출된 핀(100A)의 경우에도, 볼 전단 강도(ball shear strength)는 필라로 형성된 일반적인 핀의 볼 전단 강도보다 높으므로, 상기 금속 소켓(212)과의 탈부착에 문제가 없다.
도 4는 본 발명의 기술적 사상의 다른 실시예로서, 도 2의 CC로 표시된 부분을 나타내는 부분 확대도이다.
도 4를 참조하면, 리버스 리플로우용 심재(110) 및 상기 리버스 리플로우용 심재(110)의 전부에 형성된 솔더 페이스트(120B)를 핀(100B)으로 이용하여 금속 소켓(212)에 결합된 모습을 나타낸다.
리버스 리플로우용 심재(110)의 코어(111)와 제1 금속층(113)은 앞서 도 1에서 설명한 바와 동일할 수 있다. 한편, 제2 금속층(115B)은 솔더층을 형성하는 과정에서 상기 솔더 페이스트(120B)와 합금을 형성할 수 있다. 도면에는, 상기 제2 금속층(115B)의 전부가 상기 솔더 페이스트(120B)로 둘러싸이는 핀(100B)을 구성하는 반도체 패키지(10B)를 나타낸다.
일부 실시예들에서, 상기 제2 금속층(115B)은 자신의 일부 두께에 대해서 상기 솔더 페이스트(120B)와 합금을 형성할 수 있다. 상기 제2 금속층(115B)이 상기 솔더 페이스트(120B)와 합금을 형성하므로, 상기 코어(111)의 표면으로부터 멀어질수록 제2 금속층(115B)을 이루는 성분의 농도는 점차 감소할 수 있다.
상기 제2 금속층(115B)은 약 0.1㎛ 내지 약 0.3㎛의 얇은 두께를 갖기 때문에, 상기 제2 금속층(115B) 전체가 가열과 함께 용해되어 상기 솔더 페이스트(120B)와 합금을 형성할 수 있다. 도시하지는 않았지만, 상기 제2 금속층(115B) 전체가 상기 솔더 페이스트(120B)와 합금 및/또는 금속간 화합물을 형성할 수 있으나, 이에 한정되는 것은 아니다.
이와 같이, 상기 제2 금속층(115B) 전체가 상기 솔더 페이스트(120B)와 금속간 화합물을 형성하는 경우, 이는 고성능 소자(high power device)에 적용이 가능하다.
또는, 상기 제1 금속층(113)의 일부 또는 전부는 상기 솔더 페이스트(120B)와 금속간 화합물을 형성함으로써 계면층을 형성할 수도 있다. 또는, 상기 금속간 화합물은 상기 코어(111)의 성분을 포함할 수도 있다. 특히, 상기 제1 금속층(113) 전체가 상기 솔더 페이스트(120B)와 금속간 화합물을 형성하는 경우, 상기 제1 금속층(113)은 존재하지 않고 계면층이 직접 코어(111)의 표면에 존재할 수도 있다.
여기서, 상기 금속간 화합물은 예를 들어, (Ni,Cu)3Sn4, (Cu,Ni)6Sn5, 및 Ni3Sn4 로 구성되는 군으로부터 선택된 하나 이상일 수 있지만, 코어(111), 제1 금속층(113), 제2 금속층(115B), 및 상기 솔더 페이스트(120B)의 물질에 따라, 다른 금속간 화합물이 형성될 수도 있다. 상기 계면층 내에는 상기 제1 금속층(113)으로부터 유래한 성분과 상기 솔더 페이스트(120B)로부터 유래한 성분의 금속간 화합물이 존재할 수 있다. 또는, 상기 계면층 내에는 상기 제2 금속층(115B)으로부터 유래한 성분과 상기 솔더 페이스트(120B)로부터 유래한 성분의 합금이 존재할 수 있다.
상기 솔더 페이스트(120B)는 상기 리버스 리플로우용 심재(110)의 전면(whole surface)에서 상기 제2 금속층(115B)과의 혼합에 의해, 상기 제2 금속층(115B)이 없을 때보다 젖음성이 향상될 수 있다.
상기 범프 패드(132)의 제1 직경(132R)은 상기 리버스 리플로우용 심재(110)의 제2 직경(110R)보다 작거나, 실질적으로 동일할 수 있다. 즉, 상기 범프 패드(132)의 상면은 상기 리버스 리플로우용 심재(110)와 전부 오버랩될 수 있다.
상기 금속 소켓(212)은 상기 솔더 페이스트(120B)와 직접 접촉할 수 있다. 즉, 상기 금속 소켓(212)은 상기 리버스 리플로우용 심재(110)와 직접 접촉하지 않을 수 있다.
또한, 후술하겠지만, 상기 제2 금속층(115B)의 전부가 상기 솔더 페이스트(120B)로 둘러싸이는 핀(100B)의 경우에도, 볼 전단 강도(ball shear strength)는 필라로 형성된 일반적인 핀의 볼 전단 강도보다 높으므로, 상기 금속 소켓(212)과의 탈부착에 문제가 없다.
도 5는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지에서 핀의 강도를 나타내는 그래프이다.
도 5를 참조하면, 제2 금속층의 일부가 솔더 페이스트로부터 노출된 핀(100A)의 볼 전단 강도 및 제2 금속층의 전부가 솔더 페이스트로 둘러싸이는 핀(100B)의 볼 전단 강도를 각각 나타낸다.
물리적으로 금속 소켓에 연결되는 핀을 일반적인 솔더볼을 형성할 경우, 볼 전단 강도가 낮아 핀의 변형이 발생한다. 이를 해결하기 위하여, 핀은 약 150gf 이상의 볼 전단 강도를 만족하여야 한다.
본 실험에서 사용된 일 실시예의 핀(100A)은 평균 볼 전단 강도가 약 268.4gf로, 다른 실시예의 핀(100B)은 평균 볼 전단 강도가 약 268.0gf로 측정되었다.
즉, 본 실험에서 사용된 핀들(100A, 100B)은 기준 강도(150gf)의 약 180% 정도의 수치를 가지는 것으로 확인되었으며, 이는 금속 소켓과의 탈부착에 문제가 없는 수치이므로, 핀 그리드 어레이 방식의 반도체 패키지에 적용 가능하다.
도 6은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지의 제조 방법을 나타내는 순서도이다.
본 발명의 기술적 사상에 따른 반도체 패키지의 제조 방법(S10)은 다음과 같은 공정 순서를 포함할 수 있다. 어떤 실시예가 달리 구현 가능한 경우에 특정한 공정 순서는 설명되는 순서와 다르게 수행될 수도 있다. 예를 들어, 연속하여 설명되는 두 공정이 실질적으로 동시에 수행될 수도 있고, 설명되는 순서와 반대의 순서로 수행될 수도 있다.
도 6을 참조하면, 범프 패드가 배치되는 제1 기판을 제공하는 제1 단계(S110), 금속 소켓이 배치되는 제2 기판을 제공하는 제2 단계(S120), 범프 패드 상에 솔더 페이스트 또는 솔더 범프를 실장하는 제3 단계(S130), 솔더 페이스트 또는 솔더 범프 상에 리버스 리플로우용 심재를 배치하는 제4 단계(S140), 적어도 리버스 리플로우용 심재의 측면 상에 솔더층을 형성하도록 솔더 페이스트 또는 솔더 범프를 리플로우하는 제5 단계(S150), 그리고 리버스 리플로우용 심재 및 이와 접합된 솔더 페이스트 또는 솔더 범프가 핀의 역할을 수행하여 핀을 금속 소켓에 결합하는 제6 단계(S160)를 포함하는 반도체 패키지의 제조 방법(S10)을 나타낸다.
상기 제1 내지 제6 단계(S110 내지 S160) 각각에 대한 기술적 특징은 후술하는 도 7a 내지 도 7e를 통하여 상세히 설명하도록 한다.
도 7a 내지 도 7e는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지의 제조 방법을 순서에 따라 나타내는 단면도들이다.
도 7a를 참조하면, 범프 패드(132)를 갖는 반도체 장치(130)가 제공되고, 상기 범프 패드(132) 상에 솔더 페이스트(120)를 실장하는 단계를 나타낸다.
반도체 장치(130)는 제1 기판(134), 상기 제1 기판(134)의 표면에 형성된 범프 패드(132), 및 상기 제1 기판(134)에 배치된 반도체 소자들을 포함할 수 있다.
상기 솔더 페이스트(120)는 도전성의 금속 분말이 액상의 플럭스와 혼합되어 있는 혼합물일 수 있다. 상기 솔더 페이스트(120)의 상면(120T)은 편평할 수 있다. 또한, 상기 솔더 페이스트(120)의 폭이 상기 범프 패드(132)의 폭과 실질적으로 동일하도록 실장할 수 있다.
도 7b를 참조하면, 금속 소켓(212)을 가지는 모듈 장치(210)가 제공된다.
상기 모듈 장치(210)는 제2 기판(214), 상기 제2 기판(214)의 상부면에 형성된 금속 소켓(212)을 포함할 수 있다. 상기 금속 소켓(212)은 이의 중심부에 핀(100, 도 7d 참조)이 탈부착될 수 있도록, 중심부가 오목한 Y자 형상으로 형성될 수 있다.
상기 금속 소켓(212)은 전도성의 소켓일 수 있다. 상기 금속 소켓(212)은 예를 들어, 구리(Cu) 소켓, 니켈(Ni) 소켓, 또는 니켈이 도금된 알루미늄(Al) 소켓일 수 있으나, 이에 한정되는 것은 아니다.
도 7c를 참조하면, 솔더 페이스트(120)의 상면(120T) 상에 리버스 리플로우용 심재(110)를 배치하는 단계를 나타낸다.
리버스 리플로우용 심재(110)는 예를 들어, 코어(111)의 직경이 약 21㎛ 내지 약 500㎛이고, 제1 금속층(113)의 두께가 약 1㎛ 내지 약 5㎛이고, 제2 금속층(115)의 두께가 약 0.01㎛ 내지 약 0.3㎛일 수 있다. 다만, 상기 리버스 리플로우용 심재(110)의 직경이 이에 한정되는 것은 아니다.
상기 리버스 리플로우용 심재(110)의 자체 무게로 인하여, 솔더 페이스트(120)에 상기 리버스 리플로우용 심재(110)의 일부가 잠길 수 있다.
도 7d를 참조하면, 상기 리버스 리플로우용 심재(110)의 적어도 측면에 솔더층을 형성하기 위하여, 상기 솔더 페이스트(120)에 리플로우 공정을 수행하는 단계를 나타낸다.
상기 솔더 페이스트(120)의 온도를 상승시키면, 상기 솔더 페이스트(120)가 용융되어 상기 리버스 리플로우용 심재(110)의 표면을 코팅하게 된다. 구체적으로, 상기 솔더 페이스트(120)는 용융되어 상기 리버스 리플로우용 심재(110)의 측벽을 타고 이동하여, 결과적으로는 상기 리버스 리플로우용 심재(110)의 적어도 측면을 덮게 된다.
상기 리버스 리플로우용 심재(110)보다 상기 솔더 페이스트(120)가 아래쪽에 위치하여도 용융된 상기 솔더 페이스트(120)는 중력의 방향을 역행하여 상기 리버스 리플로우용 심재(110)의 표면을 따라 상승할 수 있다. 이때, 용융된 상기 솔더 페이스트(120)의 점도가 상당히 감소하기 때문에 상기 리버스 리플로우용 심재(110)는 용융되지 않은 상기 솔더 페이스트(120) 위에 처음 배치되었을 때보다 제1 기판(134) 쪽으로 가깝게 이동할 수 있다. 이러한 리버스 리플로우용 심재(110)의 움직임, 그 표면에서의 표면 장력, 및 상기 리버스 리플로우용 심재(110)의 표면을 이루는 제2 금속층(115, 도 1 참조)과 상기 솔더 페이스트(120) 사이의 친화성에 의하여, 상기 솔더 페이스트(120)가 중력에도 불구하고 상승하는 것으로 추정된다.
상기 리플로우 공정은 약 200℃ 내지 약 300℃의 온도에서 수행될 수 있다. 또한, 상기 리플로우 공정은 약 20초 내지 약 100초 동안 수행될 수 있다.
이로써, 상기 리버스 리플로우용 심재(110) 및 상기 솔더 페이스트(120)를 이용한 핀(100)이 상기 제1 기판(134) 상에 다수로 형성될 수 있다.
도 7e를 참조하면, 핀(100)과 금속 소켓(212)을 사이에 두고, 모듈 장치(210) 상에 반도체 장치(130)를 배치하는 단계를 나타낸다.
여기서, 상기 반도체 장치(130) 및 상기 모듈 장치(210)는 일정 거리만큼 서로 이격되도록 배치될 수 있다. 즉, 결합 공정을 진행하기 전, 상기 반도체 장치(130) 및 상기 모듈 장치(210)를 각각의 핀(100)과 이에 대응하는 금속 소켓(212)이 정확하게 결합하도록 정렬할 수 있다. 일부 실시예들에서, 상기 반도체 장치(130)는 상기 모듈 장치(210)에 결합(또는 부착)될 뿐만 아니라 분리(또는 탈착)될 수 있다.
다시 도 2를 참조하면, 상기 핀(100) 및 상기 금속 소켓(212)이 결합하여, 핀 그리드 어레이 방식의 반도체 패키지(10)를 형성하도록 공정을 진행할 수 있다.
본 발명의 기술적 사상에 따르면, 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)를 핀(100)으로 이용함으로써, 리버스 리플로우용 심재(110)의 최외곽층을 구성하는 제2 금속층(115, 도 1 참조)의 물질 특성에 따라, 내부식 및 내산화 특성 그리고 높은 신호 전달 특성을 모두 만족시킬 수 있다. 따라서, 공정 비용과 제조 시간을 절약할 수 있으므로, 궁극적으로 반도체 패키지(10)의 제조 효율 및 생산성을 높일 수 있다.
또한, 본 발명의 기술적 사상에 따르면, 리버스 리플로우용 심재(110) 및 솔더 페이스트(120)를 핀(100)으로 이용함으로써, 상대적으로 정밀도가 높고 접합 강도가 우수한 핀 그리드 어레이 방식의 반도체 패키지(10)를 경제적으로 제공할 수 있는 효과가 있다.
도 8은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 메모리 모듈을 나타내는 평면도이다.
도 8을 참조하면, 메모리 모듈(1000)은 인쇄회로 기판(1100) 및 복수의 반도체 패키지(1200)를 포함할 수 있다.
복수의 반도체 패키지(1200)는, 앞서 도 2에서 설명한 본 발명의 기술적 사상에 따른 반도체 패키지(10)거나, 이를 포함할 수 있다.
메모리 모듈(1000)은 인쇄회로기판의 한쪽 면에만 복수의 반도체 패키지(1200)를 탑재한 SIMM(single in-lined memory module) 또는 복수의 반도체 패키지(1200)가 양면에 배열된 DIMM(dual in-lined memory module)일 수 있다. 또한, 상기 메모리 모듈(1000)은 외부로부터의 신호들을 복수의 반도체 패키지(1200)에 각각 제공하는 AMB(advanced memory buffer)를 갖는 FBDIMM(fully buffered DIMM)일 수 있다.
도 9는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 메모리 카드를 나타내는 개략도이다.
도 9를 참조하면, 메모리 카드(2000)에는 제어기(2100)와 메모리(2200)가 전기적인 신호를 교환하도록 배치될 수 있다.
메모리(2200)는, 앞서 도 2에서 설명한 본 발명의 기술적 사상에 따른 반도체 패키지(10)거나, 이를 포함할 수 있다.
상기 메모리 카드(2000)는 다양한 종류의 카드, 예를 들어, 메모리 스틱 카드(memory stick card), 스마트 미디어 카드(smart media card: SM), 씨큐어 디지털 카드(secure digital card), 미니-씨큐어 디지털 카드(mini-secure digital card), 멀티미디어 카드(multimedia card) 등과 같은 다양한 메모리 카드를 구성할 수 있다.
도 10은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 메모리 장치를 나타내는 블록도이다.
도 10을 참조하면, 메모리 장치(3000)는 메모리 모듈(3100) 및 메모리 컨트롤러(3200)를 포함할 수 있다.
메모리 모듈(3100)은, 앞서 도 2에서 설명한 본 발명의 기술적 사상에 따른 반도체 패키지(10)거나, 이를 포함할 수 있다. 상기 메모리 장치(3000)는 호스트(Host)와 상기 메모리 모듈(3100) 간의 데이터 교환을 제어하는 메모리 컨트롤러(3200)를 포함할 수 있다.
상기 메모리 컨트롤러(3200)는 메모리 카드의 전반적인 동작을 제어하는 프로세싱 유닛(3220)을 포함할 수 있다. 또한, 상기 메모리 컨트롤러(3200)는 상기 프로세싱 유닛(3220)의 동작 메모리로써 사용되는 에스램(3210)을 포함할 수 있다. 이에 더하여, 상기 메모리 컨트롤러(3200)는 호스트 인터페이스(3230) 및 메모리 인터페이스(3250)를 더 포함할 수 있다.
상기 호스트 인터페이스(3230)는 메모리 장치(3000)와 호스트(Host)간의 데이터 교환 프로토콜을 구비할 수 있다. 상기 메모리 인터페이스(3250)는 상기 메모리 컨트롤러(3200)와 상기 메모리 모듈(3100)을 접속시킬 수 있다. 더 나아가, 상기 메모리 컨트롤러(3200)는 에러 정정 블록(3240)을 더 포함할 수 있다. 상기 에러 정정 블록(3240)은 상기 메모리 모듈(3100)로부터 독출된 데이터의 에러를 검출 및 정정할 수 있다.
도시하지는 않았지만, 상기 메모리 장치(3000)는 호스트(Host)와의 인터페이싱을 위한 코드 데이터를 저장하는 롬 장치(ROM device)를 더 포함할 수 있다. 상기 메모리 장치(3000)는 컴퓨터 시스템의 하드 디스크를 대체할 수 있는 솔리드 스테이트 드라이브(Solid State Drive)로 구현될 수 있다.
도 11은 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 전자 시스템을 나타내는 블록도이다.
도 11을 참조하면, 전자 시스템(4000)은 컨트롤러(4100), 입출력 장치(4200), 메모리 장치(4300), 인터페이스(4400), 및 버스(4500)를 포함할 수 있다.
컨트롤러(4100), 입출력 장치(4200), 메모리 장치(4300), 및/또는 인터페이스(4400)는 버스(4500)를 통하여 서로 결합될 수 있다. 상기 버스(4500)는 데이터들이 이동되는 통로에 해당한다.
상기 컨트롤러(4100)는 마이크로프로세서, 디지털 신호 프로세스, 마이크로 컨트롤러, 및 이들과 유사한 기능을 수행할 수 있는 논리 소자들 중에서 적어도 하나를 포함할 수 있다.
상기 입출력 장치(4200)는 키패드, 키보드, 터치패드, 디스플레이 장치 등을 포함할 수 있다.
상기 메모리 장치(4300)는 데이터 및/또는 커맨드 등을 저장할 수 있다. 상기 메모리 장치(4300)는, 앞서 도 2에서 설명한 본 발명의 기술적 사상에 따른 반도체 패키지(10)거나, 이를 포함할 수 있다.
상기 인터페이스(4400)는 통신 네트워크로 데이터를 전송하거나 통신 네트워크로부터 데이터를 수신하는 기능을 수행할 수 있다. 상기 인터페이스(4400)는 유선 또는 무선 형태일 수 있다. 예를 들어, 상기 인터페이스(4400)는 안테나 또는 유무선 트랜시버 등을 포함할 수 있다.
도시하지는 않았지만, 상기 전자 시스템(4000)은 상기 컨트롤러(4100)의 동작을 향상시키기 위한 동작 메모리 소자로서, 고속의 디램 소자 및/또는 에스램 소자 등을 더 포함할 수도 있다.
상기 전자 시스템(4000)은 개인 휴대용 정보 단말기(personal digital assistant), 포터블 컴퓨터(portable computer), 태블릿(tablet), 무선 전화기(wireless phone), 모바일 폰(mobile phone), 디지털 뮤직 플레이어(digital music player), 메모리 카드(memory card) 등과 같은 정보를 무선 환경에서 송신 및/또는 수신할 수 있는 모든 전자 제품에 적용될 수 있다.
도 12는 본 발명의 기술적 사상의 실시예에 따른 반도체 패키지를 포함하는 서버 시스템에 대한 네트워크를 나타내는 블록도이다.
도 12를 참조하면, 네트워크 시스템(5000)은 네트워크(5200)를 통해 연결되는 서버 시스템(5100) 및 복수의 터미널(5300, 5400, 5500)을 포함할 수 있다.
서버 시스템(5100)은 네트워크(5200)에 연결되는 복수의 터미널(5300, 5400, 5500)로부터 수신되는 요청을 처리하는 서버(5110) 및 복수의 터미널(5300, 5400, 5500)로부터 수신되는 요청에 대응되는 데이터를 저장하는 전자 장치(5120)를 포함할 수 있다.
상기 전자 장치(5120)는, 앞서 도 2에서 설명한 본 발명의 기술적 사상에 따른 반도체 패키지(10)거나, 이를 포함할 수 있다. 상기 전자 장치(5120)는 예를 들어, 솔리드 스테이트 드라이브(SSD)일 수 있다.
이상, 첨부된 도면들을 참조하여 본 발명의 기술적 사상의 실시예를 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예는 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다.
10: 반도체 패키지
100: 핀 110: 리버스 리플로우용 심재
111: 코어 113: 제1 금속층
115: 제2 금속층 120: 솔더 페이스트
132: 범프 패드 134: 제1 기판
212: 금속 소켓 214: 제2 기판

Claims (10)

  1. 제1 기판에 배치되는 범프 패드;
    제2 기판에 배치되는 금속 소켓;
    상기 범프 패드에 배치되는 리버스 리플로우용 심재;
    상기 리버스 리플로우용 심재에 솔더층을 형성하며, 상기 범프 패드와 맞닿는 솔더 페이스트 또는 솔더 범프;를 포함하고,
    상기 리버스 리플로우용 심재 및 상기 리버스 리플로우용 심재와 접합된 상기 솔더 페이스트 또는 솔더 범프가 핀의 역할을 수행하여, 상기 금속 소켓에 탈부착되고,
    상기 금속 소켓은 상기 제1 기판에 가까울수록 입구가 벌어지고,
    상기 범프 패드의 제1 직경은 상기 리버스 리플로우용 심재의 제2 직경보다 작거나 동일하고,
    상기 리버스 리플로우용 심재는,
    코어;
    상기 코어의 직접 위에 코팅되고, 니켈(Ni) 또는 코발트(Co)인 제1 금속층; 및
    상기 제1 금속층의 직접 위에 코팅되고, 금(Au) 또는 백금(Pt)인 제2 금속층;을 포함하고,
    상기 금속 소켓은 상기 제2 금속층과 두 군데에서 직접 접촉하고, 상기 탈부착에서 상기 금속 소켓과 상기 핀의 접촉부가 산화되지 않는,
    핀 그리드 어레이(Pin Grid Array) 방식의, 반도체 패키지.
  2. 제1항에 있어서,
    상기 솔더층은, 상기 리버스 리플로우용 심재의 측면에서 상기 제2 금속층과의 혼합에 의해, 상기 제2 금속층이 없을 때보다 젖음성(wetting)이 향상되는 것을 특징으로 하는 반도체 패키지.
  3. 제2항에 있어서,
    상기 솔더층은 상기 리버스 리플로우용 심재의 측면까지 형성되고,
    상기 금속 소켓은 상기 솔더층과 맞닿지 않도록, 상기 핀과 탈부착하는 것을 특징으로 하는 반도체 패키지.
  4. 삭제
  5. 제2항에 있어서,
    상기 솔더층의 두께가 상기 제1 기판으로부터 멀어짐에 따라 점차 얇아지는 것을 특징으로 하는 반도체 패키지.
  6. 제1항에 있어서,
    상기 코어의 직경은 21㎛ 내지 500㎛이고,
    상기 제2 금속층의 두께가 0.01㎛ 내지 0.3㎛인 것을 특징으로 하는 반도체 패키지.
  7. 범프 패드가 배치되는 제1 기판을 제공하는 단계;
    금속 소켓이 배치되는 제2 기판을 제공하는 단계;
    상기 범프 패드 상에 솔더 페이스트 또는 솔더 범프를 실장하는 단계;
    상기 솔더 페이스트 또는 솔더 범프 상에 리버스 리플로우용 심재를 배치하는 단계;
    적어도 상기 리버스 리플로우용 심재의 측면 상에 솔더층을 형성하도록 상기 솔더 페이스트 또는 솔더 범프를 리플로우시키는 단계; 및
    상기 리버스 리플로우용 심재 및 상기 리버스 리플로우용 심재와 접합된 상기 솔더 페이스트 또는 솔더 범프가 핀의 역할을 수행하여, 상기 핀을 상기 금속 소켓에 결합하는 단계;를 포함하고,
    상기 금속 소켓은 상기 제1 기판에 가까울수록 입구가 벌어지고,
    상기 리버스 리플로우용 심재는,
    코어;
    상기 코어의 직접 위에 코팅되고, 니켈(Ni) 또는 코발트(Co)인 제1 금속층; 및
    상기 제1 금속층의 직접 위에 코팅되고, 금(Au) 또는 백금(Pt)인 제2 금속층;을 포함하고,
    상기 금속 소켓은 상기 제2 금속층과 두 군데에서 직접 접촉하고, 상기 결합하는 단계에서 상기 금속 소켓과 상기 핀의 접촉부가 산화되지 않는,
    핀 그리드 어레이(Pin Grid Array) 방식의, 반도체 패키지의 제조 방법.
  8. 제7항에 있어서,
    상기 범프 패드의 제1 직경은 상기 리버스 리플로우용 심재의 제2 직경보다 작거나 동일한 것을 특징으로 하는 반도체 패키지의 제조 방법.
  9. 제7항에 있어서,
    상기 솔더층은 상기 리버스 리플로우용 심재의 측면까지 형성되고,
    상기 금속 소켓은 상기 솔더층과 맞닿지 않도록, 상기 핀과 결합하는 것을 특징으로 하는 반도체 패키지의 제조 방법.
  10. 삭제
KR1020200065396A 2020-05-29 2020-05-29 핀 그리드 어레이 방식의 반도체 패키지 KR102392856B1 (ko)

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