TWI433265B - 半導體裝置 - Google Patents
半導體裝置 Download PDFInfo
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- TWI433265B TWI433265B TW098127357A TW98127357A TWI433265B TW I433265 B TWI433265 B TW I433265B TW 098127357 A TW098127357 A TW 098127357A TW 98127357 A TW98127357 A TW 98127357A TW I433265 B TWI433265 B TW I433265B
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- 229910052751 metal Inorganic materials 0.000 title claims description 85
- 239000002184 metal Substances 0.000 title claims description 85
- 238000004519 manufacturing process Methods 0.000 title description 13
- 239000004065 semiconductor Substances 0.000 claims description 74
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 59
- 229920005591 polysilicon Polymers 0.000 claims description 59
- 239000000758 substrate Substances 0.000 claims description 50
- 238000002955 isolation Methods 0.000 claims description 43
- 239000000463 material Substances 0.000 claims description 23
- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 9
- 229910004166 TaN Inorganic materials 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910019001 CoSi Inorganic materials 0.000 claims description 3
- 229910010038 TiAl Inorganic materials 0.000 claims description 3
- 229910006249 ZrSi Inorganic materials 0.000 claims description 3
- 229910004129 HfSiO Inorganic materials 0.000 claims description 2
- 229910005881 NiSi 2 Inorganic materials 0.000 claims description 2
- 210000000988 bone and bone Anatomy 0.000 claims description 2
- 229910000420 cerium oxide Inorganic materials 0.000 claims 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 description 119
- 238000000034 method Methods 0.000 description 83
- 230000008569 process Effects 0.000 description 55
- 238000005229 chemical vapour deposition Methods 0.000 description 16
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 15
- 239000000126 substance Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 13
- 229910052732 germanium Inorganic materials 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005240 physical vapour deposition Methods 0.000 description 10
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical group [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 238000000059 patterning Methods 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000005498 polishing Methods 0.000 description 7
- 238000007517 polishing process Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 5
- 239000003989 dielectric material Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 229910052735 hafnium Inorganic materials 0.000 description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 description 5
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 5
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 5
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- 240000004050 Pentaglottis sempervirens Species 0.000 description 2
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- -1 zirconium silicates Chemical class 0.000 description 2
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 1
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910001152 Bi alloy Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910016006 MoSi Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- YUNHQXWHVFZHGY-UHFFFAOYSA-N [O-2].[Y+3].[C+4] Chemical compound [O-2].[Y+3].[C+4] YUNHQXWHVFZHGY-UHFFFAOYSA-N 0.000 description 1
- 239000004964 aerogel Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- MRPWWVMHWSDJEH-UHFFFAOYSA-N antimony telluride Chemical compound [SbH3+3].[SbH3+3].[TeH2-2].[TeH2-2].[TeH2-2] MRPWWVMHWSDJEH-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-M hydroxide Chemical compound [OH-] XLYOFNOQVPJJNP-UHFFFAOYSA-M 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910000484 niobium oxide Inorganic materials 0.000 description 1
- URLJKFSTXLNXLG-UHFFFAOYSA-N niobium(5+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Nb+5].[Nb+5] URLJKFSTXLNXLG-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920000052 poly(p-xylylene) Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000001012 protector Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 241000894007 species Species 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 229910000314 transition metal oxide Inorganic materials 0.000 description 1
- 229910000326 transition metal silicate Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
本發明係有關於半導體技術,且特別是有關於一種用於高介電常數金屬閘極技術之電阻裝置及其製造方法。
多晶矽電阻已被廣泛用於傳統積體電路設計中,包含用於RC震盪器、限制電流之電阻(current limitation resistance)、ESD保護器(ESD protect)、RF後置驅動器(RF post driver)、晶片終端電阻(on-chip termination)及阻抗匹配(impedance matching)等。對於閘極置換技術(通常稱為後閘極製程)來說,多晶矽電阻器通常包含矽化物區域,其電阻率較低,因此需要較大的區域。單晶矽電阻器(例如,形成於半導體基材中的電阻器)已被提出以解決上述問題,然而,單晶矽電阻器無法提供精確的阻抗匹配及用於類比電路的電容量,例如無線射頻及混合模式的電路。
多晶矽電子熔絲(eFuses)已被廣泛用於傳統記憶積體電路設計中。對於高介電常數金屬閘極技術來說,由於多晶矽層上形成有金屬閘極且多晶矽層下形成有矽化物,因此電阻率偏低,欲燒毀電子熔絲變得相對困難。接觸點、通孔及銅金屬的使用已被提出可解決上述問題,然而,這些嘗試無法解決關於程式化電壓(programming voltage)的問題。
因此,業界需要的是一種具有能夠滿足適當電阻率需求的電阻器或電子熔絲之製造方法。
本發明提供一種半導體裝置,包含:一半導體基材;一隔離結構,形成於該基材中,用以隔離該基材之一主動區,該隔離結構係由一第一材料形成;一主動裝置,形成於該基材之該主動區中,該主動區具有一高介電常數介電質及一金屬閘極;以及一被動裝置,形成於該基材之該隔離結構中,該被動裝置係由與該第一材料不同之一第二材料形成及具有一預定之電阻。
本發明也提供一種半導體裝置,包含:一半導體基材;一隔離結構,形成於該基材中,用以隔離該基材之一第一區域及一第二區域,一第一電晶體及一第二電晶體,分別形成於該第一區域及該第二區域中,且該第一電晶體及該第二電晶體各自具有一高介電常數介電質及一金屬閘極;以及一多晶矽電阻器,形成於該隔離結構中,其中該多晶矽電阻器之一表面與該隔離結構之一表面位於同一平面上。
本發明又提供一種半導體裝置,包含:一半導體基材;一隔離結構,形成於該基材中,用以隔離該基材之一主動區;一電晶體,形成該主動區中,該電晶體具有一包含高介電常數介電層及一金屬層之閘極結構;以及一熔絲結構,形成於該隔離結構上,該熔絲結構具有一連接部分,其包含該高介電常數介電層及該金屬層,其中該連接部分未包含位於該金屬層上不具有多晶矽層。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
本發明接下來將會提供許多不同的實施例以實施本發明中不同的特徵。各特定實施例中的組成及配置將會在以下作描述以簡化本發明。這些為實施例並非用於限定本發明。此外,在本說明書的各種例子中可能會出現重複的元件符號以便簡化描述,但這不代表在各個實施例及/或圖示之間有何特定的關連。此外,一第一元件形成於一第二元件“上方”、“之上”、“之下”或“上”可包含實施例中的該第一元件與第二元件直接接觸,或也可包含該第一元件與第二元件之間更有其他額外元件使該第一元件與第二元件無直接接觸。
參見第1圖,其顯示為依照本發明各種情況所繪示之製造具有金屬閘極之半導體裝置之方法100的流程圖。並參見第2A至2F圖,其顯示為依照第1圖中之方法100製造半導體裝置200於各個階段之剖面圖。值得注意的是,半導體裝置中的部分元件可由CMOS的製造流程來製造。因此,可於方法100之前、之中或之後提供額外的製程,且其中某些製程在此僅會作些簡單的描述。再者,第2A至2F圖係可簡化以使本發明之概念易於明瞭。
方法100起始於方塊110,其為提供半導體基材。在第2A圖中,基材202可包含半導體晶圓,例如矽晶圓。或者,基材202可包含其他元素半導體,例如鍺。基材202也可包含化合物半導體,例如碳化矽、砷化鎵、砷化銦及磷化銦。基材202可包含合金半導體,例如鍺化矽、碳鍺化矽、磷砷化鎵及磷銦化鎵。在一實施例中,基材202包含位於基塊(bulk)半導體上之磊晶層(epi layer)。此外,基材202包含半導體上覆絕緣體(semiconductor-on-insulator;SOI)結構。例如,基材202可包含由像是佈植氧加以分離(SIMOX)之製程形成之埋入氧化(buried oxide;BOX)層。在各種實施例中,基材202可包含埋入層,例如N型埋入層(NBL)、P型埋入層(PBL)及/或包含埋入氧化(BOX)層之埋入介電層。
接著,進行方塊120,其為在基材中形成隔離結構以隔離基材的第一區域及第二區域。隔離區域204,例如淺溝槽隔離(STI)或局部矽氧化(LOCOS),包含形成於基材中的隔離元件,以定義及電性隔離各種主動區域206、208。在進一步的實施例中,隔離結構204可由一系列之製程形成,例如成長墊化層(pad oxide)、形成低壓化學氣相沉積(LPCVD)氮化物層、使用光阻及罩幕進行圖案化形成開口、在溝槽202中蝕刻出溝槽、選擇性地成長熱氧化溝槽襯層以改善溝槽界面、以化學氣相沉積形成之氧化物填滿溝槽,及進行化學機械研磨(CMP)以回蝕刻及平坦化隔離結構204。
接著,方法100繼續進行方塊130,其為在隔離結構中形成電阻結構。在第2B圖中,光阻層212可形成在基材202上並可以光學微影、浸潤、微影、離子束寫入或其他合適技術來進行圖案化形成開口214。開口214可包含各種形狀,例如線形(liner)、矩形、狗骨頭形(dog bone)、多邊形或其他合適形狀。部分的隔離結構204由開口214暴露出來,並由包含乾蝕刻、濕蝕刻或乾蝕刻及濕蝕刻製程的組合蝕刻形成溝槽216。溝槽216的深度可由蝕刻製程來精確控制,以調控用於電阻裝置的電阻值。例如,可以已知蝕刻速率之蝕刻製程對蝕刻氧化物的時間變化,來控制溝槽深度。
在第2C圖中,多晶矽層220可沉積在氮化物層210上且填充隔離結構204中的溝槽216。多晶矽層220可由化學氣相沉積或其他合適沉積製程形成。在第2D圖中,可進行化學機械研磨(CMP)製程以回蝕刻多晶矽層220,且可停止於氮化物層210。
因此,多晶矽電阻裝置230可形成在隔離結構204中。值得注意的是,多晶矽電阻裝置230可包含純的多晶矽,其可於隨後由摻雜製程作摻雜(例如形成如下討論之輕摻雜源/汲極區(LDD)或源/汲極區(S/D))。或者,可選擇性地在溝槽216中沉積摻雜的多晶矽材料以摻雜多晶矽電阻裝置230,來取代先沉積純的多晶矽再對純的多晶矽作摻雜之製程。在第2E圖中,氮化物層210可由習知技藝之氮化物剝離製程來移除。
接著,方法100繼續進行方塊140,其為在第一區域或第二區域中形成具有高介電常數介電層及金屬閘極的裝置。在第2F圖中,P型金氧半導體(PMOS)裝置可形成在主動區206中,及N型金氧半導體(NMOS)裝置可形成在主動區208中。可由進行包含多晶矽閘極替換(或後閘極製程)之CMOS製程流程形成PMOS及NMOS裝置。在後閘極製程中,起初可先形成虛置多晶矽閘極及接著可進行CMOS製程流程,形成半導體裝置200的各種元件(例如輕摻雜源/汲極區(LDD)、側壁間隔物、源/汲極區(S/D)、抵擋保護氧化物(RPO)、矽化物元件、接觸蝕刻停止層等(CESL)),直到由高密度電漿(HDP)製程或其他合適技術來沉積層間介電層,再對層間介電層進行化學機械研磨(CMP)製程以暴露出此虛置多晶矽閘極結構,並於隨後以回蝕刻或其他合適技術移除此虛置多晶矽閘極結構而形成溝槽。可以一或多種金屬層填充此溝槽,並於隨後進行金屬之化學機械研磨製程以回蝕刻及平坦化此閘極結構。因此,虛置閘極結構可被替換為金屬閘極結構。隨後,繼續進行半導體裝置200的進一步製程以形成接觸點(contacts)/通孔(vias)及內連線元件,例如金屬層及層間介電層,以電性連接PMOS裝置、NMOS裝置、電阻裝置及其他微電子裝置(在此未顯示)以形成積體電路。半導體裝置200的各種元件包NMOS及PMOS裝置,係在此簡短討論如下。
例如,閘極結構可形成在基材202上,包含閘極介電質234及金屬閘極236。閘極介電質234可包含高介電常數介電材料,例如金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物(transition metal-oxides)、過渡金屬氮化物(transition metal-nitrides)、過渡金屬矽酸鹽(transition metal-silicates)、金屬氮氧化物、金屬鋁化物(metal aluminates)、矽酸鋯(zirconium silicate)、鋁酸鋯(zirconium alumiante)、HfO、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或前述之組合。閘極介電質234可具有多層結構,例如一層為氧化矽(例如界面層),另一層為高介電常數介電材料。閘極介電質234之厚度約為10至30。可使用化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)、熱氧化法、其他合適製程或前述之組合來形成閘極介電質。
金屬閘極236可用於連接金屬內連線且可配置於閘極介電質234上。金屬閘極236可包含TiN、TaN、TaC、CoSi、ZrSi2
、MoSi2
、TaSi2
、NiSi2
、WN、TiAl、TiNAl、Al、其他導體材料或前述之組合。金屬閘極236可由化學氣相沉積(CVD)、物理氣相沉積(PVD)、電鍍、其他合適製程或前述之組合形成,並接著可以對金屬之化學機械研磨製程來平坦化閘極結構。金屬閘極236可具有多層結構,並可由多次製程形成。在某些其他實施例中,蓋層(例如氧化鑭或氧化鋁)可形成在高介電常數介電層之上或之下,以調控金屬閘極之有效功函數來作為適當的PMOS或NMOS裝置。
閘極結構可由使用包含光學微影圖案化及蝕刻之製程形成。以下描述一種用於圖案化閘極介電質及虛置多晶矽閘極結構之示範方法。以適當製程在多晶矽層上形成光阻層,例如旋轉塗佈,接著由適當的微影圖案化方法進行圖案化以圖案化光阻元件。在經由多個製程步驟及適當結果後,此光阻層的圖案可由乾蝕刻製程轉移至底下的多晶矽層及閘極介電質。接著可剝除此光阻層。在另一實施例中,可使用硬罩幕層於並形成於多晶矽層上。光阻層的圖案可轉移至硬罩幕層上,並接著轉移至多晶矽層以形成虛置多晶矽閘極。硬罩幕層可包含氮化矽、氮氧化矽、碳化矽及/或其他合適材料,並可由化學氣相沉積(CVD)或物理氣相沉積(PVD)之方法形成。
在進行完前述之閘極圖案化或蝕刻製程後,可在半導體基材202中形成輕摻雜源/汲極區(也可稱為LDD區)。可由離子佈植製程摻雜P型(例如硼或二氟化硼)摻質及/或N型(例如磷或砷)摻質至輕摻雜源/汲極區,且可包含對於PMOS裝置206及NMOS裝置208之各種習知技藝之摻雜輪廓。如前述,多晶矽電阻裝置230可選擇性地在此製程中作摻雜。
側壁間隔物240可形成在閘極結構兩側之側壁上。側壁間隔物240可包含介電材料,例如氧化矽。或者,側壁間隔物可選擇性地包含氮化矽、碳化矽、氮氧化矽或前述之組合。在某些實施例中,側壁間隔物240可具有多層結構。側壁間隔物240可由習知技藝之沉積及蝕刻(非等向性蝕刻技術)形成。
P型的源/汲極區可形成於PMOS裝置206中,及N型的源/汲極區可形成於NMOS裝置208中。源/汲極區可位於閘極結構之兩側並***閘極結構中。此源/汲極區可直接形成在半導體基材202上、P型井區結構中、N型井區結構中、雙井區結構中或為***結構。此源/汲極區可包含種摻雜輪廓,且可由多次的離子佈植步驟形成。可進行快速熱退火(RTP)步驟來活化摻雜區域。如前述,多晶矽電阻裝置230可選擇性地在此製程中作摻雜。
在某些實施例中,阻擋保護氧化物(resist protective layer;RPO)可形成在某些或全部的多晶矽電阻裝置230上,及可在隨後的矽化製程中作為矽化物的阻擋層。因此,多晶矽電阻裝置230可不包含會使電阻降低之矽化物區域。半導體裝置200可進一步包含形成在基材202上各種接觸點及金屬元件。矽化物元件可由矽化製程形成,例如自我矽化製程,其為在矽結構旁形成金屬材料,然後上昇溫度以進行退火並造成金屬與其底下的矽進行反應形成矽化物,再將未反應的金屬蝕刻移除。此矽化物材料可自我對準以形成在各種元件上,例如源/汲極區或其他摻雜區域,以減少接觸電阻。
此外,複數個圖案化之介電層及導電層形成在基材202上以形成多重內連線結構以連接PMOS及NMOS裝置(例如P型及N型摻雜裝置,像是源/汲極區、接觸區域、金屬閘極)、多晶矽電阻裝置及其他積體電路之微電子裝置(此處未顯示)。在一實施例中,形成層間介電層(ILD)及多層內連線(MLI)結構。在進一步的實施例中,多層內連線(MLI)結構可包含導體材料,例如鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物或前述之組合,稱為鋁內連線(aluminum interconnects)。
鋁內連線(aluminum interconnects)可由包含物理氣相沉積(或濺鍍)、化學氣相沉積或前述之組合形成。其他形成鋁內連線之製造技術包含光學微影製程及蝕刻,以圖案化導體材料來形成垂直連接(通孔及接觸點)或水平連接(導線)。或者,也可使用銅多層內連線以形成金屬圖案。銅內連線可包含銅、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物或前述之組合。銅內連線可由包含化學氣相沉積、濺鍍、電鍍或其他合適製程之技術形成。
層間介電層材料包含氧化矽。或者,層間介電層包含具有低介電常數之材料。在一實施例中,介電層包含二氧化矽、氮化矽、氮氧化矽、聚亞醯胺、旋塗式玻璃(SOG)、氟摻雜玻璃(FSG)、碳摻雜氧化矽(carbon doped silicon oxide)(例如SiCOH)、Black(Applied Materials of Santa Clara,California)、乾凝膠(Xerogel)、氣凝膠(Aerogel)、非結晶氟化碳、聚對二甲苯(Parylene)、雙苯環丁烯(bis-benzocyclobutenes;BCB)、SiLK(Dow Chemical,Midland,Michigan)、聚亞醯胺及/或前述之組合。介電層可由包含旋轉塗佈、化學氣相沉積或其他合適製程之技術形成。
可在積體製程(integrated process)中形成多層內連線(MLI)及層間介電層(ILD)結構,例如鑲嵌(damascene)製程。在鑲嵌製程中,可使用金屬(例如銅)作為內連線的導體材料。也可額外或交替地使用其他金屬或金屬合金作為各種導體元件。因此,氧化矽、氟摻雜矽玻璃或低介電常數材料可用於作為層間介電層(ILD)。在鑲嵌製程中,為在介電層中形成溝槽並以銅填充此溝槽,之後再以化學機械研磨回蝕刻及平坦化基材表面。
參見第3圖,其顯示為依照本發明各種情況所繪示之製造具有金屬閘極電子熔絲(eFuse)之半導體裝置之方法300的流程圖。並參見第4A至4E圖,其顯示為依照第3圖中之方法300製造半導體裝置400於各個階段之剖面圖。半導體裝置400可由後閘極製程製造,且可與於第2圖中的半導體裝置200的製造作整合。因此,在第2及4圖中,相似的元件具有相同的號碼以簡化明瞭。此外,半導體裝置400可由與前述之半導體裝置200的相同製程製造。
方法300起始於方塊310,其為提供半導體基材。在第4A圖中,半導體裝置400可包含半導體基材202。複數個隔離區域,例如淺溝槽隔離(STI)204,形成在基材202中,以隔離一或多個裝置。例如,淺溝槽隔離204可用於隔離MOS裝置(近似於第2圖中的PMOS裝置206及NMOS裝置208)。此外,可在淺溝槽隔離204上形成電子熔絲(eFuse)裝置404。
接著,方法300繼續進行方塊320,其為在第一區域形成具有虛置閘極之電晶體及在第二區域形成虛置熔絲。在後閘極製程中,可形成MOS裝置402及電子熔絲(eFuse)裝置404,其中虛置多晶矽閘極410及虛置熔絲412為對應於MOS裝置402及電子熔絲(eFuse)裝置404形成。虛置多晶矽閘極410及虛置熔絲裝置412可由沉積及圖案化各種材料層形成,以形成對應於MOS裝置402的閘極結構及電子熔絲裝置404的熔絲結構。
例如,閘極介電層234可形成在基材202上。閘極介電層234可包含界面氧化層及高介電常數介電層。閘極介電層234之厚度約為10至30。半導體裝置400可進一步包含蓋層,例如氧化鑭或氧化鋁,以調控金屬層之有效功函數來作為適當的PMOS及NMOS裝置。金屬阻障層416可形成在閘極介電層234上。金屬阻障層416可作為阻障及防止高介電常數介電層與隨後沉積之多晶矽層之間的費米能階釘扎(Fermi level pinning)。例如,金屬阻障層416包含氮化鈦,其厚度約為10至200。金屬阻障層416可由化學氣相沉積或其他合適技術形成。多晶矽層可形成在金屬阻障層416上。此多晶矽層之厚度約為400至800。可圖案化此多晶矽層以形成MOS裝置402之虛置多晶矽閘極410及電子熔絲裝置404之虛置熔絲412。
MOS裝置402的閘極結構及電子熔絲裝置404的熔絲結構可由包含光學微影圖案化及蝕刻之製程形成。以下描述一種用於圖案化閘極結構及熔絲結構之示範方法。形成硬罩幕層420於多晶矽層上,形成圖案化光阻層於硬罩幕層上。將光阻層之圖案轉移至硬罩幕層420上,並接著轉移至多晶矽層上,以形成虛置多晶矽閘極410及虛置熔絲412。硬罩幕層420可包含氮化矽、氮氧化矽、碳化矽及/或其他適當介電材料,並可由像是化學氣相沉積或物理氣相沉積之方法形成。
隨後,半導體裝置400可進行CMOS製造流程以形成各種元件,例如輕摻雜源/汲極區(LDD)425、側壁間隔物240、源/汲極區430及矽化物區432。可形成應力層於MOS裝置402及電子熔絲裝置404上。例如,可形成接觸蝕刻停止層(CESL)440,且其可包含氮化矽、氮氧化矽及/或其他合適材料。介電層,例如層間介電層(ILD)450,可由化學氣相沉積、高密度電漿化學氣相沉積(HDP-CVD)、旋轉塗佈、物理氣相沉積(或濺鍍)或其他合適方法形成在接觸蝕刻停止層(CESL)440上。層間介電層450可包含氧化矽或低介電常數材料。
接著,繼續進行方塊330,其為移除電晶體之虛置閘極及熔絲之虛置熔絲,並因而形成第一溝槽及第二溝槽。在第4B圖中,可在層間介電層450上進行化學機械研磨455以暴露虛置多晶矽閘極410及虛置熔絲412。化學機械研磨製程455可停止於硬罩幕層420並繼續過研磨(over-polishing)以移除硬罩幕層420。在第4C圖中,可進行回蝕刻製程、乾蝕刻、濕蝕刻或其他合適製程來移除虛置多晶矽閘極410及虛置熔絲412。例如,濕蝕刻製程可包含暴露在含氫氧化物之溶液(例如氫氧化銨)、去離子水及/或其他合適蝕刻溶液中。因此,可在閘極結構及熔絲結構中形成溝槽460、462。值得注意的是,在蝕刻多晶矽的製程中,因為金屬阻障層416作為蝕刻阻障,因此可降低高介電常數介電層遭到損害的風險。
接著,繼續進行方塊340,其為形成金屬以填充第一及第二溝槽。在第4D圖中,可沉積一或多個金屬層以形成MOS裝置402的金屬閘極及熔絲裝置404的金屬熔絲,金屬層470可包含任何合適於形成金屬閘極之材料,包含功函數金屬層、填充金屬層、襯層、界面層、晶種層(seed layer)等。例如,金屬層470可包含功函數金屬層(例如N型或P型功函數金屬)及填充金屬層。功函數金屬層可包含TiN、TiAlN、TaN、TiSiN、WN、TaC、TaCN或前述之組合。填充金屬層可包含鋁、銅、鎢或其他合適材料。金屬層470可由物理氣相沉積、化學氣相沉積、電鍍或其他合適技術形成。
接著,繼續進行方塊350,其為進行化學機械研磨(CMP)製程。在第4E圖中,可在金屬層470上進行化學機械研磨製程480以平坦化MOS裝置402的閘極結構及電子熔絲裝置404的熔絲結構。因此,電子熔絲裝置404可包含閘極介電層234、金屬阻障層416及金屬閘極層470。金屬閘極層470在進行化學機械研磨製程480後之厚度約為800。因此,MOS裝置402及電子熔絲裝置404可由相同製程形成,無須額外的罩幕層。可知的是,半導體裝置400可進行更進一步的製程以形成各種元件,例如接觸點(contacts)/通孔(vias)、內連線金屬層、層間介電層、保護層等,如上述討論。
參見第5圖,其顯示為使用於第4圖中之半導體裝置400之電子熔絲裝置500的俯瞰圖。電子熔絲裝置500可包含陽極部分502、陰極部分504及連接部分506。複數個接觸點510可連接至陽極部分502及陰極部分504以電性連接電子熔絲裝置500至半導體裝置之內連線結構。可施以程式化電壓(programming voltages),經由接觸點510跨越陽極502與陰極504,以燒毀電子熔絲裝置500。也就是說,可燒毀電子熔絲裝置500的連接部分,並形成斷路的情況。可以觀察到,相較於金屬/多晶矽/矽化物熔絲結構,在高介電常數金屬閘極技術中的全金屬熔絲結構可使程式化電壓獲得改善。
本發明所述之結構及方法皆可具有各種實施例、修飾及變化。在一實施例中,半導體裝置可進一步包含位於基材及閘極結構上之應力層。此應力層可包含氮化矽、氮氧化矽、氧化矽及碳化矽。在另一實施例中,源/汲極區可具有不同的結構,例如***、凹陷或施以應力。在又一實施例中,半導體裝置可包含(但不限於)垂直擴散金氧半導體(VDMOS)、其他型態之高功率MOS電晶體、鰭式場效電晶體(FinFET)及應變的MOS結構。在更其他實施例中,形成在隔離結構中之電阻結構可包含多晶矽電子熔絲或其他被動裝置。
本發明可在在此揭示的各種實施例中到不同的優點。例如,本發明提供一種簡單又有經濟效益的方法來在高介電常數金屬閘極技術中合併多晶矽電阻裝置及金屬電子熔絲裝置。此外,在此所述之方法及裝置可輕易的與現有的CMOS製程及半導體製造設備整合。再者,在此所述之方法及裝置提供一種簡單的方式來控制多晶矽電阻裝置的電阻值及避免在製程中於多晶矽電阻裝置中形成矽化物。並且,在此所述之方法及裝置提供一種簡單的方式來改善用於先進技術製程節點(例如45nm或更小)之電子熔絲的程式化電壓。可知的是,在此所述之各種實施例提供了不同的優點,且沒有特定的優點需適用於全部的實施例。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。例如,雖然半導體裝置是描述於後閘極製程中,也可以前閘極製程製造PMOS及NMOS裝置(無需虛置多晶矽閘極結構)或以包含前閘極製程(形成一種型態之金屬閘極)及後閘極製程(形成其他型態的金屬閘極)之混成製程製造。
200...半導體裝置
202...基材
204...隔離結構
206、208...主動區
210...氮化物層
212...光阻層
214...開口
216...溝槽
220...多晶矽層
230...多晶矽電阻裝置
234...閘極介電質
236...金屬閘極
240...側壁間隔物
400...半導體裝置
402...MOS裝置
404...電子熔絲
410...虛置多晶矽閘極
412...虛置熔絲
416...金屬阻障層
420...硬罩幕層
425...輕摻雜源/汲極區
430...源/汲極區
432...矽化物區
440...接觸蝕刻停止層
450...層間介電層
455...化學機械研磨製程
460、462...溝槽
470...金屬層
480...化學機械研磨製程
500...電子熔絲裝置
502...陽極部分
504...陰極部分
506...連接部分
510...接觸點
第1圖依照本發明之一實施例之具有置於隔離結構中之電阻結構之半導體裝置製造方法之流程圖。
第2A~2F圖為依照第1圖之製造方法製造半導體裝置之一系列剖面圖。
第3圖依照本發明之一實施例之具有置於隔離結構中之金屬閘極電子熔絲之半導體裝置製造方法之流程圖。
第4A~4E圖為依照第3圖之製造方法製造半導體裝置之一系列剖面圖。
第5圖為可使用於第4圖之半導體裝置之電子熔絲結構之俯瞰圖。
500...電子熔絲裝置
502...陽極部分
504...陰極部分
506...連接部分
510...接觸點
Claims (20)
- 一種半導體裝置,包含:一半導體基材;一隔離結構,形成於該基材中,用以隔離該基材之一主動區,該隔離結構係由一第一材料形成;一主動裝置,形成於該基材之該主動區中,該主動區具有一高介電常數介電質及一金屬閘極;以及一被動裝置,形成於該基材之該隔離結構中,該被動裝置係由與該第一材料不同之一第二材料形成,及具有一預定(predefined)之電阻,其中該被動裝置之下表面高於該隔離結構之下表面。
- 如申請專利範圍第1項所述之半導體裝置,其中該第二材料係包含一多晶矽。
- 如申請專利範圍第1項所述之半導體裝置,其中該第一材料係包含一氧化矽。
- 如申請專利範圍第1項所述之半導體裝置,其中該主動裝置係包含一PMOS裝置或一NMOS裝置。
- 如申請專利範圍第1項所述之半導體裝置,其中該被動裝置係包含矩形、狗骨頭形(dog bone shape)或多邊形之形狀。
- 如申請專利範圍第5項所述之半導體裝置,其中該形狀之深度係與該被動裝置之該預定電阻相關。
- 如申請專利範圍第1項所述之半導體裝置,其中該隔離結構係包含一淺溝槽隔離(STI)結構。
- 一種半導體裝置,包含: 一半導體基材;一隔離結構,形成於該基材中,用以隔離該基材之一第一區域及一第二區域;一第一電晶體及一第二電晶體,分別形成於該第一區域及該第二區域中,且該第一電晶體及該第二電晶體各自具有一高介電常數介電質及一金屬閘極;以及一多晶矽電阻器,形成於該隔離結構中,其中該多晶矽電阻器之一表面與該隔離結構之一表面位於同一平面上,其中該多晶矽電阻器之下表面高於該隔離結構之下表面。
- 如申請專利範圍第8項所述之半導體裝置,其中該第一及第二電晶體各自係為一PMOS裝置或一NMOS裝置。
- 如申請專利範圍第8項所述之半導體裝置,其中該高介電常數介電質係包含HfO、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或前述之組合。
- 如申請專利範圍第8項所述之半導體裝置,其中該金屬閘極係包含TiN、TaN、TaC、CoSi、ZrSi2 、MOSi2 、TaSi2 、NiSi2 、WN、TiAl、TiNAl、Al或前述之組合。
- 如申請專利範圍第8項所述之半導體裝置,其中該多晶矽電阻器係包含一摻雜之多晶矽。
- 一種半導體裝置,包含:一半導體基材;一隔離結構,形成於該基材中,用以隔離該基材之一主動區; 一電晶體,形成該主動區中,該電晶體具有一包含高介電常數介電層及一金屬層之閘極結構;以及一熔絲結構,形成於該隔離結構上,該熔絲結構具有一連接部分,其包含該高介電常數介電層及該金屬層,其中該連接部分之該金屬層上不具有多晶矽層。
- 如申請專利範圍第13項所述之半導體裝置,其中該電晶體係包含一PMOS裝置或一NMOS裝置。
- 如申請專利範圍第13項所述之半導體裝置,其中該隔離結構係包含一淺溝槽隔離結構。
- 如申請專利範圍第13項所述之半導體裝置,其中該金屬閘極係包含TiN、TaN、TaC、CoSi、ZrSi2 、WN、TiAl、TiNAl、Al或前述之組合。
- 如申請專利範圍第13項所述之半導體裝置,其中該電晶體之閘極結構之該金屬層上不具有該多晶矽層。
- 如申請專利範圍第13項所述之半導體裝置,其中該熔絲結構係包含一電子熔絲(eFuse)裝置。
- 如申請專利範圍第13項所述之半導體裝置,其中該電晶體之金屬層係與該熔絲結構之金屬層共平面。
- 如申請專利範圍第13項所述之半導體裝置,更包含一第二隔離結構,形成於該基材中;以及一多晶矽電阻器,置於該第二隔離結構中,以使該電阻器之頂部平面與該第二隔離結構之頂部平面共平面。
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-
2009
- 2009-04-30 US US12/432,926 patent/US20100059823A1/en not_active Abandoned
- 2009-08-14 TW TW098127357A patent/TWI433265B/zh active
- 2009-08-21 CN CN2009101673440A patent/CN101673738B/zh active Active
-
2011
- 2011-08-23 US US13/216,034 patent/US8334572B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20100059823A1 (en) | 2010-03-11 |
US8334572B2 (en) | 2012-12-18 |
CN101673738A (zh) | 2010-03-17 |
US20110303982A1 (en) | 2011-12-15 |
CN101673738B (zh) | 2012-09-26 |
TW201011860A (en) | 2010-03-16 |
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