FR3007198B1 - Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication - Google Patents
Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabricationInfo
- Publication number
- FR3007198B1 FR3007198B1 FR1355476A FR1355476A FR3007198B1 FR 3007198 B1 FR3007198 B1 FR 3007198B1 FR 1355476 A FR1355476 A FR 1355476A FR 1355476 A FR1355476 A FR 1355476A FR 3007198 B1 FR3007198 B1 FR 3007198B1
- Authority
- FR
- France
- Prior art keywords
- manufacturing
- component
- active region
- nmos transistor
- compression stresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000006835 compression Effects 0.000 title 1
- 238000007906 compression Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7846—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the lateral device isolation region, e.g. STI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1355476A FR3007198B1 (fr) | 2013-06-13 | 2013-06-13 | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication |
US14/300,663 US9263518B2 (en) | 2013-06-13 | 2014-06-10 | Component, for example NMOS transistor, with active region with relaxed compression stresses, and fabrication method |
US14/715,090 US20150255540A1 (en) | 2013-06-13 | 2015-05-18 | Component, for example nmos transistor, with active region with relaxed compression stresses, and fabrication method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1355476A FR3007198B1 (fr) | 2013-06-13 | 2013-06-13 | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3007198A1 FR3007198A1 (fr) | 2014-12-19 |
FR3007198B1 true FR3007198B1 (fr) | 2015-06-19 |
Family
ID=49713123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1355476A Expired - Fee Related FR3007198B1 (fr) | 2013-06-13 | 2013-06-13 | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication |
Country Status (2)
Country | Link |
---|---|
US (2) | US9263518B2 (fr) |
FR (1) | FR3007198B1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3007198B1 (fr) * | 2013-06-13 | 2015-06-19 | St Microelectronics Rousset | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication |
FR3018139B1 (fr) | 2014-02-28 | 2018-04-27 | Stmicroelectronics (Rousset) Sas | Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees |
FR3021457B1 (fr) * | 2014-05-21 | 2017-10-13 | St Microelectronics Rousset | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et condensateur de decouplage associe |
FR3025335B1 (fr) | 2014-08-29 | 2016-09-23 | Stmicroelectronics Rousset | Procede de fabrication d'un circuit integre rendant plus difficile une retro-conception du circuit integre et circuit integre correspondant |
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JPH0799771B2 (ja) | 1992-06-26 | 1995-10-25 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 皮膜中の応力を制御する方法 |
US5783846A (en) | 1995-09-22 | 1998-07-21 | Hughes Electronics Corporation | Digital circuit with transistor geometry and channel stops providing camouflage against reverse engineering |
US7067406B2 (en) * | 1997-03-31 | 2006-06-27 | Intel Corporation | Thermal conducting trench in a semiconductor structure and method for forming the same |
US6924552B2 (en) | 2002-10-21 | 2005-08-02 | Hrl Laboratories, Llc | Multilayered integrated circuit with extraneous conductive traces |
JP2004165378A (ja) | 2002-11-12 | 2004-06-10 | Sharp Corp | 半導体装置 |
US6979606B2 (en) | 2002-11-22 | 2005-12-27 | Hrl Laboratories, Llc | Use of silicon block process step to camouflage a false transistor |
JP4102334B2 (ja) * | 2004-06-16 | 2008-06-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP4994581B2 (ja) * | 2004-06-29 | 2012-08-08 | 富士通セミコンダクター株式会社 | 半導体装置 |
US20070090417A1 (en) * | 2005-10-26 | 2007-04-26 | Chiaki Kudo | Semiconductor device and method for fabricating the same |
JP2007142276A (ja) * | 2005-11-21 | 2007-06-07 | Toshiba Corp | 半導体装置及びその製造方法 |
US7888214B2 (en) | 2005-12-13 | 2011-02-15 | Globalfoundries Singapore Pte. Ltd. | Selective stress relaxation of contact etch stop layer through layout design |
JP4764160B2 (ja) | 2005-12-21 | 2011-08-31 | 株式会社東芝 | 半導体装置 |
US8354726B2 (en) | 2006-05-19 | 2013-01-15 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
JP2008028357A (ja) | 2006-07-24 | 2008-02-07 | Hynix Semiconductor Inc | 半導体素子及びその製造方法 |
US7436030B2 (en) | 2006-08-10 | 2008-10-14 | International Business Machines Corporation | Strained MOSFETs on separated silicon layers |
US7482215B2 (en) | 2006-08-30 | 2009-01-27 | International Business Machines Corporation | Self-aligned dual segment liner and method of manufacturing the same |
US7442601B2 (en) | 2006-09-18 | 2008-10-28 | Advanced Micro Devices, Inc. | Stress enhanced CMOS circuits and methods for their fabrication |
JP2008091536A (ja) | 2006-09-29 | 2008-04-17 | Toshiba Corp | 半導体装置及びその製造方法 |
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US8044464B2 (en) | 2007-09-21 | 2011-10-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP2009105279A (ja) | 2007-10-24 | 2009-05-14 | Fujitsu Microelectronics Ltd | 半導体装置の製造方法及び半導体装置 |
US7727834B2 (en) | 2008-02-14 | 2010-06-01 | Toshiba America Electronic Components, Inc. | Contact configuration and method in dual-stress liner semiconductor device |
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US8847319B2 (en) * | 2012-03-09 | 2014-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy structure for multiple gate dielectric interface and methods |
US8524556B1 (en) * | 2012-03-14 | 2013-09-03 | United Microelectronics Corp. | Resistor and manufacturing method thereof |
US8710593B2 (en) * | 2012-04-12 | 2014-04-29 | United Microelectronics Corp. | Resistor and manufacturing method thereof |
US20130277754A1 (en) * | 2012-04-20 | 2013-10-24 | Chia-Wen Liang | Semiconductor Integrated Structure |
JP2014038952A (ja) * | 2012-08-17 | 2014-02-27 | Fujitsu Semiconductor Ltd | 半導体装置の製造方法 |
US9012966B2 (en) * | 2012-11-21 | 2015-04-21 | Qualcomm Incorporated | Capacitor using middle of line (MOL) conductive layers |
FR3007198B1 (fr) * | 2013-06-13 | 2015-06-19 | St Microelectronics Rousset | Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et procede de fabrication |
US9728637B2 (en) * | 2013-11-14 | 2017-08-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Mechanism for forming semiconductor device with gate |
FR3018139B1 (fr) * | 2014-02-28 | 2018-04-27 | Stmicroelectronics (Rousset) Sas | Circuit integre a composants, par exemple transistors nmos, a regions actives a contraintes en compression relachees |
-
2013
- 2013-06-13 FR FR1355476A patent/FR3007198B1/fr not_active Expired - Fee Related
-
2014
- 2014-06-10 US US14/300,663 patent/US9263518B2/en active Active
-
2015
- 2015-05-18 US US14/715,090 patent/US20150255540A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US9263518B2 (en) | 2016-02-16 |
FR3007198A1 (fr) | 2014-12-19 |
US20140367784A1 (en) | 2014-12-18 |
US20150255540A1 (en) | 2015-09-10 |
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