TWI763644B - 半導體結構及相關之成形加工方法 - Google Patents

半導體結構及相關之成形加工方法

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TWI763644B
TWI763644B TW105140718A TW105140718A TWI763644B TW I763644 B TWI763644 B TW I763644B TW 105140718 A TW105140718 A TW 105140718A TW 105140718 A TW105140718 A TW 105140718A TW I763644 B TWI763644 B TW I763644B
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TW201740530A (zh
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朱振樑
龔達淵
霍克孝
陳奕寰
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台灣積體電路製造股份有限公司
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Abstract

係揭示一種半導體結構。該半導體結構包括：一基板，具一第一導電性；一第一區，具該第一導電性且形成在該基板中；一第二區，具該第一導電性且形成在該第一區中，其中該第二區具有高於該第一區的一較高摻雜密度；一源極區，具一第二導電性且形成在該第二區中；一汲極區，具該第二導電性且形成在該基板中；一接觸點區，具該第一導電性且形成在該第二區中並相鄰於該源極區；以及一阻劑保護氧化物(RPO)層，形成在該第二區的一頂部表面上。也揭示一種相關之成形加工方法。

Description

半導體結構及相關之成形加工方法
本揭露係關於一種半導體結構及相關之成形加工方法。
半導體積體電路(integrated circuit，IC)產業經歷了快速的成長。於IC材料及設計的技術進步已產生其中各代具有比上一代更小且更複雜之電路的數代IC。然而，這些進步增加了加工及製造IC的複雜性，且為了實現這些進步，需要在IC加工及製造上有相稱的發展。例如，由於由諸如金屬氧化物半導體場效電晶體(metal-oxide-semiconductor field effect transistor，MOSFET)之裝置所構成的半導體電路係適於用在高電壓應用，當為了晶片上系統技術(system-on-chip，SoC)，高電壓裝置係併入有低電壓裝置(如，邏輯裝置)時，會產生問題。
本揭露的一個實施例係提供一種半導體結構。該半導體結構包括：一基板，具一第一導電性；一第一區，具該第一導電性且形成在該基板中；一第二區，具該第一導電性且形成在該第一區中，其中該第二區具有高於該第一區的一較高摻雜密度；一源極區，具一第二導電性且形成在該第二區中；一汲極區，具該第二導電性且形成在該基板中；一接觸點區， 具該第一導電性且形成在該第二區中並相鄰於該源極區；以及一阻劑保護氧化物(RPO)層，形成在該第二區的一頂部表面上。
本揭露的一個實施例係提供一種半導體結構。該半導體結構包括：一基板，具一第一導電性；一閘極結構，形成在該基板上；一區，具該第一導電性且形成在該基板中；一源極區，具一第二導電性且形成在該區中；一汲極區，具該第二導電性且形成在該基板中；以及一接觸點區，具該第一導電性、且形成在該區中並相鄰於該源極區，其中該源極區以及該接觸點區不被在該區中的一隔離部件結構分開。
本揭露的一個實施例係提供一種用於成形加工一半導體結構的方法。該方法包括：提供一基板具一第一導電性；形成一第一區具該第一導電性且在該基板中；形成一第二區具該第一導電性且在該第一區中，其中該第二區具有高於該第一區的一較高摻雜密度；形成一閘極結構在該基板上；形成一源極區具一第二導電性且在該第二區中；形成一汲極區具該第二導電性且在該基板中；形成一接觸點區具該第一導電性且在該第二區中並相鄰於該源極區；以及形成一阻劑保護氧化物(RPO)層在該第二區的一頂部表面上。
100:高電壓半導體裝置
202:半導體基板
204:隔離部件結構
205、207、209:光阻層
206:N-井
208:第一P-井
210:閘極結構
210a:閘電極
210b:閘極介電層
211:第二P-井
214:經圖案化光阻層
230:側壁間隔件
232:源極區
234:汲極區
236:p型接觸點區
250、252:阻劑保護氧化物層
260:層間介電層
262:源極自對準金屬矽化物區
264:汲極自對準金屬矽化物區
266:P+自對準金屬矽化物區
268:多層互連件結構
272、273、274、275:溝渠
D:距離
本揭露之態樣將在與隨附圖式一同閱讀下列詳細說明下被最佳理解。請注意，根據業界標準作法，各種特徵未依比例繪製。事實上，為了使討論內容清楚，各種特徵的尺寸可刻意放大或縮小。
圖1至11係根據本揭露的例示性實施例繪示在各種成形加工階段之高電壓半導體裝置的圖。
下列揭露提供許多用於實施本揭露之不同特徵的不同實施例、或實例。為了簡化本揭露，於下描述組件及配置的具體實例。當然這些僅為實例而非意圖為限制性。例如，在下面說明中，形成第一特徵在第二特徵上方或上可包括其中第一及第二特徵係經形成為直接接觸之實施例，以及也可包括其中額外特徵可形成在第一與第二特徵之間而使得第一及第二特徵不可直接接觸之實施例。此外，本揭露可重複參考編號及/或字母於各種實例中。此重複係為了簡單與清楚之目的且其本身並不決定所討論的各種實施例及/或構形之間的關係。
再者，空間相關詞彙，諸如“在...之下”、“下面”、“下”、“上面”、“上”和類似詞彙，可為了使說明書便於描述如圖式繪示的一個元件或特徵與另一個(或多個)元件或特徵的相對關係而使用於本文中。除了圖式中所畫的方位外，這些空間相對詞彙也意圖用來涵蓋裝置在使用中或操作時的不同方位。該設備可以其他方式定向(旋轉90度或於其它方位)，據此在本文中所使用的這些空間相關說明符可以類似方式加以解釋。
儘管用以闡述本揭露寬廣範疇的數值範圍和參數係近似值，但是係盡可能精確地報告在具體實例中所提出的數值。然而，任何數值固有地含有某些必然自相應測試測量中發現的標準偏差所導致的誤差。亦，如本文中所使用，詞彙“約”一般意指在距給定值或範圍的10%、5%、1%、或0.5%內。替代地，詞彙“約”意指在本技術領域具有通常知識者所認知之平均值的可接受標準誤差內。除操作/工作實例外，或除非有另行具體指明，否則在所有情況下，所有的數值範圍、量、值、及百分比，諸如本文中所揭示之用於材料數量、時間持續期間、溫度、操作條件、量的比、及類似者的那些，應理解成以詞彙“約”所修飾者。據此，除非有相反指示， 否則本揭露及所附申請專利範圍中所提出之數值參數係可依所欲變化之近似值。最少，各數值參數應至少按照所報告之有效位數之數目且藉由施加習知四捨五入技術而解釋。本文中，範圍可表示成從一個端點至另一個端點或在兩個端點之間。除非有另行指明，否則本文揭露的所有範圍係包含端點。
圖1至11係根據本揭露的例示性實施例繪示在各種成形加工階段之高電壓半導體裝置100的圖。請注意，為了更佳理解所揭示之實施例，圖1至11被簡化。再者，高電壓半導體裝置100可用以作為具有各種P型金屬氧化物半導體(P-type metal-oxide semiconductor，PMOS)以及N型金屬氧化物半導體(N-type metal-oxide-semiconductor，NMOS)電晶體的晶片上系統裝置，該等電晶體被成形加工以在不同電壓位準操作。PMOS以及NMOS電晶體可提供低電壓功能，包括邏輯/記憶體裝置以及輸入/輸出裝置；以及高電壓功能，包括功率管理裝置。例如，提供低電壓功能之電晶體，其以標準CMOS技術可具有1.1伏特(V)的操作(或汲極)電壓、或其以在標準CMOS技術中的特殊(輸入/輸出)電晶體可具有1.8/2.5/3.3V的操作(或汲極)電壓。此外，提供中等/高電壓功能之電晶體可具有5V或更大(如，20至35V)的操作(或汲極)電壓。可理解到高電壓半導體裝置100也可包括電阻、電容器、電感、二極體、以及其它典型實施在積體電路中的合適微電子裝置。在本實施例中，高電壓半導體裝置100包括n型高電壓MOS(n-type high voltage MOS，NHVMOS)裝置。
參考圖1，係提供半導體基板202。基板202可包括半導體晶圓，諸如矽晶圓。替代地，基板202可包括其它元素型半導體諸如鍺。基板202也可包括化合物半導體，諸如碳化矽、鎵砷、砷化銦、或磷化銦。再者，基 板202可包括合金半導體，諸如矽鍺、碳化矽鍺、磷化鎵砷、以及磷化鎵銦。在一實施例中，基板202包括係上覆主體半導體的磊晶層(epi layer)。又者，基板202可包括絕緣體上半導體(semiconductor-on-insulator，SOI)結構。例如，基板202可包括藉由製程諸如植入氧之分離(separation by implanted oxygen，SIMOX)所形成之埋藏氧化物(buried oxide，BOX)層。在各種實施例中，基板202可包括埋層，諸如n型埋層(n-type buried layer，NBL)、p型埋層(p-type buried layer，PBL)、及/或包括埋藏氧化物(BOX)層之埋藏介電層。在本實施例中，繪示成n型HVMOS，基板202包括p型矽基板(p-基板)。為了形成互補式HVMOS，n型埋層，即深n-井(deep n-well，DNW)可深深地植入在p-基板202的p型HVMOS的主動區下。
隔離部件結構204，諸如包括隔離部件之淺溝渠隔離(shallow trench isolation，STI)或矽的局部氧化(local oxidation of silicon，LOCOS)可形成在基板202中以界定並電隔離各種主動區。作為一個實例，STI部件的形成可包括乾蝕刻溝渠在基板中，以及以絕緣體材料諸如氧化矽、氮化矽、或氧氮化矽填充溝渠。經填充溝渠可具有多層結構，諸如熱氧化物襯墊層，其係填充有氮化矽或氧化矽。在該實施例的進一步中，STI結構係可使用諸如下列之加工順序創建：生長墊氧化物；形成低壓力化學氣相沉積(low pressure chemical vapor deposition，LPCVD)氮化物層；使用光阻以及加以遮罩而圖案化STI開口；蝕刻溝渠在基板中；視需要地生長熱氧化物溝渠襯墊，以改善溝渠介面；以CVD氧化物填充溝渠；使用化學機械研磨(chemical mechanical polishing，CMP)加工，以回蝕及平坦化；以及使用氮化物剝除製程，以移除氮化矽。
在圖2中，N-井(N-well，NW)206係藉由本技術領域中已知的離子植入或擴散技術形成在P-基板202的各種區中。例如，在光微影製程或其它合適的製程中，N-井遮罩係用來圖案化光阻層205。例示性光微影製程可包括光阻塗佈、軟烘烤、遮罩對準、曝光、曝光後烘烤、顯影、以及硬烘烤之加工步驟。可實施利用n型摻雜物，諸如砷或磷的離子植入，以形成N-井(NW)206在基板202中。N-井206可被指稱為NHVMOS裝置的經延伸汲極。
在圖3中，第一P-井(1stPW)208係藉由本技術領域中已知的離子植入或擴散技術形成在P-基板202的各種區中。例如，第一P-井208可藉由植入p型摻雜材料，諸如硼、鎵、鋁、銦、其組合、或類似物而形成。第一P-井208可採與如上面為了N-井206所討論者相似之方式形成。P-井遮罩係用於圖案化保護N-井206的光阻層207。可實施利用p型摻雜物，諸如硼的離子植入，以形成第一P-井208在隨後將形成源極部件的區中。請注意，也可實施其它離子植入製程，以調整在基板202的其它主動區中之芯NMOS以及PMOS裝置的閥值電壓，如本技術領域已知。
在圖4中，第二P-井(2ndPW)211可藉由本技術領域中已知的離子植入或擴散技術形成在P-基板202的各種區中。例如，第二P-井211可藉由植入p型摻雜材料，諸如硼、鎵、鋁、銦、其組合、或類似物而形成。第二P-井211可採與如上面為了N-井206以及第一P-井208所討論者相似之方式形成。P-井遮罩係用於圖案化保護N-井206以及第一P-井208的光阻層209。可實施利用p型摻雜物，諸如硼的離子植入，以形成第二P-井211在隨後將形成源極部件的區中。請注意，也可實施其它離子植入製程，以調整在基板202的其它主動區中之芯NMOS以及PMOS裝置的閥值電壓，如本技術 領域已知。由於第二P-井211係嵌入在第一P-井208中，組合摻雜密度係高於藉由單一5V CMOS製程所形成的習用P-井。該等P-井的組合摻雜密度係在自約1017/cm3至約1018/cm3之範圍中。
在圖5中，閘極結構210係形成在半導體基板202上。在此實施例中，閘極結構210包括形成在基板202上的閘極介電層210b以及形成在閘極介電層210b上的閘電極210a。又，閘極結構210係上覆N-井206的一部分以及第一P-井208的一部分。閘極介電層210b可包括氧化矽層。替代地，閘極介電層210b可視需要包括高k介電材料、氧氮化矽、其它合適的材料、或其組合。高k介電材料可選自金屬氧化物、金屬氮化物、金屬矽酸鹽、過渡金屬氧化物、過渡金屬氮化物、過渡金屬矽酸鹽、金屬之氧氮化物、金屬鋁酸鹽、矽酸鋯、鋁酸鋯、氧化鉿、或其組合。閘極介電層210b可具有多層結構，諸如一層氧化矽以及另一層高k介電材料。閘極介電層210b係可使用化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)、熱氧化物、其他合適的製程、或其組合形成。
閘電極210a係可用以耦合至金屬互連件且可上覆閘極介電層210b放置。閘電極210a可包括經摻雜多晶矽(polysilicon)。替代地，閘電極210a可包括金屬，諸如Al、Cu、W、Ti、Ta、TiN、TaN、NiSi、CoSi、其它合適的導電材料、或其組合。閘電極210a可藉由CVD、PVD、鍍覆、及其它適當製程形成。閘電極210a可具有多層結構且可在使用不同製程之組合的多步驟製程中形成。
接著使用包括光微影圖案化以及蝕刻之製程來圖案化形成在基板202上的閘極介電層210b以及閘電極210a，以形成複數個閘極結構。用於圖 案化閘極介電層210b以及閘電極210a的例示性方法係於下面敘述。光阻層係藉由合適的製程諸如旋塗形成在多晶矽層上，以及接著藉由適當微影圖案化方法被圖案化以形成經圖案化光阻部件。光阻的圖案可接著以複數個加工步驟以及各種適當順序，而藉由乾蝕刻製程轉移到下方多晶矽層及閘極介電層，以形成閘電極以及閘極介電。其後，光阻層可被剝除。在另一實施例中，僅閘電極210a被圖案化。在又一實施例中，硬遮罩層可被使用並形成在多晶矽層上。經圖案化光阻層係形成在硬遮罩層上。光阻層的圖案被轉移到硬遮罩層且接著被轉移到多晶矽層，以形成閘電極210a。硬遮罩層可包括氮化矽、氧氮化矽、碳化矽、及/或其它合適的介電材料，且可使用諸如CVD或PVD之方法形成。
在圖6中，側壁間隔件230係形成在閘極結構210的二側上。側壁間隔件230可包括介電材料諸如氧化矽。替代地，側壁間隔件230可視需要包括氮化矽、碳化矽、氧氮化矽、或其組合。在一些實施例中，側壁間隔件230可具有多層結構。側壁間隔件230可藉由沉積以及蝕刻(非等向性蝕刻技術)形成，如本技術領域已知。
在圖7中，源極區232係形成在第二P-井211中，以及汲極區234係形成在N-井206中，其中源極區232以及汲極區234係n型(指稱為N+或重摻雜區)。n型源極區232以及n型汲極區234可置放在閘極結構210的相對側且藉此分隔開。在一些實施例中，源極區232可實質上自對準到該等側壁間隔件的一者。又，汲極區234可與該等側壁間隔件的另一者分開。據此，經圖案化光阻層214可保護延伸超出該等側壁間隔件的另一者的外邊緣之半導體基板202的一部分。在本實施例中，源極區232以及汲極區234 包括n型摻雜物諸如P或As。源極區232以及汲極區234可藉由諸如離子植入或擴散之方法形成。
在一些實施例中，源極區232可藉由植入濃度在約1019/cm3與約1020/cm3之間的n型摻雜物，諸如磷形成。再者，汲極區234可藉由植入濃度在約1019/cm3與約1020/cm3之間的n型摻雜物，諸如磷形成。可使用快速熱退火(rapid thermal annealing，RTA)製程以活化經植入摻雜物。在各種實施例中，源極區232以及汲極區234可具有藉由多製程植入所形成之不同摻雜概況。應注意，為了在基板的其它主動區中的PMOS裝置，可實施用以形成具p型之源極/汲極(指稱為P+或重摻雜區)的製程。據此，包括本實施例之NMOS裝置可被經圖案化光阻層214保護。
在圖8中，p型接觸點區236(指稱為P+或重摻雜區)係形成在第二P-井211中，其中源極區232以及汲極區234係n型。接觸點區236可以是P+接觸點環的部件。P+接觸點環可環繞汲極區234以及源極區232。因此，從剖面圖看，可能有另一P+區在汲極區234的右側。然而，為簡潔起見，在汲極區234的右側的P+區在此省略。接觸點區236係相鄰於源極區232形成且與源極區232分開距離D。
接觸點區236可藉由植入濃度在約1019/cm3與約1020/cm3之間的p型摻雜物，諸如硼形成。接觸點區236可透過第二P-井211以及第一P-井208耦合至半導體裝置100的p型本體(基板202)。為了消除本體效果，接觸點區236可直接透過源極接點耦合至源極區232。
在圖9中，阻劑保護氧化物(resist protective oxide，PRO)層250係形成在閘極結構210、側壁間隔件230、源極區232、汲極區234、接觸點區236、以及隔離部件結構204上方。RPO層250係作為介電膜，且在一實施 例中包括二氧化矽。可用於PRO層250的替代介電薄膜的實例係氮化矽、氧氮化矽、摻雜氧之氮化矽、及/或經氮化氧化物。在圖10中，圖9之RPO層250係部分地被蝕刻掉，留下在接觸點區236與源極區232之間的至少一部分上方的RPO層252。RPO層252可在下面所討論之後續自對準矽化物(矽化物)製程期間作用為矽化物封阻層。不使用矽化物製程的裝置區域被RPO層252覆蓋。RPO層252可藉由施加例如部分移除RPO層250的氧化物濕蝕刻而界定。此保護在RPO層252下面的區域免於矽化物之形成。
與本技術領域中的現有半導體裝置相比，本揭露消除在接觸點區236與源極區232之間的隔離部件結構諸如STI。以此方式，基板電流可在較短路徑中流動到接觸點區236而不需採取不然將在現有的結構中需要之較長繞道，藉此防止寄生雙極性接面電晶體(bipolar junction transistor，BJT)被觸發。結果，可獲得半導體裝置100之增加的崩潰電壓。如上所述，接觸點區236係相鄰於源極區232形成且與源極區232分開距離D。為了避免在第二P-井211中接觸點區236與源極區232之間的電導通，距離D經組態以大於閥值距離。
在圖10的例示性實施例中，RPO層252可替在接觸點區236與源極區232之間之第二P-井211的表面封阻後續矽化物製程。尤其，RPO層252完全覆蓋在接觸點區236與源極區232之間之第二P-井211的表面，以及RPO層252可進一步延伸至接觸點區236及/或源極區232一段特定距離。
可理解到半導體裝置100可經歷進一步CMOS加工，如本技術領域已知。例如，半導體裝置100可進一步包括形成各種接點以及金屬部件在基板202上。矽化物部件可藉由矽化形成，諸如自對準金屬矽化物，其中金屬材料係形成在Si結構旁邊，接著升高溫度以退火並造成下方矽與金屬之 間的反應以便形成矽化物，以及蝕刻掉未反應金屬。自對準金屬矽化物材料可自對準以被形成在各種部件，諸如源極區232、汲極區234及/或閘電極210a上，以減少接觸電阻。在該情況中，源極自對準金屬矽化物區262係形成在源極區232中，汲極自對準金屬矽化物區264形成在汲極區234中，以及P+自對準金屬矽化物區266係形成在接觸點區236中，如圖11所顯示，RPO層252不與自對準矽化物區262及自對準矽化物區266中之任一者對準。
亦，為了形成多層互連件，其係用以將在基板202中的各種p型以及n型摻雜區，諸如源極區232、汲極區234及/或閘電極210a耦合，複數個經圖案化介電層以及導電層係形成在基板202上。在一實施例中，層間介電(interlayer dielectric，ILD)層260以及多層互連件(multilayer interconnect，MLI)結構268係呈一組態形成，而使得ILD層260將各金屬層與其它金屬層分開並隔離。在該實施例的進一步中，MLI結構268包括形成在基板202上的接點、通路以及金屬線。在一個實例中，MLI結構268可包括被指稱為鋁互連件之導電材料，諸如鋁、鋁/矽/銅合金、鈦、氮化鈦、鎢、多晶矽、金屬矽化物、或其組合。鋁互連件可藉由包括物理氣相沉積(或濺鍍)、化學氣相沉積(CVD)、或其組合之製程形成。用以形成鋁互連件的其它製造技術可包括光微影加工以及蝕刻以圖案化用於垂直連接(通路及接點)以及水平連接(導線)之導電材料。替代地，銅多層互連件可用於形成金屬圖案。銅互連件結構可包括銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、鎢、多晶矽、金屬矽化物、或其組合。銅互連件可藉由包括CVD、濺鍍、鍍覆、或其它合適的製程之技術形成。
ILD層260包括氧化矽。替代地或額外地，ILD層260包括具有低介電常數，諸如小於約3.5的介電常數之材料。在一實施例中，介電層包括二氧化矽、氮化矽、氧氮化矽、聚醯亞胺、旋塗玻璃(spin-on glass，SOG)、氟化-經摻雜矽玻璃(fluoride-doped silicate glass，FSG)、摻雜碳之氧化矽、Black Diamond®(Applied Materials of Santa Clara,Calif.)、乾凝膠、氣凝膠、不定型氟化碳、聚對二甲苯、雙-苯并環丁烷(bis-benzocyclobutene，BCB)、SILK®(Dow Chemical,Midland,Mich.)、聚醯亞胺、及/或其它合適的材料。介電層可藉由包括旋塗、CVD、或其它合適的製程之技術形成。
MLI結構268以及ILD層260可在積體製程，諸如鑲嵌製程中形成。在鑲嵌製程中，金屬諸如銅係用來作為用於互連之導電材料。另一金屬或金屬合金可額外地或替代地使用於各種導電部件。據此，氧化矽、氟化矽酸鹽玻璃、或低介電常數(k)材料可使用於ILD層260。在鑲嵌製程期間，溝渠係形成在介電層中，且銅係填充在溝渠中。如圖11所顯示，填充有金屬諸如銅之溝渠272係形成在ILD層260中以將源極區232的源極自對準金屬矽化物區262互連至上MLI結構268；填充有金屬諸如銅之溝渠274係形成在ILD層260中以將汲極區234的汲極自對準金屬矽化物區264互連至上MLI結構268；填充有金屬諸如銅之溝渠273係形成在ILD層260中以將閘電極210a互連至上MLI結構268；以及填充有金屬諸如銅之溝渠271係形成在ILD層260中以將RPO層252互連至上MLI結構268以及進一步至源極區232。如圖11所顯示，RPO層252不與填充有金屬之溝渠272、273、274、275中之任一者對準。如本技術領域已知，可在之後實施化學機械研磨(CMP)技術已回蝕並平坦化基板表面。
在各種實施例中，本方法及結構係提供增進性能的高電壓裝置。與具有刻意放置在基板中於源極區與耦合到p型本體的P+區之間的STI部件之現有結構相比，藉由移除在接觸點區236與源極區232之間的隔離部件結構，以及實施RPO層252至少覆蓋在接觸點區236與源極區232之間之第二P-井211的表面，崩潰電壓以及操作能帶寬度可被顯著地增加而不會犧牲導電電阻。再者，本文中所揭示之高電壓裝置以及製作其之方法可採取用於形成用於邏輯裝置(低電壓)之NMOS及PMOS裝置(CMOS製程流程)的相同製程成形加工而不需要額外光遮罩及/或其他製程。因此，用於成形加工包括高電壓以及邏輯裝置二者的SoC的成本被保持在低。
所揭示結構及方法可具有各種實施例、修改及變化。高電壓裝置可以不限於n型MOS裝置且可擴展至除了所有摻雜種類可以相反以及具有DNW埋藏基板之外係具有相似結構及組態的p型MOS裝置。相應尺寸係根據為了所欲電晶體性能之設計修改。進一步實施例也可包括但不限於垂直擴散金屬氧化物半導體(vertical diffused metal-oxide-semiconductor，VDMOS)、其他種類的高功率MOS電晶體、鰭式結構場效電晶體(Fin structure field effect transistors，FinFET)、以及應變MOS結構。
本揭露的一個實施例係提供一種半導體結構。該半導體結構包括：一基板，具一第一導電性；一第一區，具該第一導電性且形成在該基板中；一第二區，具該第一導電性且形成在該第一區中，其中該第二區具有高於該第一區的一較高摻雜密度；一源極區，具一第二導電性且形成在該第二區中；一汲極區，具該第二導電性且形成在該基板中；一接觸點區，具該第一導電性且形成在該第二區中並相鄰於該源極區；以及一阻劑保護氧化物(RPO)層，形成在該第二區的一頂部表面上。
本揭露的一個實施例係提供一種半導體結構。該半導體結構包括：一基板，具一第一導電性；一閘極結構，形成在該基板上；一區，具該第一導電性且形成在該基板中；一源極區，具一第二導電性且形成在該區中；一汲極區，具該第二導電性且形成在該基板中；以及一接觸點區，具該第一導電性、且形成在該區中並相鄰於該源極區，其中該源極區以及該接觸點區不被在該區中的一隔離部件結構分開。
本揭露的一個實施例係提供一種用於成形加工一半導體結構的方法。該方法包括：提供一基板具一第一導電性；形成一第一區具該第一導電性且在該基板中；形成一第二區具該第一導電性且在該第一區中，其中該第二區具有高於該第一區的一較高摻雜密度；形成一閘極結構在該基板上；形成一源極區具一第二導電性且在該第二區中；形成一汲極區具該第二導電性且在該基板中；形成一接觸點區具該第一導電性且在該第二區中並相鄰於該源極區；以及形成一阻劑保護氧化物(RPO)層在該第二區的一頂部表面上。
前面列述了數個實施例的特徵以便本技術領域具有通常知識者可更佳地理解本揭露之態樣。本技術領域具有通常知識者應了解它們可輕易地使用本揭露作為用以設計或修改其他製程及結構之基礎以實現本文中所介紹實施例的相同目的及/或達成本文中所介紹實施例的相同優點。本技術領域具有通常知識者也應體認到此等均等構造不會悖離本揭露之精神及範疇，以及它們可在不悖離本揭露之精神及範疇下做出各種改變、取代、或替代。
100‧‧‧高電壓半導體裝置
202‧‧‧半導體基板
204‧‧‧隔離部件結構
206‧‧‧N-井
208‧‧‧第一P-井
210‧‧‧閘極結構
210a‧‧‧閘電極
210b‧‧‧閘極介電層
211‧‧‧第二P-井
230‧‧‧側壁間隔件
232‧‧‧源極區
234‧‧‧汲極區
236‧‧‧p型接觸點區
252‧‧‧阻劑保護氧化物層

Claims (10)

  1. 一種半導體結構，其包含：一基板，具一第一導電性；一第一區，具該第一導電性且形成在該基板中；一第二區，具該第一導電性且形成在該第一區中，其中該第二區具有高於該第一區的一摻雜密度；一閘極結構，形成於該基板上，自一俯視圖來看，該閘極結構與該第一區重疊且不與該第二區重疊；一源極區，具一第二導電性且形成在該第二區中；一第一自對準矽化物區，形成於該源極區中；一汲極區，具該第二導電性且形成在該基板中；一接觸點區，具該第一導電性且形成在該第二區中並相鄰於該源極區；一第二自對準矽化物區，其形成於該接觸點區中；一阻劑保護氧化物(RPO)層，形成在該第二區的一頂部表面上，其中該RPO層在該源極區與該接觸點區之間形成於該第二區之該頂部表面上；及一層間介電(ILD)層，形成於該基板上並覆蓋該RPO層，其中該ILD層包複數個填充有金屬之溝渠，且該RPO層不與該些填充有金屬之溝渠、該第一自對準矽化物區及該第二自對準矽化物區中之任一者對準。
  2. 如請求項1之半導體結構，其中該RPO層進一步延伸以覆蓋該源極區之一頂部表面之至少一部分。
  3. 如請求項1之半導體結構，其中該RPO層進一步延伸以覆蓋該接觸點區之一頂部表面之至少一部分。
  4. 一種半導體結構，其包括：一基板，其具有一第一導電性；一第一區，其具有該第一導電性、形成於該基板中；一第二區，其具有該第一導電性、形成於該第一區中，其中該第二區具有高於該第一區之一摻雜密度；一閘極結構，其形成於該基板上，自一俯視圖來看，該閘極結構與該第一區重疊且不與該第二區重疊；一源極區，其具有一第二導電性、形成於該第二區中；一第一自對準矽化物區，其形成於該源極區中；一汲極區，其具有該第二導電性、形成於該基板中；一接觸點區，其具有該第一導電性、形成於該第二區中且相鄰於該源極區；一第二自對準矽化物區，其形成於該接觸點區中；一介電膜，其在該源極區與該接觸點區之間形成於該第二區之一頂部表面上；及一層間介電(ILD)層，形成於該基板上並覆蓋該介電膜，其中該ILD層包複數個填充有金屬之溝渠； 其中該源極區與該接觸點區不被該第二區中之一隔離部件結構分離，且該介電膜不與該些填充有金屬之溝渠、該第一自對準矽化物區及該第二自對準矽化物區中之任一者對準。
  5. 如請求項4之半導體結構，其中側壁間隔件形成於該閘極結構之每一側上。
  6. 一種半導體結構，其包括：一基板，其具有一第一導電性；一第一區，其具有該第一導電性、形成於該基板中；一第二區，其具有該第一導電性、在一閘極結構之一第一側處形成於該第一區中，其中該第二區具有高於該第一區之一摻雜密度；該閘極結構，其形成於該基板上，自一俯視圖來看，該閘極結構與該第一區重疊且不與該第二區重疊；一源極區，其具有一第二導電性、形成於該第二區中；一第一自對準矽化物區，其形成於該源極區中；一接觸點區，其具有該第一導電性、形成於該第二區中且相鄰於該源極區；一第二自對準矽化物區，其形成於該接觸點區中；一汲極區，其具有該第二導電性、在該閘極結構之與該第一側相對之一第二側處形成於該基板中；及一介電膜，其在該源極區與該接觸點區之間形成於該第二區之一頂部表面上；及 一層間介電(ILD)層，形成於該基板上並覆蓋該介電膜，其中該ILD層包複數個填充有金屬之溝渠；其中該源極區係在該閘極結構與該接觸點區之間，且該接觸點區係與該源極區具有一分開距離，並且該介電膜不與該些填充有金屬之溝渠、該第一自對準矽化物區及該第二自對準矽化物區中之任一者對準。
  7. 一種用於製作一半導體結構之方法，其包括：提供具有一第一導電性之一基板；在該基板中形成具有該第一導電性之一第一區；在該第一區中形成具有該第一導電性之一第二區，其中該第二區具有高於該第一區之一摻雜密度；在該基板上形成一閘極結構；在該第二區中形成具有一第二導電性之一源極區；在該基板中形成具有該第二導電性之一汲極區；在該第二區中且相鄰於該源極區形成具有該第一導電性之一接觸點區；在該閘極結構之該形成之後於該基板上方形成一阻劑保護氧化物(RPO)層以至少覆蓋該第二區及該汲極區；蝕刻掉該RPO層之一部分，該RPO層之一未經蝕刻部分係在該源極區與該接觸點區之間位於該第二區之一頂部表面上，該基板於該RPO層之該未經蝕刻部分下方不包含隔離部件結構；及在該基板以及該RPO層之該未經蝕刻部分上方形成一層間介電(ILD)層，該ILD層係與該RPO層之該未經蝕刻部分、該源極區、該汲極區及該 接觸點區接觸。
  8. 如請求項7之方法，其中該蝕刻掉該RPO層之該部分包括：蝕刻掉除該第二區上方之該RPO層之該未經蝕刻部分之外的該RPO層。
  9. 一種用於製作一半導體結構之方法，其包括：形成具有一第一導電性之一基板；在該基板上形成一閘極結構；在該基板中形成具有該第一導電性之一區；在該區中形成具有一第二導電性之一源極區；在該基板中形成具有該第二導電性之一汲極區；在該區中且相鄰於該源極區形成具有該第一導電性之一接觸點區；在該閘極結構之該形成之後於該基板上方形成介電膜以至少覆蓋該區、該閘極結構及該汲極區；蝕刻掉該介電膜之一部分，該介電膜之一未經蝕刻部分係在該源極區與該接觸點區之間位於該區之頂部表面上；及在該基板以及該介電膜之該未經蝕刻部分上方形成一層間介電(ILD)層，該ILD層係與該介電膜之該未經蝕刻部分、該源極區、該汲極區及該接觸點區接觸；其中該源極區與該接觸點區不被該區中之一隔離部件結構分離。
  10. 一種用於製作一半導體結構之方法，其包括： 形成具有一第一導電性之一基板；在該基板上形成一閘極結構；在該閘極結構之一第一側處於該基板中形成具有該第一導電性之一區；在該區中形成具有一第二導電性之一源極區；在該區中且相鄰於該源極區形成具有該第一導電性之一接觸點區；在該閘極結構之與該第一側相對之一第二側處於該基板中形成具有該第二導電性之一汲極區；在該閘極結構之該形成之後於該基板上方形成一介電膜以至少覆蓋該區、該閘極結構及該汲極區；蝕刻掉該介電膜之一部分，該介電膜之一未經蝕刻部分係在該源極區與該接觸點區之間位於該區之一頂部表面上，該基板於該介電膜之該未經蝕刻部分下方不包含隔離部件結構；及在該基板以及該介電膜之該未經蝕刻部分上方形成一層間介電(ILD)層，該ILD層係與該介電膜之該未經蝕刻部分、該源極區、該汲極區及該接觸點區接觸；其中該源極區係在該閘極結構與該接觸點區之間，且該接觸點區係與該源極區具有一分開距離。
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