TWI430726B - 電路連接材料、使用其之薄膜狀電路連接材料、電路構件之連接構造及其製造方法 - Google Patents
電路連接材料、使用其之薄膜狀電路連接材料、電路構件之連接構造及其製造方法 Download PDFInfo
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- TWI430726B TWI430726B TW099102691A TW99102691A TWI430726B TW I430726 B TWI430726 B TW I430726B TW 099102691 A TW099102691 A TW 099102691A TW 99102691 A TW99102691 A TW 99102691A TW I430726 B TWI430726 B TW I430726B
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Classifications
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R11/00—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts
- H01R11/01—Individual connecting elements providing two or more spaced connecting locations for conductive members which are, or may be, thereby interconnected, e.g. end pieces for wires or cables supported by the wire or cable and having means for facilitating electrical connection to some other wire, terminal, or conductive member, blocks of binding posts characterised by the form or arrangement of the conductive interconnection between the connecting locations
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
- C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
- C09J9/00—Adhesives characterised by their physical nature or the effects produced, e.g. glue sticks
- C09J9/02—Electrically-conducting adhesives
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- H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
- H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
- H01B1/20—Conductive material dispersed in non-conductive organic material
- H01B1/22—Conductive material dispersed in non-conductive organic material the conductive material comprising metals or alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
- H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04026—Bonding areas specifically adapted for layer connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/29099—Material
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Description
本發明係關於電路連接材料、用此之薄膜狀電路連接材料、電路構件之連接構造及其製造方法。
從先前,已知將液晶顯示器、TCP(Tape Carrier Package:捲帶式封裝)與FPC(Flexible Printed Circuit:撓性印刷電路板)、TCP、或FPC與印刷電路板等之電路構件相互連接之電路構件之連接構造,如此電路構件相互連接,使用接著劑中分散導電粒子(例如,異向導電性接著劑)(參照例如,特開昭59-120436號公報、特開昭60-191228號公報、特開平1-251787號公報、特開平7-90237號公報、特開2001-189171號公報)。
另一方面,伴隨著近年之電子機器之小型化,進行薄膜化電路之高密度化,於電路構件之電路電極間之間隔或電路電極之寬幅呈非常的窄,難以確保電路電極間之高絕緣性。於此,於電路構件,為確保電路電極間之高絕緣性,認為需要於電路電極間設由有機絕緣性物質、二氧化矽、氮化矽所成之絕緣層。
圖7係,表示電路構件之連接構造之先前例之剖面圖。如圖7所示,電路構件之連接構造100係,具備:第1電路構件131、第2電路構件141,第1電路構件131與第2電路構件141係以電路連接構件150連接。第1電路構件131係以電路基板132、於電路基板132之一面132a上鄰接形成之電路
電極133及絕緣層134所構成,絕緣層134之一部分係呈跨上電路電極133之緣之情形。即,絕緣層134之一部分係,以電路基板132之一面132a作為基準較電路電極133為厚地形成。又,第2電路構件141係與第1電路構件131相同之構成,由電路基板142、於電路基板142之一面142a上鄰接形成之電路電極143及絕緣層144所構成,於絕緣層144之一部分係呈跨上電路電極143之緣之情形。另一方面,電路連接構件150係例如於苯并鳥糞胺樹脂粒子之表面形成鍍鎳層之導電粒子152分散於絕緣性物質151中者。於此,例如導電粒子之平均粒徑為5μm,而硬度(K值)為7490N/mm2
。
但是,前述先前之電路構件之連接構造100,具有以下所示課題。
即,於圖7所示電路構件之連接構造100,有相對之電路電極133、143間之接觸電阻變大的同時,電氣特性之長期可靠性不足之問題。
本發明係有鑑於上述情事進行者,以提供可充分降低相對電路電極間之連接阻抗,且優於電氣特性之長期可靠性之電路連接材料、使用該等之薄膜狀電路連接材料、電路構件之連接構造及其製造方法為目的。
本發明者們銳意研究解決上述課題之結果,發現產生上述課題之原因為特別是導線粒子之硬度。即,本發明者們,發現若導電粒子之硬度過大,則導電粒子被跨上電路
電極之緣之絕緣膜相互間夾住,導電粒子無法充分地與電路電極133、143之雙方接觸,其結果為相對之電路電極133、143間之連接阻抗將變大。然後,本發明者們以於電路構件絕緣膜之一部份跨上電路電極之緣之情形為前提,進一步累積銳意研究解決上述課題之結果,發現可藉由利用以硬化處理使40℃之儲存模量及25~100℃之平均熱膨脹係數成特定範圍,且使導電粒子之平均粒徑及硬度成特定範圍之電路連接材料,解決上述課題,達至本發明。
即,本發明係一種電路連接材料,其係連接第1電路構件及第2電路構件,該第1電路構件係第1電路電極及第1絕緣層於第1電路基板之主面上鄰接形成;,該第2電路構件係第2電路電極及第2絕緣層於第2電路基板之主面上鄰接形成;電路連接材料,其係連接於第1及第2電路構件之至少一方以絕緣層之至少一部份作為基準較電路電極厚地形成之第1電路構件及第2電路構件,其特徵在於:包含:接著劑組合物;及導電粒子,其平均粒徑為1μm以上、未達10μm,且硬度為1.961~6.865GPa,藉由硬化處理,呈於40℃之儲存模量為0.5~3GPa,25℃至100℃之平均熱膨脹係數為30~200ppm/℃。
根據該電路連接材料,使其介在於第1及第2電路構件之間,經由第1及第2電路構件加熱及加壓而硬化處理,則可充分減低相對之電路電極間之連接阻抗。又,可提供優於電氣特性之長期可靠性之構造。
如上述可充分減低電路電極間之連接阻抗可能係由於相
互連接電路構件之際,於絕緣層及與其相對之電路電極間,或於絕緣層間夾到導電粒子,導電粒子適度地扁平化,可使相對之電路電極間之距離充分地變小。又,優於相對之電路電極間之電氣特性之長期可靠性可能係藉由電路連接材料之硬化處理,牢固地連接第1之電路構件與第2之電路構件,充分減低第1電路電極與第2電路電極間之距離之經時變化。
又,本發明係一種薄膜狀電路連接材料,其特徵在於將上述電路連接材料形成為薄膜狀而成。
該薄膜狀電路連接材料為薄膜狀,容易使用。因此,根據該薄膜狀電路連接材料,於連接第1電路構件及第2電路構件之際,可容易地使其介在於該等之間,可容易地進行第1電路構件與第2電路構件之連接作業。
又,本發明係一種電路構件之連接構造,其具備:第1電路構件,其係於上第1電路電極及第1絕緣層第1電路基板之主面鄰接形成;第2電路構件,其係第2電路電極及第2絕緣層於第2電路基板之主面上鄰接形成;及電路連接構件,其係設於第1電路構件之主面及第2電路構件之主面之間,相互連接於第1及第2電路構件,於第1及第2電路構件之至少一方,絕緣層之至少一部份以電路基板之主面作為基準較電路電極厚地形成,其特徵在於:電路連接構件,包含:絕緣性物質;及導電性粒子,其平均粒徑為1μm以上、未達10μm,且硬度為1.961~6.865GPa,電路連接構件於40℃之儲存模量為0.5~3GPa,25℃至100℃之平均
熱膨脹係數為30~200ppm/℃,第1電路電極與第2電路電極,經由導電粒子電性連接。
根據該電路構件,由於第1電路電極與第2電路電極經由導電粒子電性連接,可充分減低第1及第2電極間之連接阻抗。又,成為優於電氣特性之長期可靠性者。
又,本發明係一種電路構件之連接構造之製造方法,該電路構件之連接構造具備:第1電路構件,其係第1電路電極及第1絕緣層於第1電路基板之主面上鄰接形成;第2電路構件,其係第2電路電極及第2絕緣層於第2電路基板之主面上鄰接形成;及電路連接構件,其係設於第1電路構件之主面及第2電路構件之主面之間,相互連接於第1及第2電路構件,於第1及第2電路構件之至少一方,絕緣層之至少一部份以電路基板之主面作為基準較電路電極厚地形成,其特徵在於:使上述薄膜狀電路連接材料介在於第1電路基板之主面與第2電路基板之主面之間,藉由經由第1及第2電路構件加熱及加壓電路連接材料而硬化處理,使第1電路電極與第2電路電極連接,將第1電路電極與第2電路電極經由前述導電粒子電性連接。
根據該電路構件連接構造之製造方法,使上述電路連接材料,介在於第1電路基板之主面與第2電路基板之主面之間,藉由經由第1及第2電路構件加熱及加壓電路連接材料而硬化處理,則可充分減低相對之電路電極間之連接阻抗,且可得優於電氣特性之長期可靠性之電路構件連接構造。
可得可充分減低相對之電路電極間之連接阻抗之電路構件連接構造,認為係因於相互連接電路構件之際,於絕緣層與對其相對之電路電極間,或相對之絕緣層間夾到導電粒子,導電粒子被適度地扁平化,可使相對之電路電極間之距離充分地變小。又,認為可得可充分減低相對之電路電極間之連接阻抗之電路構件連接構造,認為係因藉由電路材料之硬化處理,牢固地連接第1電接構件與第2連接構件,可充分減低第1電路電極與第2電路電極間之距離之經時變化。
以下,參照添附圖面說明本發明之適宜之實施形態。再者,同一要素使用相同符號,省略重複說明。
[電路構件之連接構造之實施形態]
首先,說明關於本發明之電路構件之連接構造。
圖1係關於本發明之電路構件之連接構造之一實施形態之概略剖面圖,圖2係圖1之部份放大剖面圖。如圖1及圖2所示,本實施形態之電路構件之連接構造200具備:相互相對之第1電路部30及第2電路部40於第1電路構件30與第2電路部40之間,設有連接該等之電路連接構件10。
第1電路構件30具備:電路基板(第1電路基板)31;電路電極(第1電路電極)32,其係形成於電路基板31之主面31a上;及絕緣層(第1絕緣層)33,其係形成於電路基板31之主面31a上。電路電極32與絕緣層33於電路基板31上相互連接形成。於此,絕緣層33之兩緣部33a呈跨上電路電極32
之緣之狀態。即,絕緣層33之兩緣部33a以電路基板31之主面31a作為基準較電路電極32之中央部為厚地形成。再者,此時絕緣層33之緣部33a之厚度係指由電路基板31之主面31a至絕緣層33之緣部33a之表面之距離。
另一方面,第2電路構件40具備:電路基板41;電路電極(第2電路電極)42,其係形成於電路基板41之主面41a上;及絕緣層(第2絕緣層)43,其係形成於電路基板41之主面41a上。再者,絕緣層43之兩緣部43a跨上電路電極42之緣,以電路基板41之主面41a作為基準較電路電極42為厚地形成之處與第1電路構件30之情形相同。
然後,於第1電路構件30與第2電路構件40相對之狀態,絕緣層33之緣部33a與絕緣層43之緣部43a之間之間隔成為較電路電極32與電路電極42之間之間隔為窄。
又於電路連接構件10,將其構成之材料之40℃之儲存模量為0.5~3GPa,25℃至100℃之平均熱膨脹係數為30~200ppm/℃。電路連接構件10含有:絕緣性物質11及導電粒子12,導電粒子12係平均粒徑為1μm以上、未達10μm,且硬度為1.961~6.865GPa。
於該電路構件之連接構造200,電路電極32、42經由導電粒子12電性連接。即,導電粒子12與電路電極32、42之雙方直接接觸。又,絕緣層33之緣部33a與絕緣層43之緣部43a間夾著導電粒子12之情形,導電粒子12係呈不妨礙電路電極32、42間之電性連接之扁平狀態。
於該電路構件之連接構造200,如上所述,相對之電路
電極32與電路電極42經由導電粒子12電性連接。因此,可充分地減低電路電極32、42間之連接阻抗。因此,可使電路電極32、42間電流之流動圓滑,可充分地發揮電路所擁有的功能。又,藉由電路連接構件10以如上所述構成,藉由緩和電路構件30或40與電路連接構件10之介面應力,可實現高的接著強度,且可長時間持續該狀態。即,充分地防止電路電極32、42間距離之經時變化,可充分提高電路電極32、42間之電氣特性之長期可靠性。
於此,詳細說明藉由於電路連接構件10中包含具有上述範圍內之硬度之導電粒子12,可充分減低電路電極32、42間之連接阻抗之理由。
首先,由於在電路連接構件10含有絕緣性物質11,為充分減低電路電極32、42間之連接阻抗,需要導電粒子12接觸電路電極32、42雙方,為使導電粒子12與電路電極32、42雙方接觸,未扁平化之導電粒子12之粒徑A、與絕緣層43之緣部43a相對之絕緣層33之緣部33a間之距離D1、及電路電極32之厚度與絕緣層33之緣部33a之厚度差D3、電路電極42之厚度與絕緣層43之緣部43a之厚度差D2需要滿足下式(1):D1+D2+D3≦A (1)
即,與絕緣層33之緣部33a相對之絕緣層43之緣部43a間之距離D1,需要滿足下式(2)之條件:D1≦A-D2-D3 (2)
於此,假設導電粒子具有超過6.865GPa程度之極高的
硬度則例如電路構件30之絕緣層33之緣部33a、與電路構件40之絕緣層43之緣部43a間夾著導電粒子之情形,導電粒子無法扁平化,絕緣層33之緣部33a與電路構件40之絕緣層43之緣部43a間之距離D1無法充分變小。其結果為D1無法滿足上述式(2)。即,電路電極32、42間之距離(D1+D2+D3)較導電粒子12之粒徑A為大。因此,電路電極32、42間之導電粒子呈無法與電路電極32、42雙方接觸,電路電極32、42間之連接阻抗將變大。
對此,若導電粒子12具有1.961~6.865GPa之硬度,則導電粒子12例如夾於絕緣層33之緣部33a、與電路構件40之絕緣層43之緣部43a間之情形會被扁平化。因此,D1成為滿足上述式(2)之條件,導電粒子12與電路電極32、42雙方接觸,可充分地減低電路電極32、42間之接觸阻抗。
再者,將構成上述電路連接構件10之材料之硬化後於40℃之儲存模量為未達0.5GPa之情形,接著強度呈不足,超過3GPa,則因內部應力增大接觸部之連接阻抗、或接著劑剝離。又,上述平均熱膨脹係數為未達30ppm/℃之情形則,接著強度不足,超過200ppm/℃則,因內部應力增大接觸部之連接阻抗、或接著劑剝離。
又,導電粒子12之硬度超過6.865GPa之情形,由於導電粒子12無法充分扁平化,減少導電粒子12與電路電極32、42之接觸面積連接阻抗上升,無法充分確保相對之電路電極32、42間之電性連接。另一方面,導電粒子12之硬度未達1.961GPa之情形,由於導電粒子12無法追隨電路
電極32、42於高溫高濕時之間隔變動,無法充分減低電路電極32、42間之連接阻抗。
再者,導電粒子12之硬度,當導電粒子12有鍍敷之情形,可由將鍍敷後之導電粒子使用微小壓縮試驗機(株式會社島津製作所製),使導電粒子由導電粒子之直徑變形10%時之施重P(MPa,Kgf),導電粒子之半徑r(mm)及壓縮之際之位移△(mm),以下式(3)求得:導電粒子硬度=(3/2)×P×△(-3/2)
×r(-1/2)
(3)
又導電粒子12之平均粒徑為未達1μm之情形,導電粒子太小無法接觸電路電極之雙方,無法充分確保電性連接,10μm以上之情形,則難以適用於具有高密度電路之電路構件。
其次,詳細說明導電粒子12之構成。於圖3(a)及(b)係表示導電粒子12之種種形態之剖面圖。如圖3(a)所示,導電粒子12係由有機高分子所成之核體12a,與形成於該核體12a上之金屬層12b所構成。於所關形態之導電粒子12,導電粒子12之硬度係大致由核體12a之硬度所支配。然後,核體12a之硬度係依存於材料之有機高分子之構造、交聯點之距離、交聯度等。因此,為使導電粒子12之硬度成為上述範圍,將後述之有機高分子之材料、構造等之要素適當選擇即可。
作為構成核體12a之有機高分子,丙烯酸樹脂、苯乙烯樹脂、苯并鳥糞胺樹脂、矽膠樹脂、聚丁乙烯樹脂等可舉。又,上述有機高分子亦可以為具有基於構成上述樹脂
之單體之反覆單位之中至少2種以上任意組合之構造之供聚合物,苯并鳥糞胺、丙烯酸酯、二烯丙基對苯二甲酸酯、四甲醯甲烷四丙烯酸酯、二乙烯基苯及苯乙烯所成之群所選之至少兩種以上共聚合所得者為佳,組合四甲醯甲烷四丙烯酸酯、二乙烯基苯及苯乙烯所得之共聚合物更佳。
其中,苯并鳥糞胺等,由於在分子中具有剛直的構造,其交聯點間距離亦短,於共聚合物中使如此之分子之含有率高,可得硬的導電粒子12。又使有機高分子之交聯度高,亦可得到硬的導電粒子12。
另一方面,於丙烯酸酯、二烯丙基對苯二甲酸酯等,由於交聯距離會變長,於共聚合物中使如此之分子之含有率高,可得柔軟的導電粒子12。又使有機高分子之交聯度低,亦可得到柔軟的導電粒子12。
因此,藉由適宜選擇構成核體12a之有機高分子,其交聯點間距離、交聯度,可得具有上述範圍之硬度之導電粒子12。
形成於核體12a上之金屬層12b係,例如銅、鎳、鎳合金、銀或銀合金所構成,金屬層12b,可使用無電電鍍法對核體12a鍍敷該等金屬形成。於此,鎳合金係根據於鍍敷浴中調配之添加劑有種種,習知者有鎳-磷、鎳-硼等合金。再者,對其他合金亦有同樣者。金屬層12b之厚度(鍍敷厚度),以50nm~170nm為佳,以50nm~150nm更佳。厚度未達50nm,則有產生鍍敷缺陷(剝離)等連接阻抗變
大的傾向,超過170nm,則於導電粒子12間產生凝結,有於鄰接電路電極間產生短路之傾向。
又導電粒子12係,如圖3(b)所示亦可於金屬層12b上進一步具備最外層12c。最外層12c係由金或鈀所構成,於該等金屬層12b上藉由取代鍍敷形成。藉由設該最外層12c,於電路電極32、42間,可達成進一步良好的連接阻抗。即可將連接阻抗充分減低。最外層12c之厚度為15~70nm為佳。厚度未達15nm之情形,有因鍍敷之缺陷難以得到充分的效果之傾向。另一方面,厚度超過70nm之情形,雖可達成良好的連接阻抗,惟由於所使用之鍍敷液量相乘地增加,有使製造成本邊非常高的傾向。又,設最外層12c之情形,金屬層12b之膜厚以70~170nm為佳。膜厚為未達70nm,則有產生鍍敷缺陷(剝離)等連接阻抗變大的傾向,超過170nm,則於導電粒子12間產生凝結,有於鄰接電路電極間產生短路之傾向。
又,於上述電路構件之連接構造200,上述第1電路構件30絕緣層33之緣部33a之厚度與電路電極32之中央部之厚度差D3為50~600nm,於第2電路構件40絕緣層43之緣部43a之厚度與電路電極42之厚度差D2為50~600nm之情形,相對之電路電極32、42間之連接阻抗之減低效果成特別顯著。
於絕緣層33、43,只要以絕緣材料構成即可並無特別限制,惟通常以有機絕緣性物質、二氧化矽或氮化矽所構成。又,電路電極32、42通常其全體係以金、銀、錫、鉑
族之金屬或ITO(銦-錫氧化物)所構成,惟電路電極32、42,亦可僅將其表面以上述物質構成。再者,電路基板31、41之材料並無特別限制,惟通常係有機絕緣性物質、玻璃或矽。
上述電路構件之連接構造200係於第1及第2電路構件30、40之電路電極32、42之面積分別為15000μm2
以下之情形仍可達成良好的連接阻抗。又,於相對之電路電極32、42間之平均導電粒子數為3個以上之情形,可達成更佳的連接阻抗。於此,所謂平均導電粒子數係指一個電路電極之導電粒子數之平均值。於此情形,可充分地減低相對之電路電極32、42間之連接阻抗。又,平均導電粒子數為6個以上之情形,可達成更佳的連接阻抗。此係因相對之電路電極32、42間之連接阻抗夠低。又於電路電極32、42間之平均導電粒子數為2個以下之情形則,連接阻抗過高,有電子電路無法正常運作之虞。
又於上述電路構件之連接構造200,電路連接構件10之玻璃轉移溫度以60~200℃為佳。玻璃轉移溫度未達60℃之情形,有於高溫下,接著強度降低,連接阻抗上升之傾向,超過200℃之情形,有於電路連接構件10產生龜裂,第1或第2之電路構件30、40之介面應力變大,接著強度降低之傾向。
作為第1電路構件30及第2電路構件40之具體例,半導體晶片、阻抗體晶片、電容晶片等晶片產品,印刷基板等可舉。於該等電路構件,通常設有多數(依照情形亦可為單
數)電路電極(電路端子)。又,作為連接構造之形態,亦有IC晶片與晶片搭載基板之連接構造,電氣電路相互連接之構造之形態。特別是電路構件為IC晶片之情形,於連接構造之製造步驟即使不形成凸塊,由於可充分確保電路電極間之電性連接,可省略於連接構造之製造步驟省略凸塊形成步驟,可大大地減低製造成本及製造時間。
[電路構件連接構造之製造方法]
其次,說明上述電路構件連接構造200之製造方法。
首先,準備上述之第1電路構件30與第2電路構件40。
另一方面,準備薄膜狀形成之電路連接材料(以下,稱為薄膜狀電路連接材料)50(參照圖4)。作為薄膜狀電路連接材料50,使用包含:接著劑組合物51,其對第1電路構件30及第2電路構件40硬化處理而硬化者;上述導電粒子12,且藉由硬化處理,呈於40℃之儲存模量為0.5~3GPa,25℃至100℃之平均熱膨脹係數為30~200ppm/℃者。薄膜狀電路連接材料50之厚度,以10~50μm為佳。再者,對薄膜狀電路連接材料50之細節將於後述。
其次,於第1電路構件30上,載置薄膜狀電路連接材料50。接著,將第2電路構件40,載置於薄膜狀電路連接材料50上。藉此,可於第1電路構件30與第2電路構件40之間介在薄膜狀電路連接材料50。此時,薄膜狀電路連接材料50為薄膜狀,容易使用。因此,根據該薄膜狀電路連接材料50,可於連接第1電路構件30與第2電路構件40之際,可使之容易地介在於該等間,可容易地進行第1電路構件30
與第2電路構件40之連接作業。
其次,經由第1電路構件30與第2電路構件40邊將薄膜狀電路連接材料50加熱向圖5之箭頭A及B方向加熱加壓施以硬化處理(參照圖5),於第1電路構件30與第2電路構件40之間形成電路連接構件10(參照圖1)。此時,藉由硬化處理,使電路連接構件10於40℃之儲存模量為0.5~3GPa,且25℃至100℃之平均熱膨脹係數為30~200ppm/℃。再者,硬化處理,可藉由一般的方法進行,其方法根據接著劑組合物適宜選擇。
如此地,使薄膜狀電路連接材料50介在於第1電路構件30與第2電路構件40之間,經由第1或第2電路構件30、40邊將薄膜狀電路連接材料50加熱加壓而硬化處理,則薄膜狀電路連接材料50中之導電粒子12即使夾於相對之絕緣層43之緣部43a與絕緣層33之緣部33a之間,由於被扁平化,可充分地使電路電極32與電路電極42之間之距離變小。
另一方面,由於對薄膜狀電路連接材料50進行加熱,電路電極32與電路電極42之間之距離充分小的狀態硬化接著劑組合物51,增大對第1電路構件30或第2電路構件40之接著強度。如此,第1電路構件30與第2電路構件40經由電路連接構件10連接。因此,可使導電粒子12與相對之電路電極32、42雙方接觸。即,電路電極32與電路電極42電性連接。因此,於所得電路構件之連接構造200,可使相對之電路電極32、42間之連接阻抗充分地小。
又,藉由使電路連接構件10,於40℃之儲存模量為
0.5~3GPa,25℃至100℃之平均熱膨脹係數為30~200ppm/℃,即使在高溫高濕環境下,仍可使因電路連接構件10之膨脹之電路電極32與電路電極42間之距離之經時變化充分小。即,即使在高溫高濕環境下,可充分減低相度電路電極32、42間之連接阻抗,有於電氣特性之長期可靠性。
再者,於上述實施形態,用薄膜狀電路連接材料50製造電路構件之連接構造,惟亦可取代薄膜狀電路連接材料50使用後述之電路連接材料。於此情形,將電路連接材料溶於溶劑,將該溶液,於第1電路構件30或第2電路構件40之任一塗布乾燥,可使之介在於第1及第2電路構件30、40間。
[電路連接材料]
其次,詳細說明上述薄膜狀電路連接材料50之構成。
薄膜狀電路連接材料50係將電路連接材料形成為薄膜狀而成者,電路連接材料含有:上述導電粒子12;及接著劑組合物51,以於40℃之儲存模量為0.5~3GPa(0.7~2GPa更佳),且25℃至100℃之平均熱膨脹係數為30~200ppm/℃之材料構成。
藉由硬化處理於40℃之儲存模量呈未達0.5GPa之電路連接材料則,接著強度不足,另一方面,藉由硬化處理於40℃之儲存模量超過3GPa之電路連接材料,則因內部應力增大於連接部之連接阻抗,或發生接著劑剝離。又,藉由熱處理上述平均熱膨脹係數呈未達30ppm/℃之電路連
接材料,則接著強度不足,另一方面,藉由硬化處理上述平均熱膨脹係數超過200ppm/℃之電路連接材料,則會有因內部應力增大連接部之連接阻抗,或接著劑剝離。
又電路連接材料,以玻璃轉移溫度呈60~200℃者為佳,呈60~1800℃者更佳。藉由硬化處理玻璃轉移溫度呈未達60℃之電路連接材料,則於電路構件之連接構造200,有於高溫之接著強度降低,發生連接阻抗上升之傾向,藉由硬化處理玻璃轉移溫度超過200℃之電路連接材料,則由於以高溫且長時間硬化,增大於電路連接構件10之內部應力,產生龜裂。又,由於電路構件30或40之介面應力變大,有因電路連接構件10之接著強度降低之傾向。
包含於電路連接材料中之接著劑組合物具有接著性,只要是藉由對第1及第2電路構件30、40之硬化處理而硬化。又,接著劑組合物係,藉由硬化處理於40℃之儲存模量呈0.5~3GPa(以0.7~2GPa更佳),且25℃至100℃之平均熱膨脹係數呈30~200ppm/℃者任何均可,惟作為如此之接著劑組合物,以含有環氧樹脂與環氧樹脂之潛在性硬化劑之組合物為佳。
作為上述環氧樹脂,可舉雙酚A型環氧樹脂、雙酚F型環氧樹脂、雙酚S型環氧樹脂、酚醛型環氧樹脂、甲氧基酚醛型環氧樹脂、雙酚A酚醛型環氧樹脂、雙酚F酚醛型環氧樹脂、脂環式環氧樹脂、縮水甘油脂型環氧樹脂、縮水甘油胺型環氧樹脂、乙內醯型環氧樹脂、異氰酸酯型環氧樹脂、脂肪族鏈狀環氧樹脂等。該等環氧樹脂亦可鹵化,
亦可為加氫者。又,該環氧樹脂亦可並用兩種以上。
上述環氧樹脂之潛在性硬化劑係只要可使環氧樹脂硬化者即可,作為如此之潛在性硬化劑,可舉陰離子聚合性觸媒型硬化劑、陽離子聚合性觸媒型硬化劑、聚加成型硬化劑等。該等可以單獨或兩種以上之混合物使用。該等之中,由優於速硬化性,可不考慮化學當量之處,以陰離子或陽離子聚合性觸媒型硬化劑為佳。
作為陰離子或陽離子聚合性觸媒型硬化劑,例如,三級胺類、咪唑類、肼系化合物、三氟化硼-胺錯合物、單核氫化物陽離子鹽(鋶鹽、銨鹽等)、胺亞醯胺、二胺馬來腈、密胺及其衍生物、多胺之鹽、氰胍等,亦可使用該等之變形物。作為聚加成型硬化劑,可舉多胺類、多硫醇、多酚、酸酐等。
作為陰離子聚合性觸媒型硬化劑,調合三級胺類或咪唑類之情形,環氧樹脂可以160℃~200℃左右的中溫加熱數10秒~數小時左右硬化。為此可使時間(活化期)較長而佳。
作為陽離子聚合性觸媒型硬化劑,以能線照射使環氧樹脂硬化之感光性單核氫化物陽離子鹽(主要使用芳香族重鹽、芳香族鋶鹽等)為佳。又,作為能線照射以外以加熱活化以硬化環氧樹脂者有脂肪族鋶鹽等。此種硬化劑,因具有速硬化性之特徵而佳。
將該等硬化劑以聚胺基甲酸酯系、聚脂系等高分子物質、或鎳、銅等金屬薄膜及矽酸鈣等無機物披覆微膠囊化
者,因可使時間延長而佳。
又,作為上述接著劑組合物,使用以含有自由基聚合性物質、藉由加熱產生游離自由基之硬化劑之組合物亦佳。
上述自由基聚合性物質係具有以自由基聚合之官能基之物質,作為該等自由基聚合性物質,可舉丙烯酸酯(含有對應之甲基丙烯酸酯。以下相同)化合物、馬來醯胺化合物、檸康亞醯胺樹脂、納迪克亞醯胺樹脂等。自由基聚合性物質可使用單體或寡聚物之狀態,又,亦可並用單體與寡聚物。
作為丙烯酸酯化合物之具體例,可舉甲基丙烯酸酯、乙基丙烯酸酯、異丙基丙烯酸酯、異丁基丙烯酸酯、乙二醇二丙烯酸酯、二乙二醇二丙烯酸酯、三羥甲基丙烷三丙烯酸酯、四甲醯甲烷四丙烯酸酯、2-羥基-1,3-二丙烯酸氧丙烷、2,2-二[4-(丙烯氧甲氧基)苯基]丙烷、二環戊烯基丙烯酸酯、三環癸烯基丙烯酸酯、三(丙烯醯氧乙基)異氰酸酯、胺基甲酸丙烯酸酯等。該等可以單獨或混合兩種以上使用。又,依需亦可使用對苯二酚、甲基醚對苯二酚類等之聚合禁止劑。又,由提高耐熱特性之觀點,丙烯酸酯化合物具有二環戊烯基、三環癸烯基及三氮雜環所成之群所選之至少一個取代基為佳。
馬來醯胺化合物係於分子中至少含有兩個以上馬來醯胺基,作為如此之馬來醯胺化合物,例如,1-甲基-2,4-二馬來醯胺苯、N,N'-m-苯二馬來醯胺、N,N'-p-苯二馬來醯胺N,N'-m-甲苯二馬來醯胺、N,N'-4,4-二苯二馬來醯胺、
N,N'-4,4-(3,3'-二甲基二苯)二馬來醯胺、N,N'-4,4-(3,3'-二甲基二苯甲烷)二馬來醯胺、N,N'-4,4-(3,3'-二乙基二苯甲烷)二馬來醯胺、N,N'-4,4-二苯甲烷二馬來醯胺、N,N'-4,4-二苯丙烷二馬來醯胺、N,N'-3,3'-二苯碸二馬來醯胺、N,N'-4,4-二苯醚二馬來醯胺、2,2-二(4-(4-馬來醯胺苯氧基)苯基)丙烷、2,2-二(3-s-丁基-4,8-(4-馬來醯胺苯氧基)苯基)丙烷、1,1-二(4-(4-馬來醯胺苯氧基)苯基)癸烷、4,4'-環亞己基-二(1-(4-馬來醯胺苯氧基)-2-環己基苯、2,2-二(4-(4-馬來醯胺苯氧基)苯基)六氟丙烷等。該等可以單獨或混合兩種以上使用。
上述檸康亞醯胺樹脂係於分子中聚合至少具有一個檸康亞醯胺化合物而成者。作為檸康亞醯胺化合物可舉,例如,苯檸康亞醯胺、1-甲基-2,4-二檸康亞醯胺苯、N,N'-m-苯二檸康亞醯胺、N,N'-p-苯二檸康亞醯胺、N,N'-4,4-二苯二檸康亞醯胺、N,N'-4,4-(3,3-二甲基二苯)二檸康亞醯胺、N,N'-4,4-(3,3-二甲基二苯甲烷)二檸康亞醯胺、N,N'-4,4-(3,3-二乙基二苯甲烷)二檸康亞醯胺、N,N'-4,4-二苯甲烷二檸康亞醯胺、N,N'-4,4-二苯丙烷二檸康亞醯胺、N,N'-4,4-二苯醚二檸康亞醯胺、N,N'-4,4-二苯碸二檸康亞醯胺、2,2-二(4-(4-檸康亞醯胺苯氧)苯)丙烷、2,2-二(3-s-丁基-3,4-(4-檸康亞醯胺苯氧)苯)丙烷、1,1-二(4-(4-檸康亞醯胺苯氧)苯)癸烷、4,4'-環亞己基-二(1-(4-檸康亞醯胺苯氧)苯氧)-2-環己基苯、2,2-二(4-(4-檸康亞醯胺苯氧)苯)六氟丙烷等,該等可以單獨或混合兩種以上使用。
上述納迪克亞醯胺樹脂係於分子中聚合至少具有一個納迪克亞醯胺化合物而成者。作為納迪克亞醯胺化合物可舉,例如,苯納迪克亞醯胺、1-甲基-2,4-二納迪克亞醯胺苯、N,N'-m-苯二納迪克亞醯胺、N,N'-p-苯二納迪克亞醯胺、N,N'-4,4-二苯二納迪克亞醯胺、N,N'-4,4-(3,3-二甲基二苯)二納迪克亞醯胺、N,N'-4,4-(3,3-二甲基二苯甲烷)二納迪克亞醯胺、N,N'-4,4-(3,3-二乙基二苯甲烷)二納迪克亞醯胺、N,N'-4,4-二苯甲烷二納迪克亞醯胺、N,N'-4,4-二苯丙烷二納迪克亞醯胺、N,N'-4,4-二苯醚二納迪克亞醯胺、N,N'-4,4-二苯碸二納迪克亞醯胺、2,2-二(4-(4-納迪克亞醯胺苯氧)苯)丙烷、2,2-二(3-s-丁基-3,4-(4-納迪克亞醯胺苯氧)苯)丙烷、1,1-二(4-(4-納迪克亞醯胺苯氧)苯)癸烷、4,4'-環亞己基-二(1-(4-納迪克亞醯胺苯氧)苯氧)-2-環己基苯、2,2-二(4-(4-納迪克亞醯胺苯氧)苯)六氟丙烷等,該等可以單獨或混合兩種以上使用。
於上述自由基聚合物質並用以下述化學式(I)所示具有磷酸酯構造之自由基聚合性物質,則可提升對電路電極(構成材料為金屬等無機物)表面之接著強度而佳:
[上述式中,n為表示1~3之整數]。
具有磷酸酯構造之自由基聚合性物質係無水磷酸與2-氫
氧乙基(甲基)丙烯酸酯反應而得。作為具有磷酸酯構造之自由基聚合性物質,具體地有,單(2-甲基丙烯醯氧乙基)酸磷酸、二(2-甲基丙烯醯氧乙基)酸磷酸等,該等可以單獨或混合兩種以上使用。
上述化學式(I)所示具有磷酸酯構造之自由基聚合性物質之調合量係對自由基聚合性物質與依需調合之薄膜形成材之和100重量部,以0.01~50重量部為佳,以0.5~5重量部更佳。
上述自由基聚合性物質,可與乙烯丙烯酸酯並用。於該情形,乙烯丙烯酸酯之調合量係對自由基聚合性物質與依需調合之薄膜形成材之和100重量部,以0.1~10重量部為佳,以0.5~5重量部更佳。
藉由加熱產生游離自由基之硬化劑係藉由加熱分解產生游離自由基之硬化劑,作為該等硬化劑,可舉過氧化化合物、重氮系化合物等。如此之硬化劑係以目的之連接溫度,連接時間、活化期等適宜選定。於該等之中,由於可提高反應性、活化期,以半衰期10小時之溫度為40℃以上,且,半衰期1分鐘之溫度為180℃以下之有機過氧化物為佳,以半衰期10小時之溫度為60℃以上,且,半衰期1分鐘之溫度為170℃以下之有機過氧化物更佳。
上述硬化劑之調合量係以連接時間為25秒以下之情形,為得充分的反應率,對自由基聚合性物質與依需調合之薄膜形成材之和100重量部,以2~10重量部為佳,以4~8重量部更佳。再者,連接時間未限定之情形之硬化劑之調合量
係對自由基聚合性物質與依需調合之薄膜形成材之和100重量部,以0.05~20重量部為佳,以0.1~10重量部更佳。
更具體地,作為藉由加熱產生游離自由基之硬化劑,可舉二醯基過氧化物、過氧碳酸酯、過氧酯、過氧縮酮、二烷基過氧化物、氫過氧化物、過氧矽烷等。又,由抑制電路電極32、42之腐蝕之觀點,硬化劑以含於硬化劑中之氯離子或有機酸之濃度以5000ppm以下為佳,進一步,於加熱分解後產生之有機酸越少者為佳。如此之硬化劑,具體地可由,過氧酯、二烷基過氧化物、過氧氫、過氧矽烷選定,由可得高反應性之過氧酯選定為佳。上述硬化劑,可適宜混合使用。
作為過氧酯,可舉枯基過氧新癸酯、1,1,3,3-四甲基丁基過氧新癸酯、1-環己基-1-甲基以基過氧新癸酯、t-己基過氧新癸酯、t-丁基過氧新戊酸酯,1,1,3,3-四甲丁基過氧-2-乙基己酯、2,5-二甲基-2,5-二(2-乙基己醯過氧)己烷、1-環己基-1-甲基乙基過氧-2-乙基己酯、t-己基過氧-2-乙基己酯、t-丁基過氧-2-乙基己酯、t-丁基過氧異丁酯、1,1-二(t-丁基過氧)環己烷、t-己基過氧異丙基單碳酸酯、t-丁基過氧-3,5,5-三甲基己酯、t-丁基過氧月桂酸酯、2,5-二甲基-2,5-二(m-甲苯醯過氧)己烷、t-丁基過氧異丙基單碳酸酯、t-丁基過氧-2-乙基己基單碳酸酯、t-己基過氧苯甲酯、t-丁基過氧乙酸酯等。
作為二烷基過氧化物,可舉α,α'-二(t-丁基過氧)二異丙苯、二枯基過氧化物、2,5-二甲基-2,5-二(二(t-丁基過氧)
己烷、t-丁基枯基過氧化物等。
作為氫過氧化物,可舉氫過氧化二異丙苯、氫過氧化枯烯等。
作為二醯基過氧化物,可舉異丁過氧化物、2,4-二氯甲苯醯過氧化物、3,5,5-酸甲基己醯過氧化物、辛醯過氧化物、月桂醯過氧化物、硬酯酸醯過氧化物、琥珀醯過氧化物、苯甲醯過氧甲苯、苯甲醯過氧化物等。
作為過氧碳酸酯、可舉二-n-丙基過氧二碳酸酯、二異丙基過氧二碳酸酯、二(4-t-丁基環己基)過氧二碳酸酯、二-2-乙氧基甲氧基過氧二碳酸酯、二(2-乙基己基過氧)二碳酸酯、二甲氧基丁基過氧二碳酸酯、二(3-甲基-3-甲氧基丁基過氧)二碳酸酯等。
作為過氧縮酮,可舉1,1-二(t-己基過氧)-3,3,5-三甲基環己烷、1,1-二(t-己基過氧)環己烷、1,1-二(t-丁基過氧)-3,3,5-三甲基環己烷、1,1-二(t-丁基過氧)環十二烷、2,2-二(t-丁基過氧)癸烷等。
作為過氧矽烷,可舉t-丁基三甲基過氧矽烷、二(t-丁基)二甲基過氧矽烷、t-丁基三乙烯基過氧矽烷、二(t-丁基)二乙烯基過氧矽烷、三(t-丁基)乙烯基過氧矽烷、t-丁基三丙烯基過氧矽烷、二(t-丁基)二丙烯基過氧矽烷、三(t-丁基)丙烯基過氧矽烷等。
該等硬化劑可單獨或混合兩種以上使用,亦可混合分解促進劑、抑制劑等使用。又,將該等硬化劑以聚胺基甲酸酯樹脂系、聚乙烯系高分子物質披覆微膠囊化者,可使時
間延長而佳。
於本實施形態之電路連接材料,依需要,可添加薄膜形成材。所謂薄膜形成材係將液狀物固形化將構成組合物成薄膜形狀之情形,使該薄膜之使用容易,付與不容易斷裂、破碎、黏著之機械特性等者,於通常之狀態(常壓狀態)可當作薄膜使用者。作為薄膜形成材,可舉苯氧樹脂、聚乙烯甲醛樹脂、聚苯乙烯樹脂、聚乙烯縮丁醛樹脂、聚酯樹脂、聚醯胺、二甲苯樹脂、聚胺基甲酸酯等。於該等之中,由於優於接著性、相溶性、耐熱性、機械強度以苯氧樹脂為佳。
苯氧樹脂係將二官能基苯酚類與表鹵醇以高分子量反應,或者藉由聚加成二官能基環氧樹脂與二官能基苯酚類所得之樹脂。苯氧樹脂係,可例如以二官能基苯酚類1莫耳與表鹵醇0.985~1.015莫耳及存在鹼金屬氫氧化物等之觸媒下,於非反應性溶劑中40~120℃之溫度反應而得。又,作為苯氧樹脂,由樹脂之機械特性或熱特性之點,特別是以二官能基環氧樹脂與二官能基苯酚類之調合當量比以環氧基/苯氫氧基=1/0.9~1/1.1,存在鹼金屬化合物、有機磷係化合物、環氧胺系化合物等觸媒下,以沸點為120℃以上之醯胺系、醚系、酮系、內酯系、醇系等有機溶劑中,反應固體量為50重量部以下之條件加熱為50~200℃聚加成反應而得者為佳。
作為上述二官能基環氧樹脂,可舉雙酚A型環氧樹脂、雙酚F型環氧樹脂、可舉AD型環氧樹脂、雙酚S型環氧樹
脂、二苯二縮水甘油醚、甲基取代二苯二縮水甘油醚等。上述二官能基苯酚類係具有兩個苯酚性氫氧基者,作為如此之二官能基苯酚類,例如對苯二酚類、雙酚A、雙酚F、雙酚AD、雙酚S、雙酚茀、甲基取代雙酚茀、二羥基苯、甲基取代二羥基苯等之雙酚類。苯氧樹脂,亦可係由自由基聚合性官能基、或環氧基、其他反應性化合物改質者。苯氧樹脂,可單獨使用,亦可混合兩種以上使用。
本實施形態之電路連接材料,亦可進一步含有由丙烯酸、丙烯酸酯及丙烯腈等所成之群所選之至少一種為單體成分之聚合物或共聚物。於此,由於優於應力緩和,併用含有縮水甘油醚基之縮水甘油醚基丙烯酸酯或縮水甘油基丙烯酸甲酯之共聚物系丙烯酸橡膠為佳。該等丙烯酸橡膠之分子量(重量平均分子量),由提高接著劑之凝集力之點以20萬以上為佳。
於本實施形態之電路連接材料,亦可進一步含有橡膠微粒子、充填劑、軟化劑、促進劑、老化防子劑、著色劑、難燃劑、觸變劑、耦合劑、苯酚樹脂、密胺樹脂、異氰酸酯類等。
橡膠粒子係粒子之平均粒徑為調合之導電粒子12之平均粒徑之2倍以下,且於室溫(25℃)之彈性模量為導電粒子12及接著劑組合物於室溫之彈性模量之1/2以下者即可,特別是,橡膠微粒子之材質為矽膠、丙烯乳劑、SBR、NBR、聚丁二烯橡膠之微粒子,適於單獨或混合兩種以上使用。三維交聯之該等橡膠微粒子,優於耐溶劑性、容易
分散於接著劑組合物中。
於電路連接材料含有充填劑之情形,由於可提升連接可靠性而佳。充填劑,只要是其最大徑未達導電粒子12之粒徑即可使用。充填劑之調合量係對接著劑組合物100體積部為5~60體積部為佳。調合量超過60體積部則,連接可靠性提升效果有飽和之傾向,另一方面,未達5體積部則有充填劑之添加效果不足之傾向。
作為上述耦合劑,以含有乙烯基、丙烯基、環氧基或異氰酸酯基之化合物,因可提升接著性而佳。
於上述電路連接材料,導電粒子12係對上述接著劑組合物100體積部添加0.1~30體積部為佳,其添加量根據用途區分使用。再者,為防止因過剩的導電粒子12之鄰接電路電極之短路等,以添加0.1~10體積部更佳。
再者,薄膜狀電路連接材料50,可於担體(PET(聚乙烯對苯二甲酸)薄膜等)上使用塗布裝置(無圖示)將上述電路連接材料塗布,以特定時間熱風乾燥製作。
本發明係並非限定於前述實施形態者。例如於上述實施形態,於第1電路構件及第2電路構件之任一,以電路基板之主面作為基準絕緣層之緣部較電路電極為厚地形成,惟只要如圖6所示,例如僅於第2電路構件40,使絕緣層43之緣部43a較電路電極42為厚地形成即可。於第1電路構件40,未形成絕緣層亦無所謂。
[實施例]
以下,將本發明之內容,使用實施例更具體地說明,惟
本發明並非限定於該等實施例者。
(導電粒子之製作)
四甲醯甲烷四丙烯酸酯、二乙烯苯及苯乙烯單體改變混合比,作為聚合起始劑使用苯基過氧化物懸濁聚合,分級所得聚合物,得到表1及表2所示具有平均粒徑及導電粒子之核體。
將所得各核體以無電鍍Ni或無電鍍Ag。鍍敷處理之際藉由鍍敷液之使用量、處理溫度及時間改變鍍敷厚度,得到目的之導電粒子No.1,3,5~7,10~12。又,進行Ni鍍敷之導電粒子進一步將Au取代鍍敷得到目的之導電粒子No.2,4,8,9,13,14。又,進行Ni鍍敷之導電粒子進一步將Pd取代鍍敷得到目的之導電粒子No.15~17。於所得導電粒子之鍍敷厚度亦一併示於表1及表2。再者,於表1及表2,導電粒子之硬度為,SI單位之GPa表示,惟為參考,將以Kgf/mm2
為單位之資料併記於括弧內。
(實施例1)
苯酚樹脂(聯合碳化物公司製、商品名PKHC、平均分子量45,000)50g,溶於甲苯/乙酸乙酯以重量比=50/50之混合
溶劑,作為固體量40重量%之溶液。
然後,於該溶液,以固體量重量比調合苯酚樹脂30g、雙酚A型環氧樹脂30g、作為環氧樹脂之潛在性硬化劑諾巴爵(Novacure,旭千葉株式會社製,商品名3941HPS)40g。進一步,於該溶液對接著劑組合物100體積部,調合分散導電粒子No.1,5體積部,調製電路連接材料含有液。再者,上述潛在性硬化劑諾巴爵3941HPS係,以咪唑改質體為核,將其表面以聚胺基甲酸酯披覆而成之平均粒徑5μm之微膠囊型硬化劑,分散於液狀雙酚F型環氧樹脂中之牡粒型硬化劑。
其次,將該電路連接材料含有液,使用塗布裝置塗布於單面表面處理之厚80μm之PET薄膜,以70℃熱風乾燥10分鐘得到厚度20μm之薄膜狀電路連接材料。
(實施例2)
取代於實施例1之導電粒子1,使用導電粒子2之外,與實施例1同樣地得到實施例2之薄膜狀電路連接材料。
(實施例3)
取代於實施例1之導電粒子1,使用導電粒子3之外,與實施例1同樣地得到實施例3之薄膜狀電路連接材料。
(實施例4)
取代於實施例1之導電粒子1,使用導電粒子4之外,與實施例1同樣地得到實施例4之薄膜狀電路連接材料。
(實施例5)
取代於實施例1之導電粒子1,將導電粒子1以2.5體積
部,導電粒子2以2.5體積部調合分散之外,與實施例1同樣地得到實施例5之薄膜狀電路連接材料。
(實施例6)
取代於實施例1之導電粒子1,使用導電粒子15之外,與實施例1同樣地得到實施例6之薄膜狀電路連接材料。
(比較例1)
取代於實施例1之導電粒子1,使用導電粒子6之外,與實施例1同樣地得到比較例1之薄膜狀電路連接材料。
(比較例2)
取代於實施例1之導電粒子1,使用導電粒子7之外,與實施例1同樣地得到比較例2之薄膜狀電路連接材料。
(比較例3)
取代於實施例1之導電粒子1,使用導電粒子8之外,與實施例1同樣地得到薄膜狀電路連接材料。
(比較例4)
取代於實施例1之導電粒子1,使用導電粒子9之外,與實施例1同樣地得到薄膜狀電路連接材料。
(比較例5)
取代於實施例1之導電粒子1,使用導電粒子10之外,與實施例1同樣地得到薄膜狀電路連接材料。
(比較例6)
取代於實施例1之導電粒子1,使用導電粒子11之外,與實施例1同樣地得到薄膜狀電路連接材料。
(比較例7)
取代於實施例1之導電粒子1,使用導電粒子13之外,與實施例1同樣地得到薄膜狀電路連接材料。
(比較例8)
取代於實施例1之導電粒子1,使用導電粒子14之外,與實施例1同樣地得到薄膜狀電路連接材料。
(比較例9)
取代於實施例1之導電粒子1,使用導電粒子16之外,與實施例1同樣地得到薄膜狀電路連接材料。
(比較例10)
取代於實施例1之導電粒子1,使用導電粒子17之外,與實施例1同樣地得到薄膜狀電路連接材料。
(連接阻抗評價試驗1)
(電路構件之製作)
於聚亞醯胺薄膜(厚度40μm)上,形成線寬9μm、間距30μm之銅電路(厚8μm)500條,作為第1電路構件製造撓性電路板(2層FPC)。又,作為第1電路構件,以聚亞醯胺、銅箔(厚18μm)、接著聚亞醯胺與銅箔之接著劑所成之3層構成,製作線寬7μm、間距30μm之撓性電路板(3層FPC)。
另一方面,於玻璃基板(厚1.1mm)上,線寬15μm、間距30μm之銦-錫氧化物(ITO)電路(厚度200nm)形成500條,於該玻璃基板上之ITO電路間蒸鍍氮化矽,形成由ITO電路中心600nm厚之絕緣膜,製作第2電路構件。
(電路構件之連接)
首先於第2電路構件上,貼上實施例1~6及比較例1~10之薄膜狀電路連接材料(寬1mm)之接著面後,以70℃、0.5MPa、加熱加壓5秒鐘,將薄膜狀電路連接材料假設連接於第2電路構件將PET薄膜剝離。其後,於第1電路構件之2層FPC,與第2電路構件之間,介在薄膜狀電路連接材料的方式配置2層FPC。然後,經由第1電路構件及第2電路構件將薄膜狀電路連接材料以180℃、3MPa加熱加壓10秒鐘。
如此得到電路構件之連接構造。又,第1電路構件之3層FPC與第2電路構件之連接一與上述同樣地進行,如此得到電路構件之連接構造。
(連接阻抗之測定)
針對上述電路構件之連接構造,分別於初期(連接後)、及於80℃、90%RH之高溫高濕槽中保持1000小時(高溫高濕處理)後,以多功能電表,測定電路之阻抗值。結果示於表3。再者,於表3,阻抗值以鄰接電路間之阻抗150點之平均值與三倍標準偏差之值之和(x+3σ)表示。
(存在於電路電極上之導電粒子之計數)
電路構件之連接後,以顯微鏡目視將存在於上述連接構造之各電路電極之導電粒子數。電路電極上之導電粒子數,以存在於151個電極上之導電粒子之平均表示。結果示於表3。
(電路連接構件之儲存模量及平均熱膨脹係數)
確認到實施例1~6及比較例1~10之薄膜狀電路連接材料之硬化處理後於40℃之儲存模量為0.5~3GPa之範圍,平
均熱膨脹係數為30~200ppm/℃之範圍。
根據示於表3之結果,確認到使用實施例1~6之薄膜狀電路連接材料之電路構件之連接構造,於第1電路構件為2層FPC、3層FPC之情形,於初期全部顯示良好的連接阻抗,高溫高濕處理後,亦幾乎沒有連接阻抗之上昇。
對此,使用比較例1~10之薄膜狀電路連接材料之電路構件之連接構造,於初期之連接阻抗高,特別是高溫高濕處
理後之連接阻抗之上升顯著。此為,於使用比較例1,3,5,7,9之薄膜狀電路連接材料之電路構件之連接構造,所使用之導電粒子之硬度過於柔軟無法追隨因高溫高濕之相對之電路電極間之距離之變動引起高溫高濕處理後之連接阻抗上升。
又,使用比較例2,4,6,8,10之薄膜狀電路連接材料之電路構件之連接構造,則由於所使用之導電粒子之硬度過高無法得到充分的導電粒子之扁平,初期之連接阻抗變高,又,由於無法追隨因高溫高濕之相對之電路電極間之距離之變動引起高溫高濕處理後之連接阻抗上升。
(連接阻抗評價試驗2)
(電路構件之製作)
於配置40個,凸塊面積100μm×100μm、間距200μm、高20μm之金凸塊之IC晶片,於凸塊間蒸鍍氮化矽,形成由凸塊中心600nm厚之絕緣膜,製作第1電路構件。
又於玻璃基板(厚1.1mm)上,以銦-錫氧化物(ITO)形成厚度200nm之電路。然後,於該玻璃基板上之ITO電路間蒸鍍氮化矽,形成由ITO電路中心600nm厚之絕緣膜,製作第2電路構件。
(電路構件之連接)
作為第1電路構件,取代2層FPC或3層FPC使用上述IC晶片之外,與評價試驗1之情形同樣地連接第1電路構件與第2電路構件,得到電路構件之連接構造。
(連接阻抗之測定)
針對上述電路構件之連接構造,分別於初期(連接後)、及高溫高濕處理後,以與評價試驗1同樣的方法測定連接阻抗。結果示於表4。再者,於表4,阻抗值以鄰接電路間之阻抗150點之平均值與三倍標準偏差之值之和(x+3σ)表示。
(存在於電路電極上之導電粒子之計數)
電路構件之連接後,將存在於上述連接構造之各電路電極之導電粒子數以與評價試驗1同樣的方法計數。電路電極上之導電粒子數,以存在於40個電極上之導電粒子之平均表示。結果是於表4。
使用實施例1~6之薄膜狀電路連接材料之電路構件之連接構造係,取代評價試驗1之2層FPC或3層FPC,使用上述IC晶片作為第1電路構件使用之情形,亦確認到於初期全部顯示良好的連接阻抗,高溫高濕處理後,亦幾乎沒有連接阻抗之上昇。
對此,使用比較例1~10之薄膜狀電路連接材料之電路構件之連接構造,與評價試驗1之情形同樣地,於初期之連接阻抗高,特別是高溫高濕處理後之連接阻抗之上升顯著。
如以上所說明,根據本發明之電路連接材料、電路構件之連接構造及其製造方法,於相互連接相對之電路構造之情形,可充分減低相對電路電極間之連接阻抗。
又,根據本發明之薄膜狀電路連接材料,加上上述效果,於連接第1電路構件與第2電路構件之際,可使之容易地介在於該等之間,可容易地進行第1電路構件與第2電路構件之連接作業。
10‧‧‧電路連接構件
11‧‧‧絕緣性物質
12‧‧‧導電粒子
12a‧‧‧核體
12b‧‧‧金屬層
12c‧‧‧最外層
30‧‧‧電路構件
31‧‧‧基板
31a‧‧‧基板31之面
32‧‧‧電路電極
33‧‧‧絕緣層
33a‧‧‧絕緣層33之緣部
40‧‧‧電路構件
41‧‧‧基板
41a‧‧‧基板41之面
42‧‧‧電路電極
43‧‧‧絕緣層
43a‧‧‧絕緣層43之緣部
50‧‧‧薄膜狀電路連接材料
51‧‧‧接著劑組合物
100‧‧‧電路構件之連接構造
131‧‧‧第1電路構件
132‧‧‧電路基板
132a‧‧‧電路基板132之一面
133‧‧‧電路電極
134‧‧‧絕緣層
141‧‧‧第2電路構件
142‧‧‧電路基板
142a‧‧‧電路基板142之一面
143‧‧‧電路電極
144‧‧‧絕緣層
150‧‧‧電路連接構件
151‧‧‧絕緣性物質
152‧‧‧導電粒子
200‧‧‧電路構件之連接構造
300‧‧‧電路構件之連接構造
D1‧‧‧距離
D2‧‧‧厚度差
D3‧‧‧厚度差
圖1表示關於本發明之電路構件之連接構造之一實施形態之概略剖面圖。
圖2係圖1之部份放大剖面圖。
圖3(a)(b)係表示圖1之導電粒子之種種形態之剖面圖。
圖4係表示關於本發明之薄膜狀電路連接材料一實施形態之剖面圖。
圖5係表示關於本發明之電路構件連接構造之製造方法之一步驟之圖。
圖6係表示關於本發明之電路構件之連接構造之其他實施形態之剖面圖。
圖7係先前之電路構件之連接構造之一例之剖面圖。
10‧‧‧電路連接構件
11‧‧‧絕緣性物質
12‧‧‧導電粒子
12a‧‧‧核體
12b‧‧‧金屬層
12c‧‧‧最外層
30‧‧‧電路構件
31‧‧‧基板
31a‧‧‧基板31之面
32‧‧‧電路電極
33‧‧‧絕緣層
33a‧‧‧絕緣層33之緣部
41‧‧‧基板
41a‧‧‧基板41之面
40‧‧‧電路構件
42‧‧‧電路電極
43‧‧‧絕緣層
43a‧‧‧絕緣層43之緣部
200‧‧‧電路構件之連接構造
Claims (19)
- 一種電路連接材料,其係用於連接第1電路構件及第2電路構件,該第1電路構件係第1電路電極及第1絕緣層於第1電路基板之主面上鄰接形成;該第2電路構件係第2電路電極及第2絕緣層於第2電路基板之主面上鄰接形成;於前述第1及第2電路構件之至少一方,前述絕緣層之至少一部份以前述主面作為基準較前述電路電極為厚地形成,且前述絕緣層之至少一部份跨上前述電路電極之緣者;且含有接著劑組合物;及導電粒子,其平均粒徑為1μm以上、未達10μm,且硬度為4.441~6.865GPa;藉由硬化處理,於40℃之儲存彈性模數成為0.5~3GPa,硬化處理後之25℃至100℃之平均熱膨脹係數成為30~200ppm/℃。
- 如申請專利範圍第1項之電路連接材料,其中前述導電粒子具備:核體,其由有機高分子所組成;及金屬層,其係形成於該核體上,由銅、鎳、鎳合金、銀或銀合金所組成;前述金屬層之厚度為50~170nm。
- 如申請專利範圍第1項之電路連接材料,其中前述導電粒子具備:最外層,其由金或鈀所組成;前述最外層之厚度為15~70nm。
- 如申請專利範圍第1項之電路連接材料,其中前述接著劑組合物包含:環氧樹脂;及前述環氧樹脂之潛在性硬化劑。
- 如申請專利範圍第1項之電路連接材料,其中前述接著劑組合物包含:自由基聚合性物質;及藉由加熱產生游離自由基之硬化劑。
- 如申請專利範圍第1項之電路連接材料,其中藉由硬化處理,玻璃轉移溫度成為60~200℃。
- 如申請專利範圍第1項之電路連接材料,其中進一步含有薄膜形成材料。
- 如申請專利範圍第7項之電路連接材料,其中前述薄膜形成材料為苯氧基樹脂。
- 一種薄膜狀電路連接材料,其特徵在於:將申請專利範圍第1項之電路連接材料形成為薄膜狀而成。
- 一種電路構件之連接構造,其具備:第1電路構件,其係第1電路電極及前述第1絕緣層於第1電路基板之主面上鄰接形成;第2電路構件,其係第2電路電極及第2絕緣層於第2電路基板之主面上鄰接形成;及電路連接構件,其係設於前述第1電路構件之主面與前述第2電路構件之主面之間,將前述第1及第2電路構件彼此連接;於前述第1及第2電路構件之至少一方,前述絕緣層之至少一部份以前述電路基板之主面作為基準較前述電路電極為厚地形成,且前述絕緣層之至少一部份跨上前述電路電極之緣;且前述電路連接構件包含:絕緣性物質;及導電粒子, 其平均粒徑為1μm以上、未達10μm,且硬度為4.441~6.865GPa;前述電路連接構件於40℃之儲存彈性模數為0.5~3GPa且25℃至100℃之平均熱膨脹係數為30~200ppm/℃;前述第1電路電極與前述第2電路電極經由前述導電粒子電性連接。
- 如申請專利範圍第10項之電路構件之連接構造,其中前述導電粒子具備:核體,其由有機高分子所組成;及金屬層,其係形成於該核體上,由銅、鎳、鎳合金、銀或銀合金所組成;前述金屬層之厚度為50~170nm。
- 如申請專利範圍第10項之電路構件之連接構造,其中前述導電粒子具備:最外層,其由金或鈀所組成;前述最外層之厚度為15~70nm。
- 如申請專利範圍第10項之電路構件之連接構造,其中於前述絕緣層之至少一部份以前述電路基板之主面作為基準較前述電路電極為厚地形成之電路構件,前述絕緣層之至少一部份之厚度與前述電路電極之厚度之差為50~600nm。
- 如申請專利範圍第10項之電路構件之連接構造,其中前述電路連接構件之玻璃轉移溫度為60~200℃。
- 如申請專利範圍第10項之電路構件之連接構造,其中前述絕緣層係由有機絕緣性物質、二氧化矽及氮化矽之任一所構成。
- 如申請專利範圍第10項之電路構件之連接構造,其中於 前述第1及第2電路構件之至少一方,前述電路電極之表面積為15000μm2 以下,且於前述第1電路電極與前述第2電路電極間之平均導電粒子數為3個以上。
- 如申請專利範圍第10項之電路構件之連接構造,其中於前述第1及第2電路構件之至少一方,前述電路電極具有表面層,其係由金、銀、錫、鉑族之金屬或銦錫氧化物所構成。
- 如申請專利範圍第10項之電路構件之連接構造,其中於前述第1及第2電路構件之至少一方,前述電路基板係由有機絕緣性物質、玻璃或矽所構成。
- 一種電路構件之連接構造之製造方法,該電路構件之連接構造具備:第1電路構件,其係第1電路電極及前述第1絕緣層於第1電路基板之主面上鄰接形成;第2電路構件,其係第2電路電極及第2絕緣層於第2電路基板之主面上鄰接形成;及電路連接構件,其係設於前述第1電路構件之主面及前述第2電路構件之主面之間,連接前述第1及第2電路構件彼此;於前述第1及第2電路構件之至少一方,前述絕緣層之至少一部份以前述電路基板之主面作為基準較前述電路電極為厚地形成,且前述絕緣層之至少一部份跨上前述電路電極之緣;該方法為:使申請專利範圍第9項之薄膜狀電路連接材料介於前 述第1電路基板之主面與前述第2電路基板之主面之間;藉由經由前述第1及第2電路構件將前述電路連接材料加熱及加壓而硬化處理,連接前述第1電路構件與前述第2電路構件,使前述第1電路電極與前述第2電路電極經由前述導電粒子電性連接。
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CN1723590A (zh) | 2006-01-18 |
KR20050074641A (ko) | 2005-07-18 |
EP2182585B1 (en) | 2011-08-10 |
EP1628363A1 (en) | 2006-02-22 |
MY137507A (en) | 2009-02-27 |
EP1628363A4 (en) | 2006-03-15 |
WO2005002002A1 (ja) | 2005-01-06 |
CN100380741C (zh) | 2008-04-09 |
TW201021649A (en) | 2010-06-01 |
EP2182585A1 (en) | 2010-05-05 |
US20060100314A1 (en) | 2006-05-11 |
CN101232128A (zh) | 2008-07-30 |
DE602004024672D1 (de) | 2010-01-28 |
TWI455151B (zh) | 2014-10-01 |
KR100732017B1 (ko) | 2007-06-25 |
CN101232128B (zh) | 2010-12-08 |
EP2282374A1 (en) | 2011-02-09 |
TWI396487B (zh) | 2013-05-11 |
TW200505312A (en) | 2005-02-01 |
JPWO2005002002A1 (ja) | 2006-08-10 |
US8501045B2 (en) | 2013-08-06 |
TW201131584A (en) | 2011-09-16 |
US8043709B2 (en) | 2011-10-25 |
US20090321116A1 (en) | 2009-12-31 |
JP4293187B2 (ja) | 2009-07-08 |
US20110247870A1 (en) | 2011-10-13 |
US8202622B2 (en) | 2012-06-19 |
US20110247757A1 (en) | 2011-10-13 |
EP1628363B1 (en) | 2009-12-16 |
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