TWI411052B - 撓性板上覆晶應用之可撓性電路基板 - Google Patents

撓性板上覆晶應用之可撓性電路基板 Download PDF

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TWI411052B
TWI411052B TW095142149A TW95142149A TWI411052B TW I411052 B TWI411052 B TW I411052B TW 095142149 A TW095142149 A TW 095142149A TW 95142149 A TW95142149 A TW 95142149A TW I411052 B TWI411052 B TW I411052B
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circuit substrate
mounting pad
dielectric layer
circuit
flip chip
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Charles Cohn
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Agere Systems Inc
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01ELECTRIC ELEMENTS
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H05K2201/09818Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
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    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
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    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
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Description

撓性板上覆晶應用之可撓性電路基板
本發明係關於積體電路晶片之電路基板,本發明之具體實施例提供用於撓性板上覆晶應用之改良式可撓性電路基板。
直接晶片附著(DCA)指一種半導體組裝技術,其中一積體電路晶片係直接安裝於其之最後電路基板上並電連接至其之最後電路基板,而不用經歷傳統組裝與封裝。有利地,在DCA中消除習知的裝置封裝可簡化製程並減少該積體電路晶片於該最後電路基板上會佔據的空間。由於該積體電路晶片與該電路基板間之較短互連路徑,而亦會改善效能。
覆晶附著至一可撓性電路基板(撓性板上覆晶(FCoF))係DCA之一種變化,其係逐漸發展成電子裝置之部分種類之構造的主流程序。一覆晶包含一積體電路晶片,其具有附著至該晶片之焊墊的多個導電焊塊。於FCoF中。此等焊塊係直接附著至一可撓性電路基板。該可撓性電路基板(依次)包含銅電線路,其可用以使該覆晶以一種類似於習知剛性印刷電路板之方式與其他電子組件連接在一起。可撓性電路基板係延伸地用於其中需要其之可折彎與彎曲成可撓性形狀之獨特能力的應用。可撓性電路基板例如係用於筆記型電腦、硬碟機、PCMCIA(個人電腦記憶卡國際協會)連接器、攜行電腦塢、指向裝置、光碟唱機與行動電話。
將一覆晶安裝於一可撓性電路基板上涉及將該覆晶上之焊塊附著至併入該可撓性電路基板之銅電線路。於一可撓性電路基板中,此等銅電線路一般係以聚合物覆蓋層之部分種類(通常稱為「焊料遮罩」)來加以覆蓋。據此,於該聚合物覆蓋層中產生開口以產生附著區,進而使該覆晶上之焊塊能夠接近下方的銅電線路。隨後運用一高溫回焊程序以使該等焊塊永久附著至該等銅電線路。接著,一非導電性側填滿材料係分配至該覆晶與該可撓性電路基板之間的區域中。該側填滿材料會保護該等焊塊免受濕氣與其他環境危害物的侵害;對該裝配件提供額外機械強度;以及補償該覆晶與該可撓性電路基板間的熱膨脹差異。
由於該側填滿材料具有許多功能,該側填滿材料最好能完全且均勻地填充該覆晶與該可撓性電路基板間的區域。此需要精確地控制覆晶與可撓性電路基板間的距離(「平衡距離」)。不幸地,在習知的FCoF應用中,此平衡距離係受許多因素所影響,包括該可撓性電路基板上之附著區的尺寸、該聚合物覆蓋層(即,焊料遮罩)的厚度、焊塊合金之延展性與該等焊塊之回焊剖面。例如,若在該可撓性電路基板上曝露一大的附著區,則座落於該區之焊塊在該高溫回焊程序期間將具有沿該等曝露之銅電線路而蜷縮的趨勢。此使得該平衡距離會縮小,並危及於該覆晶與該可撓性電路基板間一完全且均勻之側填滿材料層的應用。
因此,需要一種用於FCoF應用之改良式可撓性電路基板,其可在該覆晶與該可撓性電路基板間促進一與習知可撓性電路基板相比之下較大且較均勻之平衡距離。
本發明藉由提供一種用於FCoF應用之改良式可撓性電路基板來滿足上文所指明的需求。此電路基板之具體實施例運用實質上與該可撓性電路基板之表面齊平的安裝襯墊。以此方式,優點係在該可撓性電路基板與一所附著之覆晶間產生一與習知可撓性電路基板相比之下較大且較均勻之平衡距離。
根據本發明之一態樣,一種用於附著至一積體電路晶片之電路基板包含一電線路、一安裝襯墊與一介電層。該安裝襯墊具有一第一表面、一或多個側壁與一第二表面。該第一表面係附著至該電線路。依次地,該介電層實質上會覆蓋該安裝襯墊之一或多個側壁並具有一實質上與該等安裝襯墊之第二表面共平面的最上部表面。
於一說明性具體實施例中,一電路基板係可撓性且係配置成用於附著至一具有複數個焊塊的覆晶。該電路基板包含複數個電線路與相等數目之安裝襯墊。每一安裝襯墊具有一下表面、一側壁與一上表面。每一安裝襯墊之下表面係附著至一個別電線路。一介電層會覆蓋該等安裝襯墊之側壁並具有一實質上與該等安裝襯墊之上表面共平面的最上部表面。此外,於該等安裝襯墊之上表面上置放安裝襯墊蓋,並使該等安裝襯墊蓋於該介電層之最上部表面稍微突出。
優點係,此電路基板組態會在一覆晶附著至該電路基板時使該等安裝襯墊蓋能夠侷限該覆晶之焊塊。此侷限會限制該等焊塊的崩潰。因此,在一可於覆晶與電路基板間促進形成一完全且均勻之側填滿材料層的範圍內便可更加輕易維持該覆晶與該電路基板間的平衡距離。一較可靠晶片/基板裝配件從而係在運用具有根據本發明態樣之特徵的電路基板之情況下形成。
本發明之此等與其他特徵及優點將因結合隨附圖式來閱讀下列之詳細說明而變得明白。
本文中將結合示範性電路基板與形成該等示範性電路基板之方法來說明本發明。然而,應瞭解的是本發明並不限於本文中所顯示與說明之特定配置、材料、薄膜層與處理步驟。熟悉此項技術者將明白可對該等說明性具體實施例進行修改。
明確地說,關於處理步驟,應強調的是本文中所提供之說明並不意欲包括成功形成一功能性電路基板所需要的全部處理步驟。而是,為求說明之簡潔而刻意不說明某些習慣上用於形成此類電路基板之處理步驟(例如,清理步驟)。然而,熟悉此項技術者將輕易發現該等在此廣義說明中遭省略的處理步驟。此外,用於製造電路基板之處理步驟的細節可於許多出版物中發現,例如,編者C.A.Harper,電子材料及處理手冊,第三版,McGraw-Hill,2003,其係以提及之方式併入本文。
亦應瞭解的是隨附圖式中所顯示之各層及/或區域並未按比例而繪製。此外,為求說明之簡潔,該等圖式係僅侷限於該等顯示本發明之態樣所必須的說明性電路基板區域。於實際應用中,根據本發明之態樣的電路基板將很可能比該等於本文中所說明之電路基板更大。然而,該等更大之電路基板將仍歸屬本發明之範疇內。
圖1A與1B顯示根據本發明之一說明性具體實施例的電路基板100。圖1A係一平面圖,而圖1B係截取圖1A中所指明之平面的放大斷面圖。該電路基板包含一下部介電層110與一上部介電層120。於此等介電層中併入多個電線路(其全體由電線路130來代表)。安裝襯墊(其全體由安裝襯墊140來代表)係附著至每一電線路的上表面。最後,安裝襯墊蓋(其全體由安裝襯墊蓋150來代表)係附著至每一安裝襯墊的上表面。
基於說明之目的,在由圖1A與1B中所顯示之安裝襯墊140之上表面所界定之一平面中該等安裝襯墊係圓形。因此,每一安裝襯墊具有一單一側壁。然而,此形狀純粹係說明性,且其他安裝襯墊形狀將仍歸屬本發明之範疇內。例如,於一些應用中,可能偏好使用方形的安裝襯墊。此類安裝襯墊將具有四個側壁。方形安裝襯墊(例如)可能較適合一些類型的微影處理設備。
根據本發明之一態樣,圖1A與1B中所顯示之電路基板100係撓性。為成為撓性,該等介電層110、120較佳地包含一聚合物材料,例如(但不限於)聚醯亞胺。於該等安裝襯墊之下區域中的該下部介電層較佳地係約30微米厚,而該上部介電層較佳地係25微米厚。但是,其他厚度可同樣地適合且將為熟悉此項技術者所明白。該等電線路130與安裝襯墊140較佳地包含銅,因為銅的電阻率低。該等電線路與安裝襯墊較佳地具有約25微米之厚度。該等安裝襯墊蓋150較佳地包含沈積於鎳之上的金並具有約5微米的總厚度。鎳可阻止銅在該等銅安裝襯墊與附著至該等安裝襯墊蓋之相對側之特徵間的相互擴散。金可防止鎳遭氧化。
根據本發明之另一態樣,圖1A與1B中所顯示之特有電路基板100係配置成用於附著至一覆晶。但是,應注意,一電路基板並不一定得配置成用於附著至一特定類型之積體電路晶片才屬於本發明之範疇內。覆晶之設計、操作特性與製程將為熟悉此項技術者所熟知。此外,覆晶係詳細地說明於許多已經出版之出版物中,包括1999年CRC出版社編者G.R.Blackwell《電子封裝手冊》,其係以引用方式併入本文。簡言之,如同其他類型之積體電路晶片,覆晶一般係運用習知半導體處理技術而於一半導體晶圓上製造成重複的圖案。形成該等覆晶之後,焊塊係於該等覆晶之頂部附著至焊墊,同時該等覆晶仍包含在該半導體晶圓中。該等覆晶之焊墊係透過該等覆晶之金屬化層級而在該等覆晶內電連接至該半導體電路。一般而言,該等焊塊(依次)包含鉛且亦可包含錫。焊塊可以許多方式多以形成或置放於該等覆晶上,包括蒸鍍、電鍍、印刷、噴射、凸塊與直接置放。
參考圖2A與2B可較佳地瞭解一覆晶對電路基板100的附著。一包含附著至該電路基板100之覆晶210之裝配件200的平面圖係顯示於圖2A中。同一裝配件之放大斷面圖係顯示於圖2B中,其截取圖2A中所指明之平面。該覆晶包含多個焊塊(其全體由焊塊220來代表)。一側填滿材料230會填充該覆晶與該電路基板間的區域。
該覆晶210上之焊塊220係以使該覆晶在其之焊塊朝下的情況下置放於該電路基板之頂部上時焊塊之位置匹配該電路基板100上之安裝襯墊蓋150之位置的方式來加以配置。此配置使每一焊塊能夠直接附著至一相對應的安裝襯墊蓋。該覆晶對該電路基板之實際附著較佳地係由一高溫回焊程序來完成。該高溫回焊程序所利用之溫度取決於該等焊塊所採用之特定焊料合金,並將為熟悉此項技術者所熟知。
應注意的是在將該等焊塊220置放成接觸該等安裝襯墊蓋150之前,該等焊塊及/或安裝襯墊蓋視情況可以一助熔劑材料加以塗布。助熔劑會從欲進行焊接之表面移除氧化作用並防止在焊接程序本身期間之進一步的氧化作用。
一旦達成附著,該側填滿材料230較佳地係應用至該裝配件200。該側填滿材料可沿著該覆晶210之一或二邊緣進行針狀分配。其係藉由毛細管作用引入該覆晶與電路基板100間的區域,隨後並經熱固化以形成一永久的接合。如前述,完全且均勻應用該側填滿材料十分重要,因為該側填滿材料會保護該等焊塊免受濕氣與其他環境危害物的侵害;對該裝配件提供額外機械強度;以及補償該覆晶與該可撓性電路基板間的熱膨脹差異。該側填滿材料較佳地包含一環氧樹脂黏著劑。
根據本發明之一態樣,應注意的是該上部介電層120之最上部表面實質上係與該等安裝襯墊140之上表面共平面。在此配置之情況下,該等安裝襯墊蓋150會稍微突出於該上部介電層的表面之上。此配置具有許多優點。至少一優點依靠在典型高溫回焊程序期間,焊料將延伸(或蜷縮)於金屬表面上(即,「弄濕」該等金屬表面),但不會延伸於介電質、非金屬表面上的事實。據此,在高溫回焊之後,該覆晶210之焊塊220將傾向於侷限於其個別安裝襯墊蓋之頂部,因為該等安裝襯墊蓋會在該電路基板100之表面上形成分離的金屬島。
在該高溫回焊程序期間將該等焊塊220侷限於該等安裝襯墊蓋150之頂部將在該覆晶附著程序期間限制該等焊塊的崩潰。一給定之焊塊在回焊期間橫向延伸得愈多,則該焊塊之高度將減少得愈多。然而,在精確控制延伸之程度時,如同本文中所說明之具體實施例的情況中,一給定之焊塊在附著期間就高度而言將減少得較少。從而在該電路基板100與該附著之覆晶210間與一習知電路基板相比之下會獲得一較大且較均勻的平衡距離。據此,在一可於覆晶與電路基板間促進形成一完全且均勻之側填滿材料層的範圍內便可更加輕易地維持該平衡距離。因此,一較可靠晶片/基板裝配件係在運用具有根據本發明態樣之特徵的電路基板之情況下形成。
此外,進一步的利益可藉由對該電路基板100添加一或多個散熱器而獲得。圖3顯示具有一添加之散熱器310的裝配件200。該散熱器310係直接附著至該等電線路130中之一者的下表面。該散熱器較佳地包含一具有高導熱性之金屬材料,例如(但不限於)銅、銀、金或鋁。該散熱器較佳地亦具有如鰭般之突出物,其作用以提升從該散熱器至該散熱器周圍之環境空氣的熱對流傳送。
優點係,附著至該散熱器310之電線路130與該電線路之附屬安裝襯墊140會結合以從該覆晶210至該散熱器310形成低熱阻路徑。從而係增強來自該覆晶之熱散逸。此外,甚至更大的熱散逸增強可藉由運用多個如同圖3中所顯示之散熱器,或藉由運用一毗鄰於附著至相同電位之一個以上安裝襯墊之電線路的較大散熱器而獲得。附著至一個以上安裝襯墊之電線路通常係用於習知電路基板,例如接地匯流條。
現參考圖4A至4I說明一種形成該電路基板100的說明性方法。首先,一電線路層130L(較佳地包含銅)係運用一黏著劑而暫時附著至一剛性支撐板420,並產生圖4A中所顯示的裝配件。該剛性支撐板在該初始處理步驟期間作用以支撐該裝配件。於此處理時間點,該電線路層可視情況(例如)若該電線路層係由銅形成則藉由運用包含氫氣酸之溶液來加以化學粗糙化。該電線路層之粗糙化將提升稍後所沈積之層的黏著力。
接著,該等安裝襯墊140係藉由一圖案電鍍程序來形成。首先,於圖4A裝配件上沈積一第一光阻層430。該第一光阻層較佳地包含一適當的乾膜光聚合物,例如市面上可獲得之杜邦(DuPont)印刷電路材料(美國北卡羅來納州的三角研究園區)。該第一光阻層之厚度較佳地係等於該等安裝襯墊之所需厚度(例如,25微米)。該等安裝襯墊之負影像隨後係藉由習知的曝光與顯影技術而形成於該第一光阻層中。該結果裝配件係顯示於圖4B中。接著,安裝襯墊材料(較佳地包含銅)係電鍍至圖4B裝配件上。該安裝襯墊材料僅沈積於該電線路層130L之曝露部分上。從而,形成安裝襯墊140,如同圖4C中所顯示。
在形成該等安裝襯墊140之後,剝除該第一光阻層430,並產生圖4D中所顯示之裝配件。接著,於該裝配件之表面上形成該上部介電層120。形成該上部介電層較佳地係藉由一熱塑性聚合物積層(例如,聚醯亞胺)之真空輔助積層法。此種聚合物積層在市面上可從(例如)Rogers股份有限公司(美國康乃迪克州的Rogers)獲得。此等類型之聚合物積層的積層法包含運用一液壓機對欲積層之裝配件施加壓力。該液壓機具有二個加熱壓板,其在施加壓力時橫跨該裝配件使熱均勻分佈。於真空輔助積層法中,該等壓板係密封於真空環境中。藉助於真空,在積層法程序期間所需之壓力便較少,且實際上在該聚合物積層與其上將有所附著之基板間沒有捕捉任何的空氣。該聚合物積層隨後係加以固化,而沈積於該等安裝襯墊之上表面上之該聚合物積層的任何殘餘物係藉由習知基於過錳酸鹼除污程序來加以移除。該結果裝配件係顯示於圖4E中。此時,該暫時性剛性支撐板420不再需要繼續進行處理,而可加以移除。
接著,於該電線路層130L之下表面上沈積一第二光阻層440。如同於該第一光阻層430之情況中,該第二光阻層較佳地包含一適當的乾膜光聚合物。在該第二光阻層就適當位置的情況下,該裝配件係曝露於一電鍍處理以在該等安裝襯墊140之上表面上沈積該安裝襯墊蓋150,並且較佳地包含於鎳上所沈積的金。該結果裝配件係顯示於圖4F中。
接著,該等電線路130之正影像係藉由習知的曝光與顯影技術而圖案化至該第二光阻層440中。該結果裝配件係顯示於圖4G中。在該圖案化第二光阻層就適當位置的情況下,該裝配件隨後係曝露於一濕式化學蝕刻劑,其作用以蝕刻該電線路層130L之遭曝露部分,以便能界定該等分離的電線路。該濕式化學蝕刻劑(例如)可包含氯化鐵之溶液。在此濕式蝕刻程序期間,該等安裝襯墊蓋150會作用為一抗蝕劑,並從而保護該等安裝襯墊140免於遭蝕刻。該結果裝配件係顯示於圖4H中。此時,該等電線路130之下表面可視情況再次加以化學粗糙化,以提升稍後所沈積之層的黏著力。
欲完成該電路基板,一層下部介電層材料(例如,聚醯亞胺)係運用與形成該上部介電層120所使用之聚合物積層相似的適當聚合物積層經壓力/真空積層成圖4H裝配件之下面部分。此形成該下部介電層110。在固化該下部介電層之後,圖4I中所顯示之裝配件便產生。圖4I中之電路基板係與圖1B中所顯示之電路基板100相同。
重要地,應瞭解的是,儘管本發明之說明性具體實施例於本文中已參考隨附圖式加以說明,然而本發明並不限於此等明確的具體實施例。例如,一電路基板可配置成用於附著至一與該等說明性具體實施例中所說明之積體電路晶片完全不同類型的積體電路晶片,且仍歸屬本發明之範疇內。此外,形成一電路基板的元件與材料於其他具體實施例中可有所不同。熟悉此項技術者將發現可進行多種其他變更與修改,而不會背離隨附申請專利範圍之範疇。
100...電路基板
110...下部介電層
120...上部介電層
130...電線路
130L...電線路層
140...安裝襯墊
150...安裝襯墊蓋
200...裝配件
210...覆晶
220...焊塊
230...側填滿材料
310...散熱器
420...剛性支撐板
430...第一光阻層
440...第二光阻層
圖1A顯示根據本發明一說明性具體實施例之一電路基板的平面圖。
圖1B顯示圖1A之電路基板的斷面圖。
圖2A顯示一包含附著至圖1A電路基板之覆晶之裝配件的平面圖。
圖2B顯示圖2A裝配件之斷面圖。
圖3顯示具有一添加之散熱器之圖2A裝配件的斷面圖。
圖4A至4I顯示在不同形成階段期間之圖1A電路基板。
100...電路基板
110...下部介電層
120...上部介電層
130...電線路
140...安裝襯墊
150...安裝襯墊蓋
200...裝配件
210...覆晶
220...焊塊
230...側填滿材料

Claims (9)

  1. 一種用於附著至一積體電路晶片的電路基板,該電路基板包含:一電線路;一安裝襯墊,該安裝襯墊具有一第一表面、一或多個側壁與一第二表面,該第一表面係附著至該電線路;以及一在該安裝襯墊形成後形成之介電層,該介電層實質上覆蓋該安裝襯墊之該一或多個側壁並具有實質上與該安裝襯墊之該第二表面共平面的一最上部表面,以及一安裝襯墊蓋,該安裝襯墊蓋係置放於該安裝襯墊之該第二表面上且突出於該介電層之該最上部表面之上方。
  2. 如請求項1之電路基板,其中該電路基板係撓性。
  3. 如請求項1之電路基板,其中該電路基板係配置成用於附著至一覆晶。
  4. 如請求項1之電路基板,其進一步包含一第二介電層,其中該電線路之至少一部分係形成於實質上覆蓋該安裝襯墊之該一或多個側壁之介電層與該第二介電層間。
  5. 如請求項1之電路基板,其進一步包含一散熱器。
  6. 一種裝配件,其包含:一電路基板,該電路基板包括:一電線路;一安裝襯墊,該安裝襯墊具有一第一表面、一或多個側壁與一第二表面,該第一表面係附著至該電線路; 一在該安裝襯墊形成後形成之介電層,該介電層實質上覆蓋該安裝襯墊之該一或多個側壁並具有實質上與該安裝襯墊之該第二表面共平面的一最上部表面;以及一安裝襯墊蓋,該安裝襯墊蓋係置放於該安裝襯墊之該第二表面上且突出於該介電層之該最上部表面之上方;以及一積體電路晶片,該積體電路晶片附著至該電路基板。
  7. 如請求項6之裝配件,其中該積體電路晶片係一覆晶,其包含複數個焊塊。
  8. 如請求項7之裝配件,其中該等焊塊中之一者係電連接至該電路基板上的安裝襯墊蓋。
  9. 一種形成用於附著至一積體電路晶片之一電路基板的方法,該方法包含下列步驟:形成一電線路層;形成一安裝襯墊,該安裝襯墊具有一第一表面、一或多個側壁與一第二表面,該第一表面係附著至該電線路;在該安裝襯墊形成後形成一介電層,該介電層實質上覆蓋該安裝襯墊之該一或多個側壁並具有實質上與該安裝襯墊之該第二表面共平面的一最上部表面;以及形成一安裝襯墊蓋,該安裝襯墊蓋係置放於該安裝襯墊之該第二表面上且突出於該介電層之該最上部表面之上方。
TW095142149A 2006-02-23 2006-11-14 撓性板上覆晶應用之可撓性電路基板 TWI411052B (zh)

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