TWI410947B - Shfit register - Google Patents
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本發明係相關於一種移位暫存器，尤指一種可降低漏電流之移位暫存器。The invention relates to a shift register, in particular to a shift register capable of reducing leakage current.
液晶顯示器之閘極驅動器利用移位暫存器來產生循序之掃描訊號。目前移位暫存器可透過非晶矽(amorphous silicon,a-Si)薄膜電晶體(thin film transistors,TFTs)以及低溫多晶矽(low temperature polycrystalline silicon,LTPS)薄膜電晶體製造於液晶顯示器之玻璃基板上。移位暫存器通常具有多級的電路，所以某些薄膜電晶體會導通一段很長的時間。然而，當電壓持續或頻繁的施加至薄膜電晶體以及低溫多晶矽薄膜電晶體一段很長的時間時，將使得薄膜電晶體退化而無法適當的運作，降低了移位暫存器的可靠度。The gate driver of the liquid crystal display utilizes a shift register to generate a sequential scan signal. At present, the shift register can be fabricated on a glass substrate of a liquid crystal display through amorphous silicon (a-Si) thin film transistors (TFTs) and low temperature polycrystalline silicon (LTPS) thin film transistors. on. Shift registers typically have multiple stages of circuitry, so some thin film transistors can conduct for a long period of time. However, when the voltage is applied to the thin film transistor and the low temperature polycrystalline thin film transistor for a long period of time, the thin film transistor is degraded and cannot function properly, which reduces the reliability of the shift register.
請參考第1圖，第1圖為先前技術之移位暫存器之示意圖。在第N個移位暫存器100中，第一電晶體Q1用來驅動第二電晶體Q2。第一電晶體Q1之控制端與第一端電性連接於移位暫存器的輸入端，用以接收來自上一級SR(N-1)之輸出訊號。第一電晶體Q1之第二端電性連接於第二電晶體Q2之控制端。第二電晶體Q2之第一端用來接收第一訊號CK1，第二電晶體Q2之第二端電性連接於移位暫存器的輸出端OUT，以根據驅動節點G之電壓將第一訊號CK1傳輸至輸出端OUT。移位暫存器100包含一第一下拉模組110以及一第二下拉模組120。第三電晶體Q3以及第九電晶體Q9電性連接於輸出端OUT，用來在輸出端OUT輸出高準位電壓後，將輸出端OUT之電壓拉至低準位電壓VSS。第六電晶體Q6以及第十電晶體Q10電性連接於驅動節點G，用來在輸出端OUT輸出高準位電壓後將驅動節點G之電壓拉至低準位電壓VSS以關閉第二電晶體Q2。第一下拉模組110以及第二下拉模組120根據第一訊號CK1以及第二訊號CK2分別執行下拉任務約50%的時間。在第一下拉模組110中，第九電晶體Q9與第十電晶體Q10之控制端電性連接於節點K，節點K之電壓由第十二電晶體Q12與第十三電晶體Q13所決定。在第二下拉模組中，第三電晶體Q3與第六電晶體Q6之控制端電性連接於節點P，節點P之電壓由第四電晶體Q4與第五電晶體Q5所決定。第十一電晶體Q11用來將節點K之電壓拉至低準位電壓VSS。第七電晶體Q7用來在輸出端OUT輸出高準位電壓時，將節點P之電壓拉至低準位電壓VSS。另外，第八電晶體Q8電性連接於節點P，用來在輸出端OUT輸出高準位電壓時，將節點P之電壓拉至低準位電壓VSS。Please refer to FIG. 1 , which is a schematic diagram of a prior art shift register. In the Nth shift register 100, the first transistor Q1 is used to drive the second transistor Q2. The control terminal of the first transistor Q1 and the first terminal are electrically connected to the input end of the shift register for receiving the output signal from the upper stage SR (N-1). The second end of the first transistor Q1 is electrically connected to the control end of the second transistor Q2. The first end of the second transistor Q2 is used to receive the first signal CK1, and the second end of the second transistor Q2 is electrically connected to the output terminal OUT of the shift register to be first according to the voltage of the driving node G. The signal CK1 is transmitted to the output terminal OUT. The shift register 100 includes a first pull-down module 110 and a second pull-down module 120. The third transistor Q3 and the ninth transistor Q9 are electrically connected to the output terminal OUT for pulling the voltage of the output terminal OUT to the low level voltage VSS after the output terminal OUT outputs the high level voltage. The sixth transistor Q6 and the tenth transistor Q10 are electrically connected to the driving node G for pulling the voltage of the driving node G to the low level voltage VSS to turn off the second transistor after the output terminal OUT outputs the high level voltage. Q2. The first pull-down module 110 and the second pull-down module 120 respectively perform a pull-down task for about 50% of the time according to the first signal CK1 and the second signal CK2. In the first pull-down module 110, the control terminals of the ninth transistor Q9 and the tenth transistor Q10 are electrically connected to the node K, and the voltage of the node K is controlled by the twelfth transistor Q12 and the thirteenth transistor Q13. Decide. In the second pull-down module, the control terminals of the third transistor Q3 and the sixth transistor Q6 are electrically connected to the node P, and the voltage of the node P is determined by the fourth transistor Q4 and the fifth transistor Q5. The eleventh transistor Q11 is used to pull the voltage of the node K to the low level voltage VSS. The seventh transistor Q7 is used to pull the voltage of the node P to the low level voltage VSS when the output terminal OUT outputs a high level voltage. In addition, the eighth transistor Q8 is electrically connected to the node P for pulling the voltage of the node P to the low level voltage VSS when the output terminal OUT outputs the high level voltage.
第二訊號CK2與第一訊號CK1為互補訊號。因此，當第一訊號CK1為高準位電壓，第二訊號CK2為之低準位電壓VSS時，節點P之電壓為低準位電壓VSS，節點K之電壓為高準位電壓，除了在輸出端OUT為高準位電壓時，節點K之電壓將被第十一電晶體Q11拉至低準位電壓VSS。同樣地，當第一訊號CK1為低準位電壓VSS，第二訊號CK2為之高準位電壓時，節點K之電壓為低準位電壓VSS，節點P之電壓為高準位電壓，除了在輸出端OUT為高準位電壓時，節點P之電壓將被第七電晶體Q7以及第八電晶體Q8拉至低準位電壓VSS。The second signal CK2 and the first signal CK1 are complementary signals. Therefore, when the first signal CK1 is a high level voltage and the second signal CK2 is a low level voltage VSS, the voltage of the node P is a low level voltage VSS, and the voltage of the node K is a high level voltage, except at the output. When terminal OUT is a high level voltage, the voltage of node K will be pulled to the low level voltage VSS by the eleventh transistor Q11. Similarly, when the first signal CK1 is the low level voltage VSS and the second signal CK2 is the high level voltage, the voltage of the node K is the low level voltage VSS, and the voltage of the node P is the high level voltage, except When the output terminal OUT is at a high level voltage, the voltage of the node P will be pulled to the low level voltage VSS by the seventh transistor Q7 and the eighth transistor Q8.
節點K及節點P之電壓分別約50%的時間在高準位電壓以及約50%的時間在低準位電壓VSS。在高準位電壓時，電晶體導通，此時電晶體之臨界值漂移增加，而在低準位電壓時，電晶體之臨界值漂移減少。當高準位電壓與低準位電壓為反相時，臨界值漂移增加量等於臨界值漂移減少量，臨界值漂移之淨值大體上為零，移位暫存器之運作便視為穩定的。然而，目前的高準位電壓約等於+18V，而低準位電壓VSS約等於-6V。因此，由節點K以及節點P所控制之第三電晶體Q3、第六電晶體Q6、第九電晶體Q9以及第十電晶體Q10之臨界值漂移將隨時間而增加，使得移位暫存器不穩定。The voltages of node K and node P are respectively at a high level voltage of about 50% and a low level voltage VSS of about 50% of the time. At high voltages, the transistor is turned on, at which point the threshold drift of the transistor increases, while at low levels, the threshold drift of the transistor decreases. When the high-level voltage and the low-level voltage are opposite to each other, the threshold value drift increase amount is equal to the threshold value drift reduction amount, and the threshold value drift net value is substantially zero, and the operation of the shift register is regarded as stable. However, the current high level voltage is approximately equal to +18V, while the low level voltage VSS is approximately equal to -6V. Therefore, the threshold drift of the third transistor Q3, the sixth transistor Q6, the ninth transistor Q9, and the tenth transistor Q10 controlled by the node K and the node P will increase with time, so that the shift register Unstable.
因此，本發明之一目的在於提供一種移位暫存器。Accordingly, it is an object of the present invention to provide a shift register.
本發明係提供一種移位暫存器，包含複數個電性連接之移位單元，其中第n個移位單元包含一提升電路、一提升驅動電路、一下拉電路以及一下拉驅動電路。該提升電路用來根據一第一訊號及一驅動節點之電壓輸出該第一訊號至一輸出節點。該提升驅動電路電性連接於該提升電路，用來根據第(n-1)個移位單元之驅動節點之電壓輸出一第二訊號至該驅動節點。該下拉電路電性連接於該提升電路，用來根據第(n+2)個移位單元之驅動節點之電壓輸出一低準位電壓至該輸出節點。該下拉驅動電路電性連接於該提升驅動電路，用來根據該第一訊號及一第三訊號輸出該低準位電壓至該驅動節點。其中n為正整數。The invention provides a shift register comprising a plurality of electrically connected shifting units, wherein the nth shifting unit comprises a lifting circuit, a lifting driving circuit, a pull-down circuit and a pull-down driving circuit. The boosting circuit is configured to output the first signal to an output node according to a first signal and a voltage of a driving node. The boosting driving circuit is electrically connected to the boosting circuit for outputting a second signal to the driving node according to the voltage of the driving node of the (n-1)th shifting unit. The pull-down circuit is electrically connected to the boosting circuit for outputting a low level voltage to the output node according to the voltage of the driving node of the (n+2)th shifting unit. The pull-down driving circuit is electrically connected to the boosting driving circuit, and is configured to output the low-level voltage to the driving node according to the first signal and a third signal. Where n is a positive integer.
請參考第2圖，第2圖為本發明之移位暫存器之示意圖。移位暫存器包含複數個電性連接之移位單元200，每一個移位單元200包含一提升電路210、一提升驅動電路220、一下拉電路230以及一下拉驅動電路240。提升電路210包含一第一電晶體M1。提升驅動電路220包含一第二電晶體M2以及一第三電晶體M3。下拉電路230包含一第四電晶體M4以及一第五電晶體M5。下拉驅動電路包含一第一下拉驅動模組、一第二下拉驅動模組以及一第六電晶體M6。第一下拉驅動模組包含一第七電晶體M7、一第八電晶體M8、一第9電晶體M9以及一第十電晶體M10。第二下拉驅動模組包含一第十一電晶體M11、一第十二電晶體M12、第十三電晶體M13、一第十四電晶體M14以及一第十五電晶體M15。提升電路210根據第一訊號CKO及驅動節點Q之電壓輸出第一訊號CKO至輸出節點OUT。第n個移位單元(n為正整數)之提升驅動電路220根據第(n-1)個移位單元之驅動節點Q之電壓輸出第二訊號XCKO至驅動節點Q。下拉電路230根據第(n+2)個移位單元之驅動節點Q之電壓輸出低準位電壓VSS至輸出節點OUT。下拉驅動電路240包含一第一下拉驅動模組241，一第二下拉驅動模組242，以及一第六電晶體M6。第六電晶體M6電性連接於第一下拉驅動模組241及第二下拉驅動模組242之間。下拉驅動電路240根據第一訊號CKO及第三訊號CKE輸出低準位電壓VSS至驅動節點Q。Please refer to FIG. 2, which is a schematic diagram of the shift register of the present invention. The shift register includes a plurality of electrically connected shifting units 200. Each of the shifting units 200 includes a boosting circuit 210, a boosting driving circuit 220, a pull-down circuit 230, and a pull-down driving circuit 240. The boost circuit 210 includes a first transistor M1. The boost driving circuit 220 includes a second transistor M2 and a third transistor M3. The pull-down circuit 230 includes a fourth transistor M4 and a fifth transistor M5. The pull-down driving circuit includes a first pull-down driving module, a second pull-down driving module, and a sixth transistor M6. The first pull-down driving module includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The second pull-down driving module includes an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. The boosting circuit 210 outputs the first signal CKO to the output node OUT according to the voltages of the first signal CKO and the driving node Q. The boosting circuit 220 of the nth shifting unit (n is a positive integer) outputs the second signal XCKO to the driving node Q according to the voltage of the driving node Q of the (n-1)th shifting unit. The pull-down circuit 230 outputs the low level voltage VSS to the output node OUT according to the voltage of the driving node Q of the (n+2)th shift unit. The pull-down driving circuit 240 includes a first pull-down driving module 241, a second pull-down driving module 242, and a sixth transistor M6. The sixth transistor M6 is electrically connected between the first pull-down driving module 241 and the second pull-down driving module 242. The pull-down driving circuit 240 outputs the low-level voltage VSS to the driving node Q according to the first signal CKO and the third signal CKE.
第一電晶體M1之第一端用來接收第一訊號CKO，第一電晶體M1之第二端電性連接於輸出節點OUT。第二電晶體M2之第一端用來接收第二訊號XCKO，第二電晶體M2之控制端電性連接於第(n-1)個移位單元之驅動節點Q，第二電晶體M2之第一端電性連接於驅動節點Q。第三電晶體M3之第一端電性連接於輸出節點OUT，第三電晶體M3之控制端用來接收第三訊號CKE，第三電晶體M3之第二端用來接收低準位電壓VSS。第四電晶體M4之第一端電性連接於輸出節點OUT，第四電晶體M4之控制端電性連接於第(n+2)個移位單元之驅動節點Q，第四電晶體M4之第二端用來接收低準位電壓VSS。第五電晶體M5之第一端電性連接於驅動節點Q，第五電晶體M5之控制端電性連接於第(n+2)個移位單元之驅動節點Q，第五電晶體M5之第二端用來接收低準位電壓VSS。第七電晶體M7之第一端用來接收第三訊號CKE，第七電晶體M7之控制端電性連接於第七電晶體M7之第一端，第七電晶體M7之第二端電性連接於第一節點P。第八電晶體M8之第一端電性連接於驅動節點Q，第八電晶體M8之控制端電性連接於第一節點P，第八電晶體M8之第二端用來接收低準位電壓VSS。第九電晶體M9之第一端電性連接第一節點p，第九電晶體M9之控制端用來接收該第一訊號CKO，第九電晶體M9之第二端用來接收低準位電壓VSS。第十電晶體M10之第一端電性連接於第一節點P，第十電晶體M10之控制端電性連接於驅動節點Q，第十電晶體M10之第二端用來接收低準位電壓VSS。第十一電晶體M11之第一端用來接收第一訊號CKO，第十一電晶體M11之控制端電性連接於第十一電晶體M11之第一端，第十一電晶體M11之第二端電性連接於第二節點K。第十二電晶體M12之第一端電性連接於驅動節點Q，第十二電晶體M12之控制端電性連接於第二節點K，第十二電晶體M12之第二端用來接收低準位電壓VSS。第十三電晶體M13之第一端電性連接於第二節點K，第十三電晶體M13之控制端用來接收第三訊號CKE，第十三電晶體M13之第二端用來接收低準位電壓VSS。第十四電晶體M14之第一端電，性連接於第二節點K，第十四電晶體M14之控制端電性連接於驅動節點Q，第十四電晶體M14之第二端用來接收低準位電壓VSS。第十五電晶體M15之第一端電性連接於輸出節點OUT，第十五電晶體M15之控制端電性連接於第二節點K，第十五電晶體M15之第二端用來接收低準位電壓VSS。The first end of the first transistor M1 is used to receive the first signal CKO, and the second end of the first transistor M1 is electrically connected to the output node OUT. The first end of the second transistor M2 is used to receive the second signal XCKO, and the control end of the second transistor M2 is electrically connected to the driving node Q of the (n-1)th shifting unit, and the second transistor M2 The first end is electrically connected to the driving node Q. The first end of the third transistor M3 is electrically connected to the output node OUT, the control end of the third transistor M3 is used to receive the third signal CKE, and the second end of the third transistor M3 is used to receive the low level voltage VSS. . The first end of the fourth transistor M4 is electrically connected to the output node OUT, and the control end of the fourth transistor M4 is electrically connected to the driving node Q of the (n+2)th shifting unit, and the fourth transistor M4 The second terminal is used to receive the low level voltage VSS. The first end of the fifth transistor M5 is electrically connected to the driving node Q, and the control end of the fifth transistor M5 is electrically connected to the driving node Q of the (n+2)th shifting unit, and the fifth transistor M5 The second terminal is used to receive the low level voltage VSS. The first end of the seventh transistor M7 is for receiving the third signal CKE, the control end of the seventh transistor M7 is electrically connected to the first end of the seventh transistor M7, and the second end of the seventh transistor M7 is electrically Connected to the first node P. The first end of the eighth transistor M8 is electrically connected to the driving node Q, the control end of the eighth transistor M8 is electrically connected to the first node P, and the second end of the eighth transistor M8 is used to receive the low level voltage. VSS. The first end of the ninth transistor M9 is electrically connected to the first node p, the control end of the ninth transistor M9 is used to receive the first signal CKO, and the second end of the ninth transistor M9 is used to receive the low level voltage VSS. The first end of the tenth transistor M10 is electrically connected to the first node P, the control end of the tenth transistor M10 is electrically connected to the driving node Q, and the second end of the tenth transistor M10 is used for receiving the low level voltage. VSS. The first end of the eleventh transistor M11 is used to receive the first signal CKO, and the control end of the eleventh transistor M11 is electrically connected to the first end of the eleventh transistor M11, and the eleventh transistor M11 The two ends are electrically connected to the second node K. The first end of the twelfth transistor M12 is electrically connected to the driving node Q, the control end of the twelfth transistor M12 is electrically connected to the second node K, and the second end of the twelfth transistor M12 is used for receiving the low The level voltage VSS. The first end of the thirteenth transistor M13 is electrically connected to the second node K, the control end of the thirteenth transistor M13 is used to receive the third signal CKE, and the second end of the thirteenth transistor M13 is used to receive the low The level voltage VSS. The first end of the fourteenth transistor M14 is electrically connected to the second node K, the control end of the fourteenth transistor M14 is electrically connected to the driving node Q, and the second end of the fourteenth transistor M14 is used for receiving Low level voltage VSS. The first end of the fifteenth transistor M15 is electrically connected to the output node OUT, the control end of the fifteenth transistor M15 is electrically connected to the second node K, and the second end of the fifteenth transistor M15 is used for receiving the low The level voltage VSS.
請參考第3圖，第3圖為第2圖之移位暫存器之訊號之波形圖。第一訊號CKO與第二訊號XCKO為互補訊號。第三訊號CKE與第四訊號XCKE為互補訊號。在時序t0時，第(n-1)個移位單元之驅動節點Q(n-1)為為高準位電壓VDD，所以第二電晶體M2導通，但此時第二訊號XCKO為低準位電壓VSS，所以驅動節點Q為低準位電壓VSS。在時序t1時，驅動節點Q(n-1)為第二高準位電壓VD2，所以第二電晶體M2導通，因此第二訊號XCKO之高準位電壓VDD傳輸至驅動節點Q。在本發明中，移位單元利用驅動節點Q(n-1)之第二高準位電壓VD2來驅動第二電晶體M2，可降低第二電晶體M2之導通電阻，提升高準位電壓VDD傳輸至驅動節點Q之速度。另外，在時序t1時，第一訊號CKO為低準位電壓VSS，第三訊號CKE為高準位電壓VDD，第三訊號CKE之高準位電壓VDD傳輸至節點P，然而此時第六電晶體M6、第十電晶體M10以及第十四電晶體M14因為驅動節點Q(n-1)為高準位電壓VDD而導通，所以節點P以及節點K之電壓將被拉至低準位電壓VSS，使得第八電晶體M8、第十二電晶體M12以及第十五電晶體M15關閉。在時序t2時，第一訊號CKO為高準位電壓VDD，因為第一電晶體M1之第一端以及控制端之間的電容耦合，所以驅動節點Q之電壓會被提升至第二高準位電壓VD2，第一電晶體M1之導通電阻將更低，此時第一訊號CKO為高準位電壓VDD，所以輸出節點OUT為高準位電壓VDD。另外，在時序t2時，第一訊號CKO為高準位電壓VDD，第三訊號CKE為低準位電壓VSS，第一訊號CKO之高準位電壓VDD傳輸至節點K，然而此時第六電晶體M6、第十電晶體M10以及第十四電晶體M14因為驅動節點Q(n-1)之電壓為第二高準位VD2而導通，所以節點P以及節點K之電壓將被拉至低準位電壓VSS，使得第八電晶體M8、第十二電晶體M12以及第十五電晶體M15關閉。在本發明中，第六電晶體M6電性連接於第一下拉驅動模組以及第二下拉驅動模組之間，當第六電晶體M6導通時，可幫助拉低節點P以及節點K之電壓，減少第八電晶體M8、第十二電晶體M12以及第十五電晶體M15關閉產生漏電流效應。Please refer to Figure 3, which is a waveform diagram of the signal of the shift register of Figure 2. The first signal CKO and the second signal XCKO are complementary signals. The third signal CKE and the fourth signal XCKE are complementary signals. At the timing t0, the driving node Q(n-1) of the (n-1)th shifting unit is at the high level voltage VDD, so the second transistor M2 is turned on, but at this time, the second signal XCKO is low. The bit voltage is VSS, so the drive node Q is the low level voltage VSS. At the timing t1, the driving node Q(n-1) is the second high-level voltage VD2, so the second transistor M2 is turned on, so the high-level voltage VDD of the second signal XCKO is transmitted to the driving node Q. In the present invention, the shifting unit drives the second transistor M2 by using the second high-level voltage VD2 of the driving node Q(n-1), which can lower the on-resistance of the second transistor M2 and increase the high-level voltage VDD. The speed of transmission to the drive node Q. In addition, at the timing t1, the first signal CKO is the low level voltage VSS, the third signal CKE is the high level voltage VDD, and the high level voltage VDD of the third signal CKE is transmitted to the node P, but at this time, the sixth power The crystal M6, the tenth transistor M10, and the fourteenth transistor M14 are turned on because the driving node Q(n-1) is at the high level voltage VDD, so the voltages of the node P and the node K are pulled to the low level voltage VSS. The eighth transistor M8, the twelfth transistor M12, and the fifteenth transistor M15 are turned off. At the timing t2, the first signal CKO is the high level voltage VDD. Because of the capacitive coupling between the first end of the first transistor M1 and the control terminal, the voltage of the driving node Q is raised to the second high level. At the voltage VD2, the on-resistance of the first transistor M1 will be lower. At this time, the first signal CKO is the high level voltage VDD, so the output node OUT is the high level voltage VDD. In addition, at the timing t2, the first signal CKO is the high level voltage VDD, the third signal CKE is the low level voltage VSS, and the high level voltage VDD of the first signal CKO is transmitted to the node K, but at this time, the sixth power The crystal M6, the tenth transistor M10, and the fourteenth transistor M14 are turned on because the voltage of the driving node Q(n-1) is the second high level VD2, so the voltages of the node P and the node K are pulled to the low level. The bit voltage VSS causes the eighth transistor M8, the twelfth transistor M12, and the fifteenth transistor M15 to be turned off. In the present invention, the sixth transistor M6 is electrically connected between the first pull-down driving module and the second pull-down driving module, and when the sixth transistor M6 is turned on, the node P and the node K can be pulled down. The voltage, reducing the eighth transistor M8, the twelfth transistor M12, and the fifteenth transistor M15 are turned off to generate a leakage current effect.
接著，移位單元將根據第(n+2)個電晶體之驅動節點Q(n+2)之電壓進行重置。在時序t3時，驅動節點Q(n+2)為高準位電壓VDD，使得第四電晶體M4以及第五電晶體M5導通，所以驅動節點Q以及輸出節點OUT之電壓被拉至低準位電壓VSS。同時，第一訊號CKO為低準位電壓VSS，第三訊號CKE訊號為高準位電壓VDD，所以第七電晶體M7導通，因此節點P為高準位電壓VDD，使得第八電晶體M8導通，所以驅動節點Q之電壓被拉至低準位電壓VSS。另外，第三電晶體T3亦導通，將輸出節點OUT拉至低準位電壓VSS。在時序t4時，驅動節點Q(n+2)之電壓為第二高準位電壓VD2，將使得第四電晶體M4以及第五電晶體M5之導通電阻更低，可以更有效地將驅動節點Q以及輸出節點OUT拉至低準位電壓VSS。同時，第一訊號CKO為高準位電壓VDD，第三訊號CKE訊號為低準位電壓VSS，所以第十一電晶體M11導通，因此節點K為高準位電壓VDD，使得第十二電晶體M12以及第十五電晶體M15導通，所以驅動節點Q以及輸出節點OUT皆為低準位電壓VSS。在本發明中，第四電晶體M4以及第五電晶體M5利用第(n+2)個電晶體之驅動節點Q(n+2)之電壓作控制，而非第(n+1)個電晶體之驅動節點Q(n+1)，主要是因為驅動節點Q(n+1)在時序t2時就被拉至高準位電壓VDD，此時若第四電晶體M4以及第五電晶體M5導通將使輸出節點OUT之電壓被拉低。Then, the shifting unit resets according to the voltage of the driving node Q(n+2) of the (n+2)th transistor. At timing t3, the driving node Q(n+2) is the high level voltage VDD, so that the fourth transistor M4 and the fifth transistor M5 are turned on, so the voltages of the driving node Q and the output node OUT are pulled to the low level. Voltage VSS. At the same time, the first signal CKO is the low level voltage VSS, and the third signal CKE signal is the high level voltage VDD, so the seventh transistor M7 is turned on, so the node P is the high level voltage VDD, so that the eighth transistor M8 is turned on. Therefore, the voltage of the driving node Q is pulled to the low level voltage VSS. In addition, the third transistor T3 is also turned on to pull the output node OUT to the low level voltage VSS. At the timing t4, the voltage of the driving node Q(n+2) is the second high-level voltage VD2, which will make the on-resistance of the fourth transistor M4 and the fifth transistor M5 lower, and the driving node can be more effectively driven. Q and the output node OUT are pulled to the low level voltage VSS. At the same time, the first signal CKO is the high level voltage VDD, and the third signal CKE signal is the low level voltage VSS, so the eleventh transistor M11 is turned on, so the node K is the high level voltage VDD, so that the twelfth transistor M12 and the fifteenth transistor M15 are turned on, so the driving node Q and the output node OUT are both low level voltage VSS. In the present invention, the fourth transistor M4 and the fifth transistor M5 are controlled by the voltage of the driving node Q(n+2) of the (n+2)th transistor, instead of the (n+1)th electric The driving node Q(n+1) of the crystal is mainly because the driving node Q(n+1) is pulled to the high level voltage VDD at the timing t2, and at this time, if the fourth transistor M4 and the fifth transistor M5 are turned on The voltage at the output node OUT will be pulled low.
綜上所述，本發明之移位暫存器利用驅動節點Q(n-1)之第二高準位電壓VD2來推動第n個移位單元，可使驅動節點Q(n)之電壓的上升加速。另外，移位單元利用驅動節點Q(n+2)作為重置的驅動節點Q(n)或輸出節點OUT(n)之電壓，因為驅動節點Q具有第二高準位電壓VD2，可以降低電晶體的導通電阻而幫助將電壓拉低。本發明之移位暫存器提供電晶體M16作為節點K與節點P連接之橋樑，可幫助拉低節點P以及節點K之電壓，減少第八電晶體M8、第十二電晶體M12以及第十五電晶體M15關閉產生漏電流效應。In summary, the shift register of the present invention uses the second high level voltage VD2 of the driving node Q(n-1) to push the nth shift unit to drive the voltage of the node Q(n). The acceleration is accelerated. In addition, the shifting unit utilizes the driving node Q(n+2) as the voltage of the reset driving node Q(n) or the output node OUT(n), because the driving node Q has the second high-level voltage VD2, which can reduce the power. The on-resistance of the crystal helps pull the voltage low. The shift register of the present invention provides the transistor M16 as a bridge connecting the node K and the node P, which can help lower the voltage of the node P and the node K, and reduce the eighth transistor M8, the twelfth transistor M12 and the tenth The five-electrode M15 is turned off to produce a leakage current effect.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
100．．．移位單元100. . . Shift unit
110．．．第一下拉模組110. . . First pulldown module
120．．．第二下拉模組120. . . Second pulldown module
200．．．移位單元200. . . Shift unit
210．．．提升電路210. . . Lifting circuit
220．．．提升驅動電路220. . . Lift drive circuit
230．．．下拉電路230. . . Pull-down circuit
240．．．下拉驅動電路240. . . Pull-down drive circuit
241．．．第一下拉模組241. . . First pulldown module
242．．．第二下拉模組242. . . Second pulldown module
Q1~Q13．．．電晶體Q1~Q13. . . Transistor
M1~M15．．．電晶體M1~M15. . . Transistor
G、Q．．．驅動節點G, Q. . . Drive node
OUT．．．輸出節點OUT. . . Output node
K、P．．．節點K, P. . . node
CKO．．．第一訊號CKO. . . First signal
XCKO．．．第二訊號XCKO. . . Second signal
CKE．．．第三訊號CKE. . . Third signal
XCKE．．．第四訊號XCKE. . . Fourth signal
VSS．．．低準位電壓VSS. . . Low level voltage
VDD．．．高準位電壓VDD. . . High level voltage
VD2．．．第二高準位電壓VD2. . . Second high level voltage
第1圖為先前技術之移位暫存器之示意圖。Figure 1 is a schematic diagram of a prior art shift register.
第2圖為本發明之移位暫存器之示意圖。Figure 2 is a schematic diagram of the shift register of the present invention.
第3圖為第2圖之移位暫存器之訊號之波形圖。Figure 3 is a waveform diagram of the signal of the shift register of Figure 2.
200．．．移位單元200. . . Shift unit
210．．．提升電路210. . . Lifting circuit
220．．．提升驅動電路220. . . Lift drive circuit
230．．．下拉電路230. . . Pull-down circuit
240．．．下拉驅動電路240. . . Pull-down drive circuit
241．．．第一下拉模組241. . . First pulldown module
242．．．第二下拉模組242. . . Second pulldown module
M1~M15．．．電晶體M1~M15. . . Transistor
Q．．．驅動節點Q. . . Drive node
OUT．．．輸出節點OUT. . . Output node
K、P．．．節點K, P. . . node
CKO．．．第一訊號CKO. . . First signal
XCKO．．．第二訊號XCKO. . . Second signal
CKE．．．第三訊號CKE. . . Third signal
VSS．．．低準位電壓VSS. . . Low level voltage
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98121816A TWI410947B (en) | 2009-06-29 | 2009-06-29 | Shfit register |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW98121816A TWI410947B (en) | 2009-06-29 | 2009-06-29 | Shfit register |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201101285A TW201101285A (en) | 2011-01-01 |
| TWI410947B true TWI410947B (en) | 2013-10-01 |
Family
ID=44836978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW98121816A TWI410947B (en) | 2009-06-29 | 2009-06-29 | Shfit register |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI410947B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI431742B (en) * | 2011-04-27 | 2014-03-21 | Unimicron Technology Corp | Method of fabricating circuit board and basic circuit board |
| CN103680386B (en) * | 2013-12-18 | 2016-03-09 | 深圳市华星光电技术有限公司 | For GOA circuit and the display device of flat pannel display |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW290679B (en) * | 1995-03-06 | 1996-11-11 | Thomson Multimedia Sa |
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2009
- 2009-06-29 TW TW98121816A patent/TWI410947B/en active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW290679B (en) * | 1995-03-06 | 1996-11-11 | Thomson Multimedia Sa |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201101285A (en) | 2011-01-01 |
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