TWI521490B - Display panel and gate driver - Google Patents
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Description
本發明是有關於一種顯示面板，且特別是有關於一種顯示面板之閘極驅動器。 The present invention relates to a display panel, and more particularly to a gate driver for a display panel.
近來，各種液晶顯示器的產品已經相當地普及。為了有效地提升液晶顯示器的可視面積，適用於窄邊框的顯示面板技術不斷地被提出。 Recently, various liquid crystal display products have become quite popular. In order to effectively increase the viewing area of a liquid crystal display, a display panel technology suitable for a narrow bezel has been continuously proposed.
然而，隨著顯示器之解析度不斷提升，閘極驅動器可驅動顯示面板進行充電的時間越來越短。為了維持一定的畫素充電率，閘極驅動器中多個電晶體之尺寸必定需要增加。如此，會使閘極驅動器動態功耗與電路布局面積增加，反而更難以適用於窄邊框的應用。 However, as the resolution of the display continues to increase, the gate driver can drive the display panel for charging for shorter and shorter times. In order to maintain a certain pixel charging rate, the size of a plurality of transistors in the gate driver must be increased. In this way, the gate driver dynamic power consumption and circuit layout area increase, but it is more difficult to apply to narrow frame applications.
因此，如何能有效降低閘極驅動器之電路面積，並同時維持良好的畫素充電率，實屬當前重要研發課題之一，亦成為當前相關領域亟需改進的目標。 Therefore, how to effectively reduce the circuit area of the gate driver while maintaining a good pixel charging rate is one of the current important research and development topics, and has become an urgent target for improvement in related fields.
為了解決上述的問題，本揭示內容之一態樣提供了 一種顯示面板。顯示面板包含多條閘極線與閘極驅動器。閘極驅動器包含多個串接之驅動級，其中每一驅動級用以輸出閘極驅動信號至多條閘極線之對應一者，驅動級中之第N級驅動級包含輸入單元、驅動單元與下拉單元。輸入單元用以將第(N-1)級驅動級輸出之閘極驅動信號傳送至第一控制節點，其中N為正整數，且第(N-1)級驅動級輸出之閘極驅動信號包含連續的第一脈波與第二脈波。驅動單元用以根據第一控制節點之電壓位準而輸出閘極驅動信號。下拉單元用以在第二脈波的致能期間後將閘極驅動信號下拉至第一電壓。其中在第一脈波的致能期間內，輸入單元將第一控制節點之電壓位準上拉至第二電壓，在第二脈波的致能期間後，驅動單元將該第一控制節點之電壓位準上拉至第三電壓，且第三電壓大於第二電壓。 In order to solve the above problems, one aspect of the present disclosure provides A display panel. The display panel contains multiple gate lines and gate drivers. The gate driver comprises a plurality of serially connected driving stages, wherein each driving stage is configured to output a gate driving signal to a corresponding one of the plurality of gate lines, and the Nth stage driving stage of the driving stage comprises an input unit, a driving unit and Pull down the unit. The input unit is configured to transmit a gate driving signal of the (N-1)th stage driving stage output to the first control node, where N is a positive integer, and the gate driving signal of the (N-1)th stage driving stage output comprises A continuous first pulse and a second pulse. The driving unit is configured to output a gate driving signal according to a voltage level of the first control node. The pull-down unit is configured to pull the gate drive signal to the first voltage after the enable period of the second pulse. The input unit pulls up the voltage level of the first control node to the second voltage during the enabling period of the first pulse wave, and after the enabling period of the second pulse wave, the driving unit drives the first control node The voltage level is pulled up to a third voltage, and the third voltage is greater than the second voltage.
本揭示內容之另一態樣提供了一種閘極驅動器。閘極驅動器包含多個串接之驅動級，且多個驅動級中每一者包含輸入單元、驅動單元以及下拉單元。輸入單元包含第一輸入端，第二輸入端與輸出端。輸入單元之第一輸入端用以接收前級閘極驅動信號，輸入單元之第二輸入端用以接收第一時脈信號，且輸入單元之輸出端電性耦接控制節點。驅動單元包含第一輸入端，第二輸入端與輸出端。驅動單元之第一輸入端電性耦接控制節點，驅動單元之第二輸入端用以接收第二時脈信號，且驅動單元之輸出端用以輸出本級閘極驅動信號，其中第一時脈信號與第二時脈信號為反相。下拉單元包含第一開關、第二開關、第三開關、 第四開關、第五開關與第六開關。第一開關具有第一端、第二端以及控制端，其中第一開關之控制端用以接收第一時脈信號，第一開關之第一端電性耦接第一開關之控制端。第二開關具有第一端、第二端以及控制端，其中第二開關之控制端電性連接第一開關之控制端，且第二開關之第一端電性連接第一開關之第一端。第三開關具有第一端、第二端以及控制端，其中第三開關之控制端用以接收前級閘極驅動信號，第三開關之第一端電性耦接第一開關之第二端，且第三開關之第二端用以接收第一電壓。第四開關具有第一端、第二端以及控制端，其中第四開關之控制端用以接收前級閘極驅動信號，第四開關之第一端電性耦接第二開關之第二端，且第四開關之第二端用以接收第一電壓。第五開關具有一第一端、一第二端以及一控制端，其中第五開關之控制端電性耦接第二開關之第二端，第五開關之第一端電性耦接控制節點制節點，且第五開關之第二端電性耦接驅動單元之輸出端。第六開關具有第一端、第二端以及控制端，其中第六開關之控制端電性耦接第二開關之第二端，第六開關之第一端電性耦接驅動單元之輸出端，且第六開關之第二端用以接收第一電壓。 Another aspect of the present disclosure provides a gate driver. The gate driver includes a plurality of serially connected driver stages, and each of the plurality of driver stages includes an input unit, a drive unit, and a pull down unit. The input unit includes a first input, a second input and an output. The first input end of the input unit is configured to receive the front gate drive signal, the second input end of the input unit is configured to receive the first clock signal, and the output end of the input unit is electrically coupled to the control node. The driving unit includes a first input end, a second input end and an output end. The first input end of the driving unit is electrically coupled to the control node, the second input end of the driving unit is configured to receive the second clock signal, and the output end of the driving unit is configured to output the driving signal of the current level, wherein the first time The pulse signal is inverted from the second clock signal. The pull-down unit includes a first switch, a second switch, and a third switch, The fourth switch, the fifth switch, and the sixth switch. The first switch has a first end, a second end, and a control end, wherein the control end of the first switch is configured to receive the first clock signal, and the first end of the first switch is electrically coupled to the control end of the first switch. The second switch has a first end, a second end, and a control end, wherein the control end of the second switch is electrically connected to the control end of the first switch, and the first end of the second switch is electrically connected to the first end of the first switch . The third switch has a first end, a second end, and a control end, wherein the control end of the third switch is configured to receive the driving signal of the front stage, and the first end of the third switch is electrically coupled to the second end of the first switch And the second end of the third switch is configured to receive the first voltage. The fourth switch has a first end, a second end, and a control end, wherein the control end of the fourth switch is configured to receive the driving signal of the front stage, and the first end of the fourth switch is electrically coupled to the second end of the second switch And the second end of the fourth switch is configured to receive the first voltage. The fifth switch has a first end, a second end, and a control end, wherein the control end of the fifth switch is electrically coupled to the second end of the second switch, and the first end of the fifth switch is electrically coupled to the control node The node is connected, and the second end of the fifth switch is electrically coupled to the output end of the driving unit. The sixth switch has a first end, a second end, and a control end, wherein the control end of the sixth switch is electrically coupled to the second end of the second switch, and the first end of the sixth switch is electrically coupled to the output end of the driving unit And the second end of the sixth switch is configured to receive the first voltage.
綜上所述，本發明之技術方案與現有技術相比具有明顯的優點和有益效果。藉由上述技術方案，可達到相當的技術進步，並具有產業上的廣泛利用價值，本揭示內容所揭示之顯示面板與閘極驅動器可具有多種驅動方式，並可提供畫素陣列較高的充電率，進而可使顯示面板的開口 率提升，或是可使閘極驅動器之面積得以降低，以符合窄邊框應用的需求。 In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. With the above technical solution, considerable technological progress can be achieved, and the industrial use value is widely used. The display panel and the gate driver disclosed in the disclosure can have various driving modes and can provide high charging of the pixel array. Rate, which in turn allows the opening of the display panel The rate is increased, or the area of the gate driver can be reduced to meet the needs of narrow-frame applications.
為讓本揭示內容能更明顯易懂，所附符號之說明如下： In order to make the disclosure more obvious, the attached symbols are as follows:
100‧‧‧顯示面板 100‧‧‧ display panel
122‧‧‧畫素陣列 122‧‧‧ pixel array
140‧‧‧源極驅動器 140‧‧‧Source Driver
GL1、GL2、GL3~GLN‧‧‧閘極線 GL1, GL2, GL3~GLN‧‧‧ gate line
200a、300‧‧‧驅動級 200a, 300‧‧‧ drive level
G[1]、G[2]~G[n-1]、G[n]‧‧‧閘極驅動信號 G[1], G[2]~G[n-1], G[n]‧‧‧ gate drive signals
240‧‧‧驅動單元 240‧‧‧ drive unit
262‧‧‧下拉控制電路 262‧‧‧ Pull-down control circuit
A、B‧‧‧控制節點 A, B‧‧‧ control node
P1、P2‧‧‧脈波 P1, P2‧‧‧ pulse wave
120‧‧‧顯示區 120‧‧‧ display area
124‧‧‧畫素 124‧‧‧ pixels
160、200‧‧‧閘極驅動器 160, 200‧‧ ‧ gate driver
DL1、DL2、DL3、DL4~DLN‧‧‧資料線 DL1, DL2, DL3, DL4~DLN‧‧‧ data lines
XHC、HC‧‧‧時脈信號 XHC, HC‧‧‧ clock signals
Din‧‧‧初始脈波 Din‧‧‧ initial pulse wave
220‧‧‧輸入單元 220‧‧‧ input unit
260‧‧‧下拉單元 260‧‧‧ Pulldown unit
264‧‧‧下拉電路 264‧‧‧ Pulldown circuit
VSS、V1、V2、V3、V4、△V‧‧‧電壓 VSS, V1, V2, V3, V4, △V‧‧‧ voltage
C‧‧‧電容 C‧‧‧ capacitor
T11、T12、T21、T31、T32、T41、T42、T43、T44‧‧‧開關 T11, T12, T21, T31, T32, T41, T42, T43, T44‧‧‧ switch
T1、T2、T3、T4、T5‧‧‧時段 T1, T2, T3, T4, T5‧‧‧
為讓本發明之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1圖根據本揭示內容之一實施例繪示一種顯示面板之示意圖；第2A圖根據本揭示內容之一實施例繪示一種閘極驅動器的示意圖；第2B圖根據本揭示內容之一實施例繪示第2A圖所示之驅動級的示意圖；第3圖為根據本揭示內容之一實施例繪示第N級驅動級的示意圖；第4圖根據本揭示內容之一實施例繪示第3圖中之驅動級之操作的訊號時序示意圖；第5A圖根據本揭示內容之一實施例繪示在時段T1內第3圖之驅動級中各開關之狀態示意圖；第5B圖根據本揭示內容之一實施例繪示在時段T2內第3圖之驅動級中各開關之狀態示意圖；第5C圖根據本揭示內容之一實施例繪示在時段T5內第3圖之驅動級中各開關之狀態示意圖；以及第6圖根據本揭示內容之另一實施例繪示第3圖中之驅動級之操作的訊號時序示意圖。 The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood. 2A is a schematic diagram of a gate driver according to an embodiment of the present disclosure; FIG. 2B is a schematic diagram showing a driving stage shown in FIG. 2A according to an embodiment of the present disclosure; FIG. 3 is a schematic diagram according to the present disclosure. A schematic diagram of an Nth stage driver stage is shown in FIG. 4; FIG. 4 is a schematic diagram showing the timing of the operation of the driver stage in FIG. 3 according to an embodiment of the present disclosure; FIG. 5A is according to the disclosure. An embodiment shows a state diagram of each switch in the driving stage of FIG. 3 in the period T1; FIG. 5B illustrates the state of each switch in the driving stage of FIG. 3 in the period T2 according to an embodiment of the present disclosure. FIG. 5C is a schematic diagram showing the state of each switch in the driving stage of FIG. 3 in the period T5 according to an embodiment of the present disclosure; and FIG. 6 is a third diagram according to another embodiment of the present disclosure. Drive level Schematic diagram of the signal timing of the operation.
下文係舉實施例配合所附圖式作詳細說明，但所提供之實施例並非用以限制本發明所涵蓋的範圍，而結構操作之描述非用以限制其執行之順序，任何由元件重新組合之結構，所產生具有均等功效的裝置，皆為本發明所涵蓋的範圍。此外，圖式僅以說明為目的，並未依照原尺寸作圖。為使便於理解，下述說明中相同元件將以相同之符號標示來說明。 The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of structural operations is not intended to limit the order of execution thereof The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions. For ease of understanding, the same elements in the following description will be denoted by the same reference numerals.
關於本文中所使用之『第一』、『第二』、...等，並非特別指稱次序或順位的意思，亦非用以限定本發明，其僅僅是為了區別以相同技術用語描述的元件或操作而已。 The terms "first", "second", etc., as used herein, are not intended to refer to the order or the order, and are not intended to limit the invention, only to distinguish the elements described in the same technical terms. Or just operate.
關於本文中所使用之『約』、『大約』或『大致』一般通常係指數值之誤差或範圍約百分之二十以內，較好地是約百分之十以內，而更佳地則是約百分五之以內。文中若無明確說明，其所提及的數值皆視作為近似值，即如『約』、『大約』或『大致』所表示的誤差或範圍。 As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within about 20%, preferably within about 10%, and more preferably, It is about five percent. In the text, unless otherwise stated, the numerical values referred to are regarded as approximations, that is, the errors or ranges indicated by "about", "about" or "roughly".
另外，關於本文中所使用之『耦接』或『連接』，均可指二或多個元件相互直接作實體或電性接觸，或是相互間接作實體或電性接觸，亦可指二或多個元件相互操作或動作。 In addition, the term "coupled" or "connected" as used herein may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other, or Multiple components operate or act upon each other.
第1圖根據本揭示內容之一實施例繪示一種顯示面板100之示意圖。如第1圖所示，顯示面板100包括影像顯示區120、源極驅動器140以及閘極驅動器160。影像 顯示區120包括由多條資料線(如：N條資料線DL1~DLN)與多條閘極線(如：M條閘極線GL1~GLM)配置而形成的畫素陣列122以及多個畫素124，且畫素124配置於上述畫素陣列122中。 FIG. 1 is a schematic diagram of a display panel 100 according to an embodiment of the present disclosure. As shown in FIG. 1, the display panel 100 includes an image display area 120, a source driver 140, and a gate driver 160. image The display area 120 includes a pixel array 122 and a plurality of paintings formed by a plurality of data lines (eg, N data lines DL1 to DLN) and a plurality of gate lines (eg, M gate lines GL1 to GLM). The pixel 124 and the pixel 124 are disposed in the pixel array 122 described above.
源極驅動器140耦接資料線DL1~DLN，並用以輸出資料信號透過資料線DL1~DLN傳送至影像顯示區120給對應的畫素124，而閘極驅動器160耦接閘極線GL1~GLM，並用以輸出閘極驅動信號依序至閘極線GL1~GLM，透過閘極線GL1~GLM傳送至影像顯示區120給對應的畫素124。 The source driver 140 is coupled to the data lines DL1 DL DLN, and is configured to transmit the data signals to the image display area 120 to the corresponding pixels 124 through the data lines DL1 DL DLN, and the gate driver 160 is coupled to the gate lines GL1 GGLM. The output gate driving signals are sequentially transmitted to the gate lines GL1 G GLM and transmitted to the image display area 120 through the gate lines GL1 G GLM to the corresponding pixels 124 .
第2A圖根據本揭示內容之一實施例繪示一種閘極驅動器200的示意圖。如第2A圖所示，閘極驅動器200包含多級驅動級200a。每一驅動級200a彼此互相串接，且每一級驅動級200a用以輸出閘極驅動信號G[n]至閘極線GL1~GLM中之對應者。 2A is a schematic diagram of a gate driver 200 in accordance with an embodiment of the present disclosure. As shown in FIG. 2A, the gate driver 200 includes a multi-level driver stage 200a. Each of the driver stages 200a is connected to each other in series, and each stage of the driver stage 200a is used to output a gate drive signal G[n] to a corresponding one of the gate lines GL1 G GLM.
第2B圖根據本揭示內容之一實施例繪示第2A圖所示之驅動級200a的示意圖。以第N級驅動級200a為例，第N級驅動級200a包含輸入單元220、驅動單元240與下拉單元260，其中N為一正整數。 FIG. 2B is a schematic diagram showing the driver stage 200a shown in FIG. 2A according to an embodiment of the present disclosure. Taking the Nth stage driver stage 200a as an example, the Nth stage driver stage 200a includes an input unit 220, a driving unit 240, and a pull down unit 260, where N is a positive integer.
輸入單元220之第一輸入端用以接收第(N-1)級閘極驅動信號G[n-1]或初始脈波Din(當N=1時)，輸入單元220之第二輸入端用以接收時脈信號XHC，且輸入單元220之輸出端電性耦接控制節點A。 The first input end of the input unit 220 is configured to receive the (N-1)th gate drive signal G[n-1] or the initial pulse Din (when N=1), and the second input of the input unit 220 The clock signal XHC is received, and the output end of the input unit 220 is electrically coupled to the control node A.
驅動單元240之第一輸入端電性耦接於控制節點 A，驅動單元240之第二輸入端用以接收時脈信號HC，且驅動單元240之輸出端用以輸出本級閘極驅動信號G[n]。其中，上述之時脈信號XHC與時脈信號HC互為反相。 The first input end of the driving unit 240 is electrically coupled to the control node A, the second input end of the driving unit 240 is configured to receive the clock signal HC, and the output end of the driving unit 240 is configured to output the gate driving signal G[n] of the current stage. The clock signal XHC and the clock signal HC are opposite to each other.
以操作而言，輸入單元220用以將第(N-1)級驅動級200a輸出的閘極信號G[n-1]或或初始脈波Din(當N=1時)傳送至控制節點A，以調整控制節點A之電壓位準。驅動單元240用以根據控制節點A之電壓位準而輸出本級閘極驅動信號G[n]。下拉單元260電性耦接輸入單元220與驅動單元240。下拉單元260用以接收第(N-1)級驅動級200a輸出的閘極信號G[n-1]或初始脈波Din(當N=1時)以及時脈信號XHC，以將本級閘極驅動信號G[n]下拉至電壓VSS。 In operation, the input unit 220 is configured to transmit the gate signal G[n-1] outputted by the (N-1)th stage driving stage 200a or the initial pulse wave Din (when N=1) to the control node A. To adjust the voltage level of the control node A. The driving unit 240 is configured to output the gate driving signal G[n] of the current level according to the voltage level of the control node A. The pull-down unit 260 is electrically coupled to the input unit 220 and the driving unit 240. The pull-down unit 260 is configured to receive the gate signal G[n-1] outputted by the (N-1)th stage driving stage 200a or the initial pulse wave Din (when N=1) and the clock signal XHC to turn the gate The pole drive signal G[n] is pulled down to the voltage VSS.
此外，本揭示內容所示之閘極驅動器200可產生不同類型的閘極驅動信號G[n]，而使顯示陣列122以不同的極性驅動方式(例如：點反轉、圖框反轉、列反轉、欄反轉等等)。具體而言，如第2A圖所示，第1級驅動級200a之輸入單元220的第一輸入端更用以接收初始脈波DIN，上述之不同的極性驅動方式可依據實際需求而透過初始脈波DIN進行設定來完成。 In addition, the gate driver 200 shown in the present disclosure can generate different types of gate driving signals G[n], and the display array 122 can be driven in different polarities (eg, dot inversion, frame inversion, column). Reverse, column inversion, etc.). Specifically, as shown in FIG. 2A, the first input end of the input unit 220 of the first stage driving stage 200a is further configured to receive an initial pulse wave DIN, and the different polarity driving modes may be transmitted through the initial pulse according to actual needs. The wave DIN is set to complete.
以下段落將提出各個實施例，來說明上述驅動級200a的功能與應用，但本發明並不僅以下所列的實施例為限。 The following paragraphs will set forth various embodiments to explain the functions and applications of the above-described driver stage 200a, but the present invention is not limited to the embodiments listed below.
請參照第3圖，第3圖為根據本揭示內容之一實施例繪示第N級驅動級300的示意圖。如第3圖所示，輸入單元220包含開關T11與開關T12。開關T11之控制端電 性耦接輸入單元220之第一輸入端，以接收第(N-1)級驅動級200a輸出的閘極驅動信號G[n-1]或初始脈波Din(若N=1時)，且開關T11之第一端電性耦接開關T11之控制端。開關T12之控制端電性耦接輸入單元220之第二輸入端，以接收時脈信號XHC。開關T12之第一端電性耦接開關T11之第二端，開關T12之第二端電性耦接至輸入單元220之輸出端(亦即控制節點A)。如此，當開關T11與開關T12皆為導通時，第(N-1)級驅動級200a輸出的閘極驅動信號G[n-1]可傳送至控制節點A，以調整控制節點A之電壓位準。 Please refer to FIG. 3 , which is a schematic diagram of an Nth stage driver stage 300 according to an embodiment of the present disclosure. As shown in FIG. 3, the input unit 220 includes a switch T11 and a switch T12. Control terminal of switch T11 The first input terminal of the input unit 220 is coupled to receive the gate driving signal G[n-1] outputted by the (N-1)th stage driving stage 200a or the initial pulse wave Din (if N=1), and The first end of the switch T11 is electrically coupled to the control end of the switch T11. The control terminal of the switch T12 is electrically coupled to the second input of the input unit 220 to receive the clock signal XHC. The first end of the switch T12 is electrically coupled to the second end of the switch T11, and the second end of the switch T12 is electrically coupled to the output end of the input unit 220 (ie, the control node A). Thus, when both the switch T11 and the switch T12 are turned on, the gate drive signal G[n-1] outputted by the (N-1)th stage of the driver stage 200a can be transmitted to the control node A to adjust the voltage level of the control node A. quasi.
再者，如第3圖所示，驅動單元240包含開關T21與電容C。開關T21之控制端電性耦接至驅動單元240之第一輸入端(亦即控制節點A)，開關T21之第一端電性耦接驅動單元240之第二輸入端，以接收時脈信號HC，且開關T21之第二端電性耦接至驅動單元240之輸出端，以輸出本級閘極驅動信號G[n]。電容C電性耦接控制節點A與開關T21之間，以提供穩壓作用。 Furthermore, as shown in FIG. 3, the driving unit 240 includes a switch T21 and a capacitor C. The control terminal of the switch T21 is electrically coupled to the first input end of the driving unit 240 (ie, the control node A). The first end of the switch T21 is electrically coupled to the second input end of the driving unit 240 to receive the clock signal. HC, and the second end of the switch T21 is electrically coupled to the output end of the driving unit 240 to output the gate driving signal G[n] of the current stage. The capacitor C is electrically coupled between the control node A and the switch T21 to provide a voltage stabilization function.
下拉單元260包含下拉控制電路262與下拉電路264。下拉控制電路262用以根據第(N-1)級驅動級輸出之閘極驅動信號G[n-1]或初始脈波Din(若N=1時)調整控制節點B之電壓位準。下拉電路264電性耦接控制節點B，並用以根據控制節點B之電壓位準而將本級閘極驅動信號G[n]下拉至電壓VSS，其中電壓VSS為低位準電壓。 The pull-down unit 260 includes a pull-down control circuit 262 and a pull-down circuit 264. The pull-down control circuit 262 is configured to adjust the voltage level of the control node B according to the gate drive signal G[n-1] outputted by the (N-1)th stage drive stage or the initial pulse wave Din (if N=1). The pull-down circuit 264 is electrically coupled to the control node B and is configured to pull down the gate drive signal G[n] of the current stage to the voltage VSS according to the voltage level of the control node B, wherein the voltage VSS is a low level voltage.
具體而言，下拉控制電路262包含開關T41、開關 T42、開關T43與開關T44。開關T41之控制端用以接收時脈信號XHC，且開關T41之第一端電性耦接開關T41之控制端。開關T43之控制端電性耦接開關T41之第二端，開關T43之第一端電性耦接開關T41之第一端，且開關T43之第二端電性耦接控制節點B。開關T42之控制端用以接收第(N-1)級驅動級200a輸出之閘極驅動信號G[n-1]或初始脈波Din(若N=1時)。開關T42之控制端用以接收第(N-1)級驅動級200a輸出之閘極驅動信號G[n-1]或初始脈波Din(若N=1時)，開關T42之第一端電性耦接開關T41之第二端，且開關T42之第二端用以接收電壓VSS。開關T44之控制端用以接收第(N-1)級驅動級200a輸出之閘極驅動信號G[n-1]或初始脈波Din(若N=1時)，開關T44之第一端電性耦接控制節點B，且開關T44之第二端用以接收電壓VSS。 Specifically, the pull-down control circuit 262 includes a switch T41 and a switch. T42, switch T43 and switch T44. The control terminal of the switch T41 is configured to receive the clock signal XHC, and the first end of the switch T41 is electrically coupled to the control terminal of the switch T41. The control terminal of the switch T43 is electrically coupled to the second end of the switch T41. The first end of the switch T43 is electrically coupled to the first end of the switch T41, and the second end of the switch T43 is electrically coupled to the control node B. The control terminal of the switch T42 is configured to receive the gate drive signal G[n-1] or the initial pulse Din (if N=1) output from the (N-1)th stage of the driver stage 200a. The control terminal of the switch T42 is configured to receive the gate drive signal G[n-1] outputted by the (N-1)th stage drive stage 200a or the initial pulse wave Din (if N=1), and the first end of the switch T42 is electrically The second end of the switch T42 is coupled to the second end of the switch T42 for receiving the voltage VSS. The control terminal of the switch T44 is configured to receive the gate drive signal G[n-1] outputted by the (N-1)th stage drive stage 200a or the initial pulse wave Din (if N=1), and the first end of the switch T44 is electrically The control node B is coupled, and the second end of the switch T44 is used to receive the voltage VSS.
接著，如第3圖所示，下拉電路264包含開關T32與開關T31。開關T32之控制端電性耦接控制節點B，開關T32之第一端電性耦接控制節點A，且開關T32之第二端用以接收本級閘極驅動信號G[n]。開關T31之控制端電性耦接控制節點B，開關T31之第一端電性耦接開關T21之第二端，且開關T31之第二端用以接收電壓VSS。 Next, as shown in FIG. 3, the pull-down circuit 264 includes a switch T32 and a switch T31. The control terminal of the switch T32 is electrically coupled to the control node B. The first end of the switch T32 is electrically coupled to the control node A, and the second end of the switch T32 is configured to receive the gate drive signal G[n] of the current stage. The control terminal of the switch T31 is electrically coupled to the control node B. The first end of the switch T31 is electrically coupled to the second end of the switch T21, and the second end of the switch T31 is configured to receive the voltage VSS.
第4圖根據本揭示內容之一實施例繪示第3圖中之驅動級300之操作的訊號時序示意圖。如第4圖所示，在此實施例中，初始脈波Din設置以具有連續的脈波P1與脈波P2。如此，可使顯示陣列122以點反轉、列反轉等驅動 方式進行操作。 FIG. 4 is a timing diagram showing the operation of the driving stage 300 in FIG. 3 according to an embodiment of the present disclosure. As shown in Fig. 4, in this embodiment, the initial pulse wave Din is set to have continuous pulse waves P1 and pulse waves P2. In this way, the display array 122 can be driven by dot inversion, column inversion, and the like. The way to operate.
第5A圖根據本揭示內容之一實施例繪示在時段T1內第3圖之驅動級300中各開關之狀態示意圖。為了方便說明，請一併參照第4圖、第2B圖與第5A圖，驅動級300之操作將搭配上述圖式一併說明。此外，下述將以第1級驅動級300為例進行說明。後續各級驅動級300之操作，可將下述說明之初始脈波Din視為前級驅動級300所輸出之閘極驅動信號G[n-1]而相應推得。 FIG. 5A is a schematic diagram showing the state of each switch in the driving stage 300 of FIG. 3 in the period T1 according to an embodiment of the present disclosure. For convenience of explanation, please refer to FIG. 4, FIG. 2B and FIG. 5A together, and the operation of the driver stage 300 will be described together with the above drawings. In addition, the first stage drive stage 300 will be described below as an example. The operation of the subsequent stages of the driver stage 300 can be similarly derived by considering the initial pulse wave Din described below as the gate drive signal G[n-1] outputted by the pre-drive stage 300.
如第4圖與第5A圖所示，於時段T1(亦即脈波P1之致能期間)時，初始脈波Din之脈波P1輸入至開關T11與開關T42，而導通開關T11、開關T42。由於此時之時脈信號XHC為高位準電壓，開關T12與開關T41因此導通，且開關T43與開關T44亦因此導通。如此，控制節點B之電壓位準可經由開關T44而被拉低至電壓VSS，以關斷開關T32與開關T31。輸入單元220可傳輸初始脈波Din至控制節點A，以將控制節點A之電壓位準拉升至電壓V1，進而導通開關T21。因此，開關T21可將具有低電壓位準的時脈信號HC輸出為本級閘極驅動信號G[1]。 As shown in FIG. 4 and FIG. 5A, during the period T1 (that is, during the enable period of the pulse wave P1), the pulse wave P1 of the initial pulse Din is input to the switch T11 and the switch T42, and the switch T11 and the switch T42 are turned on. . Since the clock signal XHC is a high level voltage at this time, the switch T12 and the switch T41 are thus turned on, and the switch T43 and the switch T44 are also turned on. As such, the voltage level of the control node B can be pulled down to the voltage VSS via the switch T44 to turn off the switch T32 and the switch T31. The input unit 220 can transmit the initial pulse Din to the control node A to pull the voltage level of the control node A to the voltage V1, thereby turning on the switch T21. Therefore, the switch T21 can output the clock signal HC having a low voltage level to the gate drive signal G[1] of the stage.
值得注意的是，在本揭示內容各個實施例中，開關T32之間的電壓差由控制節點A與本級閘極驅動信號G[1]之電壓位準所決定。習知的閘極驅動器多以控制節點A之電壓位準與電壓VSS決定下拉電路的開關的電壓差，而本揭示內容所示之驅動極300可藉由此種設置方式減小開關T32之第一端與第二端之間的電壓差，使得開關T32之漏 電流可明顯減少，進而改善驅動級300的操作可靠度。 It should be noted that in various embodiments of the present disclosure, the voltage difference between the switches T32 is determined by the voltage level of the control node A and the gate drive signal G[1] of the stage. The conventional gate driver mostly determines the voltage difference between the voltage level of the control node A and the voltage VSS to determine the voltage difference of the switch of the pull-down circuit, and the driving electrode 300 shown in the present disclosure can reduce the number of the switch T32 by this arrangement. The voltage difference between one end and the second end causes leakage of the switch T32 The current can be significantly reduced, thereby improving the operational reliability of the driver stage 300.
第5B圖根據本揭示內容之一實施例繪示在時段T2內第3圖之驅動級300中各開關之狀態示意圖。如第4圖與第5B圖所示，於時段T2(亦即脈波P1的致能期間與脈波P2的致能期間之間的時間)時，初始脈波Din之脈波P1進入禁能期間，且時脈信號XHC亦切換至低位準電壓。因此，開關T11、開關T12、開關T41、開關T42、開關T43、開關T44、開關T32與開關T31皆為關斷。由於控制節點A之電壓位準在先前時段T1內已被拉升到電壓V1，故開關T21仍可保持導通。如此一來，在時段T2內，時脈信號HC切換至高位準電壓，並經由開關T21而輸出為具有高位準電壓的本級閘極驅動信號G[1]，以讓畫素陣列122進行預充電之操作。此外，本級閘極驅動信號G[1]會經由電容C而對控制節點A再次充電，而使控制節點A之電壓位準上拉至電壓V2。 FIG. 5B is a schematic diagram showing the state of each switch in the driving stage 300 of FIG. 3 in the period T2 according to an embodiment of the present disclosure. As shown in FIGS. 4 and 5B, during the period T2 (that is, the time between the enable period of the pulse wave P1 and the enable period of the pulse wave P2), the pulse wave P1 of the initial pulse Din enters the disable period. During this period, the clock signal XHC is also switched to the low level voltage. Therefore, the switch T11, the switch T12, the switch T41, the switch T42, the switch T43, the switch T44, the switch T32, and the switch T31 are all turned off. Since the voltage level of the control node A has been pulled up to the voltage V1 in the previous period T1, the switch T21 can remain turned on. In this way, during the period T2, the clock signal HC is switched to the high level voltage, and is output as the current gate driving signal G[1] having the high level voltage via the switch T21, so that the pixel array 122 is pre-processed. Charging operation. In addition, the gate drive signal G[1] of this stage recharges the control node A via the capacitor C, and pulls the voltage level of the control node A up to the voltage V2.
再者，如第4圖所示，於時段T3時，初始脈波Din進入脈波P2之致能期間，而時脈信號XHC切換至高電壓位準。此時，驅動級300之各個開關的狀態會與先前第5A圖相同，亦即開關T11、開關T12、開關T2、開關T41、開關T42、開關T43與開關T44為導通，且開關T32與開關T31為關斷。 Furthermore, as shown in FIG. 4, during the period T3, the initial pulse Din enters the enable period of the pulse wave P2, and the clock signal XHC switches to the high voltage level. At this time, the state of each switch of the driving stage 300 is the same as that of the previous FIG. 5A, that is, the switch T11, the switch T12, the switch T2, the switch T41, the switch T42, the switch T43 and the switch T44 are turned on, and the switch T32 and the switch T31. For shutdown.
同時，時脈信號HC切換至低電壓位準，而使控制節點A之電壓位準經由驅動單元240下拉至電壓V1。然而，實作上，由於控制節點A之電壓位準於時段T2已經充 電至較高的電壓V2，因此在時段T3時，控制節點A之電壓位準僅會下拉至電壓V3，其中電壓V3高於電壓V1，且V3=V1+△V。在各個實施例中，△V大約為1~3V。 At the same time, the clock signal HC is switched to the low voltage level, and the voltage level of the control node A is pulled down to the voltage V1 via the driving unit 240. However, in practice, since the voltage level of the control node A has been charged in the period T2 The voltage is increased to a higher voltage V2, so during the period T3, the voltage level of the control node A is only pulled down to the voltage V3, wherein the voltage V3 is higher than the voltage V1, and V3 = V1 + ΔV. In various embodiments, ΔV is approximately 1 to 3V.
請再次參照第4圖，於時段T4(亦即脈波P2的致能期間後)時，初始脈波Din切換至低電壓位準，且時脈信號XHC亦切換至低位準電壓。此時，驅動級300之各個開關的狀態會與先前第5B圖相同，亦即開關T11、開關T12、開關T32、開關T31、開關T41、開關T42、開關T43與開關T44為關斷，且開關T21為導通。此時，時脈信號HC切換至高位準電壓，並經由開關T21而輸出為具有高位準電壓的本級閘極驅動信號G[1]，以讓畫素陣列122進行寫入資料信號之操作。 Referring again to FIG. 4, during the period T4 (ie, after the enable period of the pulse wave P2), the initial pulse Din is switched to the low voltage level, and the clock signal XHC is also switched to the low level voltage. At this time, the state of each switch of the driving stage 300 is the same as that of the previous FIG. 5B, that is, the switch T11, the switch T12, the switch T32, the switch T31, the switch T41, the switch T42, the switch T43 and the switch T44 are turned off, and the switch T21 is conductive. At this time, the clock signal HC is switched to the high level voltage, and is output as the current gate driving signal G[1] having the high level voltage via the switch T21, so that the pixel array 122 performs the operation of writing the data signal.
同時，本級閘極驅動信號G[1]會再次經由電容C而對控制節點A充電，而使控制節點A之電壓位準上拉至電壓V2。如先前所述，實作上，由於控制節點A之電壓位準於時段T3已經提升至較高的電壓V3。因此，在相同的充電時間下，控制節點A之電壓位準在時段T4可被拉升到更高的電壓V4，亦使得本級閘極驅動信號G[1]也隨之提升，其中電壓V4高於電壓V2，且電壓V4=V2+△V。 At the same time, the gate drive signal G[1] of this stage will again charge the control node A via the capacitor C, and pull the voltage level of the control node A up to the voltage V2. As previously stated, in practice, the voltage level of the control node A has risen to a higher voltage V3 during the time period T3. Therefore, under the same charging time, the voltage level of the control node A can be pulled up to a higher voltage V4 during the period T4, and the gate driving signal G[1] of the current stage is also increased, wherein the voltage V4 It is higher than the voltage V2, and the voltage V4=V2+ΔV.
也就是說，驅動級300可在畫素陣列122進行寫入資料信號的操作時(亦即時段T4)提供具有更高的電壓位準之閘極驅動信號G[1]進行驅動，而使畫素陣列122中多個畫素124可具有較好的充電率。因此，畫素陣列122中多個畫素124之尺寸可以減小，以改善顯示面板200之開口 率(aperture ratio)。或者，可降低驅動級300中多個開關之尺寸，以使得閘極驅動器160之面積得以降低，以更符合窄邊框應用之需求。 That is to say, the driver stage 300 can drive the gate driving signal G[1] with a higher voltage level when the pixel array 122 performs the operation of writing the data signal (ie, the period T4), and causes the drawing. The plurality of pixels 124 in the prime array 122 can have a better charging rate. Therefore, the size of the plurality of pixels 124 in the pixel array 122 can be reduced to improve the opening of the display panel 200. Aperture ratio. Alternatively, the size of the plurality of switches in the driver stage 300 can be reduced to reduce the area of the gate driver 160 to better meet the needs of narrow bezel applications.
第5C圖根據本揭示內容之一實施例繪示在時段T5內第3圖之驅動級300中各開關之狀態示意圖。如第4圖與第5C圖所示，於時段T5時，初始脈波Din與時脈信號HC皆為低位準電壓，且時脈信號XHC為高位準電壓。因此，開關T12、開關T41、開關T43為導通，且開關T11、開關T42與開關T43為關斷。時脈信號XHC可經由開關T43而將控制節點B之電壓位準拉升至高位準電壓，進而導通開關T32與開關T31。如此，控制節點A之電壓位準以及本級閘極驅動信號G[1]皆被下拉至低位準電壓(例如為電壓VSS)。 FIG. 5C is a schematic diagram showing the state of each switch in the driving stage 300 of FIG. 3 in the period T5 according to an embodiment of the present disclosure. As shown in FIG. 4 and FIG. 5C, at the time period T5, the initial pulse wave Din and the clock signal HC are both low level voltages, and the clock signal XHC is a high level voltage. Therefore, the switch T12, the switch T41, and the switch T43 are turned on, and the switch T11, the switch T42, and the switch T43 are turned off. The clock signal XHC can pull the voltage level of the control node B to a high level voltage via the switch T43, thereby turning on the switch T32 and the switch T31. Thus, the voltage level of the control node A and the gate drive signal G[1] of the current stage are both pulled down to a low level voltage (for example, voltage VSS).
第6圖根據本揭示內容之另一實施例繪示第3圖中之驅動級300之操作的訊號時序示意圖。如第4圖所示，在此實施例中，初始脈波Din亦可設置為僅具有單一的脈波P1，如此可使顯示陣列122以圖框反轉、欄反轉等驅動方式進行操作。在僅具有單一脈波P1之操作，可參考於前述實施例中時段T1與時段T2之間的操作說明，於此不再重複贅述。 FIG. 6 is a timing diagram showing the operation of the driving stage 300 in FIG. 3 according to another embodiment of the present disclosure. As shown in FIG. 4, in this embodiment, the initial pulse wave Din can also be set to have only a single pulse wave P1, so that the display array 122 can be operated in a driving manner such as frame inversion and column inversion. For the operation of having only a single pulse wave P1, reference may be made to the operation description between the time period T1 and the time period T2 in the foregoing embodiment, and the details are not repeated herein.
於本揭示內容之各個實施例中，各個開關可為各類型之電晶體，例如為金屬氧化物半導體場效電晶體(MOSFET)、底閘型電晶體、頂閘型電晶體、薄膜電晶體等等。上述僅為例示，本發明並不以此為限。 In various embodiments of the present disclosure, each switch may be a transistor of each type, such as a metal oxide semiconductor field effect transistor (MOSFET), a bottom gate transistor, a top gate transistor, a thin film transistor, or the like. Wait. The foregoing is merely illustrative, and the invention is not limited thereto.
綜上所述，本揭示內容所揭示之顯示面板與閘極驅動器可具有多種驅動方式，並可提供畫素陣列較高的充電率，進而可使顯示面板的開口率提升，或是可使閘極驅動器之面積得以降低，以符合窄邊框應用的需求。 In summary, the display panel and the gate driver disclosed in the present disclosure can have various driving modes, and can provide a higher charging rate of the pixel array, thereby increasing the aperture ratio of the display panel or enabling the gate. The area of the pole drive is reduced to meet the needs of narrow bezel applications.
雖然本發明已以實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached.
300‧‧‧驅動級 300‧‧‧Driver
G[n]、G[n-1]‧‧‧閘極驅動信號 G[n], G[n-1]‧‧‧ gate drive signal
240‧‧‧驅動單元 240‧‧‧ drive unit
260‧‧‧下拉單元 260‧‧‧ Pulldown unit
264‧‧‧下拉電路 264‧‧‧ Pulldown circuit
C‧‧‧電容 C‧‧‧ capacitor
T11、T12、T21、T31、T32、T41、T42、T43、T44‧‧‧開關 T11, T12, T21, T31, T32, T41, T42, T43, T44‧‧‧ switch
XHC、HC‧‧‧時脈信號 XHC, HC‧‧‧ clock signals
Din‧‧‧初始脈波 Din‧‧‧ initial pulse wave
220‧‧‧輸入單元 220‧‧‧ input unit
262‧‧‧下拉控制電路 262‧‧‧ Pull-down control circuit
A、B‧‧‧控制節點 A, B‧‧‧ control node
VSS‧‧‧電壓 VSS‧‧‧ voltage
Claims (9)
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| TW103112319A TWI521490B (en) | 2014-04-02 | 2014-04-02 | Display panel and gate driver |
| CN201410211058.0A CN104008738B (en) | 2014-04-02 | 2014-05-19 | Display Panel and Gate Driver |
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| TW103112319A TWI521490B (en) | 2014-04-02 | 2014-04-02 | Display panel and gate driver |
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| TWI521490B true TWI521490B (en) | 2016-02-11 |
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| TWI533272B (en) * | 2014-09-26 | 2016-05-11 | 友達光電股份有限公司 | Display device and driving method thereof |
| TWI537914B (en) * | 2014-10-22 | 2016-06-11 | 友達光電股份有限公司 | Display panel, gate driver and control method |
| US9325311B1 (en) * | 2014-11-20 | 2016-04-26 | Innolux Corporation | Gate driver and display device using the same |
| CN105869593B (en) * | 2016-06-01 | 2018-03-13 | 深圳市华星光电技术有限公司 | A kind of display panel and its gate driving circuit |
| TWI616860B (en) * | 2017-06-27 | 2018-03-01 | 友達光電股份有限公司 | Gate driving circuit and operating method thereof |
| CN107358927B (en) * | 2017-07-31 | 2019-07-23 | 武汉华星光电半导体显示技术有限公司 | A kind of scan drive circuit and device |
| US10665192B2 (en) | 2017-07-31 | 2020-05-26 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Scan driving circuit and apparatus thereof |
| CN107195281B (en) | 2017-07-31 | 2019-01-15 | 武汉华星光电半导体显示技术有限公司 | A kind of scan drive circuit and device |
| CN107909980B (en) * | 2017-12-27 | 2020-08-04 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display device with same |
| TWI728783B (en) * | 2020-04-21 | 2021-05-21 | 友達光電股份有限公司 | Display device |
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| TWI336870B (en) * | 2006-09-01 | 2011-02-01 | Au Optronics Corp | Signal-driving system and shift register unit thereof |
| US7872506B2 (en) * | 2008-11-04 | 2011-01-18 | Au Optronics Corporation | Gate driver and method for making same |
| CN103646636B (en) * | 2013-12-18 | 2015-11-25 | 合肥京东方光电科技有限公司 | Shift register, gate driver circuit and display device |
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