TWI460702B - Display device and shift register thereof - Google Patents

Display device and shift register thereof Download PDF

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TWI460702B
TWI460702B TW101126019A TW101126019A TWI460702B TW I460702 B TWI460702 B TW I460702B TW 101126019 A TW101126019 A TW 101126019A TW 101126019 A TW101126019 A TW 101126019A TW I460702 B TWI460702 B TW I460702B
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unit
voltage
electrically coupled
control
scan
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TW101126019A
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TW201405508A (en
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Jyu Yu Chang
jun wei Lai
Po Yuan Shen
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Au Optronics Corp
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Description

顯示裝置及其移位暫存電路Display device and shift register circuit thereof

本發明是有關於一種掃描驅動電路，且特別是有關於一種移位暫存電路及其顯示裝置。The present invention relates to a scan driving circuit, and more particularly to a shift register circuit and a display device therefor.

隨著目前市場上對於顯示裝置窄邊框的需求，會希望將顯示裝置(例如是液晶顯示裝置)內部的移位暫存電路的體積/面積縮減，以符合對於顯示裝置厚度越來越薄及邊框越來越窄的訴求。然而，習知的移位暫存電路為了維持電路穩定性，無法減少元件，因此在顯示裝置中仍佔用相當大的體積/面積，而使顯示裝置的厚度及顯示裝置邊框的大小難以降低。With the current demand for a narrow bezel of a display device on the market, it may be desirable to reduce the volume/area of the shift temporary storage circuit inside the display device (for example, a liquid crystal display device) to conform to the thinner and wider border of the display device. A narrower appeal. However, the conventional shift register circuit cannot reduce the components in order to maintain circuit stability, and therefore still occupies a considerable volume/area in the display device, and it is difficult to reduce the thickness of the display device and the size of the frame of the display device.

在目前顯示裝置的製程中，利用內建掃描驅動電路(Gate driver On Array，GOA)的技術製作移位暫存電路，藉以符合輕薄短小的設計趨勢。In the current manufacturing process of the display device, the technology of the built-in scan driver circuit (Gate driver on Array, GOA) is used to fabricate the shift temporary storage circuit, so as to conform to the trend of light, thin and short design.

然而在目前的閘極驅動電路基板處於關閉(off)狀態時，其通常是以0伏特當作開關元件(例如，α-Si TFT或IGZO TFT等)的關閉電壓，但是有時會因為開關元件的特性導致所述的關閉電壓產生飄移而造成漏電流的問題，嚴重時還可能導致所述的移位暫存電路發生輸出失效的問題。However, when the current gate driving circuit substrate is in an off state, it is usually 0 volts as a switching voltage of a switching element (for example, an α-Si TFT or an IGZO TFT, etc.), but sometimes because of a switching element. The characteristic causes the shutdown voltage to drift and cause leakage current, and in severe cases, the output temporary circuit may cause output failure.

本發明提出一種移位暫存電路及其顯示裝置，可改善開關元件因為關閉電壓產生飄移而造成漏電流的問題，並且更進一步縮小移位暫存電路的電路佈局面積。The invention provides a shift temporary storage circuit and a display device thereof, which can improve the leakage current caused by the drift of the switching element due to the off voltage, and further reduce the circuit layout area of the shift temporary storage circuit.

因此，本發明的移位暫存電路，包括有：上拉單元、驅動單元、第一控制單元、第一下拉單元、第二控制單元、第二下拉單元與電壓調整單元。所述的上拉單元用以依據第一時脈訊號，第三掃描訊號，以及第二驅動電壓，以輸出第一驅動電壓。所述的驅動單元具有一個接收與第一時脈訊號相位相反的第二時脈訊號的第一端、一個電性耦接於上拉單元的控制端，與一個輸出第一掃描訊號的第二端。所述的第一控制單元電性耦接於驅動單元的控制端與電壓源，用以依據第一系統時脈訊號使驅動單元的控制端的電位被下拉至第一電壓。所述的第一下拉單元具有一個電性耦接於驅動單元的第二端的第一端，一個電性耦接於電壓調整單元的輸出端的第二端，以及一個接收第二掃描訊號的控制端。所述的第二控制單元分別電性耦接於驅動單元的控制端與電壓源，用以依據第二系統時脈訊號使驅動單元的控制端的電位被下拉至第一電壓。所述的第二下拉單元具有一個電性耦接於驅動單元的控制端的第一端，一個電性耦接於電壓調整單元的輸出端的第二端，以及一個接收第二掃描訊號的控制端。所述的電壓調整單元電性耦接於電壓源，用以輸出第二電壓。Therefore, the shift register circuit of the present invention includes: a pull-up unit, a driving unit, a first control unit, a first pull-down unit, a second control unit, a second pull-down unit, and a voltage adjusting unit. The pull-up unit is configured to output a first driving voltage according to the first clock signal, the third scan signal, and the second driving voltage. The driving unit has a first end receiving a second clock signal opposite to the phase of the first clock signal, a control end electrically coupled to the pull-up unit, and a second outputting the first scan signal end. The first control unit is electrically coupled to the control end of the driving unit and the voltage source for pulling down the potential of the control terminal of the driving unit to the first voltage according to the first system clock signal. The first pull-down unit has a first end electrically coupled to the second end of the driving unit, a second end electrically coupled to the output end of the voltage adjusting unit, and a control for receiving the second scanning signal end. The second control unit is electrically coupled to the control end of the driving unit and the voltage source for pulling down the potential of the control end of the driving unit to the first voltage according to the second system clock signal. The second pull-down unit has a first end electrically coupled to the control end of the driving unit, a second end electrically coupled to the output end of the voltage adjusting unit, and a control end receiving the second scanning signal. The voltage adjustment unit is electrically coupled to the voltage source for outputting the second voltage.

為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;

請參照圖1A，圖1A係為本發明實施例之移位暫存電路之示意圖。如圖1A所示，本發明實施例之第N級移位暫存單元100包括有上拉單元10、驅動單元20、第一控制單元30、第一下拉單元33、第二控制單元40、第二下拉單元43與電壓 調整單元50。Please refer to FIG. 1A. FIG. 1A is a schematic diagram of a shift temporary storage circuit according to an embodiment of the present invention. As shown in FIG. 1A, the Nth stage shift register unit 100 of the embodiment of the present invention includes a pull-up unit 10, a driving unit 20, a first control unit 30, a first pull-down unit 33, and a second control unit 40. Second pull-down unit 43 and voltage Adjustment unit 50.

上拉單元10用以依據第一時脈訊號HC1，第三掃描訊號G(n-1)，以及第二驅動電壓Q(n-1)，以輸出第一驅動電壓Q(n)。更具體的說，上拉單元10包括有開關元件10a與開關元件10b。所述的開關元件10a與開關元件10b可例如是由N型薄膜電晶體所構成。所述的開關元件10a的第一端接收第一時脈訊號HC1，開關元件10a的控制端接收第N-1級移位暫存單元(圖中未示)的上拉單元輸出的第二驅動電壓Q(n-1)。開關元件10b的第一端接收第N-1級移位暫存單元輸出的第三掃描訊號G(n-1)，開關元件10b的控制端電性耦接於開關元件10a的第二端，開關元件10b的第二端用以輸出第一驅動電壓Q(n)。The pull-up unit 10 is configured to output the first driving voltage Q(n) according to the first clock signal HC1, the third scanning signal G(n-1), and the second driving voltage Q(n-1). More specifically, the pull-up unit 10 includes a switching element 10a and a switching element 10b. The switching element 10a and the switching element 10b can be formed, for example, of an N-type thin film transistor. The first end of the switching element 10a receives the first clock signal HC1, and the control end of the switching element 10a receives the second driving of the output of the pull-up unit of the N-1th stage shift register unit (not shown). Voltage Q(n-1). The first end of the switching element 10b receives the third scanning signal G(n-1) outputted by the N-1th stage shifting unit, and the control end of the switching element 10b is electrically coupled to the second end of the switching element 10a. The second end of the switching element 10b is for outputting the first driving voltage Q(n).

驅動單元20具有接收第二時脈訊號HC2的第一端21、一個電性耦接於上拉單元10的控制端23，與一個輸出第一掃描訊號G(n)的第二端25。更具體的說，驅動單元20包括有開關元件20a，所述的開關元件20a可例如是由N型薄膜電晶體所構成，所述的開關元件20a的第一端21接收與第一時脈訊號HC1相位相反的第二時脈訊號HC2，開關元件20a的控制端23電性耦接於上拉單元10，於開關元件20a處於導通狀態時，開關元件20a的第二端25輸出第一掃描訊號G(n)。The driving unit 20 has a first end 21 for receiving the second clock signal HC2, a control end 23 electrically coupled to the pull-up unit 10, and a second end 25 for outputting the first scanning signal G(n). More specifically, the driving unit 20 includes a switching element 20a, which may be formed, for example, by an N-type thin film transistor, and the first end 21 of the switching element 20a receives the first clock signal. The second clock signal HC2 of the opposite phase of the HC1, the control terminal 23 of the switching element 20a is electrically coupled to the pull-up unit 10. When the switching element 20a is in the conducting state, the second terminal 25 of the switching element 20a outputs the first scanning signal. G(n).

第一控制單元30分別電性耦接於驅動單元20的控制端23與電壓源VSS，並依據第一系統時脈訊號LC1來將驅動單元20的控制端23的電位下拉至電壓源VSS所提供的第一電壓。第一控制單元30包括有開關元件30a~30f。所述的開關元件30a~30f可例如是由N型薄膜電晶體所構成。所述的開關元件30f的第一端分別電性耦接於驅動單元20的第二端，與儲能單元C的第一端。儲能單元C的第二端電性耦接於第一驅 動電壓Q(n)。開關元件30f的第二端電性耦接於電壓調整單元50的輸出端，以接收電壓調整單元50所輸出的第二電壓。值得注意的是，第二電壓的電位係高於第一電壓的電位。舉例來說，第二電壓的電位可為-6伏特，而第一電壓的電位可為-9伏特。開關元件30f的控制端電性耦接於開關元件30e的控制端。所述的開關元件30e的第一端電性連接上拉單元10的開關元件10b的第二端。開關元件30e的第二端電性耦接於電壓源VSS，以接收第一電壓。開關元件30a的控制端與第一端用以接收第一系統時脈訊號LC1。The first control unit 30 is electrically coupled to the control terminal 23 of the driving unit 20 and the voltage source VSS, and pulls down the potential of the control terminal 23 of the driving unit 20 to the voltage source VSS according to the first system clock signal LC1. The first voltage. The first control unit 30 includes switching elements 30a to 30f. The switching elements 30a to 30f may be formed, for example, of an N-type thin film transistor. The first end of the switching element 30f is electrically coupled to the second end of the driving unit 20 and the first end of the energy storage unit C. The second end of the energy storage unit C is electrically coupled to the first drive Dynamic voltage Q(n). The second end of the switching element 30f is electrically coupled to the output of the voltage adjusting unit 50 to receive the second voltage output by the voltage adjusting unit 50. It is worth noting that the potential of the second voltage is higher than the potential of the first voltage. For example, the potential of the second voltage can be -6 volts, and the potential of the first voltage can be -9 volts. The control end of the switching element 30f is electrically coupled to the control end of the switching element 30e. The first end of the switching element 30e is electrically connected to the second end of the switching element 10b of the pull-up unit 10. The second end of the switching element 30e is electrically coupled to the voltage source VSS to receive the first voltage. The control end and the first end of the switching element 30a are configured to receive the first system clock signal LC1.

如圖1A所示，開關元件30b的第一端電性耦接於開關元件30a的第二端，開關元件30b的控制端用以接收第一驅動電壓Q(n)，而開關元件30b的第二端電性耦接於電壓源VSS，以接收第一電壓。開關元件30c的第一端電性耦接於開關元件30a的第一端，開關元件30c的控制端電性耦接於開關元件30a的第二端，而開關元件30c的第二端電性耦接於開關元件30e的控制端。開關元件30d的第一端電性耦接於開關元件30c的第二端，開關元件30d的控制端電性耦接於第一驅動電壓Q(n)，而開關元件30d的第二端電性耦接於電壓源VSS，以接收第一電壓。As shown in FIG. 1A, the first end of the switching element 30b is electrically coupled to the second end of the switching element 30a, and the control end of the switching element 30b is configured to receive the first driving voltage Q(n), and the switching element 30b The two ends are electrically coupled to the voltage source VSS to receive the first voltage. The first end of the switching element 30c is electrically coupled to the first end of the switching element 30a, the control end of the switching element 30c is electrically coupled to the second end of the switching element 30a, and the second end of the switching element 30c is electrically coupled. Connected to the control terminal of the switching element 30e. The first end of the switching element 30d is electrically coupled to the second end of the switching element 30c, the control end of the switching element 30d is electrically coupled to the first driving voltage Q(n), and the second end of the switching element 30d is electrically The voltage source VSS is coupled to receive the first voltage.

第一下拉單元33具有一電性耦接於驅動單元20的第二端25的第一端，一電性耦接於電壓調整單元50之輸出端的第二端，用以接收第二電壓，以及接收第二掃描訊號G(n+1)的控制端。此第一下拉單元33用以依據第二掃描訊號G(n+1)來將驅動單元20的第二端25的電位下拉至第二電壓。更具體的說，第一下拉單元33包括有開關元件33a，所述的開關元件33a可例如是由N型薄膜電晶體所構成。所述的開關元件33a 的第一端電性耦接於驅動單元20的開關元件20a的第二端，開關元件33a的控制端接收第N+1級移位暫存單元(圖中未示)輸出的第二掃描訊號G(n+1)，而開關元件33a的第二端電性耦接於電壓調整單元50之輸出端，用以接收第二電壓。The first pull-down unit 33 has a first end electrically coupled to the second end 25 of the driving unit 20, and a second end electrically coupled to the output end of the voltage adjusting unit 50 for receiving the second voltage. And receiving a control end of the second scan signal G(n+1). The first pull-down unit 33 is configured to pull down the potential of the second terminal 25 of the driving unit 20 to the second voltage according to the second scanning signal G(n+1). More specifically, the first pull-down unit 33 includes a switching element 33a, which may be formed, for example, of an N-type thin film transistor. The switching element 33a The first end is electrically coupled to the second end of the switching element 20a of the driving unit 20, and the control end of the switching element 33a receives the second scanning signal output by the N+1th stage shifting unit (not shown) G(n+1), and the second end of the switching element 33a is electrically coupled to the output of the voltage adjusting unit 50 for receiving the second voltage.

第二控制單元40分別電性耦接於驅動單元20的控制端23與電壓源VSS，並依據第二系統時脈訊號LC2來將驅動單元20的控制端23的電位下拉至電壓源VSS所提供的第一電壓。第二控制單元40包括有開關元件40a~40f。所述的開關元件40a~40f可例如是由N型薄膜電晶體所構成。所述的開關元件40f的第一端電性耦接於驅動單元20的第二端，開關元件40f的第二端電性耦接於電壓調整單元50之輸出端，以接收第二電壓，而開關元件40f的控制端電性耦接於開關元件40e的控制端。所述的開關元件40e的第一端電性連接上拉單元10的開關元件10b的第二端，開關元件40e的第二端電性耦接於電壓源VSS，以接收第一電壓。開關元件40a的控制端與第一端用以接收第二系統時脈訊號LC2。The second control unit 40 is electrically coupled to the control terminal 23 of the driving unit 20 and the voltage source VSS, and pulls down the potential of the control terminal 23 of the driving unit 20 to the voltage source VSS according to the second system clock signal LC2. The first voltage. The second control unit 40 includes switching elements 40a-40f. The switching elements 40a-40f can be formed, for example, of an N-type thin film transistor. The first end of the switching element 40f is electrically coupled to the second end of the driving unit 20, and the second end of the switching element 40f is electrically coupled to the output end of the voltage adjusting unit 50 to receive the second voltage. The control end of the switching element 40f is electrically coupled to the control end of the switching element 40e. The first end of the switching element 40e is electrically connected to the second end of the switching element 10b of the pull-up unit 10, and the second end of the switching element 40e is electrically coupled to the voltage source VSS to receive the first voltage. The control end and the first end of the switching element 40a are configured to receive the second system clock signal LC2.

如圖1A所示，開關元件40b的第一端電性耦接於開關元件40a的第二端，開關元件40b的控制端用以接收第一驅動電壓Q(n)，而開關元件40b的第二端電性耦接於電壓源VSS，以接收第一電壓。開關元件40c的第一端電性耦接於開關元件40a的第一端，開關元件40c的控制端電性耦接於開關元件40a的第二端，而開關元件40c的第二端電性耦接於開關元件40e的控制端。開關元件40d的第一端電性耦接於開關元件40c的第二端，開關元件40d的控制端電性耦接於第一驅動電壓Q(n)，而開關元件40d的第二端電性耦接於電壓源VSS，以接收第一電壓。As shown in FIG. 1A, the first end of the switching element 40b is electrically coupled to the second end of the switching element 40a, the control end of the switching element 40b is configured to receive the first driving voltage Q(n), and the first of the switching element 40b The two ends are electrically coupled to the voltage source VSS to receive the first voltage. The first end of the switching element 40c is electrically coupled to the first end of the switching element 40a, the control end of the switching element 40c is electrically coupled to the second end of the switching element 40a, and the second end of the switching element 40c is electrically coupled. Connected to the control terminal of the switching element 40e. The first end of the switching element 40d is electrically coupled to the second end of the switching element 40c, the control end of the switching element 40d is electrically coupled to the first driving voltage Q(n), and the second end of the switching element 40d is electrically The voltage source VSS is coupled to receive the first voltage.

第二下拉單元43具有一電性耦接於驅動單元20的控制端23的第一端，一電性耦接於電壓調整單元50之輸出端的第二端，用以接收第二電壓，以及一個接收第二掃描訊號G(n+1)的控制端。此第二下拉單元43用以依據第二掃描訊號G(n+1)來將驅動單元20的控制端的電位下拉至第二電壓。更具體的說，第二下拉單元43包括有開關元件43a，所述的開關元件43a可例如是由N型薄膜電晶體所構成。所述的開關元件43a的第一端電性耦接於驅動單元20的開關元件20a的控制端，開關元件43a的控制端接收第N+1級移位暫存單元(圖中未示)輸出的第二掃描訊號G(n+1)，而開關元件43a的第二端電性耦接於電壓調整單元50之輸出端，以接收第二電壓。The second pull-down unit 43 has a first end electrically coupled to the control end 23 of the driving unit 20, a second end electrically coupled to the output end of the voltage adjusting unit 50, for receiving the second voltage, and a Receiving the control end of the second scan signal G(n+1). The second pull-down unit 43 is configured to pull down the potential of the control terminal of the driving unit 20 to the second voltage according to the second scanning signal G(n+1). More specifically, the second pull-down unit 43 includes a switching element 43a, which may be formed, for example, of an N-type thin film transistor. The first end of the switching element 43a is electrically coupled to the control end of the switching element 20a of the driving unit 20, and the control end of the switching element 43a receives the output of the (N+1)th shifting temporary storage unit (not shown). The second scan signal G(n+1), and the second end of the switching element 43a is electrically coupled to the output of the voltage adjusting unit 50 to receive the second voltage.

電壓調整單元50電性耦接於電壓源VSS，以接收第一電壓。電壓調整單元50用以將第一電壓轉換為第二電壓，並將第二電壓輸出至第一下拉單元33與第二下拉單元43。The voltage adjustment unit 50 is electrically coupled to the voltage source VSS to receive the first voltage. The voltage adjustment unit 50 is configured to convert the first voltage into a second voltage and output the second voltage to the first pull-down unit 33 and the second pull-down unit 43.

請參照圖1B，圖1B為本發明實施例之電壓調整單元之電路示意圖。如圖1B所示，移位暫存單元101的電壓調整單元50包括有開關元件T1。所述的開關元件T1具有一個控制端13，一個電性耦接於開關元件T1的控制端13、第一控制單元30與第二控制單元40的第一端11，與一個電性耦接電壓源VSS的第二端15。更具體的說，所述的開關元件T1可例如是N型薄膜電晶體。開關元件T1的第一端11分別電性耦接於開關元件30f的第二端與開關元件40f的第二端；開關元件T1的第二端15用以接收第一電壓，並電性耦接至第一控制單元30與第二控制單元40。Please refer to FIG. 1B. FIG. 1B is a schematic circuit diagram of a voltage adjustment unit according to an embodiment of the present invention. As shown in FIG. 1B, the voltage adjustment unit 50 of the shift register unit 101 includes a switching element T1. The switching element T1 has a control terminal 13 , a control terminal 13 electrically coupled to the switching element T1 , a first end 11 of the first control unit 30 and the second control unit 40 , and an electrical coupling voltage The second end 15 of the source VSS. More specifically, the switching element T1 can be, for example, an N-type thin film transistor. The first end 11 of the switching element T1 is electrically coupled to the second end of the switching element 30f and the second end of the switching element 40f. The second end 15 of the switching element T1 is configured to receive the first voltage and be electrically coupled. To the first control unit 30 and the second control unit 40.

值得一提的是，本發明之移位暫存單元100由於採用了電壓調整單元50來提供所需之第二電壓，因此移位暫存單元100 僅需接收來自移位暫存電路外部之電壓源VSS所提供的第一電壓即可，而不需要另外接收第二電壓。如此一來，便可減少電源線的電路佈線面積。It is worth mentioning that the shift register unit 100 of the present invention uses the voltage adjusting unit 50 to provide the required second voltage, so the shift register unit 100 is shifted. It is only necessary to receive the first voltage supplied from the voltage source VSS outside the shift register circuit without additionally receiving the second voltage. In this way, the circuit wiring area of the power line can be reduced.

接下來，請參照圖1C，圖1C為本發明實施例之電壓調整單元之另一電路示意圖。如圖1C所示，移位暫存單元102的電壓調整單元50包括有二極體D1。所述的二極體D1具有一個正極端(圖中未標示)與一個負極端(圖中未標示)。所述二極體D1的負極端電性耦接於電壓源VSS，用以接收第一電壓，而所述二極體D1的正極端用以輸出第二電壓。Next, please refer to FIG. 1C. FIG. 1C is another schematic diagram of a circuit of a voltage adjustment unit according to an embodiment of the present invention. As shown in FIG. 1C, the voltage adjustment unit 50 of the shift register unit 102 includes a diode D1. The diode D1 has a positive terminal (not shown) and a negative terminal (not shown). The negative terminal of the diode D1 is electrically coupled to the voltage source VSS for receiving the first voltage, and the positive terminal of the diode D1 is configured to output the second voltage.

接下來，請參照圖2，圖2繪示為本發明實施例之控制時序示意圖，其中水平軸表示為時間，垂直軸表示為電壓。如圖2所示，第一時脈訊號HC1與第二時脈訊號HC2相位相反。當第一系統時脈訊號LC1係為高位準，第一驅動電壓Q(n)係為低位準時，第一控制單元30係輸出一高位準訊號，因而開啟了第一下拉單元33與第二下拉單元43，以透過第二電壓將第一驅動控制電壓Q(n)下拉，因而關閉驅動單元20。當第一驅動電壓Q(n)係為高位準時，第一控制單元30會被拉至第一電壓而呈現低位準，而關閉第一下拉單元33與第二下拉單元43，使第一掃描訊號G(n)不致發生經由下拉單元漏電的情形，確保第一掃描訊號G(n)具有正確的波形。此外，第一系統時脈訊號LC1與第二系統時脈訊號LC2相位相反，當第二系統時脈訊號LC2係為高位準，而第一系統時脈訊號LC1係為低位準時，可交替使用第二控制單元40與第一控制單元30藉以延長所述之開關壽命。Next, please refer to FIG. 2. FIG. 2 is a schematic diagram of control timing according to an embodiment of the present invention, wherein a horizontal axis is represented as time and a vertical axis is represented as a voltage. As shown in FIG. 2, the first clock signal HC1 is opposite in phase to the second clock signal HC2. When the first system clock signal LC1 is at a high level and the first driving voltage Q(n) is at a low level, the first control unit 30 outputs a high level signal, thereby opening the first pull down unit 33 and the second The pull-down unit 43 pulls down the first drive control voltage Q(n) through the second voltage, thereby turning off the drive unit 20. When the first driving voltage Q(n) is at a high level, the first control unit 30 is pulled to the first voltage to present a low level, and the first pull-down unit 33 and the second pull-down unit 43 are turned off to make the first scan. The signal G(n) does not cause leakage through the pull-down unit, ensuring that the first scan signal G(n) has the correct waveform. In addition, the first system clock signal LC1 is opposite to the second system clock signal LC2. When the second system clock signal LC2 is at a high level, and the first system clock signal LC1 is at a low level, the first system can be used alternately. The second control unit 40 and the first control unit 30 thereby extend the life of the switch.

請一併參照圖1A與圖3，圖3係為本發明實施例之顯示裝置的示意圖。如圖3所示，本發明實施例之顯示裝置300包括有顯示單元310、資料驅動單元320、掃描驅動單元330與 時序控制單元340。所述顯示裝置例如為液晶顯示裝置(liquid crystal display)、電漿顯示裝置(plasma display panel,PDP)、電致發光顯示裝置(electroluminescent display)，電泳顯示裝置(electrophorectic display)，場發射顯示裝置(field emission display)...等，但不以此為限，任何需要時序輸出之顯示裝置皆涵蓋於本發明實施例之範圍。Please refer to FIG. 1A and FIG. 3 together. FIG. 3 is a schematic diagram of a display device according to an embodiment of the present invention. As shown in FIG. 3, the display device 300 of the embodiment of the present invention includes a display unit 310, a data driving unit 320, and a scan driving unit 330. Timing control unit 340. The display device is, for example, a liquid crystal display device, a plasma display panel (PDP), an electroluminescent display device, an electrophorec display device, and a field emission display device ( Field emission display), etc., but not limited thereto, any display device requiring timing output is encompassed by the scope of the embodiments of the present invention.

顯示單元310包含複數條掃描線與複數條資料線(圖中未示)用以分別接收由掃描驅動單元330所輸出的複數個掃描訊號，以及由資料驅動單元320所輸出的複數個資料訊號以顯示畫面。資料驅動單元320電性耦接於顯示單元310中的資料線，以提供上述資料訊號至上述資料線。掃描驅動單元330電性耦接於顯示單元310中的掃描線，以提供上述掃描訊號至上述掃描線。The display unit 310 includes a plurality of scan lines and a plurality of data lines (not shown) for respectively receiving the plurality of scan signals output by the scan driving unit 330, and the plurality of data signals output by the data driving unit 320. Display the screen. The data driving unit 320 is electrically coupled to the data line in the display unit 310 to provide the data signal to the data line. The scan driving unit 330 is electrically coupled to the scan line in the display unit 310 to provide the scan signal to the scan line.

如圖3所示，掃描驅動單元330包括有複數級移位暫存單元，如移位暫存單元100、移位暫存單元110...至移位暫存單元190所示。所述的移位暫存單元110...至移位暫存單元190可具有相同或類似於移位暫存單元100的架構。所述的第N級移位暫存單元100的輸出端分別電性耦接於顯示單元310與第N+1級的移位暫存單元110。所述的第N+1級移位暫存單元110的輸出端分別電性耦接於顯示單元310與第N+2級的移位暫存單元，以此類推串接至移位暫存單元190。As shown in FIG. 3, the scan driving unit 330 includes a plurality of stages of shift register units, such as the shift register unit 100, the shift register unit 110, ... to the shift register unit 190. The shift register unit 110... to the shift register unit 190 may have the same or similar architecture to the shift register unit 100. The output of the Nth stage shift register unit 100 is electrically coupled to the display unit 310 and the shift register unit 110 of the (N+1)th stage. The output of the N+1th stage shift register unit 110 is electrically coupled to the display unit 310 and the N+2 stage shift register unit, and so on to the shift register unit. 190.

如上所述，移位暫存單元100、移位暫存單元110與移位暫存單元190分別透過電壓源VSS接收第一電壓，並且透過電壓調整單元50取得所需的第二電壓。如圖3所示，時序控制單元340分別電性耦接於資料驅動單元320與掃描驅動單元330，以控制資料驅動單元320與掃描驅動單元330。As described above, the shift register unit 100, the shift register unit 110, and the shift register unit 190 receive the first voltage through the voltage source VSS, respectively, and the pass voltage adjustment unit 50 acquires the required second voltage. As shown in FIG. 3, the timing control unit 340 is electrically coupled to the data driving unit 320 and the scan driving unit 330 to control the data driving unit 320 and the scan driving unit 330.

綜上所述，本發明的移位暫存單元及其顯示裝置，透過本發明實施例揭露之電路設計使得驅動單元的開關元件於輸出下拉期間能維持關閉的狀態，藉以改善驅動單元的開關元件因為關閉電壓產生飄移而造成漏電流的問題。另外，本發明的移位暫存單元還透過電壓調整單元進一步縮小移位暫存電路的電路佈局面積。In summary, the shift register unit of the present invention and the display device thereof are designed such that the switching elements of the driving unit can be maintained in a closed state during the output pull-down period, thereby improving the switching elements of the driving unit. The problem of leakage current is caused by the drift of the off voltage. In addition, the shift register unit of the present invention further reduces the circuit layout area of the shift register circuit through the voltage adjusting unit.

雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10‧‧‧上拉單元10‧‧‧Upper pull unit

11‧‧‧第一端11‧‧‧ first end

13‧‧‧控制端13‧‧‧Control terminal

15‧‧‧第二端15‧‧‧second end

100‧‧‧移位暫存單元100‧‧‧Shift register unit

101‧‧‧移位暫存單元101‧‧‧Shift register unit

102‧‧‧移位暫存單元102‧‧‧Shift register unit

110‧‧‧移位暫存單元110‧‧‧Shift register unit

190‧‧‧移位暫存單元190‧‧‧Shift register unit

20‧‧‧驅動單元20‧‧‧Drive unit

21‧‧‧第一端21‧‧‧ first end

23‧‧‧控制端23‧‧‧Control terminal

25‧‧‧第二端25‧‧‧ second end

30‧‧‧第一控制單元30‧‧‧First Control Unit

300‧‧‧顯示裝置300‧‧‧ display device

310‧‧‧顯示單元310‧‧‧Display unit

320‧‧‧資料驅動單元320‧‧‧Data Drive Unit

330‧‧‧掃描驅動單元330‧‧‧Scan Drive Unit

340‧‧‧時序控制單元340‧‧‧Sequence Control Unit

33a‧‧‧第一下拉單元33a‧‧‧First pulldown unit

40‧‧‧第二控制單元40‧‧‧Second control unit

43a‧‧‧第二下拉單元43a‧‧‧Secondary pull-down unit

50‧‧‧電壓調整單元50‧‧‧Voltage adjustment unit

C‧‧‧儲能單元C‧‧‧ Energy storage unit

D1‧‧‧二極體D1‧‧‧ diode

G(n)‧‧‧第一掃描訊號G(n)‧‧‧ first scan signal

G(n+1)‧‧‧第二掃描訊號G(n+1)‧‧‧second scan signal

G(n-1)‧‧‧第三掃描訊號G(n-1)‧‧‧ third scan signal

HC1‧‧‧第一時脈訊號HC1‧‧‧ first clock signal

HC2‧‧‧第二時脈訊號HC2‧‧‧ second clock signal

LC1‧‧‧第一系統時脈訊號LC1‧‧‧ first system clock signal

LC2‧‧‧第二系統時脈訊號LC2‧‧‧Second system clock signal

T1‧‧‧開關元件T1‧‧‧ switching components

10a‧‧‧開關元件10a‧‧‧Switching elements

10b‧‧‧開關元件10b‧‧‧Switching elements

20a‧‧‧開關元件20a‧‧‧Switching elements

33a‧‧‧開關元件33a‧‧‧Switching elements

43a‧‧‧開關元件43a‧‧‧Switching elements

30a~30f‧‧‧開關元件30a~30f‧‧‧Switching elements

40a~40f‧‧‧開關元件40a~40f‧‧‧Switching elements

Q(n)‧‧‧第一驅動電壓Q(n)‧‧‧First drive voltage

Q(n-1)‧‧‧第二驅動電壓Q(n-1)‧‧‧second drive voltage

VSS‧‧‧電壓源VSS‧‧‧voltage source

圖1A繪示為本發明實施例之移位暫存電路之示意圖。FIG. 1A is a schematic diagram of a shift temporary storage circuit according to an embodiment of the present invention.

圖1B繪示為本發明實施例之電壓調整單元之電路示意圖。FIG. 1B is a schematic circuit diagram of a voltage adjustment unit according to an embodiment of the present invention.

圖1C繪示為本發明實施例之電壓調整單元之另一電路示意圖。FIG. 1C is a schematic diagram of another circuit of a voltage adjustment unit according to an embodiment of the present invention.

圖2繪示為本發明實施例之控制時序示意圖。2 is a schematic diagram of control timing according to an embodiment of the present invention.

圖3繪示為本發明實施例之顯示裝置的示意圖。FIG. 3 is a schematic diagram of a display device according to an embodiment of the invention.

10‧‧‧上拉單元10‧‧‧Upper pull unit

100‧‧‧移位暫存單元100‧‧‧Shift register unit

20‧‧‧驅動單元20‧‧‧Drive unit

21‧‧‧第一端21‧‧‧ first end

23‧‧‧控制端23‧‧‧Control terminal

25‧‧‧第二端25‧‧‧ second end

30‧‧‧第一控制單元30‧‧‧First Control Unit

33‧‧‧第一下拉單元33‧‧‧First pulldown unit

40‧‧‧第二控制單元40‧‧‧Second control unit

43‧‧‧第二下拉單元43‧‧‧Secondary pull-down unit

50‧‧‧電壓調整單元50‧‧‧Voltage adjustment unit

G(n)‧‧‧第一掃描訊號G(n)‧‧‧ first scan signal

G(n+1)‧‧‧第二掃描訊號G(n+1)‧‧‧second scan signal

G(n-1)‧‧‧第三掃描訊號G(n-1)‧‧‧ third scan signal

HC1‧‧‧第一時脈訊號HC1‧‧‧ first clock signal

HC2‧‧‧第二時脈訊號HC2‧‧‧ second clock signal

LC1‧‧‧第一系統時脈訊號LC1‧‧‧ first system clock signal

LC2‧‧‧第二系統時脈訊號LC2‧‧‧Second system clock signal

10a‧‧‧開關元件10a‧‧‧Switching elements

10b‧‧‧開關元件10b‧‧‧Switching elements

20a‧‧‧開關元件20a‧‧‧Switching elements

33a‧‧‧開關元件33a‧‧‧Switching elements

43a‧‧‧開關元件43a‧‧‧Switching elements

30a~30f‧‧‧開關元件30a~30f‧‧‧Switching elements

40a~40f‧‧‧開關元件40a~40f‧‧‧Switching elements

Q(n)‧‧‧第一驅動電壓Q(n)‧‧‧First drive voltage

Q(n-1)‧‧‧第二驅動電壓Q(n-1)‧‧‧second drive voltage

VSS‧‧‧電壓源VSS‧‧‧voltage source

Claims (10)

一種移位暫存電路，包含複數級移位暫存單元，其中每一該些移位暫存單元包含：一上拉單元，用以依據一第一時脈訊號，一第三掃描訊號，以及一第二驅動電壓，輸出一第一驅動電壓；一驅動單元，具有一第一端用以接收與該第一時脈訊號相位相反的一第二時脈訊號、一控制端電性耦接於該上拉單元，與一第二端用以輸出一第一掃描訊號；一電壓調整單元，具有一電性耦接於一電壓源的輸入端以及一輸出一第二電壓的輸出端；一第一控制單元，電性耦接於該驅動單元的控制端與該電壓源，用以依據一第一系統時脈訊號，使該驅動單元的控制端的電位被下拉至該電壓源的一第一電壓；一第一下拉單元，具有一第一端電性耦接於該驅動單元的第二端，一第二端電性耦接於該電壓調整單元的輸出端，以及一控制端用以接收一第二掃描訊號；一第二控制單元，電性耦接於該驅動單元的控制端與該電壓源，用以依據一第二系統時脈訊號，使該驅動單元的控制端的電位被下拉至該第一電壓；以及一第二下拉單元，具有一第一端電性耦接於該驅動單元的控制端，一第二端電性耦接於該電壓調整單元的輸出端，以及一控制端用以接收該第二掃描訊號。A shift register circuit includes a plurality of shift register units, wherein each of the shift register units includes: a pull-up unit for performing a third scan signal according to a first clock signal, and a second driving voltage, outputting a first driving voltage; a driving unit having a first end for receiving a second clock signal opposite to the phase of the first clock signal, and a control terminal electrically coupled to the The pull-up unit and the second end are configured to output a first scan signal; a voltage adjustment unit having an input electrically coupled to a voltage source and an output outputting a second voltage; a control unit electrically coupled to the control terminal of the driving unit and the voltage source for causing a potential of the control terminal of the driving unit to be pulled down to a first voltage of the voltage source according to a first system clock signal a first pull-down unit having a first end electrically coupled to the second end of the drive unit, a second end electrically coupled to the output of the voltage adjustment unit, and a control end for receiving a second scan signal; a second control And electrically coupled to the control end of the driving unit and the voltage source for causing the potential of the control end of the driving unit to be pulled down to the first voltage according to a second system clock signal; and a second pulldown The unit has a first end electrically coupled to the control end of the driving unit, a second end electrically coupled to the output end of the voltage adjusting unit, and a control end for receiving the second scanning signal. 如申請專利範圍第1項所述之移位暫存電路，其中該第一掃描訊號係為第N級掃描訊號，該第二掃描訊號係為第N+1 級掃描訊號，且該第三掃描訊號係為第N-1級掃描訊號。The shift register circuit of claim 1, wherein the first scan signal is an Nth scan signal, and the second scan signal is an N+1 The level scan signal, and the third scan signal is the N-1th scan signal. 如申請專利範圍第2項所述之移位暫存電路，其中該電壓調整單元係為一開關元件，具有一第一端電性耦接於該電壓源，一第二端用以輸出該第二電壓，一控制端電性耦接於該開關元件的該第二端。The shift register circuit of claim 2, wherein the voltage adjusting unit is a switching element having a first end electrically coupled to the voltage source and a second end outputting the first The second voltage is electrically coupled to the second end of the switching element. 如申請專利範圍第2項所述之移位暫存電路，其中該電壓調整單元係為一二極體，具有一正極端與一負極端，該二極體的負極端電性耦接於該電壓源，該二極體的正極端用以輸出該第二電壓。The shift register circuit of claim 2, wherein the voltage adjusting unit is a diode having a positive terminal and a negative terminal, and the negative terminal of the diode is electrically coupled to the diode A voltage source, the positive terminal of the diode is used to output the second voltage. 如申請專利範圍第3或4項所述之移位暫存電路，其中該第二電壓的電位高於該第一電壓的電位。The shift register circuit of claim 3, wherein the potential of the second voltage is higher than the potential of the first voltage. 一種顯示裝置，包括有：一顯示單元，用以分別接收複數個掃描訊號與複數個資料訊號，以顯示畫面；一資料驅動單元，電性耦接於該顯示單元，該資料驅動單元用以提供該些資料訊號至該顯示單元中之複數條資料線；一掃描驅動單元，電性耦接於該顯示單元，該掃描驅動單元用以提供該些掃描訊號至該顯示單元中之複數條掃描線；一時序控制單元，分別電性耦接於該資料驅動單元與該掃描驅動單元，用以控制該資料驅動單元與該掃描驅動單元；其中該掃描驅動單元包括有複數級移位暫存單元，每一該些移位暫存單元包括有： 一上拉單元，用以依據一第一時脈訊號，一第三掃描訊號，以及一第二驅動電壓，輸出一第一驅動電壓；一驅動單元，具有一第一端用以接收與該第一時脈訊號相位相反的一第二時脈訊號、一電性耦接於該上拉單元之控制端，與一輸出一第一掃描訊號之第二端；一電壓調整單元，一電性耦接於一電壓源的輸入端以及一輸出端用以輸出一第二電壓；一第一控制單元，電性耦接於該驅動單元的控制端與該電壓源，用以依據一第一系統時脈訊號，使該驅動單元的控制端的電位被下拉至該電壓源的一第一電壓；一第一下拉單元，具有一電性耦接於該驅動單元的第二端的第一端，一電性耦接於該電壓調整單元的輸出端的第二端，以及一接收一第二掃描訊號的控制端；一第二控制單元，電性耦接於該驅動單元的控制端與該電壓源，用以依據一第二系統時脈訊號，使該驅動單元的控制端的電位被下拉至該第一電壓；及一第二下拉單元，具有一電性耦接於該驅動單元的控制端的第一端，一電性耦接於該電壓調整單元的輸出端的第二端，以及一接收該第二掃描訊號的控制端。A display device includes: a display unit for receiving a plurality of scan signals and a plurality of data signals respectively for displaying a picture; a data driving unit electrically coupled to the display unit, the data driving unit for providing The data is transmitted to the plurality of data lines in the display unit; the scan driving unit is electrically coupled to the display unit, and the scan driving unit is configured to provide the scan signals to the plurality of scan lines in the display unit a timing control unit electrically coupled to the data driving unit and the scan driving unit for controlling the data driving unit and the scan driving unit; wherein the scan driving unit comprises a plurality of shift register units, Each of the shift register units includes: a pull-up unit for outputting a first driving voltage according to a first clock signal, a third scan signal, and a second driving voltage; a driving unit having a first end for receiving a second clock signal having a phase opposite to a clock signal, electrically coupled to the control terminal of the pull-up unit, and a second end of the output first scan signal; a voltage adjustment unit, an electrical coupling An input terminal connected to a voltage source and an output terminal for outputting a second voltage; a first control unit electrically coupled to the control terminal of the driving unit and the voltage source for using a first system a pulse signal, the potential of the control terminal of the driving unit is pulled down to a first voltage of the voltage source; a first pull-down unit having a first end electrically coupled to the second end of the driving unit, a second end connected to the output end of the voltage adjusting unit, and a control end receiving a second scanning signal; a second control unit electrically coupled to the control end of the driving unit and the voltage source, Based on a second system clock signal The potential of the control terminal of the driving unit is pulled down to the first voltage; and a second pull-down unit has a first end electrically coupled to the control end of the driving unit, and is electrically coupled to the voltage adjusting unit The second end of the output end and a control end that receives the second scan signal. 如申請專利範圍第6項所述之顯示裝置，其中第N條掃描線電性連接至該第一掃描訊號，第N+1條掃描線電性連接至該第二掃描訊號，且第N-1條掃描線電性連接至該第三掃描訊號。The display device of claim 6, wherein the Nth scan line is electrically connected to the first scan signal, and the (N+1)th scan line is electrically connected to the second scan signal, and the Nth One scan line is electrically connected to the third scan signal. 如申請專利範圍第7項所述之顯示裝置，其中該電壓調 整單元係為一開關元件，具有一電性耦接於該電壓源的第一端，一輸出該第二電壓的第二端，一電性耦接於該開關元件的第二端的控制端。The display device of claim 7, wherein the voltage is adjusted The whole unit is a switching element having a first end electrically coupled to the voltage source, a second end outputting the second voltage, and a second end electrically coupled to the control end of the second end of the switching element. 如申請專利範圍第7項所述之顯示裝置，其中該電壓調整單元係為一二極體，具有一正極端與一負極端，該二極體的負極端電性耦接該電壓源，該二極體的正極端用以輸出該第二電壓。The display device of claim 7, wherein the voltage adjustment unit is a diode having a positive terminal and a negative terminal, and the negative terminal of the diode is electrically coupled to the voltage source. The positive terminal of the diode is used to output the second voltage. 如申請專利範圍第8或9項所述之顯示裝置，其中該第二電壓的電位高於該第一電壓的電位。The display device of claim 8 or 9, wherein the potential of the second voltage is higher than the potential of the first voltage.
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