TWI393190B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI393190B
TWI393190B TW095124581A TW95124581A TWI393190B TW I393190 B TWI393190 B TW I393190B TW 095124581 A TW095124581 A TW 095124581A TW 95124581 A TW95124581 A TW 95124581A TW I393190 B TWI393190 B TW I393190B
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Hongning Yang
Jiang-Kai Zuo
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Freescale Semiconductor Inc
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Description

半導體裝置及其製造方法
本發明大體而言係關於半導體裝置及用於製造半導體裝置之方法，且特定言之係關於具有低導通電阻(Rdson)之深次微米場效電晶體。
藉由使用複數個互連件之場效應電晶體(FET)(亦稱為金屬氧化物半導體場效應電晶體(MOSFET)或簡稱為MOS電晶體)建構用於形成積體電路(IC)之製程技術及裝置結構。一典型MOS電晶體包括一作為控制電極之閘電極及間隔分開的源電極及汲電極，電流可在源電極與汲電極之間流動。施加至閘電極之控制電壓控制流經源電極與汲電極之間的一通道之電流的流動。隨著積體電路複雜性之增加，需要越來越多之MOS電晶體來建構積體電路功能。因而，減小個別MOS電晶體之大小以達成一具合理大小且能可靠地製造之積體電路變得重要。最重要的是，減小IC之尺寸使每個晶圓上之IC晶片之數量的增加，此方法已成為半導體IC工業中降低製造成本之最有效途徑。
當需要一~5V操作位準以保持訊號擺動範圍及訊雜比時，無線應用通常使用4.5－5.5 V的功率MOSFET。0.13 μm技術中對於深次微米~5 V功率場效電晶體之要求如下：(1)低導通電阻及高驅動電流(大於50%之縮放比例)；(2)低關閉狀態漏電流<1－10 pA/μm；(3)抗熱載子注入(HCI)損害之高可靠性及(4)將生產流程限制於0.18 μm或0.13 μm CMOS平臺之限制。
在當前條件下，若採用廣泛用於0.5 μm(或以上)平臺之習知結構，則在0.13 μm技術平臺中製造深次微米~5 V功率MOSFET可面臨主要挑戰。例如，由於由HCI損害引起之可靠性問題，習知之基於隔片之具有輕微摻雜的汲極(LDD)之MOSFET具有~0.5 μm之通道長度限制。為充分減少操作於5 V下的損害，閘極長度不得不增加至0.5 μm或以上。此外，可將習知之環形－源極(HS－GOLD)及閘極覆蓋之LDD汲極(GOLD)MOSFET縮小至深次微米，但由於HCI問題及擊穿問題兩者，操作電壓不得不降低至3.5 V以下。較佳之HCI性能要求較長的GOLD，此較長的GOLD要求額外的熱驅入循環。此在熱預算非常有限之0.13 μm CMOS生產流程中係不可能的。
習知之LDMOS(橫向雙擴散MOS)可在較高電壓下工作，然而，該製造製程中之兩個主要困難阻礙了將LDMOS等比例縮小至深次微米區域。在一類型之LDMOS加工中，通道長度係由非自對準離子植入界定。為滿足未對準容許度之微影要求，必須考慮一足夠之邊緣，此邊緣設定此類型之LDMOS的~0.5 μm之限制。在一第二類型之LDMOS加工中，首先藉由以複晶矽閘極(poly gate)作為遮罩之自對準植入且接著藉由後續的熱驅入以使摻雜劑擴散至通道內來進行通道摻雜。雖然此類型之LDMOS提供一較小裝置，但額外熱驅入循環之使用與熱預算非常有限之標準0.13 μm CMOS生產流程係不相容的。通常，此類型之LDMOS不能在任何先進的基於CMOS技術平臺中製造。
據推斷，由於製造製程問題(熱預算或未對準)或裝置可靠性問題(HCI或擊穿)之任一者，0.5 μm平臺中使用之~5 V MOSFET的習知結構不能縮放至0.5 μm以下。因此，需要提供一種新型的深次微米半導體裝置，且更特定言之需要提供一種具有~5 V之工作電壓之深次微米功率MOSFET。另外，需要提供一種用於製造深次微米功率MOSFET的方法，該深次微米功率MOSFET允許在~5 V範圍中工作而不會在於0.13 μm技術平臺中建置時招致任何額外的製程步驟。此外，結合伴隨圖式及本發明之此先前技術，本發明之其它所欲特徵及特性將自隨後的本發明之詳細描述及所附申請專利範圍變得明顯。
本發明之以下詳細描述實質上僅為示範性的且不意欲限制本發明或本發明之應用及使用。此外，不意欲藉由本發明之前述背景中提出之任何理論或本發明之以下詳細描述約束本發明。
圖1以截面圖示範地說明一根據本發明之一實施例之MOS電晶體100。MOS電晶體100包括一形成於一矽基板101之一表面上的非常輕微摻雜的磊晶(EPI)層102。一閘極絕緣體104係形成於該EPI表面上。一閘電極106係形成於閘極絕緣體104上。一源極區108及一汲極區110係藉由引入適合之雜質確定摻雜劑(諸如用於n通道MOS電晶體之砷或磷，或用於p通道MOS電晶體之硼)而形成於磊晶層102中。一閘極覆蓋之LDD(GOLD)區域112係形成於汲極110處。一環形(擊穿)植入區114係形成於源極108處。藉由分離GOLD區域112與環形植入區114，達成熱載子可靠性之獨立最優化及由汲極誘發之能障降低(DIBL)效應引起之表面(通道)擊穿之耐受性。
MOS電晶體100進一步包含一形成於一閘電極106之源極側邊緣處且對準該邊緣的p井116。在閘電極106周圍提供複數個隔片120。在MOS電晶體100中使用非常輕微摻雜的磊晶層102顯著增強耐HCI損害性，而p井116之加入防止源極與汲極之間的塊體擊穿(bulk punchthrough)。藉由組合側面p井與源極側環形植入區，表面及塊體擊穿兩者皆得以防止且顯著減小Vd~5 V下之關閉狀態漏電流。以先進0.13 μm技術將MOS電晶體100製造為深次微米(<0.3 μm)~5 V功率MOSEFET。因不需要在標準0.13 μm生產流程中所使用之彼等製程步驟或遮罩層之外的額外製程步驟或遮罩層，所以該製造係具成本效益的。自該新穎結構，可獲得一超低的導通電阻同時保持漏電流為低。
圖2－8說明根據本發明之一實施例之用於製造半導體裝置(諸如MOS電晶體100)之方法步驟。圖2－8說明用於MOS電晶體100之摻雜之特定類型及含量。應瞭解，反向摻雜類型及變化之摻雜含量係此揭示所期待的。儘管可使用類似方法步驟製造在雜質確定摻雜劑類型上有適合之改變的P通道MOS電晶體，但圖2－8中所說明之MOS電晶體100為N通道MOS電晶體。同樣，類似方法步驟可用於製造互補MOS(CMOS)電晶體。因MOS電晶體之製造中之多種步驟係已知的，所以為簡便起見，在本文中僅簡短提及許多習知之步驟或完全忽略該等步驟而不提供熟知之製程細節。雖然術語"MOS裝置"嚴格地指具有一金屬閘電極及一氧化物閘極絕緣體之裝置，但彼術語將廣泛用於指代任何半導體裝置，該半導體裝置包括一定位於一閘極絕緣體(氧化物或其它絕緣體)上之導電閘電極(其反過來係定位於一半導體基板上)。
圖2說明根據本發明之一實施例之MOS電晶體100之製造，其中該製程開始於提供半導體基板101(該基板具有形成於其上之輕微摻雜的磊晶層102)。在此較佳實施例中，磊晶層102經非常輕微的p摻雜，諸如用濃度在~2×101 4 /cm3 及~2×101 5 /cm3 之間的硼。與一典型P基板相比，磊晶層102提供經改良之HIC抑制。
圖3說明P井116之製造。在形成NMOS 100時，藉由硼之高能量植入(如箭頭123所指示)形成P井116。在一替代實施例中，以藉由磷之高能量植入形成之n井取代p井116以形成一PMOS。將P井116摻雜至一介於1×101 7 /cm3 至8×101 7 /cm3 範圍內之近似濃度，其中摻雜濃度越高，p井116防止塊體擊穿之能力越佳。為準備p井116之高能量植入，在磊晶層102之一部分上沈積一層圖3中所說明之光阻122。一旦p井116形成，即移除光阻122。
圖4說明形成於輕微摻雜的磊晶層102之一表面上之閘極絕緣體104。閘極絕緣體104可為一藉由在氧化環境中加熱基板102所形成之熱成長二氧化矽，或其可為一沈積絕緣體(諸如氧化矽、氮化矽、氮氧化矽)、一高介電常數絕緣體(諸如HfSiO)或其類似物。沈積絕緣體可藉由化學氣相沈積(CVD)、低壓化學氣相沈積(LPCVD)、電漿增強化學氣相沈積(PECVD)或原子層沈積(ALD)來沈積。視閘極及汲極工作電壓而定，閘極絕緣體104通常為1－50奈米(nm)厚。
根據本發明之一實施例，接下來將一層(較佳為多晶矽)沈積至閘極絕緣體104上。雖然該多晶矽層可沈積為一雜質摻雜層，但其較佳沈積為一未摻雜的多晶矽且隨後藉由離子植入予以雜質摻雜。可將一硬式遮罩材料(未圖示)(諸如氧化矽、氮化矽或氮氧化矽)沈積至該多晶矽之表面上，以幫助隨後之圖案化多晶矽。可藉由LPCVD經矽烷(SiH4 )之氫還原作用，將多晶矽材料沈積至約100 nm之厚度。亦可藉由LPCVD將該硬式遮罩材料沈積至約50 nm之厚度。
將硬式遮罩層、下伏的多晶矽之層及下伏的閘極絕緣體104之層光微影圖案化，以形成圖4中所說明之閘電極106。較佳地，閘電極106具有一與為用於設計積體電路(MOS電晶體100為其一部分)的設計規則所允許之最小線寬相等之寬度。可(例如)在Cl或HBr/O2 化學中藉由電漿蝕刻將多晶矽及閘極絕緣體蝕刻出所需圖案，且可(例如)在CHF3 、CF4 或SF6 化學中藉由電漿蝕刻來蝕刻該硬式遮罩。
現參看圖5，執行使用複數個光阻124及微影步驟之標準光微影製程，以為環形植入區114之製造作準備。環形植入區114充當裝置100中之源極擴展。在光阻124沈積之後，使MOS電晶體100接受一傾斜的單向離子植入製程。較佳地，除非環形植入區114較磊晶層102為更高之摻雜，否則使用與磊晶層102相同之摻雜材料(諸如鍺(Ge)、砷(As)、磷(P)、硼(B)及其類似物)之離子來執行該傾斜的單向離子植入。在此較佳實施例中，用硼離子將環形植入區114摻雜至一介於~5E1 8 cm3 至~6E1 8 cm3 範圍內之濃度水平。在此較佳實施例中，離子植入製程使用硼離子，該等硼離子以一自一垂直於磊晶層102之表面103之軸呈銳角α導向MOS電晶體100之表面103(即，最靠近源極區之表面)。較佳地，角α至少為7度之大小且小於約90度。在此較佳實施例中，該傾斜角植入係在45－60度之間執行以形成環形植入區114。在此較佳實施例中，可以約30 KeV之能量及以約5×101 8 /cm3 之植入摻雜濃度植入硼離子。應瞭解，因為該離子植入為單向且以一角度定向，所以離子得以植入至曝露於或朝向該等離子之源的MOS電晶體100之區域內。由於閘電極106充當遮罩，該傾斜植入得以導向閘電極106之源極側且形成一袋狀區域(被稱為環)。閘電極106進一步提供環形植入區114之自對準。如前所述，除非環形植入區104經極高摻雜，否則環形植入區114係由與磊晶層102相同之摻雜材料形成。在環形植入區114形成之後，由一磷材料形成一源極擴展(未圖示)，該磷材料係以約30 KeV之能量及一介於~5×101 8 /cm3 至~6×101 8 /cm3 範圍內之植入摻雜濃度水平呈0度角植入。接著，移除光阻124。
現參看圖6，執行使用複數個光阻126及微影步驟之標準光微影製程以為在裝置100之一汲極側上形成自對準輕微摻雜的汲極(LDD)植入區112作準備。LDD植入區112為一閘極覆蓋之LDD(GOLD)且提供優越的熱載子可靠性。LDD植入區112係由一可以約30 KeV之能量及以一介於~1×101 8 cm3 至~6×101 8 cm3 範圍內之植入摻雜濃度水平植入之磷材料形成。閘電極106在LDD植入區112之植入期間充當遮罩且提供LDD植入區112之自對準。在LDD植入區112形成之後，移除光阻126。
在圖案化閘電極106及形成環形植入區114及LDD植入區112之後，在閘電極106周圍沈積氮化物之一薄層且蝕刻該薄層以形成圖7中所說明之絕緣隔片120。接下來執行一快速熱退火(RTA)步驟以改良裝置100之特性，且進一步使LDD植入區112擴散至通道區域128內。應瞭解，在快速熱退火步驟期間，環形植入區114亦可進一步擴散至通道區域128內。將通道區域128定義為源極區108與汲極區110之間的磊晶層區域。
如圖8中所說明，閘電極106及絕緣隔片120可用作一離子植入遮罩以在磊晶層102中形成源極108及汲極110區域。藉由將閘電極106及絕緣隔片120用作一離子植入遮罩，源極區108、汲極區110及通道128得以與閘電極106自對準。對於N通道MOS電晶體而言，雖然亦可使用磷離子，但較佳藉由植入砷離子形成源極區及汲極區。源極區108及汲極區110為淺的且較佳具有小於約20 nm且最佳小於約5-10 nm之接面深度且經高雜質摻雜至每平方約10歐姆。
所提供的為一種製造一包括一半導體基板之半導體裝置之方法，該方法包含以下步驟：雜質摻雜該基板中之一區域以形成第一摻雜井；雜質摻雜該第一摻雜井之一部分內之一區域以形成一第二摻雜井；形成一閘電極，該閘電極覆蓋該基板之一表面且具有一形成於兩者之間的閘極介電質；以一自一垂直於該半導體基板之該表面之軸呈大於零之角度將一雜質離子選擇性植入至該第二摻雜井內，該雜質離子形成一與該閘電極自對準且處於該基板之一源極側上之環形植入區；雜質摻雜該第一摻雜井中之一區域以形成一與該閘電極自對準且處於該基板之一汲極側上之輕微摻雜的汲極(LDD)植入；雜質摻雜該環形植入區中之一區域；及雜質摻雜該輕微摻雜的汲極植入(LDD)中之一區域。雜質摻雜該基板中之一區域之該步驟包含植入包含一選自由鍺(Ge)、砷(As)、磷(P)及硼(B)組成之群的材料之離子之步驟。將一雜質離子選擇性植入至該第二摻雜井內之該步驟包含植入一包含一選自由鍺(Ge)、砷(As)、磷(P)及硼(B)組成之群的材料之離子之步驟。雜質摻雜該基板中之一區域以形成一第一摻雜井之該步驟包含以1×1015 /cm3 之一植入濃度植入硼之步驟。雜質摻雜該第一摻雜井之一部分內之一區域以形成一第二摻雜井之該步驟包含以15 K至500 KeV之能量及以一介於1×1017 /cm3 至2×1018 /cm3 範圍內 之植入濃度鏈式植入硼之步驟。將一雜質離子選擇性植入至該第二摻雜井內之該步驟包含以30 KeV之能量及以一介於5×1018 /cm3 至6×1018 /cm3 範圍內之植入濃度植入硼之步驟。雜質摻雜該第一摻雜井中之一區域以形成一輕微摻雜的汲極(LDD)植入之該步驟包含以30 KeV之能量及以一介於1×1018 /cm3 至5×1018 /cm3 範圍內之植入濃度植入硼之步驟。雜質摻雜該環形植入區中之一區域之該步驟包含形成一源極區，且在該輕微摻雜的汲極(LDD)植入中形成一雜質摻雜區域之該步驟包含形成一汲極區。
另外，所提供的為一種製造一包括一半導體基板之半導體裝置之方法，該方法包含以下步驟：沈積一摻雜材料以在該基板之一表面上形成一經摻雜之磊晶層；在該經摻雜之磊晶層中植入一雜質摻雜區域以形成一摻雜井；形成一閘電極，該閘電極覆蓋該基板之該表面且具有一形成於兩者之間的閘極介電質；以一自一垂直於該半導體基板之該表面之軸呈大於零之角度，將一雜質離子選擇性植入至該摻雜井內，該雜質離子形成一與該閘電極自對準且處於該基板之一源極側上之環形植入區；在該經摻雜磊晶層中植入一雜質摻雜區域，以形成一與該閘電極自對準且處於該基板之一汲極側上之輕微摻雜的汲極(LDD)植入；在該閘電極周圍形成一絕緣隔片；在該環形植入區中植入一源極區；及在該輕微摻雜的汲極植入(LDD)中植入一汲極區。將一雜質離子選擇性植入至該摻雜井內之該步驟包含：植入包含一選自由鍺(Ge)、砷(As)、磷(P)及硼(B)組成之群之材料的離子之步驟。沈積一摻雜材料以形成一經摻雜之磊晶層之該步驟包含：以2×101 4 至2×101 5 /cm之濃度沈積硼之步驟。在該經摻雜磊晶層中植入一雜質摻雜區域以形成一摻雜井之該步驟包含：以30 KeV之一能量及以一介於1×101 7 /cm3 至2×101 8 /cm3 範圍內之植入濃度植入硼之步驟。將一雜質離子選擇性植入至該摻雜井內之該步驟包含：以30 KeV之能量及以一介於5×101 8 /cm3 至6×101 8 /cm3 範圍內之植入濃度植入硼之步驟。在該經摻雜磊晶層中植入一雜質摻雜區域以形成一輕微摻雜的汲極(LDD)植入之該步驟包含：以30 KeV之能量及以一介於1×101 8 /cm3 至5×101 8 /cm3 範圍內之植入濃度植入硼之步驟。
最後，所提供的為一種包括一具有一表面之半導體基板之半導體裝置，該半導體裝置包含：一形成於該基板之該表面上的經摻雜磊晶層；一安置為覆蓋該經摻雜磊晶層之閘電極；一安置於該經摻雜磊晶層內且自該閘電極部分偏移之第一雜質摻雜區域；一安置於該第一雜質摻雜區域內之第二雜質摻雜區域；一安置於該經摻雜磊晶層內且自該閘電極部分偏移之第三雜質摻雜區域；一形成於該第二雜質摻雜區域中之源極區；及一形成於該第三雜質摻雜區域中之汲極區。該經摻雜磊晶層具有2×101 5 /cm3 之摻雜濃度。該第一雜質摻雜區域為一形成於該經摻雜磊晶層中之井區域且具有一介於1×101 7 /cm3 至8×101 7 /cm3 範圍內之摻雜濃度。該第二雜質摻雜區域為一環形植入區且具有一介於5×101 8 /cm3 至6×101 8 /cm3 範圍內之摻雜濃度。該第三雜質摻雜區域為一閘極覆蓋之低摻雜汲極(GOLD)且具有一介於1×101 8 /cm3 至5×101 8 /cm3 範圍內之摻雜濃度。一選自由鍺(Ge)、砷(As)、磷(P)及硼(B)組成之群之摻雜材料提供該經摻雜磊晶層、該第一雜質摻雜區域、該第二雜質摻雜區域、該第三雜質摻雜區域、該源極區及該汲極區之摻雜。
雖然在本發明之以上詳細描述中已給出至少一示範性實施例及製造方法，但應瞭解，存在大量變化。亦應瞭解，該或該等示範性實施例僅為實例，而不意欲以任何方式限制本發明之範疇、適用性或組態。相反，以上的詳細描述將向熟悉此項技術者提供一實施本發明之一示範性實施例的便捷線路圖，應瞭解，可在不背離如所附申請專利範圍及其合法均等物中提出之本發明之範疇的情況下，對示範性實施例中描述之元件的功能及配置做出多種改變。
100．．．MOS電晶體
101．．．半導體基板
102．．．磊晶層
103．．．表面
104．．．閘極絕緣體
106．．．閘電極
108．．．源極區
110．．．汲極區
112．．．LDD植入區
114．．．植入區
116．．．p井
120．．．隔片
122．．．光阻
123．．．箭頭
124．．．光阻
126．．．光阻
128．．．通道
圖1以截面圖示範地說明一根據本發明之一示範性實施例之半導體裝置；且圖2－8以截面圖示範地說明根據本發明之一示範性實施例相之用於製造圖1之半導體裝置的方法步驟。
100．．．MOS電晶體
101．．．半導體基板
102．．．磊晶層
104．．．閘極絕緣體
106．．．閘電極
108．．．源極區
110．．．汲極區
112．．．LDD植入區
114．．．植入區
116．．．p井
120．．．隔片

Claims (13)

  1. 一種製造一包括一具有一摻雜一第一種摻雜材料之磊晶層之半導體基板之半導體裝置之方法，該方法包含以下步驟：以該第一種摻雜材料雜質摻雜該基板中之一第一區域以在該基板之一源極側上形成一第一摻雜井；形成一閘電極，該閘電極覆蓋該基板之一表面且具有一形成於兩者之間的閘極介電質；藉由沈積光阻在該基板之一汲極側上形成一在該基板之該源極側上之環型植入區，且以一自一垂直於該半導體基板之該表面之軸呈大於零之角度，將該第一種摻雜材料之一雜質離子選擇性植入至該第一摻雜井中，該雜質離子形成該與該閘電極自對準且處於該基板之該源極側上之環形植入區；以一第二種摻雜材料在該基板上之一汲極側上雜質摻雜一第二區域，以在該基板之該汲極側上形成一與該閘電極自對準的輕微摻雜的汲極植入，其中雜質摻雜該第二區域係經由在該基板之該源極側上之一光阻執行；雜質摻雜該環形植入區中之一第三區域以形成一源極區域；及雜質摻雜該輕微摻雜的汲極植入中之一第四區域以形成一汲極區域，其中該環型植入區及該輕微摻雜的汲極植入延伸超過該源極區域及該汲極區域並延伸至一在該源極區域及該汲極區域間的通道區域。
  2. 如請求項1之方法，其中雜質摻雜該基板中之一第一區域之該步驟包含：植入包含一選自由鍺(Ge)、砷(As)、磷(P)及硼(B)組成之群之材料的離子之步驟。
  3. 如請求項1之方法，其中形成該環型植入區之該步驟包含：植入包含一選自由鍺(Ge)、砷(As)、磷(P)及硼(B)組成之群之材料的雜質離子之步驟。
  4. 如請求項1之方法，其中雜質摻雜該基板中之一第一區域以形成一第一摻雜井之該步驟包含：以1×1015 /cm3 之一植入濃度植入硼之步驟。
  5. 如請求項1之方法，其進一步包含藉由以15 K至500 KeV之能量及以一介於1×1017 /cm3 至2×1018 /cm3 範圍內之植入濃度鏈式植入硼以雜質摻雜該第一摻雜井之一部分內之一區域以形成一第二摻雜井之該步驟。
  6. 如請求項1之方法，其中形成該環型植入區之該步驟包含：以30 KeV之一能量及以一介於5×1018 /cm3 至6×1018 /cm3 範圍內之植入濃度植入硼之步驟。
  7. 如請求項1之方法，其中雜質摻雜一第二區域以形成一輕微摻雜的汲極植入之該步驟包含：以30 KeV之一能量及以一介於1×1018 /cm3 至5×1018 /cm3 範圍內之植入濃度植入硼之步驟。
  8. 一種製造一包括一半導體基板之半導體裝置之方法，該方法包含以下步驟：沈積一第一種摻雜材料以在該基板之一表面上形成一經摻雜磊晶層； 在該經摻雜磊晶層中植入一第一雜質摻雜區域以形成在該基板之一源極側上之該第一種摻雜材料之一摻雜井；形成一閘電極，該閘電極覆蓋該基板之該表面且具有一形成於兩者之間的閘極介電質；藉由沈積光阻在該基板之一汲極側上形成一在該基板之該源極側上之環型植入區，且以一自一垂直於該半導體基板之該表面之軸呈大於零之角度，選擇性植入該第一種摻雜材料之一雜質離子至該摻雜井內，該雜質離子形成該與該閘電極自對準且在該基板之該源極側上之環形植入區；在該基板之一汲極側上之該經摻雜磊晶層中植入一第二雜質摻雜區域，以在該基板之該汲極側上形成一與該閘電極自對準之一第二種摻雜材料之輕微摻雜的汲極植入，其中植入該第二雜質摻雜區域係經由在該基板之該源極側上之一光阻執行；在該閘電極周圍形成一絕緣隔片；在該環形植入區中植入一源極區；及在該輕微摻雜的汲極植入中植入一汲極區，其中該環型植入區及該輕微摻雜的汲極植入延伸超過該源極區域及該汲極區域並延伸至一在該源極區域及該汲極區域間的通道區域。
  9. 如請求項8之方法，其中形成一環型植入區之該步驟包含：植入包含一選自由鍺(Ge)、砷(As)、磷(P)及硼(B)組 成之群之材料的離子之步驟。
  10. 如請求項8之方法，其中沈積一第一種摻雜材料以形成一經摻雜磊晶層之該步驟包含：以2×1014 至2×1015 /cm3 之一濃度沈積硼之步驟。
  11. 如請求項8之方法，其中在該經摻雜磊晶層中植入一第一雜質摻雜區域以形成一摻雜井之該步驟包含：以30 KeV之一能量及以一介於1×1017 /cm3 至2×1018 /cm3 範圍內之植入濃度植入硼之步驟。
  12. 如請求項8之方法，其中形成一環型植入區之該步驟包含：以30 KeV之一能量及以一介於5×1018 /cm3 至6×1018 /cm3 範圍內之植入濃度植入硼之步驟。
  13. 如請求項8之方法，其中在該經摻雜磊晶層中植入一第二雜質摻雜區域以形成一輕微摻雜的汲極植入之該步驟包含：以30 KeV之一能量及以一介於1×1018 /cm3 至5×1018 /cm3 範圍內之植入濃度植入硼之步驟。
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