TWI343113B - Method for manufacturing substrate embedded with chip - Google Patents

Method for manufacturing substrate embedded with chip Download PDF

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Publication number
TWI343113B
TWI343113B TW096131046A TW96131046A TWI343113B TW I343113 B TWI343113 B TW I343113B TW 096131046 A TW096131046 A TW 096131046A TW 96131046 A TW96131046 A TW 96131046A TW I343113 B TWI343113 B TW I343113B
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Taiwan
Prior art keywords
prepreg
wafer
layer
circuit layer
manufacturing
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TW096131046A
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Chinese (zh)
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TW200910558A (en
Inventor
Wen Sung Chang
Jiang Wen Kung
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Priority to TW096131046A priority Critical patent/TWI343113B/en
Publication of TW200910558A publication Critical patent/TW200910558A/en
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Publication of TWI343113B publication Critical patent/TWI343113B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

1343113 九、發明說明： - 【發明所屬之技術領域】 本發明係關於一種嵌埋有晶片的基板之製作方法，尤 指一種適用於在製作時固定晶片之基板的製作方法。 5 【先前技術】 一般半導體封裝之製程，首先係將半導體晶片以非主 動面黏貼於基板頂面，進行打線接合（wire bonding)，或將 晶片以覆晶接合（Flip chip)方式與電路板電性連接墊電性 10連接。再於電路板之背面植以錫球，以電性連接至如印刷 電路板之外部電子裝置。如此，雖可達到高腳數的目的， 但是在更高頻使用時或高速操作時，其將因電性連接路徑 過長而產生電氣特性之效能無法提昇，而有所限制。另外^ 因傳統封裝需要封膠及多次的連接介面，相對地增加製程 15 之複雜度。 為此，許多研究採用將晶X埋入基板内，該嵌埋於基 # 板中之晶片係可直接與基板内層線路導通，用以縮短電 傳導路徑’並可減少訊號損失、訊號失真及提昇高速 之能力。 20 一般習知將晶片嵌埋至基板的方法，請參考圖丨，首 先，提供一第一介電層U，並在第-介電層11表面形成一 具有開口 12丨之核心板12。接著，於核心板12的開口 121内 形成-貼合層13，再將晶片14置放並暫時固定於貼合層η 表面(或將該晶片Μ之非主動面貼附一貼合層13,再將二 5 1343113 U附於第-介電層11表面），其中，該晶片14的主動面上 具有複數個電極墊⑷。然後，於開口 121内填入黏著層15 以元全固定此晶片14。繼之’於晶片14的主動面以及核心 板12的表面形成一第二介電層161，並於第二介電層16〗表 5面形成有線路層162，並且，該線路層162經由導電盲孔163 而與晶片14之電極墊141電性導通。因此完成習知之晶片後 埋至基板之方法。 然而，習知之方法中，係先需將開口 121内形成一貼合 ❿層13(或將該晶片14表面預先貼附一貼合層13)，並且將晶月 10 14暫時固定之後仍需另外使用-黏著材料(黏著層15)以將 曰曰片14¾入埋並凡全固定於核心板丨2之中。此種方式不但繁 雜，而且需要使用多種材料，才可將晶片14嵌埋並固定於 基板中，相當費時與耗材。若直接省略形成貼合層13的步 驟，則將晶片14無法暫時先固定於第一介電層⑽表面， 15而^易滑動，進而在進行後續製程時，會有開盲孔對位的 問題產生。因此，如何降低製程成本以及時效實係為在 馨 進行將晶片嵌埋至基板的方法中的一重要課題。 【發明内容】 20 有鑑於習知之缺點，本發明係提供一種嵌埋有晶片的 基板之製作方法，包括：首先，提供一第一預浸材 (prepreg)’其一側表面形成有一第一金屬層。接著，於該 第一預浸材另一側表面形成一具有開口之核心板。然後， 加熱一晶片，並將該晶片置放於該核心板之該開口内，該 6 1343113 • 可為選自絕緣板、具有線路層之電路板及金屬板所組群組 之一者。而第一預浸材與該第二預浸材較佳地分別為選自 - 由 ABF(Ajinomoto Build-up Film)、雙順丁 醯二酸醯亞胺 /三 說牌（Bismaleimide triazine ; BT)、聯二笨環 丁二缔 5 (benzocylobutene ; BCB)、液晶聚合物（Liquid cryyy Polymer)、聚亞醯胺（Polyimide ; PI)、聚乙烯醚（P〇ly (phenylene ether))、聚四氟乙烯（p〇ly (tetra flu〇r〇 ethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃纖維所 組成之群組之一者。並且，分別形成於第一預浸材與第二 10預浸材表面的第一金屬層與第二金屬層較佳地可分別為選 自銅、錫、鎳、鉻、鈦、銅-鉻合金以及錫_鉛合金中所組成 之群組之·-者。 再者，本發明分別形成於第一預浸材與第二預浸材表 面的第一線路線路增層結構及第二線路增層結構係可包括 15 一介電層、疊置於介電層上之線路層，以及形成於介電層 中且電性連接該線路層之導電盲孔。 因此，本發明係利用晶片加熱的步驟，可使得晶片在 置放至第一預浸材時，因晶片的溫度而使得第一預浸材融 化，進而可固定晶片的位置。本發明的方法係解決了習知 20 *要夕種材料以固定晶片的方法係降低了多元的製程成 本以及時效。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 8 ^43113 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 . 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進=各 5 種修飾與變更。 本發明之實施例中該等圖式均為簡化之示意圖。惟該 等圖式僅顯示與本發明有關之元件，其所顯示之元件非為 實際實施時之態樣，其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 10 實施例1 〇月參考圖2A至2E，係為本實施例進行敌埋晶片至基板 之流程示意圖。 首先，如圖2 A所示，提供一第一預浸材21，其一側表 面形成有一第一金屬層22。在此，第一預浸材21可使用的 15 材料為選自由 ABF(Ajinomoto Build-up Film)、雙順 丁醯二 酸酿亞胺/三氮阱（Bismaleimide triazine ; BT)、聯二笨環丁 二烯如!12：0(^1〇131^此；3(：^)、液晶聚合物（1^11丨(1(：^办11343113 IX. Description of the Invention: - Technical Field of the Invention The present invention relates to a method of fabricating a substrate in which a wafer is embedded, and more particularly to a method for fabricating a substrate for fixing a wafer at the time of fabrication. 5 [Prior Art] The general semiconductor package process is to first bond the semiconductor wafer to the top surface of the substrate with an inactive surface, perform wire bonding, or electrically laminate the wafer with the Flip chip. The connection pads are electrically connected to each other. A solder ball is implanted on the back of the board to electrically connect to an external electronic device such as a printed circuit board. In this way, although the purpose of the high number of feet can be achieved, in the case of higher frequency use or high speed operation, the performance of the electrical characteristics due to the excessive length of the electrical connection path cannot be improved, and is limited. In addition, since the conventional package requires sealing and multiple connection interfaces, the complexity of the process 15 is relatively increased. For this reason, many studies have buried the crystal X into the substrate, and the chip embedded in the base plate can be directly connected to the inner layer of the substrate to shorten the electrical conduction path' and reduce signal loss, signal distortion and boost. High speed capability. 20 Generally, a method of embedding a wafer into a substrate is described. Referring to the drawing, first, a first dielectric layer U is provided, and a core plate 12 having an opening 12 is formed on the surface of the first dielectric layer 11. Next, a bonding layer 13 is formed in the opening 121 of the core board 12, and the wafer 14 is placed and temporarily fixed on the surface of the bonding layer η (or the inactive surface of the wafer is attached to a bonding layer 13 Further, two 5 1343113 U are attached to the surface of the first dielectric layer 11), wherein the active surface of the wafer 14 has a plurality of electrode pads (4). Then, an adhesive layer 15 is filled in the opening 121 to completely fix the wafer 14. Then, a second dielectric layer 161 is formed on the active surface of the wafer 14 and the surface of the core board 12, and a wiring layer 162 is formed on the surface of the second dielectric layer 16 and the wiring layer 162 is electrically conductive. The blind via 163 is electrically connected to the electrode pad 141 of the wafer 14. Therefore, the method of burying the wafer to the substrate after the conventional wafer is completed. However, in the conventional method, a bonding layer 13 is formed in the opening 121 (or the surface of the wafer 14 is pre-attached to the bonding layer 13), and the crystal moon 10 14 is temporarily fixed. The adhesive material (adhesive layer 15) is used to embed the slab 143⁄4 and is completely fixed in the core slab 2. This method is complicated and requires a variety of materials to embed and fix the wafer 14 in the substrate, which is time consuming and consumable. If the step of forming the bonding layer 13 is omitted, the wafer 14 can not be temporarily fixed on the surface of the first dielectric layer (10), and the film 14 can be easily slid, thereby having the problem of opening the blind hole during the subsequent process. produce. Therefore, how to reduce the process cost and the aging process is an important issue in the method of embedding a wafer into a substrate. SUMMARY OF THE INVENTION In view of the disadvantages of the prior art, the present invention provides a method of fabricating a substrate embedded with a wafer, comprising: first, providing a first prepreg having a first metal formed on one surface thereof Floor. Next, a core plate having an opening is formed on the other side surface of the first prepreg. Then, a wafer is heated and placed in the opening of the core board, which may be one selected from the group consisting of an insulating board, a circuit board having a circuit layer, and a metal board. The first prepreg and the second prepreg are preferably selected from the group consisting of: ABF (Ajinomoto Build-up Film), Bismaleimide triazine (BT). , benzocylobutene (BCB), liquid crystal polymer (Liquid cryyy Polymer), polyimide (PI), polyvinyl ether (phenylene ether), polytetrafluoroethylene One of a group consisting of p〇ly (tetra flu〇r〇ethylene), aromatic polyamide (Aramide), epoxy resin, and glass fiber. And the first metal layer and the second metal layer respectively formed on the surfaces of the first prepreg and the second prepreg are preferably selected from the group consisting of copper, tin, nickel, chromium, titanium, and copper-chromium alloy. And the group consisting of tin-lead alloys. Furthermore, the first line line build-up structure and the second line build-up structure formed on the surfaces of the first prepreg and the second prepreg, respectively, may comprise 15 dielectric layers stacked on the dielectric layer. The upper circuit layer, and the conductive blind holes formed in the dielectric layer and electrically connected to the circuit layer. Accordingly, the present invention utilizes the step of wafer heating to cause the first prepreg to melt due to the temperature of the wafer when placed on the first prepreg, thereby fixing the position of the wafer. The method of the present invention solves the conventional method of fixing a wafer to reduce the multi-component process cost and aging. [Embodiment] The following is a description of the embodiments of the present invention by way of specific embodiments, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied by other specific embodiments. The details of the present specification may also be based on different viewpoints and applications without departing from the spirit of the invention. . The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the drawings only show the components related to the present invention, and the components shown therein are not in actual implementation, and the actual number of components in the actual implementation is a selective design and the component layout. The pattern may be more complicated. 10 Embodiment 1 Referring to Figures 2A to 2E, a flow chart of a buried chip to a substrate is performed in this embodiment. First, as shown in Fig. 2A, a first prepreg 21 is provided having a first metal layer 22 formed on one surface thereof. Here, the 15 materials which can be used for the first prepreg 21 are selected from the group consisting of ABF (Ajinomoto Build-up Film), Bismaleimide triazine (BT), and the second stupid ring. Butadiene such as! 12:0 (^1〇131^ this; 3(:^), liquid crystal polymer (1^11丨(1(:^办1)

Polymer)、聚亞酿胺（p〇iyimjde ; pi)、聚乙稀喊 (P〇ly(phenylene ether))、聚四氟乙烯（p〇iy (tetra_fiuoro 20 ethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃纖維所 組成之群組之一者。本實施例的第一預浸材21係使用 ABF。此外’第一金屬層22使用的材料可為選自銅、錫、 錄、鉻、鈦 '銅-鉻合金以及錫_鉛合金中所組成之群組之一 者。在本實施例中的第一金屬層22係使用銅。 9 1343113 之處形成-導電盲孔26,使晶片31的電極塾3 u可經由導電 盲孔26而與第二線路層251電性導通。其中，導電盲孔％形 • 成的方式可為習知的方式製作而成。例如，先於第二預其 材24内進行雷射鑽孔，再進行圖案化線路製程以電鍍= 5式形成導電盲孔26。在此，第一預浸材21表面的第一金屬 層2 2係可用以作為該基板結構散熱之用。 實施例2 請參考圖3，係、為本實施例嵌埋有晶片&基板剖視圖。 本實施例與實施例1大致相同，但不同的是蝕刻實施例1的 ，〇第一金屬層以進行其圖案化，以將第一金屬層以圖案化線 路製程形成一第一線路層221。 接著，以機械鑽孔的方式貫穿第二預浸材24、核心板23 與第一預浸材21以形成通孔，並再於通孔内加以電鍍有金 屬層271以及填入絕緣材料272而形成一電鍍導通孔27。此 15 電鍵導通孔27孔壁的金屬層271，係用以使第一線路層221 及該第二線路層251電性導通。因此，可完成本實施例中嵌 埋有晶片的基板之方法。 實施例3 凊參考圖4 ’係為本實施例欲埋有晶片的基板剖視圖。 20 本實施例與實施例1大致相同，但不同的是本實施例於具有 第二線路層25 1之第二預浸材24表面利用線路增層技術形 成一第二線路增層結構42。此第二線路增層結構42可視需 要増加層數《而此第二線路增層結構42包括有介電層421、 叠置於介電層421上利用阻層（圖未示）以曝光及顯影之方式 1343113 再加以電鍍所形成之線路層422，以及於介電層421中以雷 射鑽孔形成盲孔（圖未示）後而與線路層422同時利用電鍍之 方式所形成的導電盲孔423，且該導電盲孔423係用以電性 連接該線路層422及第二線路層251之用。在此，線路層422 5 以及導電盲孔423使用的材料係可為選自由銅、錫、鎳、鉻、 鈦以及銅-絡合金所組成之群組之一者，在本實施例係使用 銅。而介電層421可以使用的材料可使用如第二預浸材24所 述之材料，例如本實施例可使用ABF(Ajinomoto Build-up Film )等。此外，復可再於第二線路增層結構42表面形成一 10 防焊層52，此防焊層52係以曝光及顯影之方式形成有複數 個開孔521以顯露出形成於第二線路增層結構42表面的線 路層422以作為電性連接墊之部分。因此，可完成本實施例 中嵌埋有晶片的基板之方法。 實施例4 15 請參考圖5 ’係為本實施例嵌埋有晶片的基板剖視圖。 本實施例與實施例3大致相同，但不同的是本實施例再於第 一預浸材21表面的第一金屬層以蝕刻的方式予以圖案化， 以形成一第一線路層221。接著’可與實施例3的方式相同， 於具有第一線路層221之第一預浸材21表面利用線路增層 20 技術形成第一線路增層結構41。此第一線路增層結構4 1同 樣可視需要增加層數。而此第一線路增層結構41亦包括有 介電層411、疊置於介電層411上之線路層412，以及於介電 層411中形成有導電盲孔413,且該導電盲孔413係用以電性 連接該線路層412及第二線路層221之用。而形成介電層 12 1343113 4 π、線路層41 2與導電盲孔4丨3的材料以及方法係可與實施 例3中之第二線路增層結構42相同。接著，以機械鑽孔的方 式貫穿第二線路增層結構42、第二預浸材24 '核心板23、 第一預浸材21以及第一線路增層結構41，並再加以電鍍有 金屬層43 1以及填入絕緣材料432而形成一電鍍導通孔43。 此電鑛導通孔43孔壁金屬層43 1，係用以使第一線路層 22卜第一線路增層結構41中之線路層412、第二線路層251 以及第二線路增層結構42中之線路層422電性導通。另，可 再於第一線路增層結構41表面形成一防焊層5丨，此防焊層 ίο 20 5 1係形成有複數個開孔5 1丨以顯露出形成於第一線路增層 結構41表面的線路層412以作為電性連接墊之部分。而第二 線路增層結構42表面同樣亦形成一防焊層52，此防焊層52 亦形成有複數個開孔521以顯露出形成於第二線路增層結 構42表面的線路層422以作為電性連接墊之部分。因此，可 完成本實施例中嵌埋有晶片的基板結構之方法。 综上所述，本發明係將晶片加熱後，使其溫度達到可 將第一預浸材以及第二預浸材融化的溫度。當晶片置放至 核心板的開口内之第一預浸材表面時，係可融化部分的第 一預浸材以使晶片接置固定於第一預浸材上。接著，將第 二預浸材熱壓時’同時也會因晶片的溫度而融化，進而使 第-預浸材以及第二預浸材的材料溢入核心板的開孔内， 以完全將晶片固定於核心板内。本發明的方法係可使晶片 接置固定於第-預浸材上’並且在進行第二預浸材的壓合 13 1343113 片固定的問 間。 ’本發明所 ’而非僅限 時’不會導致晶片的位移，因此可解決習知晶 題。同時’亦降低了製裎的成本以及更節省： 上述實施例僅係為了方便說明而舉例而已Polymer), polyacrylamide (p〇iyimjde; pi), P〇ly (phenylene ether), polytetrafluoroethylene (p〇iy (tetra_fiuoro 20 ethylene)), aromatic nylon (Aramide), One of a group consisting of epoxy resin and glass fiber. The first prepreg 21 of the present embodiment uses ABF. Further, the material used for the first metal layer 22 may be one selected from the group consisting of copper, tin, copper, chromium, titanium 'copper-chromium alloy, and tin-lead alloy. Copper is used for the first metal layer 22 in this embodiment. At 9 1343113, a conductive via hole 26 is formed so that the electrode 塾3 u of the wafer 31 can be electrically connected to the second wiring layer 251 via the conductive via hole 26. Among them, the form of the conductive blind hole can be made in a conventional manner. For example, a laser drilling is performed in advance of the second pre-material 24, and then a patterned wiring process is performed to form a conductive blind hole 26 by electroplating. Here, the first metal layer 2 2 on the surface of the first prepreg 21 can be used as a heat sink for the substrate structure. Embodiment 2 Referring to FIG. 3, a cross-sectional view of a wafer & substrate is embedded in this embodiment. This embodiment is substantially the same as Embodiment 1, except that the first metal layer of the first embodiment is etched to pattern the first metal layer to form a first wiring layer 221 by a patterned wiring process. Then, the second prepreg 24, the core plate 23 and the first prepreg 21 are penetrated by mechanical drilling to form a through hole, and the metal layer 271 is further plated in the through hole and the insulating material 272 is filled. A plating via 27 is formed. The metal layer 271 of the wall of the via hole 27 is used to electrically connect the first circuit layer 221 and the second circuit layer 251. Therefore, the method of embedding the substrate of the wafer in this embodiment can be accomplished. Embodiment 3 Referring to Figure 4, there is shown a cross-sectional view of a substrate in which a wafer is to be buried in the present embodiment. 20 This embodiment is substantially the same as Embodiment 1, but the difference is that this embodiment forms a second line build-up structure 42 by the line build-up technique on the surface of the second prepreg 24 having the second wiring layer 25. The second line build-up structure 42 may add a layer number as needed. The second line build-up structure 42 includes a dielectric layer 421 and is stacked on the dielectric layer 421 to form an exposure layer (not shown) for exposure and development. The method 1343113 further forms a circuit layer 422 formed by electroplating, and a conductive blind hole formed by using a plating hole in the dielectric layer 421 to form a blind via hole (not shown) and simultaneously using the plating layer 422. 423, and the conductive via 423 is used for electrically connecting the circuit layer 422 and the second circuit layer 251. Here, the material used for the wiring layer 422 5 and the conductive blind via 423 may be one selected from the group consisting of copper, tin, nickel, chromium, titanium, and a copper-coalloy alloy. In this embodiment, copper is used. . As the material which can be used for the dielectric layer 421, a material such as the second prepreg 24 can be used. For example, ABF (Ajinomoto Build-up Film) or the like can be used in the embodiment. In addition, a 10 solder resist layer 52 is formed on the surface of the second line build-up structure 42. The solder resist layer 52 is formed by exposing and developing a plurality of openings 521 to form a second line. The wiring layer 422 on the surface of the layer structure 42 serves as part of the electrical connection pads. Therefore, the method of embedding the substrate of the wafer in this embodiment can be accomplished. Embodiment 4 Referring to Figure 5, a cross-sectional view of a substrate in which a wafer is embedded in the present embodiment is shown. This embodiment is substantially the same as Embodiment 3 except that the first metal layer on the surface of the first prepreg 21 is patterned in an etching manner to form a first wiring layer 221. Then, in the same manner as in the embodiment 3, the first line build-up structure 41 is formed by the line build-up 20 technique on the surface of the first prepreg 21 having the first wiring layer 221. This first line build-up structure 4 1 can also increase the number of layers as needed. The first line build-up structure 41 also includes a dielectric layer 411, a circuit layer 412 stacked on the dielectric layer 411, and a conductive via 413 formed in the dielectric layer 411, and the conductive via 413 It is used to electrically connect the circuit layer 412 and the second circuit layer 221. The material and method for forming the dielectric layer 12 1343113 4 π, the wiring layer 41 2 and the conductive via 4 丨 3 may be the same as those of the second wiring build-up structure 42 of the third embodiment. Next, the second line build-up structure 42, the second prepreg 24' core plate 23, the first prepreg 21, and the first line build-up structure 41 are penetrated by mechanical drilling, and then metallized. 43 1 and filling the insulating material 432 to form a plating via 43. The electric metal via hole 43 is formed in the hole metal layer 43 1 for making the first circuit layer 22 into the circuit layer 412, the second circuit layer 251 and the second circuit build-up structure 42 in the first line build-up structure 41. The circuit layer 422 is electrically conductive. In addition, a solder resist layer 5 形成 may be formed on the surface of the first line build-up structure 41. The solder resist layer ίο 20 5 1 is formed with a plurality of openings 5 1 丨 to be exposed in the first line build-up structure. The surface layer 412 of the surface 41 serves as part of the electrical connection pads. The surface of the second line build-up structure 42 also forms a solder resist layer 52. The solder resist layer 52 is also formed with a plurality of openings 521 to expose the circuit layer 422 formed on the surface of the second line build-up structure 42. Part of the electrical connection pad. Therefore, the method of embedding the substrate structure of the wafer in this embodiment can be accomplished. In summary, the present invention heats the wafer to a temperature at which the first prepreg and the second prepreg can be melted. When the wafer is placed on the surface of the first prepreg in the opening of the core plate, a portion of the first prepreg is melted to secure the wafer to the first prepreg. Then, when the second prepreg is hot pressed, it also melts due to the temperature of the wafer, so that the materials of the first prepreg and the second prepreg overflow into the opening of the core plate to completely wafer the wafer. Fixed in the core board. The method of the present invention allows the wafer to be attached to the first prepreg and to perform the pressing of the second prepreg 13 1334313. The present invention, rather than being limited to, does not cause displacement of the wafer, and thus the conventional crystallographic solution can be solved. At the same time, it also reduces the cost of manufacturing and more savings: The above embodiments are only examples for convenience of explanation.

主張之權利範圍自應以申請專利範圍所述為準 於上述實施例。 【圖式簡單說明】 圖1係習知之將晶片嵌埋至基板之剖視圖。 圖2 A至2E係本發明一較佳實施例之嵌埋有晶片的基板 10 之製作流程剖視圖。 圖3至圖5係本發明其他較佳實施例之嵌埋有晶片的基 板剖視圖。 【主要元件符號說明】 11 第一介電層 12,23 核心板 121,231 開σ 13 貼合層 14 晶片 141 電極墊 15 黏著層 161 第二介電層 162 線路層 163,26 導電盲孔 21 第一預浸材 22 第一金屬層 221 第一線路層 24 第二預浸材 25 第二金屬層 251 第二線路層 27,43 電鍍導通孔 271,431 金屬層 272,432 絕緣材料 31 晶片 1343113 31a 311 411,421 413,423 51,52 主動面 31b 非主動面 電極墊 41 第一線路增層結構 介電層 412,422 線路層 導電盲孔 42 第二線路增層結構 防焊層 51 1,521 開孔 15The scope of the claims is subject to the above-described embodiments as set forth in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing a conventional method of embedding a wafer into a substrate. 2A to 2E are cross-sectional views showing a manufacturing process of a substrate 10 in which a wafer is embedded in a preferred embodiment of the present invention. 3 to 5 are cross-sectional views of a substrate embedded with a wafer in accordance with another preferred embodiment of the present invention. [Main component symbol description] 11 First dielectric layer 12, 23 Core plate 121, 231 Open σ 13 Bonding layer 14 Wafer 141 Electrode pad 15 Adhesive layer 161 Second dielectric layer 162 Circuit layer 163, 26 Conductive blind hole 21 First Prepreg 22 First metal layer 221 First wiring layer 24 Second prepreg 25 Second metal layer 251 Second wiring layer 27, 43 Plating via 271, 431 Metal layer 272, 432 Insulating material 31 Wafer 1343113 31a 311 411, 421 413, 423 51, 52 active surface 31b inactive surface electrode pad 41 first line build-up structure dielectric layer 412, 422 circuit layer conductive blind hole 42 second line build-up structure solder resist layer 51 1,521 opening 15

Claims (1)

1343113 十、申請專利範圍： 1- 一種嵌埋有晶片的基板之製作方法，包括： 提供一第一預浸材（prepreg)，其一側表面形成有—第 一金屬層； 5 於該第一預浸材另一側表面形成一具有開口之核心 板； 加熱一晶片，並將該晶片置放於該核心板之該開口 内，該aa片具有一主動面及非主動面，且該主動面配置有 複數個電極墊，而該非主動面係與該第一預浸材表面接 10觸，以使該第一預浸材與加熱後之該晶片接觸時呈現熔融 態，以將該晶片之該非主動面黏固於該第一預浸材； 將一第二預浸材壓合至該晶片的主動面與該核心板表 面，並經由熱壓使該第一預浸材及該第二預浸材之材料填 入該開口内，其中，該第二預浸材未接觸核心板之一表面 15 具有一第二金屬層；以及 圖案化5亥第二金屬層以製作成一第二線路層並使該 晶片與該第二線路層電性導通。 2·如申請專利範圍第丨項所述之製作方法，復包括圖 案化該第一金屬層以製作成一第一線路層。 20 3.如申請專利範圍第2項所述之製作方法，復包括形 成至少一貫穿該第二預浸材、該核心板與該第一預浸材之 電鍍導通孔，其係使該第一線路層及該第二線路層電性 通。 4.如申請專利範圍第1項所述之製作方法復包括於 16 1343113 /、有《玄第〜線路層之該第二預浸材表面形成一第二線路增 層結構。 5.如中請專利^圍“項所述之製作方法，復包括於 具有該第-線路層之該第一預浸材表面形成一第一線 5 層結構。 6. 如申凊專利範圍第5項所述之製作方法復包括形 成至'貫穿該第二線路增層結構、該第二預浸材該核 ^板該第一預浸材與該第一線路增層結構之電鍍導通 孔，其係使該第一線路增層結構、該第一線路層、該第二 10 線路層及該第二線路增層結構電性導通。 7. 如申請專利範圍第丨項所述之製作方法，其中，加 熱該晶片的步驟係將晶片加熱至一定溫度，使該晶片接置 於該第一預浸材時能使該預浸材融化的溫度。 8. 如申請專利範圍第1項所述之製作方法，其中，該 丨5核心板係為選自絕緣板、具有線路層之電路板及金屬板所 組群組之一者。 9. 如申請專利範圍第1項所述之製作方法，其中，該 第一預浸材與該第二預浸材分別為選自由ABFXAjin〇m()t〇 Build-up Fi丨m)、雙順丁醯二酸醯亞胺/三氮阱（Bismaleimide 20 triazine ; BT)、聯二苯環 丁二稀（benzocyi〇butene ; BCB)、 液晶聚合物（Liquid Crystal Polymer)、聚亞醯胺（p〇lyimide ; PI)、聚乙稀鰱（P〇ly(phenylene ether))、聚四氟乙烤（p〇ly (tetra-fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及 玻璃纖維所組成之群組之一者。 17 1343113 1 Ο ·如申请專利氣圍第1項所述之製作方法，其今 第一金屬層與該第二金屬層分別為選自銅、錫、鎳、 鈦、銅-鉻合金以及錫-鉛合金令所組成之群組之一者 π ·如申請專利範圍第5項所述之製作方法，其中 第.線路增層結構及該第二線路增層結構分別包括一 層疊置於該介電層上之線路層以及形成於該介電 且電性連接該線路層之導電盲孔。 ，，該 絡、 I ’該 介電 層中1343113 X. Patent Application Range: 1- A method for fabricating a substrate embedded with a wafer, comprising: providing a first prepreg having a first metal layer formed on one surface thereof; The other side surface of the prepreg is formed with a core plate having an opening; a wafer is heated, and the wafer is placed in the opening of the core plate, the aa piece has an active surface and an inactive surface, and the active surface a plurality of electrode pads are disposed, and the inactive surface is 10 in contact with the surface of the first prepreg, so that the first prepreg is in a molten state when it is in contact with the heated wafer, so as to The active surface is adhered to the first prepreg; a second prepreg is pressed to the active surface of the wafer and the surface of the core plate, and the first prepreg and the second prepreg are hot pressed a material of the material is filled in the opening, wherein the second prepreg does not contact the surface 15 of the core plate has a second metal layer; and the second metal layer is patterned to form a second circuit layer and The wafer is electrically conductive to the second circuit layer. 2. The method of fabricating the invention of claim 2, further comprising patterning the first metal layer to form a first circuit layer. The manufacturing method of claim 2, further comprising forming at least one plated through hole penetrating the second prepreg, the core plate and the first prepreg, which is to make the first The circuit layer and the second circuit layer are electrically connected. 4. The manufacturing method according to Item 1 of the patent application is further included in 16 1343113 /, and a second line build-up structure is formed on the surface of the second prepreg having the "Xuan-Dian" layer. 5. The method of manufacturing a method according to the above-mentioned patent, comprising the first line 5 layer structure formed on the surface of the first prepreg having the first circuit layer. The manufacturing method of the fifth aspect includes forming a plated through hole formed through the second line build-up structure, the second prepreg, the first prepreg and the first line build-up structure. The method of manufacturing the first line build-up structure, the first circuit layer, the second 10 circuit layer, and the second line build-up structure is electrically conductive. Wherein, the step of heating the wafer is to heat the wafer to a temperature such that the wafer is placed in the first prepreg to melt the prepreg. 8. As described in claim 1 The manufacturing method, wherein the 丨5 core plate is one selected from the group consisting of an insulating plate, a circuit board having a circuit layer, and a metal plate. 9. The manufacturing method according to claim 1, wherein The first prepreg and the second prepreg are respectively selected from the group consisting of ABFXAjin〇m ()t〇Build-up Fi丨m), Bismuthimide 20 triazine (BT), benzocyi〇butene (BCB), liquid crystal polymerization Liquid Crystal Polymer, polyplylimide (PI), P〇ly (phenylene ether), p〇ly (tetra-fluoroethylene), aromatic One of a group consisting of nylon (Aramide), epoxy resin, and glass fiber. 17 1343113 1 Ο · The manufacturing method described in claim 1, the first metal layer and the second metal The layers are respectively selected from the group consisting of copper, tin, nickel, titanium, copper-chromium alloys, and tin-lead alloys. π · The manufacturing method described in claim 5, wherein the first line The build-up structure and the second line build-up structure respectively comprise a circuit layer stacked on the dielectric layer and a conductive blind hole formed on the dielectric layer and electrically connected to the circuit layer. In the dielectric layer
TW096131046A 2007-08-22 2007-08-22 Method for manufacturing substrate embedded with chip TWI343113B (en)

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TWI415234B (en) * 2009-05-25 2013-11-11 Nan Ya Printed Circuit Board Packing substrate with embedded chip
TWI553792B (en) * 2014-12-02 2016-10-11 旭德科技股份有限公司 Package structure and manufacturing method thereof
TWI660473B (en) * 2017-12-26 2019-05-21 Industrial Technology Research Institute Package structure and forming method thereof

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