TW200910558A - Method for manufacturing substrate embedded with chip - Google Patents

Method for manufacturing substrate embedded with chip Download PDF

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Publication number
TW200910558A
TW200910558A TW096131046A TW96131046A TW200910558A TW 200910558 A TW200910558 A TW 200910558A TW 096131046 A TW096131046 A TW 096131046A TW 96131046 A TW96131046 A TW 96131046A TW 200910558 A TW200910558 A TW 200910558A
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TW
Taiwan
Prior art keywords
prepreg
layer
wafer
line
core plate
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TW096131046A
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Chinese (zh)
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TWI343113B (en
Inventor
Wen-Sung Chang
Jiang-Wen Kung
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Phoenix Prec Technology Corp
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Priority to TW096131046A priority Critical patent/TWI343113B/en
Publication of TW200910558A publication Critical patent/TW200910558A/en
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Publication of TWI343113B publication Critical patent/TWI343113B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

A method for manufacturing a substrate embedded with a chip, comprising: providing a first prepreg with a first metal layer formed on one surface thereof; forming a core plate having an opening on the other surface of the first prepreg; heating a chip, and puting it in the opening of the core plate, wherein the chip has an active surface and an inactive surface, the active surface has a plurality of electrode pads thereon, and the inactive surface is contacted with the surface of the first prepreg; laminating a second prepreg on the active surface of the chip and the surface of the core plate, and filling the materials of the first and second prepreg into the opening by heat pressing, wherein the outer surface of the second prepreg has a second metal layer; and finally, patterning the second metal layer to form a second circuit layer and electrically connecting the chip with the second circuit layer.

Description

200910558 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種礙埋有晶片的基板之製作方法，尤 指-種適用於在製作時固定晶片之基板的製作方法。 5 【先前技術】 -般半導體封裝之製程，首先係將半導體晶片以非主 動面黏貼於基板頂面’進行打線接合（wire bonding)，或將 晶片以覆晶接合（Flip chip)方式與電路板電性連接塾電性 連接。再於電路板之背面植以锡球，以電性連接至如印刷 電，板之外部電子裝置。如此，雖可達到高腳數的目的， 但是在更高頻使用時或高速操作時，其將因電性連接路徑 過長而產生電氣特性之效能無法提昇，而有所限制。另外， 因傳統封裝需要封膠及多次的連接介面，相對地增加製程 15 之複雜度。 為此，許多研究採用將晶片埋入基板内，該嵌埋於基 板中之晶片係可直接與基板内層線路導通，用以縮短電性 傳導路控，並可減少訊號損失、訊號失真及提昇高速操作 之能力。 瓜1知將晶片散埋至基板的方法，請參考圖1，首 先提供一第一介電層11，並在第一介電層11表面形成一 具有開口 121之核心板12。接著，於核心板12的開口 121内 形成一貼合層13，再將晶片14置放並暫時固定於貼合層13 表面（或將該晶片14之非主動面貼附一貼合層13，再將該晶 200910558 片貼附於第一介電層π表面），其中，該晶片14的主動面上 具有複數個電極塾141。然後，於開口 121内填入黏著層15 以完全固定此晶片14。繼之，於晶片14的主動面以及核心 板12的表面形成一第二介電層16ι，並於第二介電層161表 5 面形成有線路層162，並且，該線路層162經由導電盲孔163 而與晶片14之電極墊141電性導通。因此完成習知之晶片嵌 埋至基板之方法。 然而，習知之方法中，係先需將開口 121内形成一貼合 層13(或將該晶片14表面預先貼附一貼合層i 3) ’並且將晶片 10 14暫時固定之後仍需另外使用一黏著材料（黏著層15)以將 晶片14嵌埋並完全固定於核心板12之中。此種方式不但繁 雜，而且需要使用多種材料，才可將晶片14嵌埋並固定於 基板中，相當費時與耗材。若直接省略形成貼合層13的步 驟，則將晶片14無法暫時先固定於第一介電層丨丨的表面， 15而容易滑動，進而在進行後續製程時，會有開盲孔對位的 問題產生。因此，如何降低製程成本以及時效，實係為在 進行將晶片嵌埋至基板的方法中的一重要課題。 【發明内容】 2〇 ㈣於習知之缺點，本發明係提供—種㈣有晶片的 基板之製作方法，包括：首先，提供一第一預浸材 (P叩⑻，其-側表面形成有一第一金屬層。接著，於該 第一預浸材另一側表面形成一具有開口之核心板。然後， 加熱一晶片，並將該晶片置放於該核心板之該開口内，該 200910558 晶片具有一主動面及非主動面，且該主動面配置有複數個 電極，，該非主動面係與該第一預浸材表面接觸。繼之， 將-第二預浸材壓合至該晶片的主動面與該核心板表面， 並經由熱壓使該第-預浸材及該二預浸材之材料填入該開 5 ^内’其中’該第二預浸材未接觸核心板之—表面具有— 第二金屬層。最後’圖案化該第二金屬層以製作成一第二 線路層，並使該晶片與該第二線路層電性導通。 前述本發明之製作方法，復可包括圖案化第一金屬層 以製作成一第一線路層。並且，可形成至少一貫穿第二預 10浸材、核心板與第一預浸材之電鍍導通孔，其係使第一線 路層及第二線路層電性導通。 前述本發明之製作方法，復可包括於具有第二線路層 之第二預浸材表面形成-第二線路增層結構。並且，復可 於具有第-線路層之第一預浸材表面形成一第一線路增層 Μ結構。接著，亦可形成至少一貫穿第二線路增層結構、第 二預浸材、核心板、第一預浸材與第一線路增層社 錢導通孔，其係使第-線路增層結構、第一線路層、第二 線路層及第二線路增層結構電性導通。 在本發明嵌埋有晶片的基板之製作方法中，加熱晶片 20的步驟係為將晶片加熱至一定温度，使該晶片接置於該第 一預浸材時能使該預浸材融化的溫度。 此外，本發明的核心板不限使用任何材料，較佳地， 可㈣自絕緣板、具有線路層之電路板及金屬板所組群組 之一者。而第-預浸材與該第二預浸材較佳地分別為選自 200910558 - 由 ABF(Ajinomoto Build-up Film)、雙順丁 醯二酸酿亞胺/三 氮陕（Bismaleimide triazine ; BT)、聯二苯環 丁二烯 (benzocylobutene ; BCB)、液晶聚合物（Liquid CrystalBACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a substrate in which a wafer is buried, and more particularly to a method for fabricating a substrate for fixing a wafer at the time of fabrication. 5 [Prior Art] - The semiconductor package process is firstly to bond the semiconductor wafer with the inactive surface to the top surface of the substrate for wire bonding, or to laminate the wafer with a flip chip and a circuit board. Electrical connection is electrically connected. A solder ball is implanted on the back of the board to electrically connect to an external electronic device such as a printed circuit. In this way, although the purpose of the high number of feet can be achieved, in the case of higher frequency use or high speed operation, the performance of the electrical characteristics due to the excessive length of the electrical connection path cannot be improved, and is limited. In addition, the complexity of the process 15 is relatively increased because the conventional package requires encapsulation and multiple connection interfaces. For this reason, many studies have buried the wafer into the substrate, and the chip embedded in the substrate can be directly connected to the inner layer of the substrate to shorten the electrical conduction path, and reduce signal loss, signal distortion and high speed. The ability to operate. For the method of dispersing the wafer to the substrate, please refer to FIG. 1. First, a first dielectric layer 11 is provided, and a core plate 12 having an opening 121 is formed on the surface of the first dielectric layer 11. Then, a bonding layer 13 is formed in the opening 121 of the core board 12, and the wafer 14 is placed and temporarily fixed on the surface of the bonding layer 13 (or the inactive surface of the wafer 14 is attached to the bonding layer 13 The crystal 200910558 is attached to the first dielectric layer π surface, wherein the active surface of the wafer 14 has a plurality of electrode pads 141. Then, an adhesive layer 15 is filled in the opening 121 to completely fix the wafer 14. Then, a second dielectric layer 16ι is formed on the active surface of the wafer 14 and the surface of the core board 12, and a wiring layer 162 is formed on the surface of the second dielectric layer 161, and the wiring layer 162 is electrically conductive. The hole 163 is electrically connected to the electrode pad 141 of the wafer 14. Thus, a method of embedding a conventional wafer into a substrate is completed. However, in the conventional method, it is necessary to form a bonding layer 13 in the opening 121 (or attach a bonding layer i 3 to the surface of the wafer 14) and temporarily use the wafer 10 14 after the wafer 10 14 is temporarily fixed. An adhesive material (adhesive layer 15) is used to embed the wafer 14 and completely fix it in the core board 12. This method is complicated and requires a variety of materials to embed and fix the wafer 14 in the substrate, which is time consuming and consumable. If the step of forming the bonding layer 13 is omitted, the wafer 14 can not be temporarily fixed to the surface of the first dielectric layer, 15 and can be easily slid, so that when the subsequent process is performed, the blind hole is aligned. The problem arises. Therefore, how to reduce the process cost and the aging time is an important issue in the method of embedding a wafer into a substrate. SUMMARY OF THE INVENTION [4] In the conventional disadvantages, the present invention provides a method for fabricating a substrate having a wafer, comprising: first, providing a first prepreg (P叩(8) having a side surface formed with a first surface a metal layer. Then, a core plate having an opening is formed on the other side surface of the first prepreg. Then, a wafer is heated and placed in the opening of the core plate, and the 200910558 wafer has An active surface and a non-active surface, wherein the active surface is provided with a plurality of electrodes, and the non-active surface is in contact with the surface of the first prepreg. Subsequently, the second prepreg is pressed to the active of the wafer And the surface of the core plate, and the material of the first prepreg and the two prepreg are filled into the opening by heat pressing, wherein the surface of the second prepreg is not in contact with the core plate has — a second metal layer. Finally, the second metal layer is patterned to form a second wiring layer, and the wafer is electrically connected to the second wiring layer. The foregoing manufacturing method of the present invention may include patterning. a metal layer to make a first line And forming at least one plated through hole penetrating through the second pre-10 dipping material, the core plate and the first prepreg, wherein the first circuit layer and the second circuit layer are electrically connected. The method may include forming a second prepreg surface having a second circuit layer - a second line build-up structure, and forming a first line increase on the surface of the first prepreg having the first line layer a layered structure. Then, at least one through-the second line build-up structure, the second prepreg, the core plate, the first prepreg, and the first line build-up money via hole may be formed, which is to make the first line The build-up structure, the first circuit layer, the second circuit layer, and the second line build-up structure are electrically connected. In the method of fabricating the substrate embedded with the wafer of the present invention, the step of heating the wafer 20 is to heat the wafer to a certain level. The temperature, the temperature at which the prepreg is melted when the wafer is placed on the first prepreg. Further, the core plate of the present invention is not limited to any material, preferably, (4) self-insulating board, having a line Layer circuit board and metal plate group The first prepreg and the second prepreg are preferably selected from the group consisting of 200910558 - ABF (Ajinomoto Build-up Film), bis-butane bismuth diacetate / diazonium (Bismaleimide) Triazine ; BT), benzocylobutene (BCB), liquid crystal polymer (Liquid Crystal

Polymer)、聚亞醯胺（Polyimide ; PI)、聚乙稀醚（Poly 5 (phenylene ether))、聚四氟乙稀（Poly (tetra-fluoro ethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃纖維所 組成之群組之一者。並且，分別形成於第一預浸材與第二 預浸材表面的第一金屬層與第二金屬層較佳地可分別為選 (1 自銅、錫、鎳、鉻、鈦、銅-鉻合金以及錫-鉛合金中所組成 10 之群組之一者。 再者’本發明分別形成於第一預浸材與第二預浸材表 面的第一線路線路增層結構及第二線路增層結構係可包括 一介電層、疊置於介電層上之線路層，以及形成於介電層 中且電性連接該線路層之導電盲孔。 15 因此，本發明係利用晶片加熱的步驟，可使得晶片在 置放至第一預浸材時，因晶片的溫度而使得第一預浸材融 化，進而可固定晶片的位置。本發明的方法係解決了習知Polymer), Polyimide (PI), Poly 5 (phenylene ether), Poly (tetra-fluoro ethylene), Aromatic (Aramide), Epoxy Resin And one of the groups consisting of fiberglass. And, the first metal layer and the second metal layer respectively formed on the surfaces of the first prepreg and the second prepreg are preferably respectively selected from (1, from copper, tin, nickel, chromium, titanium, copper-chromium One of the group consisting of 10 in the alloy and the tin-lead alloy. Further, the first line line build-up structure and the second line increase formed on the surfaces of the first prepreg and the second prepreg, respectively. The layer structure may include a dielectric layer, a wiring layer stacked on the dielectric layer, and a conductive via hole formed in the dielectric layer and electrically connected to the wiring layer. 15 Therefore, the present invention utilizes wafer heating. The method is such that when the wafer is placed on the first prepreg, the first prepreg is melted due to the temperature of the wafer, thereby fixing the position of the wafer. The method of the present invention solves the conventional problem.

U 需要多種材料以固定晶片的方法’係降低了多元的製程成 本以及時效。 20 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 200910558 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 本發明之實施例中該等圖式均為簡化之示意圖。惟該 5 等圖式僅顯示與本發明有關之元件，其所顯示之元件非為 實際實施時之態樣，其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 實施例1 請參考圖2A至2E，係為本實施例進行嵌埋晶片至基板 10 之流程示意圖。 首先，如圖2A所示，提供一第一預浸材21，其一側表 面形成有一第一金屬層22。在此，第一預浸材21可使用的 材料為選自由 ABF(Ajinomoto Build-up Film)、雙順 丁醯二 酸酸亞胺/三氮拼（Bismaleimide triazine ; BT)、聯二苯環丁 15 二烯（benzocylobutene ; BCB)、液晶聚合物（Liquid Crystal Polymer)、聚亞醢胺（Polyimide ; PI)、聚乙稀醚 (Poly(phenylene ether))、聚四氟乙浠（Poly (tetra-fluoro ethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃纖維所 組成之群組之一者。本實施例的第一預浸材21係使用 20 ABF。此外，第一金屬層22使用的材料可為選自銅、錫、 鎳、鉻、鈦、銅-鉻合金以及錫-鉛合金中所組成之群組之一 者。在本實施例中的第一金屬層22係使用銅。 接著，如圖2B所示，於第一預浸材21另一側表面形成 一具有開口 231之核心板23。在此，核心板23可使用的材料 200910558 為選自絕緣板、具有線路層之電路板及金屬板所組群組之 一者。在本實施例中係使用具有線路層之電路板。 然後’如圖2C所示’將晶片31置放於核心板23之開口 231内。此晶片31具有一主動面3 la及非主動面3 ib，且該主 5 動面31a配置有複數個電極墊311，非主動面Mb係與第一預 /文材21表面接觸。然而，在將晶片31置放於核心板23之開 口 231内之前，係可使用加熱板或在加熱環境中，將晶片3 j 加熱達到可使第一預浸材21融化的溫度，例如，本實施例 加熱至約100 C左右，以使該晶片3 1接置於第一預浸材21表 10 面時，能使第一預浸材21表面呈現融溶態，進而使該晶片 31之非主動面3ib直接黏固於第一預浸材21表面，或如圖2(： 所示，該晶片31將精微陷入而黏固於第一預浸材21上。 繼之，如圖2D所示，將一第二預浸材24壓合至晶片31 的主動面31a與核心板23表面，並由於晶片31經由加熱後， 15係將使第一預浸材21及第二預浸材2 4之材料可填入核心板 23的開口 231内，其中，第二預浸材24外側表面具有一第二 金屬層25。於此，第二預浸材24可使用如第一預浸材21所 述之該等材料，在本實施例中則與第一預浸材21相同。同 樣地，第二金屬層25亦可使用如第一金屬層22所述之該等 20材料，而在本實施例中則使用與第一金屬層2 2相同的材料。 最後，如圖2E所示，圖案化第二金屬層25以製作成一 第二線路層251，並於第二預浸材24内，對應於電極墊η】 之處形成一導電盲孔26，使晶片31的電極墊3 u可經由導電 盲孔26而與第二線路層251電性導通。其中，導電盲孔以形 200910558 成的方式可為各知的方式製作而成。例如，先於第二預浸 材24内進行雷射鑽孔，再進行圖案化線路製程，以電鑛方 式形成導電盲孔26。在此，第一預浸材21表面的第一金屬 層22係可用以作為該基板結構散熱之用。 5 實施例2 明參考圖3，係為本實施例嵌埋有晶片的基板剖視圖。 本實施例與實施例丨大致相同，但不同的是蝕刻實施例】的 第金屬層以進行其圖案化，以將第一金屬層以圖案化線 f) 路製程形成一第一線路層221。 1〇 接著，以機械鑽孔的方式貫穿第二預浸材24、核心板23 與第一預浸材21以形成通孔，並再於通孔内加以電鍍有金 屬層271以及填入絕緣材料272而形成一電鍍導通孔27。此 電鍍導通孔27孔壁的金屬層27卜係用以使第一線路層221 及忒第—線路層251電性導通。因此，可完成本實施例中谈 15 埋有晶片的基板之方法。 實施例3 (j 凊參考圖4，係為本實施例嵌埋有晶片的基板剖視圖。 本實施例與實施例1大致相同，但不同的是本實施例於具有 第二線路層251之第二預浸材24表面利用線路增層技術形 20 成一第二線路增層結構42。此第二線路增層結構42可視需 要増加層數。而此第二線路增層結構42包括有介電層421、 疊置於介電層421上利用阻層（圖未示）以曝光及顯影之方式 再加以電鍍所形成之線路層422，以及於介電層421中以雷 射鑽孔形成盲孔（圖未示）後而與線路層422同時利用電链之 11 200910558 方式所形成的導電盲孔423，且該導電盲孔423係用以電性 連接該線路層422及第二線路層251之用。在此，線路層422 以及導電盲孔423使用的材料係可為選自由銅、錫、鎳、鉻、 鈦以及銅-鉻合金所組成之群組之一者，在本實施例係使用 5 銅。而介電層421可以使用的材料可使用如第二預浸材24所 述之材料，例如本實施例可使用ABF(Ajin〇m〇t〇 Build叩 Film)等。此外，復可再於第二線路增層結構42表面形成一 防焊層52，此防焊層52係以曝光及顯影之方式形成有複數 、 個開孔521以顯露出形成於第二線路增層結構42表面的線 1〇路層422以作為電性連接墊之部分。因此，可完成本實施例 中嵌埋有晶片的基板之方法。 實施例4 請參考圖5，係為本實施例嵌埋有晶片的基板剖視圖。 本實施例與實施例3大致相同，但不同的是本實施例再於第 15 一預浸材21表面的第一金屬層以蝕刻的方式予以圖案化， 以形成—第一線路層22卜接著，可與實施例3的方式相同， 於具有第一線路層221之第一預浸材21表面利用線路增層 技術形成第-線路增層結構41。此第一線路增層結構個 樣可視需要增加層數。而此第一線路增層結構41亦包括有 介電層41卜疊置於介電層411上之線路層412，以及於介電 層4U中形成有導電盲孔413,且該導電盲孔413係用以電性 連接該線路層412及第二線路層221之用。而形成介電層 川線路層4!2與導電盲孔化的材料以及方法係可與實施 彳中之第—線路增層結構42相同。接著，以機械鐵孔的方 12 200910558 式貫穿第二線路增層結構42、 第二預浸材24 核心板23、 第-預浸材21以及第-線路增層結構41，並再加以電鑛有 金屬層431以及填入絕緣材料432而形成—電鍍導通孔心。 此電鍵導通孔43孔壁金屬層431，係用以使第一線路層 22卜第-線路增層結構41中之線路層412、第二線路層251 以及第二線路增層結構42中之線路層422電性導通。另，可 10 再於第-線路增層結構41表面形成—防焊層51，此防焊層 51係形成有複數個開孔511以顯露出形成於第一線路增層 結構41表面的線路層412以作為電性連接墊之部分。而^ : 線路增層結構42表面同樣亦形成一防焊層52, ^防焊層二 亦形成有複數個開孔521以顯露出形成於第二線路增層結 構42表面的線路層422以作為電性連接墊之部分。因此，可 15 完成本實施例中嵌埋有晶片的基板結構之方法。 —练上所述，本發明係將晶片加熱後，使其溫度達到可 將第一預浸材以及第二預浸材融化的溫度。當晶片置放至 核心板的開口内之第-預浸材表面時，係可融化部分的第 一預浸材以使晶片接置固定於第一預浸材上。接著，將第 二預浸材熱壓時，同時也會因晶片的溫度而融化，進而使 第一預浸材以及第二預浸材的材料溢入核心板的開孔内， 20 以70王將日日片固定於核心板内。本發明的方法係可使晶片 接置固定於第一預浸材上，並且在進行第二預浸材的壓合 時，不會導致晶片的位移，因此可解決習知晶片固定的問 題。同時，亦降低了製程的成本以及更節省時間。 13 200910558 上述實施例僅係為了方 主張之權利範圍自應以中請專 本發明所 於上述實施例。 料為準，而非僅限 5 【圖式簡單說明】 圖1係習知之將晶片嵌埋至基板之剖視圖。 圖2A至2E係本發明—較佳f施例之故埋有晶片的基板 之製作流程剖視圖。 圖3至圖5係本發明其他較佳實施例之嵌埋有晶片的基 1〇 板剖視圖。 【主要元件符號說明】 11 第一介電層 121,231 開口 14 晶片 15 黏者層 162 線路層 21 第一預浸材 221 第一線路層 25 第二金屬層 27,43 電鍍導通孔 272,432 絕緣材料 31a 主動面 311 電極墊 12,23 核心板 13 貼合層 141 電極墊 161 第二介電層 163,26 導電盲孔 22 第一金屬層 24 第二預浸材 251 第二線路層 271,431 金屬層 31 晶片 31b 非主動面 41 第一線路增層結構 14 200910558 411，421介電層 413,423導電盲孔 51,52 防焊層 412,422線路層 42 第二線路增層結構 511，521 開孔 (U's need for multiple materials to fix wafers reduces the cost and timeliness of multiple processes. [Embodiment] The embodiments of the present invention are described by way of specific embodiments, and those skilled in the art can readily understand the other advantages and advantages of the present invention from the disclosure. The present invention may be embodied or applied in other specific embodiments of the present invention, and various modifications and changes may be made without departing from the spirit and scope of the invention. The drawings in the embodiments of the present invention are simplified schematic diagrams. However, the five drawings only show the components related to the present invention, and the components shown therein are not in actual implementation, and the number of components, the shape, and the like in actual implementation are a selective design, and the components thereof. The layout type can be more complicated. Embodiment 1 Referring to Figures 2A to 2E, a flow chart of embedding a wafer to a substrate 10 is shown in the present embodiment. First, as shown in Fig. 2A, a first prepreg 21 is provided having a first metal layer 22 formed on one surface thereof. Here, the material that can be used for the first prepreg 21 is selected from ABF (Ajinomoto Build-up Film), Bismaleimide triazine (BT), and diphenylcyclobutene. 15 benzocylobutene (BCB), liquid crystal polymer (Liquid Crystal Polymer), polyimide (PI), poly(phenylene ether), polytetrafluoroethylene (Poly (tetra-) One of a group consisting of fluoro ethylene)), aromatic polyamide (Aramide), epoxy resin, and glass fiber. The first prepreg 21 of the present embodiment uses 20 ABF. Further, the material used for the first metal layer 22 may be one selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloys, and tin-lead alloys. Copper is used for the first metal layer 22 in this embodiment. Next, as shown in Fig. 2B, a core plate 23 having an opening 231 is formed on the other side surface of the first prepreg 21. Here, the material usable for the core board 23 200910558 is one selected from the group consisting of an insulating board, a circuit board having a wiring layer, and a metal board. In this embodiment, a circuit board having a wiring layer is used. Then, the wafer 31 is placed in the opening 231 of the core board 23 as shown in Fig. 2C. The wafer 31 has an active surface 3 la and an inactive surface 3 ib , and the main moving surface 31 a is provided with a plurality of electrode pads 311 , and the inactive surface Mb is in surface contact with the first pre-material 21 . However, before the wafer 31 is placed in the opening 231 of the core plate 23, the wafer 3j can be heated to a temperature at which the first prepreg 21 can be melted using a heating plate or in a heated environment, for example, The embodiment is heated to about 100 C so that when the wafer 31 is placed on the surface 10 of the first prepreg 21, the surface of the first prepreg 21 can be melted, thereby making the wafer 31 non- The active surface 3ib is directly adhered to the surface of the first prepreg 21, or as shown in Fig. 2 (:, the wafer 31 will be finely trapped and adhered to the first prepreg 21. Next, as shown in Fig. 2D A second prepreg 24 is pressed onto the active surface 31a of the wafer 31 and the surface of the core plate 23, and since the wafer 31 is heated, the first prepreg 21 and the second prepreg 2 4 will be made. The material can be filled into the opening 231 of the core plate 23, wherein the outer surface of the second prepreg 24 has a second metal layer 25. Here, the second prepreg 24 can be used as the first prepreg 21 The materials described above are the same as the first prepreg 21 in this embodiment. Similarly, the second metal layer 25 may also be used as the first metal layer 22 The 20 materials are the same, and in the present embodiment, the same material as the first metal layer 2 2 is used. Finally, as shown in FIG. 2E, the second metal layer 25 is patterned to form a second wiring layer 251. And in the second prepreg 24, a conductive blind hole 26 is formed corresponding to the electrode pad η, so that the electrode pad 3 u of the wafer 31 can be electrically connected to the second circuit layer 251 via the conductive blind hole 26 Among them, the conductive blind holes can be made in a known manner in the form of the shape of 200910558. For example, the laser drilling is performed before the second prepreg 24, and then the patterned circuit process is performed in the form of electric ore. The conductive blind hole 26 is formed. Here, the first metal layer 22 on the surface of the first prepreg 21 can be used for heat dissipation of the substrate structure. 5 Embodiment 2 Referring to FIG. 3, the embodiment is embedded with A cross-sectional view of a substrate of the wafer. This embodiment is substantially the same as the embodiment , except that the metal layer of the embodiment is etched to pattern the first metal layer to form a pattern by a patterned line f) A circuit layer 221. 1〇, the second prepreg 24, the core plate 23 and the first prepreg 21 are penetrated by mechanical drilling to form a through hole, and a metal layer 271 is further plated in the through hole and filled with an insulating material. A plating via 27 is formed 272. The metal layer 27 of the via hole of the plating via hole 27 is used to electrically conduct the first wiring layer 221 and the first wiring layer 251. Therefore, the method of the substrate in which the wafer is buried in the present embodiment can be completed. Embodiment 3 (J 凊 Referring to FIG. 4 is a cross-sectional view of a substrate in which a wafer is embedded in the present embodiment. This embodiment is substantially the same as Embodiment 1, but the difference is that the present embodiment has a second layer 251. The surface of the prepreg material 24 is formed into a second line build-up structure 42 by a line build-up technique. The second line build-up structure 42 can be added as needed. The second line build-up structure 42 includes a dielectric layer 421. a wiring layer 422 formed by being electrically plated on the dielectric layer 421 by a resist layer (not shown) by exposure and development, and a blind hole formed by laser drilling in the dielectric layer 421 (Fig. The conductive blind vias 423 formed by the electrical circuit of the circuit layer 422 are used to electrically connect the circuit layer 422 and the second circuit layer 251. Here, the material used for the wiring layer 422 and the conductive blind via 423 may be one selected from the group consisting of copper, tin, nickel, chromium, titanium, and a copper-chromium alloy. In this embodiment, 5 copper is used. The material that can be used for the dielectric layer 421 can be used, for example, a second prepreg. For the material of the material 24, for example, ABF (Ajin〇m〇t〇Build叩Film) or the like can be used in the embodiment. Further, a solder resist layer 52 can be formed on the surface of the second line build-up structure 42. The solder layer 52 is formed with a plurality of openings 521 for exposing and developing to expose the line 1 layer 422 formed on the surface of the second line build-up structure 42 as part of the electrical connection pad. A method of embedding a substrate in which a wafer is embedded in the present embodiment is described. Embodiment 4 Referring to FIG. 5, it is a cross-sectional view of a substrate in which a wafer is embedded in this embodiment. This embodiment is substantially the same as Embodiment 3, but the difference is this. The first metal layer on the surface of the fifteenth prepreg 21 is etched to form a first circuit layer 22, which can be the same as the embodiment 3, and has the first line. The surface of the first prepreg 21 of the layer 221 is formed by a line build-up technique to form the first-line build-up structure 41. The first line build-up structure may increase the number of layers as needed. The first line build-up structure 41 also includes a line having a dielectric layer 41 stacked on the dielectric layer 411 The conductive layer 413 is formed in the dielectric layer 4U, and the conductive via 413 is electrically connected to the circuit layer 412 and the second circuit layer 221 to form a dielectric layer. The material and method of the 4! 2 and the conductive blind hole can be the same as the first line-adding structure 42 of the implementation. Next, the second-layer build-up structure 42 and the second through the mechanical iron hole side 12 200910558 The prepreg 24 core plate 23, the first prepreg 21 and the first-line build-up structure 41 are further provided with a metal layer 431 and an insulating material 432 to form a plated via hole. The 43-hole wall metal layer 431 is used to electrically connect the circuit layer 412, the second circuit layer 251, and the circuit layer 422 of the second line build-up structure 42 in the first line layer 22 Turn on. In addition, a solder resist layer 51 may be formed on the surface of the first line build-up structure 41. The solder resist layer 51 is formed with a plurality of openings 511 to expose the circuit layer formed on the surface of the first line build-up structure 41. 412 is used as part of an electrical connection pad. And ^: the surface of the line build-up structure 42 also forms a solder resist layer 52. The solder resist layer 2 is also formed with a plurality of openings 521 to expose the circuit layer 422 formed on the surface of the second line build-up structure 42. Part of the electrical connection pad. Therefore, the method of embedding the substrate structure of the wafer in this embodiment can be completed. - As described above, the present invention heats the wafer to a temperature at which the first prepreg and the second prepreg can be melted. When the wafer is placed on the surface of the first prepreg in the opening of the core plate, a portion of the first prepreg is melted to secure the wafer to the first prepreg. Then, when the second prepreg is hot pressed, it also melts due to the temperature of the wafer, so that the materials of the first prepreg and the second prepreg overflow into the opening of the core plate, 20 to 70 kings. Fix the day piece in the core board. The method of the present invention allows the wafer to be attached and fixed to the first prepreg, and does not cause displacement of the wafer when the second prepreg is pressed, thereby solving the problem of conventional wafer fixing. At the same time, it also reduces the cost of the process and saves time. 13 200910558 The above embodiments are intended to cover the scope of the invention as set forth above. The material is accurate, not limited to 5 [Simplified description of the drawings] Fig. 1 is a cross-sectional view of a conventional method of embedding a wafer into a substrate. 2A to 2E are cross-sectional views showing a manufacturing process of a substrate in which a wafer is buried in the present invention. 3 to 5 are cross-sectional views showing a substrate in which a wafer is embedded in another preferred embodiment of the present invention. [Main component symbol description] 11 First dielectric layer 121, 231 Opening 14 Wafer 15 Adhesive layer 162 Circuit layer 21 First prepreg 221 First wiring layer 25 Second metal layer 27, 43 Plating via 272, 432 Insulating material 31a Active Face 311 electrode pad 12, 23 core plate 13 bonding layer 141 electrode pad 161 second dielectric layer 163, 26 conductive blind hole 22 first metal layer 24 second prepreg 251 second circuit layer 271, 431 metal layer 31 wafer 31b Inactive surface 41 First line build-up structure 14 200910558 411, 421 dielectric layer 413, 423 conductive blind hole 51, 52 solder resist layer 412, 422 circuit layer 42 second line build-up structure 511, 521 opening (

1515

Claims (1)

200910558 十、申請專利範園： 1. 一種嵌埋有晶片的基板之製作方法，包括： 提供一第一預浸材（prepreg)，I_ . 一金屬層； p p g)丨側表面形成有一第 i於該第-預浸材另—側表面形成—具㈣口之核心 晶片，並將該晶片置放於該核心板之該開口 = 片具有—主動面及非主動面，且該主動面配置有 複數個電㈣’該非主動面係與該第—預浸材表面接觸； n二預浸材壓合至該晶片的主動面與該核心板表 =並、=熱壓使該第―預浸材及該二賤材之材料填入 該開口内’其中，該第二預浸材 有核板之—表面具 15 20 =該第二金屬層以製作成一第二線路層，並使該 日日片與5玄第二線路層電性導通。 2·如申請專利範圍第i項所述之製作方法，復包 案化該第—金屬層以製作成一第一線路層。 3如申請專利範圍第2項所述之製；方法 穿:第二預浸材、該核心板與該第-預浸材之 通通孔，其係使該第一線路層及該第二線路層電性導 呈二如申請專利範圍第1項所述之製作方法，復包括於 層結；線路層之該第二預浸材表面形成-第二線路増 16 200910558 具範圍第4項所述之製作方法，復包括於 層結構。第—預浸材表面形成—第—線路增 ㈣H申請專利範圍第5項所述之製作方法，復包括形 貝穿邊第二線路增層結構、該第二預浸材、該核 N "sir ΛΑ· °χ第一預浸材與該第一線路増層結構之電鍍導通 孔，其係使該第-線路增層結構、該第_線路層、該第二 線路層及該第二線路增層結構電性導通。200910558 X. Application for Patent Park: 1. A method for fabricating a substrate embedded with a wafer, comprising: providing a first prepreg, I_. a metal layer; ppg) forming a first surface of the crucible The other surface of the first prepreg is formed with a core wafer having a (four) port, and the opening of the wafer is placed on the core plate. The sheet has an active surface and an inactive surface, and the active surface is provided with a plurality of The electric (4) 'the inactive surface is in contact with the surface of the first prepreg; n the second prepreg is pressed to the active surface of the wafer and the core plate table = and = hot pressing to make the first prepreg and The material of the two coffins is filled into the opening, wherein the second prepreg has a surface of the core plate 15 20 = the second metal layer to form a second circuit layer, and the day and the day are 5 Xuan second circuit layer is electrically conductive. 2. If the manufacturing method described in claim i is applied, the first metal layer is packaged to form a first circuit layer. 3, as claimed in claim 2, the method of wearing: the second prepreg, the core plate and the through-hole of the first prepreg, the first circuit layer and the second circuit layer The electrical conductivity is as described in the first aspect of the patent application, and is included in the layering; the second prepreg surface of the circuit layer is formed - the second line 増16 200910558 has the scope described in item 4 The manufacturing method is included in the layer structure. The first prepreg surface is formed - the first line is added (4). The manufacturing method described in claim 5, the second method includes a second line pre-glued structure, the second prepreg, and the core N " Sir χ · ° χ first prepreg and the first via layer structure of the plated vias, the first line buildup structure, the first line layer, the second line layer and the second line The buildup structure is electrically conductive. 10 1510 15 20 I如申請專利範圍第丨項所述之製作方法，其中，加 ，'、、該阳片的步驟係將晶片加熱至一定溫度，使該晶片接置 於該第一預浸材時能使該預浸材融化的溫度。 8.如申請專利範圍第丨項所述之製作方法，其中，該 核心板係為選自絕緣板、具有線路層之電路板及金屬板所 組群組之一者。 9.如申請專利範圍第1項所述之製作方法，其中，該 第一預浸材與該第二預浸材分別為選自由ABF(Ajin〇m〇t〇 Build-up Film)、雙順丁醯二酸醯亞胺/三氮阱（Bismaleimide triazine ; BT)、聯二苯環 丁二烯（benzocyl〇butene ; BCB)、 液晶聚合物（Liquid Crystal Polymer) ' 聚亞醯胺（p〇lyimide ; PI)、聚乙烯醚（Poly(phenylene ether))、聚四氟乙烯（Poly (tetra-fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及 玻璃纖維所組成之群組之一者。 10·如申請專利範圍第1項所述之製作方法，其中，該 第一金屬層與該第二金屬層分別為選自銅、錫、鎳、鉻、 17 200910558 钛、銅-鉻合金以及錫-鉛合金中所組成之群組之一者。 1 1.如申請專利範圍第5項所述之製作方法，其中，該 第一線路增層結構及該第二線路增層結構分 拓一入= 層、疊置於該介電層上 別匕括一；丨電 且電性連接該線路層之以及形成於該介電層中 1820 I The method of claim 2, wherein the step of adding the positive film is to heat the wafer to a temperature such that the wafer is placed in the first prepreg. The temperature at which the prepreg melts. 8. The manufacturing method according to claim 2, wherein the core plate is one selected from the group consisting of an insulating plate, a circuit board having a wiring layer, and a metal plate. 9. The manufacturing method according to claim 1, wherein the first prepreg and the second prepreg are respectively selected from the group consisting of ABF (Ajin〇m〇t〇Build-up Film), and Bismaleimide triazine (BT), benzocyl〇butene (BCB), Liquid Crystal Polymer 'polyimide (p〇lyimide) One of the group consisting of PI), poly(phenylene ether), poly(tetra-fluoroethylene), aromatic polyamide, epoxy resin, and glass fiber. The method of claim 1, wherein the first metal layer and the second metal layer are respectively selected from the group consisting of copper, tin, nickel, chromium, 17 200910558 titanium, copper-chromium alloy, and tin. - one of the groups formed in the lead alloy. 1 1. The method according to claim 5, wherein the first line build-up structure and the second line build-up structure are divided into layers and stacked on the dielectric layer. Included; electrically and electrically connected to the circuit layer and formed in the dielectric layer 18
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI415234B (en) * 2009-05-25 2013-11-11 Nan Ya Printed Circuit Board Packing substrate with embedded chip
US9418931B2 (en) 2014-12-02 2016-08-16 Subtron Technology Co., Ltd. Package structure and manufacturing method thereof
TWI660473B (en) * 2017-12-26 2019-05-21 Industrial Technology Research Institute Package structure and forming method thereof

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI415234B (en) * 2009-05-25 2013-11-11 Nan Ya Printed Circuit Board Packing substrate with embedded chip
US9418931B2 (en) 2014-12-02 2016-08-16 Subtron Technology Co., Ltd. Package structure and manufacturing method thereof
CN105990159A (en) * 2014-12-02 2016-10-05 旭德科技股份有限公司 Packaging structure and manufacturing method thereof
TWI553792B (en) * 2014-12-02 2016-10-11 旭德科技股份有限公司 Package structure and manufacturing method thereof
TWI660473B (en) * 2017-12-26 2019-05-21 Industrial Technology Research Institute Package structure and forming method thereof

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