JP2004343030A - Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board - Google Patents

Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board Download PDF

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JP2004343030A
JP2004343030A JP2003307897A JP2003307897A JP2004343030A JP 2004343030 A JP2004343030 A JP 2004343030A JP 2003307897 A JP2003307897 A JP 2003307897A JP 2003307897 A JP2003307897 A JP 2003307897A JP 2004343030 A JP2004343030 A JP 2004343030A
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Prior art keywords
bump
circuit board
wiring
bumps
printed circuit
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Asao Iijima
朝雄 飯島
Kimiyoshi Endo
仁誉 遠藤
Kazuo Ikenaga
和夫 池永
Hiroshi Ohira
洋 大平
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North Corp
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North Corp
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Priority to JP2003307897A priority Critical patent/JP2004343030A/en
Priority to TW093107787A priority patent/TW200507218A/en
Priority to US10/812,349 priority patent/US20040201096A1/en
Priority to KR1020040021668A priority patent/KR20040086783A/en
Priority to CN200810169136XA priority patent/CN101408688B/en
Priority to CNB2004100318947A priority patent/CN100542375C/en
Publication of JP2004343030A publication Critical patent/JP2004343030A/en
Priority to HK05106338.3A priority patent/HK1073965A1/en
Priority to US12/658,926 priority patent/US20100242270A1/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
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    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
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    • H01L2924/01078Platinum [Pt]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/3025Electromagnetic shielding

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of steps required for forming solder balls 12 for connecting bumps 6 of a wiring circuit board 2 using the bumps 6 as an interlayer connecting means to another board, e.g. a wiring layer 16 of a printed circuit board 14 to achieve low-cost manufacturing of the wiring circuit board 2. <P>SOLUTION: A plurality of bumps 6 are formed directly or via an etching barrier layer 8 on the surface portion of a wiring layer 10, and an interlayer insulating film 4 is formed on a portion where the bumps 6 are not formed on the bump forming surface of the wiring layer 10, and a solder ball 12 is directly formed on the top of each of the solder balls 6. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、例えばIC、LSI等の電子デバイス実装用の配線回路基板、特に高密度実装を実現できる配線回路基板と、その製造方法と、その配線回路基板を備えた回路モジュールに関する。   The present invention relates to a printed circuit board for mounting electronic devices such as ICs and LSIs, and more particularly to a printed circuit board capable of realizing high-density mounting, a manufacturing method thereof, and a circuit module including the printed circuit board.

本願出願人会社は、多層配線回路基板製造技術として、バンプ形成用の銅層(厚さ例えば100μm)の一方の主面に例えばニッケルからなるエッチングバリア層(厚さ例えば1μm)を例えばメッキにより形成し、更に、該エッチングバリア層の主表面に導体回路形成用の銅箔(厚さ例えば18μm)を形成した配線回路基板形成用部材をベースとして用い、それを適宜加工することにより多層配線回路基板を得る技術を開発し、その開発した技術について例えば特願2002−230142(:特開2002−43506号公報)、特願2002−66410等の出願により提案した。   As a multilayer wiring circuit board manufacturing technology, the applicant company of the present application forms an etching barrier layer (thickness, for example, 1 μm) made of, for example, nickel on one main surface of a copper layer (thickness, for example, 100 μm) for bump formation by, for example, plating. Further, a multilayer circuit board is formed by appropriately using a member for forming a circuit board having a copper foil (thickness, for example, 18 μm) for forming a conductor circuit formed on the main surface of the etching barrier layer and processing the material appropriately. Have been developed, and the developed technology has been proposed by, for example, applications such as Japanese Patent Application No. 2002-230142 (JP-A-2002-43506) and Japanese Patent Application No. 2002-66410.

このようなバンプを活かした配線回路基板のバンプと、他のプリント回路基板の配線層との半田ボールを介しての接続は、従来においては、図14に示すように行われていた。
同図において、aは配線回路基板の層間絶縁膜で、例えばポリイミドからなる。bは銅からなるバンプ、cはニッケルからなるエッチングバリア層、dは銅からなる配線層、eは上記層間絶縁膜aの各バンプb毎にその頂面を開口させるようにその上部に形成された開口孔、fは該各開口孔に形成された半田ボール下地膜で、銅下地上にニッケル、金等により形成された多層構造を有し、メッキ等により形成される。
Conventionally, the connection between the bumps of the printed circuit board utilizing the bumps and the wiring layers of the other printed circuit boards via the solder balls has been performed as shown in FIG.
In the figure, a is an interlayer insulating film of the printed circuit board, which is made of, for example, polyimide. b is a bump made of copper, c is an etching barrier layer made of nickel, d is a wiring layer made of copper, and e is formed on the interlayer insulating film a so as to open the top surface of each bump b for each bump b. The open holes f are solder ball base films formed in the respective open holes, and have a multilayer structure formed of nickel, gold or the like on a copper base, and are formed by plating or the like.

このような配線回路基板は、例えば次のようにしてつくられる。上記バンプbとなる厚い銅層と、エッチングバリア層cとなるニッケル層と、配線層dとなる薄い銅層を積層した三層構造の金属層を用意し、その銅層bを選択的にエッチングする(その際にエッチングバリア層cがエッチングストッパとなって配線層dとなる薄い銅層が侵蝕されるのを阻む)ことによりバンプbを形成し、その後、上記層間絶縁膜aのバンプb部の上面から選択的にポリイミド樹脂を化学的にエッチングすることにより或いはレーザ光照射をすることにより上記開口孔eを形成する。   Such a printed circuit board is manufactured, for example, as follows. A metal layer having a three-layer structure in which a thick copper layer serving as the bump b, a nickel layer serving as the etching barrier layer c, and a thin copper layer serving as the wiring layer d is prepared, and the copper layer b is selectively etched. (In this case, the etching barrier layer c serves as an etching stopper to prevent the thin copper layer serving as the wiring layer d from being eroded) to form the bump b, and thereafter, the bump b portion of the interlayer insulating film a The opening e is formed by selectively chemically etching the polyimide resin from the upper surface of the substrate or by irradiating a laser beam.

その後、メッキにより上記半田ボール下地膜fを形成し、該半田ボール下地膜fを選択的にエッチングすることにより配線回路を形成し、更に、銅層dの選択的エッチングにより配線層dを形成する。その後、上記選択的にエッチングされた各半田ボール下地膜f上に半田ボールgを形成する。
そして、上記各配線層dには図示しないLSI等の半導体チップの各電極が接続される等して配線回路基板に半導体チップがフェースダウンあるいはフェースアップで搭載される。
Thereafter, the solder ball base film f is formed by plating, the wiring circuit is formed by selectively etching the solder ball base film f, and the wiring layer d is formed by selective etching of the copper layer d. . Thereafter, a solder ball g is formed on each of the selectively etched solder ball base films f.
Then, the semiconductor chip is mounted face down or face up on the printed circuit board by connecting each electrode of a semiconductor chip such as an LSI (not shown) to each wiring layer d.

更に、その配線回路基板には、図14に示すようにプリント回路基板hに搭載される。具体的には、プリント回路基板hの各配線層iを、配線回路基板の、該各配線層iに対応する半田ボールgに接続することにより、配線回路基板がプリント回路基板hに搭載される。
特開2002−43506号公報 特願2002−66410
Further, the printed circuit board h is mounted on the printed circuit board as shown in FIG. Specifically, each wiring layer i of the printed circuit board h is connected to a solder ball g corresponding to each wiring layer i of the printed circuit board, so that the printed circuit board is mounted on the printed circuit board h. .
JP 2002-43506 A Japanese Patent Application No. 2002-66410

ところで、上述した従来の技術には、配線回路基板に層間絶縁膜aを形成した後、半田ボールgを形成するまでに要する工程数が多く、製造コストが高くなるという問題があった。
即ち、上記従来の技術によれば、層間絶縁膜aの形成後、その選択的エッチングにより開口孔eを形成し、メッキにより複数層の半田ボール下地膜fを形成し、その選択的エッチングを行って各バンプb毎にそれと接続された半田ボール下地膜fが独立するようにパターニングし、その後、半田ボールgを形成するというかなり多くの工程が必要であった。
By the way, the above-described conventional technique has a problem that the number of steps required to form the solder balls g after forming the interlayer insulating film a on the printed circuit board is large, and the manufacturing cost is increased.
That is, according to the above-described conventional technique, after the interlayer insulating film a is formed, an opening hole e is formed by selective etching thereof, a plurality of solder ball base films f are formed by plating, and the selective etching is performed. Therefore, it is necessary to perform a considerable number of steps of patterning each bump b so that the solder ball base film f connected thereto is independent, and then forming the solder ball g.

本発明はこのような問題を解決すべく為されたもので、バンプを層間接続手段とする配線回路基板の該バンプと他の基板、例えばプリント回路基板の配線層等との間を接続するのに要する工程を少なくすることのできるようにし、延いては、配線回路基板の低価格化を図ることを目的とする。   The present invention has been made to solve such a problem, and is intended to connect between a bump of a printed circuit board using a bump as an interlayer connection means and another board, for example, a wiring layer of a printed circuit board. It is an object of the present invention to reduce the number of steps required for the above, and to reduce the cost of the printed circuit board.

請求項1の配線回路基板は、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、該配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したことを特徴とする。
尚、配線層と、バンプとの間に、エッチングバリア層を設けることは必ずしも不可欠ではない。というのは、金属層を一方の表面側から選択的にハーフエッチング(金属層の厚さよりも適宜浅いエッチング)することによりバンプを形成するということが可能であり、その場合にはエッチングバリア層が必要ではないからである。このことは、他の請求項の配線回路基板にも当てはまる。
The printed circuit board according to claim 1, wherein a plurality of bumps are formed directly on a surface portion of the wiring layer or via an etching barrier layer, and an interlayer insulating is formed on a portion of the wiring layer where the bumps are not formed on the bump forming surface. A film is formed, and a solder ball is formed directly on the top surface of the bump or via a wiring layer formed on the surface of the interlayer insulating film so as to be connected to the bump.
It is not always essential to provide an etching barrier layer between the wiring layer and the bump. That is, it is possible to form a bump by selectively half-etching the metal layer from one surface side (etching appropriately shallower than the thickness of the metal layer), in which case the etching barrier layer is formed. It is not necessary. This applies to the printed circuit board of the other claims.

請求項2の配線回路基板は、請求項1記載の配線回路基板において、前記配線層及びバンプが銅からなることを特徴とする。
請求項3の配線回路基板は、請求項1又は2記載の配線回路基板において、前記層間絶縁膜に、バンプが多数形成されたバンプ形成領域と、バンプが形成されないフレキシブルなバンプ非形成領域とを有し、該バンプ非形成領域が曲折可能にしてなる或いは少なくとも一部にて曲折してなることを特徴とする。
According to a second aspect of the present invention, in the wiring circuit board according to the first aspect, the wiring layers and the bumps are made of copper.
According to a third aspect of the present invention, there is provided the wired circuit board according to the first or second aspect, wherein the interlayer insulating film includes a bump-formed area where a large number of bumps are formed and a flexible bump-free area where no bump is formed. Wherein the non-bump forming region is bendable or at least partially bent.

請求項4の配線回路基板は、請求項1、2又は3記載の配線回路基板において、前記各バンプの頂面が凹球面に形成され、上記バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなることを特徴とする。   According to a fourth aspect of the present invention, in the printed circuit board according to the first, second or third aspect, the top surface of each of the bumps is formed to have a concave spherical surface, and the top surface of the bump is formed directly on the concave surface of the bump. Characterized in that solder balls are formed thereon.

請求項5の回路モジュールは、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、リジットな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成されたリジットな配線回路基板と、からなり、上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記リジットな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなることを特徴とする。   6. The circuit module according to claim 5, wherein a plurality of bumps are formed directly on the surface of the wiring layer or via an etching barrier layer, and an interlayer insulating film is formed on a portion of the wiring layer where the bumps are not formed on the bump forming surface. A flexible wiring circuit board on which solder balls are formed, directly on the top surface of the bump, or via a wiring layer formed on the surface of the interlayer insulating film so as to be connected to the bump; A rigid wiring circuit board having a wiring film connected to the wiring film formed on at least one surface of the flexible insulating circuit board, and at least a part of the wiring film of the flexible wiring circuit board; At least a part of the wiring film of the printed circuit board is connected via the solder ball.

請求項6の回路モジュールは、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、フレキシブルな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成された上記配線回路基板とは別のフレキシブルな配線回路基板と、からなり、上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記別のフレキシブルな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなることを特徴とする。   7. The circuit module according to claim 6, wherein a plurality of bumps are formed directly on a surface portion of the wiring layer or via an etching barrier layer, and an interlayer insulating film is formed on a portion of the wiring layer where the bumps are not formed on the bump forming surface. A flexible wiring circuit board on which solder balls are formed, directly on the top surface of the bump, or via a wiring layer formed on the surface of the interlayer insulating film so as to connect to the bump, And a flexible wiring circuit board different from the wiring circuit board in which a wiring film connected to the wiring film is formed on at least one surface of the flexible insulating circuit board. At least a part and at least a part of the wiring film of the another flexible wiring circuit board are connected via the solder ball.

請求項7の回路モデュールは、請求項5又は6記載の回路モデュールにおいて、前記各バンプの頂面が凹球面に形成され、上記バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなることを特徴とする。
請求項8の配線回路基板の製造方法は、金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記各バンプの露出する頂面上に半田ボールを形成することを特徴とする。
The circuit module according to claim 7 is the circuit module according to claim 5 or 6, wherein a top surface of each of the bumps is formed into a concave spherical surface, and a solder ball is directly provided on the top surface formed on the concave spherical surface of the bump. It is characterized by being formed.
The method of manufacturing a printed circuit board according to claim 8 is to prepare a substrate on which a bump is formed directly on the surface of a metal layer or via an etching barrier layer, and the bump on the surface of the metal layer on the bump formation side is formed. Forming an interlayer insulating film thicker than the bumps on the unexposed portions; polishing the interlayer insulating film of the substrate until the top surfaces of the bumps are exposed; and solder balls on the exposed top surfaces of the bumps of the substrate. Is formed.

請求項9の配線回路基板の製造方法は、金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記層間絶縁膜の表面に金属層を形成し、該層間絶縁膜表面の金属層を選択的にエッチングすることにより配線層を形成し、各バンプの露出する頂面上に又は該バンプと接続された上記配線層上に半田ボールを形成することを特徴とする。   In the method for manufacturing a printed circuit board according to the ninth aspect, a substrate having a bump formed directly on a surface of a metal layer or via an etching barrier layer is prepared, and a bump is formed on a surface of the metal layer of the substrate on a bump formation side. Forming an interlayer insulating film thicker than the bumps on the portions that are not formed, polishing the interlayer insulating film of the substrate until the top surface of each bump is exposed, and forming a metal layer on the surface of the interlayer insulating film of the substrate. Forming a wiring layer by selectively etching a metal layer on the surface of the interlayer insulating film, and forming a solder ball on an exposed top surface of each bump or on the wiring layer connected to the bump. It is characterized by.

請求項10の配線回路基板の製造方法は、請求項8又は9記載の配線回路基板の製造方法において、前記層間絶縁膜を形成するよりも前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくする工程を有することを特徴とする。
請求項11の配線回路基板の製造方法は、請求項8、9又は10記載の配線回路基板の製造方法において、前記基板の前記層間絶縁膜を前記各バンプの頂面が露出するまで研磨した後、該バンプの露出した頂面上に前記半田ボールを形成する前に、該バンプの頂面をエッチングすることにより凹球面にする工程を有することを特徴とする。
According to a tenth aspect of the present invention, in the method of the eighth or ninth aspect, the bumps are pressed from above and crushed before forming the interlayer insulating film. And a step of increasing the diameter of the top surface by the method.
The method of manufacturing a printed circuit board according to claim 11 is the method of manufacturing a printed circuit board according to claim 8, 9 or 10, wherein after polishing the interlayer insulating film of the substrate until the top surface of each of the bumps is exposed. And forming a concave spherical surface by etching the top surface of the bump before forming the solder ball on the exposed top surface of the bump.

請求項12の回路モジュールは、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成した一つの配線回路基板と、液晶素子の基板を成し、透明配線膜を有する液晶装置用透明基板と、からなり、上記一つの配線回路基板の各バンプと、上記別の液晶装置用透明基板の透明配線膜の上記各バンプと対応する部分とが、直接に或いは上記バンプの頂面に形成した配線膜及び半田ボールを介して接続されて液晶装置を成すことを特徴とする。   13. The circuit module according to claim 12, wherein a plurality of bumps are formed directly on a surface portion of the wiring layer or via an etching barrier layer, and an interlayer insulating film is formed on a portion of the wiring layer where the bumps are not formed on the bump forming surface. And a transparent substrate for a liquid crystal device, which forms a substrate for the liquid crystal element and has a transparent wiring film, comprising: a bump for the one wiring circuit substrate; A portion corresponding to each of the bumps of the transparent wiring film of the transparent substrate is connected directly or via a wiring film and a solder ball formed on the top surface of the bump to form a liquid crystal device.

請求項13の回路モジュールは、請求項12記載の回路モジュールにおいて、前記一つの配線回路基板の各バンプの頂面が凹球面に形成され、その凹球面に形成された上記頂面に直接に半田ボールが形成されてなることを特徴とする。   According to a thirteenth aspect of the present invention, in the circuit module according to the twelfth aspect, the top surface of each bump of the one printed circuit board is formed into a concave spherical surface, and the top surface formed on the concave spherical surface is directly soldered to the top surface. The ball is formed.

請求項1の配線回路基板によれば、バンプの頂面に直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して半田ボールを形成してなるので、半田ボールの下地となる半田ボール下地膜をわざわざ形成する必要がなくなり、配線回路基板を製造するに必要となる製造工数の低減を図ることができる。
従って、配線回路基板の低価格化を図ることができる。
According to the printed circuit board of the first aspect, since the solder ball is formed directly on the top surface of the bump or via the wiring layer formed on the surface of the interlayer insulating film so as to be connected to the bump, It is not necessary to separately form the solder ball base film which is the base of the solder ball, and the number of manufacturing steps required for manufacturing the printed circuit board can be reduced.
Therefore, the cost of the printed circuit board can be reduced.

請求項2の配線回路基板によれば、前記配線層及びバンプが比抵抗が小さな銅からなるので、寄生抵抗を低減することができる。
請求項3の配線回路基板によれば、前記層間絶縁膜に、バンプが多数形成されたバンプ形成領域と、バンプが形成されないバンプ非形成領域とを設け、その一部を曲折して使用するので、LSI等の半導体チップを立体的に配置して使用することができ、限られた空間内に多数のチップを高密度配置することができる。
According to the wired circuit board of the second aspect, since the wiring layer and the bumps are made of copper having a small specific resistance, the parasitic resistance can be reduced.
According to the wired circuit board of the third aspect, the interlayer insulating film is provided with a bump forming region in which a large number of bumps are formed and a bump non-forming region in which no bump is formed, and a part thereof is bent and used. And semiconductor chips such as LSIs can be arranged and used three-dimensionally, and a large number of chips can be arranged with high density in a limited space.

請求項4の配線回路基板によれば、請求項1、2又は3の配線回路基板において、バンプの凹球面に形成された頂面に半田ボールを直接に形成するので、接続面積をより広くし、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができる。
請求項5の回路モジュールによれば、請求項1に係るフレキシブルな配線回路基板と、リジットな配線回路基板とを接続してなるので、フレキシブルな配線回の電極をフレキシブルな配線回路基板によって引き出すというようなことが為し得る。
According to the printed circuit board of the fourth aspect, in the printed circuit board of the first, second or third aspect, since the solder ball is directly formed on the top surface formed on the concave spherical surface of the bump, the connection area can be increased. Since the connection strength can be increased, the reliability can be further increased and the life can be prolonged.
According to the circuit module of the fifth aspect, since the flexible wiring circuit board according to the first aspect and the rigid wiring circuit board are connected to each other, the electrodes of the flexible wiring are drawn out by the flexible wiring circuit board. You can do something like that.

請求項6の回路モジュールによれば、請求項1に係るフレキシブルな配線回路基板と、フレキシブルな配線回路基板とを接続してなるので、フレキシブルな配線回路基板同士を一体化した回路モジュールを提供することができる。
請求項7の回路モジュールによれば、請求項5又は6記載の回路モジュールにおいて、バンプの凹球面に形成された頂面に半田ボールを直接に形成するので、接続面積をより広くし、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができる。
According to the circuit module of claim 6, since the flexible printed circuit board according to claim 1 and the flexible printed circuit board are connected, a circuit module in which the flexible printed circuit boards are integrated with each other is provided. be able to.
According to the circuit module of the seventh aspect, in the circuit module of the fifth or sixth aspect, since the solder ball is directly formed on the top surface formed on the concave spherical surface of the bump, the connection area is increased, and the connection strength is increased. Can be further strengthened, so that the reliability can be further increased and the service life can be prolonged.

請求項8の配線回路基板の製造方法によれば、金属層の表面にバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面にバンプより厚く層間絶縁膜を形成し、該層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記各バンプの露出する頂面上に半田ボールを形成するので、請求項1の配線回路基板を製造することができる。   According to the method of manufacturing a wired circuit board of claim 8, a substrate having a bump formed on the surface of the metal layer is prepared, and an interlayer insulating film thicker than the bump is formed on the surface of the metal layer of the substrate on the bump formation side. 2. The printed circuit board according to claim 1, wherein the interlayer insulating film is polished until the top surface of each bump is exposed, and solder balls are formed on the exposed top surface of each bump of the substrate. it can.

請求項9の配線回路基板の製造方法によれば、金属層の表面にバンプを形成した基板を用意し、該基板の金属層のバンプ形成側の面にバンプより厚く層間絶縁膜を形成し、該層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、該基板の上記各バンプの露出する頂面上に半田ボールを形成し、該基板の上記層間絶縁膜の表面に金属層を形成し、該層間絶縁膜表面の金属層を選択的にエッチングすることにより配線層を形成し、上記各バンプの露出する頂面上に又は該バンプと接続された上記配線層上に半田ボールを形成したので、層間絶縁膜の両面に配線膜を有する配線回路基板を製造することができる。   According to the method of manufacturing a wired circuit board according to claim 9, a substrate having a bump formed on a surface of a metal layer is prepared, and an interlayer insulating film thicker than the bump is formed on a surface of the metal layer on the bump formation side, The interlayer insulating film is polished until the top surface of each bump is exposed, a solder ball is formed on the exposed top surface of each bump of the substrate, and a metal layer is formed on the surface of the interlayer insulating film of the substrate. Forming a wiring layer by selectively etching a metal layer on the surface of the interlayer insulating film, and forming a solder ball on the exposed top surface of each of the bumps or on the wiring layer connected to the bumps. Since it is formed, a printed circuit board having a wiring film on both surfaces of an interlayer insulating film can be manufactured.

請求項10の配線回路基板の製造方法によれば、前記層間絶縁膜を形成する前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくするので、半田ボールの各バンプへの接着強度を充分に強めることが容易に為し得る。
請求項11の配線回路基板の製造方法は、請求項8、9又は10記載の配線回路基板の製造方法において、前記層間絶縁膜を前記各バンプの頂面が露出するまで研磨した後、該バンプの露出した頂面上に前記半田ボールを形成する前に、該バンプの頂面をエッチングすることにより凹球面にするので、その後、その頂面に形成する半田ボールのその頂面との接続面積をより広くし、接続強度をより強めることができる。従って、配線回路基板の信頼度をより高め、寿命を長くすることができる。
According to the method of manufacturing a printed circuit board according to claim 10, before forming the interlayer insulating film, the diameter of the top surface is increased by pressing and crushing each bump from above. It is easy to sufficiently increase the bonding strength to the bump.
12. The method of manufacturing a printed circuit board according to claim 11, wherein the interlayer insulating film is polished until the top surface of each of the bumps is exposed. Prior to forming the solder ball on the exposed top surface, the top surface of the bump is etched into a concave spherical surface, and thereafter, the connection area of the solder ball formed on the top surface with the top surface And the connection strength can be further increased. Therefore, the reliability of the printed circuit board can be further increased, and the life can be prolonged.

請求項12の回路モジュールによれば、液晶装置の透明配線膜を、請求項1の配線回路基板を通じて引き出すようにすることができる。
請求項13の回路モジュールによれば、請求項12の回路モジュールにおいて、バンプの凹球面に形成された頂面に半田ボールを直接に形成するので、接続面積をより広くし、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができる。
According to the circuit module of the twelfth aspect, the transparent wiring film of the liquid crystal device can be drawn through the wired circuit board of the first aspect.
According to the circuit module of the thirteenth aspect, in the circuit module of the twelfth aspect, since the solder ball is directly formed on the top surface formed on the concave spherical surface of the bump, the connection area is increased and the connection strength is further increased. Therefore, the reliability can be further increased and the life can be prolonged.

本発明は、基本的には、回路モジュール等に用いられる配線回路基板として、配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、該配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したものを提供するというものであり、上記のバンプは銅により形成することが好ましい。というのは、導電性、機械的強度が優れ、また、バンプを銅により形成して層間接続手段として用いる技術は既に本願出願人会社において確立した技術となっているからである。   The present invention basically forms a plurality of bumps directly on a surface portion of a wiring layer or via an etching barrier layer as a wiring circuit board used for a circuit module or the like, and forms a bump on a bump forming surface of the wiring layer. An interlayer insulating film is formed on a portion where the bump is not formed, and solder is formed directly on the top surface of the bump or via a wiring layer formed on the surface of the interlayer insulating film so as to connect to the bump. This is to provide a ball formed, and the bump is preferably formed of copper. The reason for this is that the conductivity and mechanical strength are excellent, and the technique of forming bumps of copper to use as interlayer connection means has already been established by the applicant company.

本発明配線回路基板の一つの良好な実施の形態は、バンプを設けたバンプ形成領域と、バンプを設けないバンプ非形成領域を設け、該バンプ非形成領域を以てフレキシブルな領域とし、バンプ形成領域を以てリジットな領域とするというものである。
また、別の良好な実施形態として、バンプはその形成後、層間絶縁膜形成前に、上から押し潰してその頂面の面積を広くすることが挙げられる。その面積を広くすることはバンプと半田ボールとの接続面積の増大に繋がり、延いては、接続強度の増大、信頼性の向上に繋がるからである。
One preferred embodiment of the wired circuit board of the present invention is to provide a bump forming region provided with bumps and a non-bump forming region where no bump is provided, and to make the non-bump forming region a flexible region, with the bump forming region. It is a rigid region.
In another preferred embodiment, after the bump is formed and before the interlayer insulating film is formed, the bump is crushed from above to increase the area of the top surface. Increasing the area leads to an increase in the connection area between the bump and the solder ball, which in turn leads to an increase in connection strength and an improvement in reliability.

また、バンプの半田ボールとの接続面となる頂面を例えばエッチングにより凹球面に形成し、その凹球面に形成された頂面に半田ボールを直接に形成することとすることも良好な実施の形態例として挙げられる。というのは、接続面積をより広くし、また半田ボールが基板に食い込んだ形になるので、接続強度をより強めることができるので、より信頼度を高め、寿命を長くすることができるからである。
尚、バンプの半田ボールとの接続面となる頂面を例えばエッチングにより凹球面に形成することとする実施の形態は、本発明における、バンプの頂面に直接半田ボールを形成することとするすべての形態に対して適用することができる。
It is also preferable that the top surface of the bump to be connected to the solder ball is formed into a concave spherical surface by, for example, etching, and the solder ball is directly formed on the top surface formed on the concave spherical surface. It is mentioned as a form example. The reason is that the connection area is made wider, and the shape of the solder ball bites into the board, so that the connection strength can be increased, so that the reliability can be increased and the life can be prolonged. .
The embodiment in which the top surface serving as the connection surface of the bump with the solder ball is formed into a concave spherical surface by, for example, etching is the same as the embodiment in which the solder ball is directly formed on the top surface of the bump in the present invention. It can be applied to the form of

以下、本発明を図示実施例に従って詳細に説明する。
図1は本発明配線回路基板の第1の実施例を示す断面図である。
図において、2は配線回路基板、4はポリイミド樹脂からなる層間絶縁膜、6は該層間絶縁膜4を略貫通するように形成された略コニーデ状のバンプで、銅からなる。そして、各バンプ6の頂面は、層間絶縁膜4から露出し、該層間絶縁膜4表面と同一平面上に位置するようにされている。
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
FIG. 1 is a sectional view showing a first embodiment of the printed circuit board of the present invention.
In the drawing, 2 is a printed circuit board, 4 is an interlayer insulating film made of a polyimide resin, and 6 is a substantially conide-shaped bump formed substantially through the interlayer insulating film 4 and made of copper. The top surface of each bump 6 is exposed from the interlayer insulating film 4 and is located on the same plane as the surface of the interlayer insulating film 4.

8は該バンプ6の底面に形成されたニッケルからなるエッチングバリア層、10は銅からなる配線層で、上記各バンプ6は上記エッチングバリア層8を介して該配線層10に形成されている。尚、該配線層10は銅膜表面に金、銀、ロジウム、錫、半田、アルミニウム等を被覆したものであっても良い。該配線層10には図1、2では図示を省略した半導体チップの電極が、或いはハンダボール付きのIC(フリップチップ)が直接に或いはボンディングワイヤを介して接続される。尚、この接続態様の各別の例を図4(A)、(B)に示し、また、その説明を後で行う。   Reference numeral 8 denotes an etching barrier layer made of nickel formed on the bottom surface of the bump 6, and reference numeral 10 denotes a wiring layer made of copper. Each bump 6 is formed on the wiring layer 10 via the etching barrier layer 8. The wiring layer 10 may be a copper film surface coated with gold, silver, rhodium, tin, solder, aluminum or the like. Electrodes of a semiconductor chip, not shown in FIGS. 1 and 2, or ICs (flip chips) with solder balls are connected to the wiring layer 10 directly or via bonding wires. 4A and 4B show other examples of this connection mode, and a description thereof will be given later.

12は各バンプ6の頂面に形成された半田ボール、14は配線回路基板2にマウントされる例えばリジットなプリント回路基板(2点鎖線で示した。)、16は該プリント回路基板14の表面に形成された配線層(2点鎖線で示した。)である。
尚、該各配線層16に、それと対応するところの配線回路基板2のバンプ6を半田ボール12を介して接続することにより、配線回路基板2のプリント回路基板14への配線回路基板2の搭載が行われる。すると、配線回路基板2とプリント回路基板14からなる回路モジュールができる。配線回路基板2は薄くフレキシブルであるのに対して、プリント回路基板14は上述したようにリジットであるので、その回路モジュールは、リジットなプリント回路基板14とフレキシブルな配線回路基板2を組み付けたものとなる。従って、例えばリジットなプリント回路基板14の電極乃至端子等をフレキシブルな配線回路基板2により電気的に導出するというような回路モジュールを得ることができる。
Reference numeral 12 denotes a solder ball formed on the top surface of each bump 6, reference numeral 14 denotes a rigid printed circuit board mounted on the printed circuit board 2 (indicated by a two-dot chain line), and reference numeral 16 denotes a surface of the printed circuit board 14. Is a wiring layer (indicated by a two-dot chain line) formed in FIG.
The wiring circuit board 2 is mounted on the printed circuit board 14 of the wiring circuit board 2 by connecting the corresponding bumps 6 of the wiring circuit board 2 to the wiring layers 16 via the solder balls 12. Is performed. Then, a circuit module including the printed circuit board 2 and the printed circuit board 2 is formed. The printed circuit board 14 is rigid, as described above, while the printed circuit board 2 is thin and flexible. Therefore, the circuit module is a combination of the rigid printed circuit board 14 and the flexible printed circuit board 2. It becomes. Accordingly, it is possible to obtain a circuit module in which, for example, the electrodes or terminals of the rigid printed circuit board 14 are electrically led out by the flexible printed circuit board 2.

このような配線回路基板2によれば、層間絶縁膜4の表面に露出する各バンプ6の頂面に直接半田ボール12を形成するので、半田ボールの下地となる半田ボール下地膜をわざわざ形成する必要がなくなり、配線回路基板2を製造するに必要となる製造工数の低減を図ることができる。   According to such a printed circuit board 2, since the solder balls 12 are formed directly on the top surfaces of the bumps 6 exposed on the surface of the interlayer insulating film 4, the solder ball base film serving as the base of the solder balls is bothersomely formed. This eliminates the necessity, and the number of manufacturing steps required for manufacturing the printed circuit board 2 can be reduced.

以下に、断面図である図2(A)〜(D)及び図3(E)〜(H)に従って図1に示した配線回路基板(第1の実施例)2の製造方法を工程順(A)〜(H)に説明する。
(A)図2(A)に示すように、中間層としてエッチングバリア層を含む三層構造の金属板20を用意する。20aは該金属板20の銅からなる厚い金属層で、選択的エッチングにより上記バンプ6となる。20bは該金属板20の中間層を成すエッチングバリア層(8)で、上記厚い金属層20aの選択的エッチングのときに次に述べる銅からなる薄い金属層(20c)が侵蝕(エッチング)されることを阻む役割を果たす。20cは選択的エッチングにより配線層10となる薄い銅からなる金属層である。
Hereinafter, the method of manufacturing the printed circuit board (first embodiment) 2 shown in FIG. 1 according to the sectional views of FIGS. 2A to 2D and FIGS. A) to (H) will be described.
(A) As shown in FIG. 2A, a metal plate 20 having a three-layer structure including an etching barrier layer as an intermediate layer is prepared. Reference numeral 20a denotes a thick metal layer made of copper of the metal plate 20, which becomes the bump 6 by selective etching. Reference numeral 20b denotes an etching barrier layer (8) serving as an intermediate layer of the metal plate 20, and a thin metal layer (20c) made of copper described below is eroded (etched) when the thick metal layer 20a is selectively etched. It plays a role in blocking things. 20c is a metal layer made of thin copper which becomes the wiring layer 10 by selective etching.

(B)次に、例えばフォトレジスト膜の塗布形成、露光、現像等によりエッチングマスク膜を形成し、該エッチングマスク膜をマスクとして上記厚い金属層20aを選択的にエッチングすることにより、バンプ6を形成する。その後、エッチングマスク膜を除去する。図2(A)はそのエッチングマスク膜の除去後の状態を示す。
(C)次に、上記エッチングバリア層20b(8)を、上記バンプ6をマスクとしてエッチングすることにより除去する。図2(C)はその除去後の状態を示す。
(B) Next, an etching mask film is formed by, for example, application and formation of a photoresist film, exposure, development, and the like, and the thick metal layer 20a is selectively etched using the etching mask film as a mask, thereby forming the bumps 6. Form. After that, the etching mask film is removed. FIG. 2A shows a state after the etching mask film is removed.
(C) Next, the etching barrier layer 20b (8) is removed by etching using the bump 6 as a mask. FIG. 2C shows the state after the removal.

(D)次に、前駆体の状態にある液状の例えばポリイミド樹脂をコータ等により塗布し、べーク処理することによりイミド化を行い、丈夫なポリイミド樹脂にする。該樹脂はバンプ6の高さより若干厚く、従って各バンプ6を覆う層間絶縁膜4を形成する。図2(D)は該層間絶縁膜4形成後の状態を示す。
(E)次に、上記層間絶縁膜4の表面部を、上記各バンプ6の頂面が完全に露出するまで研磨し、絶縁樹脂層とバンプ頂面を面一にする。図3(E)はその研磨後の状態を示す。
(D) Next, a liquid polyimide resin in a precursor state is applied by a coater or the like, and is baked to be imidized to obtain a durable polyimide resin. The resin is slightly thicker than the height of the bumps 6 and thus forms an interlayer insulating film 4 covering each bump 6. FIG. 2D shows a state after the formation of the interlayer insulating film 4.
(E) Next, the surface portion of the interlayer insulating film 4 is polished until the top surface of each bump 6 is completely exposed, so that the insulating resin layer and the bump top surface are flush with each other. FIG. 3E shows a state after the polishing.

(F)次に、上記金属層20cを選択的にエッチングすることにより配線層10を形成する。尚、該配線層10の形成前又は形成後に2点鎖線で示すように、例えば半田レジストからなるダム18を形成して半田接合面の均一化とダレによるショート防止を図るようにしても良い。
(G)次に、半田ボールとなる球状半田を各バンプ6の上記層間絶縁膜4から露出する頂面上に配置し、配線回路基板2を加熱炉に通してリフロー処理することにより各バンプ6頂面に該バンプ6接続固定された半田ボール12を形成する。図3(G)はそのリフロー処理後の状態を示す。
(F) Next, the wiring layer 10 is formed by selectively etching the metal layer 20c. As shown by a two-dot chain line before or after the formation of the wiring layer 10, a dam 18 made of, for example, a solder resist may be formed to make the solder joint surface uniform and prevent short circuit due to sagging.
(G) Next, a spherical solder to be a solder ball is arranged on the top surface of each bump 6 exposed from the interlayer insulating film 4, and the printed circuit board 2 is passed through a heating furnace and subjected to a reflow treatment, thereby forming each bump 6. A solder ball 12 connected and fixed to the bump 6 is formed on the top surface. FIG. 3G shows a state after the reflow processing.

尚、球状半田の配置は、具体的には、各バンプ6の頂面と対応する位置関係で球状半田を位置させ、真空吸引でその球状半田をその位置に保持できる治具を用い、その治具を、各球状半田が対応するバンプ6上に位置するように位置させ、真空吸引を停止することにより各球状半田の自重により対応するバンプ6頂面上に落させて位置させるという方法で行うこともできる。また、半田クリームをバンプ面に選択的に印刷し、加熱リフローすることにより、半田ボールを形成するようにしても良い。   Specifically, the arrangement of the spherical solder is performed by positioning the spherical solder in a positional relationship corresponding to the top surface of each bump 6 and using a jig capable of holding the spherical solder at that position by vacuum suction. The tool is positioned so that each spherical solder is positioned on the corresponding bump 6, and the vacuum suction is stopped to drop and position the spherical solder on the corresponding bump 6 top surface by its own weight. You can also. Alternatively, a solder ball may be formed by selectively printing solder cream on the bump surface and performing heating reflow.

(H)図3(H)は、プリント回路基板14に該配線回路基板2を搭載した状態を示す。尚、一般に、該配線回路基板2にはプリント回路基板等への搭載前に、例えば半導体チップ等が搭載されるが、図3ではその半導体チップの図示を省略した。尚、半導体チップの搭載例は後で図4(A)、(B)を参照して説明する。
このような配線回路基板2の製造方法によれば、図3(G)に示すように、層間絶縁膜4の表面に露出する各バンプ6の頂面に直接半田ボール12を形成するので、前述のように、半田ボールの下地となる半田ボール下地膜をわざわざ形成する必要がなくなり、配線回路基板2を製造するに必要となる製造工数を低減することができる。
(H) FIG. 3H shows a state in which the wiring circuit board 2 is mounted on the printed circuit board 14. Generally, for example, a semiconductor chip or the like is mounted on the printed circuit board 2 before mounting on the printed circuit board or the like, but the semiconductor chip is not shown in FIG. An example of mounting a semiconductor chip will be described later with reference to FIGS.
According to such a method of manufacturing the printed circuit board 2, the solder balls 12 are formed directly on the top surfaces of the bumps 6 exposed on the surface of the interlayer insulating film 4, as shown in FIG. As described above, there is no need to separately form the solder ball base film that is the base of the solder ball, and the number of manufacturing steps required to manufacture the printed circuit board 2 can be reduced.

図4(A)、(B)は配線回路基板2への半導体チップの各別の搭載例を示す断面図である。図1では、配線回路基板2の2点鎖線で示したリジットなプリント回路基板14への搭載例を示したが、図4(A)、(B)に示すように、本配線回路基板2には半導体チップを直接的に搭載することができるのである。
図4(A)は半導体チップの電極と配線回路基板2の配線層10との接続をワイヤボンディングにより行う搭載例を示し、図4(B)は半導体チップ24の電極10aと配線回路基板2の配線層10とを直接接続することにより配線回路基板2に半導体チップ24を搭載する搭載例を示す。
4A and 4B are cross-sectional views showing different examples of mounting a semiconductor chip on the printed circuit board 2. FIG. FIG. 1 shows an example in which the printed circuit board 2 is mounted on a rigid printed circuit board 14 indicated by a two-dot chain line. However, as shown in FIGS. Can directly mount a semiconductor chip.
FIG. 4A shows a mounting example in which the connection between the electrodes of the semiconductor chip and the wiring layer 10 of the printed circuit board 2 is performed by wire bonding, and FIG. An example of mounting the semiconductor chip 24 on the printed circuit board 2 by directly connecting the wiring layer 10 will be described.

図4(A)を参照してワイヤボンディングを用いた搭載例を説明する。図4(A)において、24はLSI等の半導体チップ、26は該半導体チップ24を配線回路基板2に固定するダイボンド接着層、28は配線回路基板2の配線層10と、半導体チップ24の電極との間を接続するボンディングワイヤで、例えば金線からなる。各電極は該ボンディングワイヤ28及び配線層10を通じていずれかのバンプ6に、更には半田ボール12に接続され、電気的に導出される。30は半導体チップ24を封止する樹脂で、通常エポキシ樹脂からなるポッテング樹脂である。   An example of mounting using wire bonding will be described with reference to FIG. In FIG. 4A, reference numeral 24 denotes a semiconductor chip such as an LSI, 26 denotes a die bonding adhesive layer for fixing the semiconductor chip 24 to the printed circuit board 2, and 28 denotes the wiring layer 10 of the printed circuit board 2 and electrodes of the semiconductor chip 24. , For example, a gold wire. Each electrode is connected to one of the bumps 6 through the bonding wire 28 and the wiring layer 10 and further to the solder ball 12, and is electrically led out. Reference numeral 30 denotes a resin for sealing the semiconductor chip 24, which is a potting resin usually made of an epoxy resin.

図4(B)を参照してフリップチップタイプのICの搭載例を説明する。IC、LSI等の半導体チップ24にはハンダからなるバンプ乃至金メッキバンプ10aが形成されており、配線基板2に搭載後、必要に応じ封止樹脂26を注入硬化させてなる。また、半導体チップ24にAuのスタッドバンプを形成し、異方性導電接着剤(図面略)を介して回路基板に接合してもよい。そのボンディング後、半導体チップ24・配線回路基板2間が樹脂26で固定され、封止される。   An example of mounting a flip-chip type IC will be described with reference to FIG. A semiconductor chip 24 such as an IC or LSI is formed with solder bumps or gold-plated bumps 10a. After being mounted on the wiring board 2, a sealing resin 26 is injected and cured as necessary. Alternatively, Au stud bumps may be formed on the semiconductor chip 24 and joined to the circuit board via an anisotropic conductive adhesive (not shown). After the bonding, the space between the semiconductor chip 24 and the wiring circuit board 2 is fixed with a resin 26 and sealed.

図5は本発明配線回路基板の第2の実施例を示す断面図である。
本実施例2’は、図1に示した実施例2とは、各バンプ6の頂面6aを凹球面に形成し、その凹球面に形成された頂面6aに半田ボール12を形成した点でのみ相違し、それ以外の点では、共通する。
このように、本実施例2’によれば、各バンプ6の頂面6aを凹球面に形成するので、頂面6aと半田ボール12との接続面積が増加し、接続強度を強めて、配線回路基板としての信頼度を高め、長寿命化を図ることができる。
FIG. 5 is a sectional view showing a second embodiment of the printed circuit board of the present invention.
Embodiment 2 'is different from Embodiment 2 shown in FIG. 1 in that the top surface 6a of each bump 6 is formed into a concave spherical surface, and the solder ball 12 is formed on the top surface 6a formed on the concave spherical surface. And the other points are common.
As described above, according to the present embodiment 2 ′, since the top surface 6a of each bump 6 is formed as a concave spherical surface, the connection area between the top surface 6a and the solder ball 12 increases, the connection strength is increased, and the wiring is increased. The reliability as a circuit board can be increased, and the life can be extended.

このように、各バンプ6の頂面6aを凹球面に形成することは、図1に示した実施例1の配線回路基板を製造する方法における、図3(F)に示す工程と、図3(G)に示す工程との間に、銅をクイックエッチングする工程を設けることにより、容易に為し得る。
図6(A)〜(C)はその凹球面形成工程とその前後の工程を工程順に示す断面図である。
(A)金属層20c〔図3(E)参照〕を選択的にエッチングすることにより配線層10を形成する。尚、該配線層10の形成前又は形成後に2点鎖線で示すように、例えば半田レジストからなるダム18を形成して半田接合面の均一化とダレによるショート防止を図るようにしても良い。図6(A)はその配線層10を形成した後の状態を示す。
Forming the top surface 6a of each bump 6 as a concave spherical surface in this manner can be achieved by the steps shown in FIG. 3F in the method of manufacturing the printed circuit board according to the first embodiment shown in FIG. This can be easily achieved by providing a step of quick etching of copper between the step shown in FIG.
6 (A) to 6 (C) are cross-sectional views showing the concave spherical surface forming step and the steps before and after it in the order of steps.
(A) The wiring layer 10 is formed by selectively etching the metal layer 20c (see FIG. 3E). As shown by a two-dot chain line before or after the formation of the wiring layer 10, a dam 18 made of, for example, a solder resist may be formed to make the solder joint surface uniform and prevent short circuit due to sagging. FIG. 6A shows a state after the wiring layer 10 is formed.

(B)次に、図6(B)に示すように、上記各バンプ6の頂面6aをウェットエッチングすることにより凹球面状にする。
(C.)次に、半田ボールとなる球状半田を各バンプ6の上記層間絶縁膜4から露出する頂面6a上に配置し、配線回路基板2を加熱炉に通してリフロー処理することにより各バンプ6頂面6a上に該バンプ6と直接に接続固定された半田ボール12を形成する。図6(C)はそのリフロー処理後の状態を示す。
このように、図6(B)に示すウェットエッチング工程を付加することにより図5に示す第2の実施例2’の配線回路基板2が得られる。尚、この実施例2の各バンプ6の頂面6aを凹球面状にすることは、図4(A)、(B)に示す各搭載例にも適用することができるし、また、バンプ6に直接に半田ボール12を形成する態様のすべてに適用し得る。
尚、ここでは回路パターン10とバンプ頂面のエツチングを別々の工程で行うように記載したが、両面同時のウェットエッチングでもよく、その方が効率がよい。
(B) Next, as shown in FIG. 6B, the top surface 6a of each bump 6 is formed into a concave spherical shape by wet etching.
(C.) Next, a spherical solder to be a solder ball is placed on the top surface 6a of each bump 6 exposed from the interlayer insulating film 4, and the printed circuit board 2 is passed through a heating furnace to perform a reflow process. On the top surface 6a of the bump 6, a solder ball 12 directly connected and fixed to the bump 6 is formed. FIG. 6C shows a state after the reflow processing.
In this way, by adding the wet etching step shown in FIG. 6B, the printed circuit board 2 of the second embodiment 2 'shown in FIG. 5 is obtained. The concave surface of the top surface 6a of each bump 6 according to the second embodiment can be applied to each mounting example shown in FIGS. 4A and 4B. The present invention can be applied to all the embodiments in which the solder ball 12 is formed directly on the substrate.
Here, the etching of the circuit pattern 10 and the top surface of the bump are described as being performed in separate steps, but wet etching may be performed on both surfaces simultaneously, which is more efficient.

図7(A)〜(E)は図2(A)〜(D)及び図3(E)〜(H)に示した配線回路基板の製造方法の一部を変形させた実施例3の要部を工程順に示す断面図である。
(A)図2(A)〜(C)で示した工程と同じ工程を行う。図7(A)はその工程を終えた状態、換言すれば、図2(C)に示した状態を示す。
ここで、図2(C)に示した状態になるまでを簡単に説明する。中間層としてエッチングバリア層を有する含む三層構造の金属板20を用意し、該金属板20の厚い金属層20aを選択的にエッチングすることにより、バンプ6を形成し、その後、上記エッチングバリア層20b(8)を、上記バンプ6をマスクとしてエッチングすることにより選択的に除去する。その状態が図7(A)に示される。
FIGS. 7A to 7E show essential parts of the third embodiment in which a part of the method of manufacturing the printed circuit board shown in FIGS. 2A to 3D and FIGS. 3E to 3H is modified. It is sectional drawing which shows a part in process order.
(A) The same steps as those shown in FIGS. 2A to 2C are performed. FIG. 7A shows a state in which the process is completed, in other words, a state shown in FIG. 2C.
Here, up to the state shown in FIG. 2C will be briefly described. A metal plate 20 having a three-layer structure including an etching barrier layer as an intermediate layer is prepared, and a bump 6 is formed by selectively etching a thick metal layer 20a of the metal plate 20. 20b (8) is selectively removed by etching using the bump 6 as a mask. The state is shown in FIG.

(B)次に、上記各バンプ6を一斉に加圧して押し潰すことにより図7(B)に示すように、該各バンプ6の頂面の径を大きくする。このように押し潰して各バンプ6の頂面の径を大きくするのは、後でその頂面に形成する半田ボールのバンプとの強度を強くし、バンプを取れにくくするためである。
即ち、配線回路基板の配線膜の狭ピッチ化、IC、LSI等の電極数の増加等の傾向から、バンプの配置密度を高めることが要求され、その結果、バンプの大きさを大きくすることが制約されている。従って、バンプとしてその頂面の径が70μm程度のものを形成しなければならないケースが生じている。
(B) Next, the diameter of the top surface of each bump 6 is increased as shown in FIG. 7B by simultaneously pressing and crushing each of the bumps 6. The reason why the diameter of the top surface of each bump 6 is increased by crushing in this way is to increase the strength of the solder ball formed on the top surface later with the bump, making it difficult to remove the bump.
That is, the tendency of narrowing the pitch of the wiring film of the wiring circuit board and increasing the number of electrodes of ICs, LSIs, and the like require increasing the arrangement density of the bumps. As a result, it is necessary to increase the size of the bumps. Restricted. Accordingly, there is a case where bumps having a top surface diameter of about 70 μm must be formed.

しかし、実際上、バンプの頂面の径は、少なくとも100μm程度ないと半田ボールのバンプへの接着強度を充分な程度に高めることが難しく、半田ボールのバンプへの接着の信頼度を充分な高さに確保することが容易ではなかった。
そこで、半田ボールのバンプへの接着強度を高めるためにバンプの頂面の面積を増やすべく、各バンプ6を一斉に加圧して押し潰すのである。このようにすると、実際に各バンプ6の頂面の径を、例えば70μm程度から例えば100μm以上に大きくすることができる。
However, in practice, unless the diameter of the top surface of the bump is at least about 100 μm, it is difficult to sufficiently increase the bonding strength of the solder ball to the bump, and the reliability of the bonding of the solder ball to the bump is sufficiently high. It was not easy to secure.
Therefore, in order to increase the area of the top surface of the bump in order to increase the bonding strength of the solder ball to the bump, the bumps 6 are simultaneously pressed and crushed. In this case, the diameter of the top surface of each bump 6 can be actually increased from, for example, about 70 μm to, for example, 100 μm or more.

(C)次に、図7(C)に示すように、各バンプ6を覆う層間絶縁膜4を形成する〔図2(D)に示す工程と同じ〕。は該層間絶縁膜4形成後の状態を示す。
(D)次に、図7(D)に示すように、上記層間絶縁膜4の表面部を、上記各バンプ6の頂面が完全に露出するまで研磨し、絶縁樹脂層とバンプ頂面を面一(ツライチ)にする[図3(E)に示す工程と同じ。]。
(C) Next, as shown in FIG. 7C, an interlayer insulating film 4 covering each bump 6 is formed [same as the step shown in FIG. 2D]. Shows a state after the interlayer insulating film 4 is formed.
(D) Next, as shown in FIG. 7D, the surface of the interlayer insulating film 4 is polished until the top surfaces of the bumps 6 are completely exposed. Make it flush (same as the step shown in FIG. 3E). ].

(E)その後、上記金属層20cを選択的にエッチングすることにより配線層10を形成し[図3(F)に示す工程と同じ。]、しかる後、半田ボール12を形成する[図3(G)に示す工程と同じ。〕。尚、該配線層10の形成前又は形成後に2点鎖線で示すように、例えば半田レジストからなるダム18を形成して半田接合面の均一化とダレによるショート防止を図るようにしても良いこと、図2及び図3に示す配線回路基板の製造方法と同じである。 (E) Then, the wiring layer 10 is formed by selectively etching the metal layer 20c [same as the step shown in FIG. After that, the solder ball 12 is formed [same as the step shown in FIG. 3 (G)]. ]. Before or after the formation of the wiring layer 10, as shown by a two-dot chain line, a dam 18 made of, for example, a solder resist may be formed to make the solder joint surface uniform and to prevent short-circuit due to sagging. 2 and 3 is the same as the method of manufacturing the printed circuit board shown in FIGS.

このような図7に示す配線回路基板の製造方法によれば、前記層間絶縁膜の形成前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくする工程を有するので、各バンプ6の頂面の径を、例えば70μm程度から100μm以上に大きくすることができる。
従って、各半田ボール12の各バンプ6への接着強度を充分に強めることが容易に為し得る。
According to the method for manufacturing the printed circuit board shown in FIG. 7, since the bumps are pressed and crushed from above before the formation of the interlayer insulating film, the diameter of the top surface is increased. The diameter of the top surface of each bump 6 can be increased, for example, from about 70 μm to 100 μm or more.
Therefore, it is easy to sufficiently increase the bonding strength of each solder ball 12 to each bump 6.

尚、各バンプ6を一斉に加圧するのは本実施例においては、エッチングバリア層8のバンプ6をマスクとしての選択的エッチング後であったが、選択的エッチング前に加圧を行うようにしても良い。
また、図7(D)に示す工程の終了後、図7(E)に示す工程の終了前に、各バンプ6の頂面6aをウェットエッチングにより凹球面状にする工程を設けても良い(実施例2参照)。これにより、バンプ6と半田ボール12との接続面積をより広め、接続強度をより強めてより信頼度の向上、長寿命化を図ることができるからである。
In the present embodiment, the bumps 6 are simultaneously pressed after the selective etching using the bumps 6 of the etching barrier layer 8 as a mask in the present embodiment. However, the pressing is performed before the selective etching. Is also good.
After the step shown in FIG. 7D, before the step shown in FIG. 7E, a step of making the top surface 6a of each bump 6 concave-spherical by wet etching may be provided ( See Example 2). Thereby, the connection area between the bump 6 and the solder ball 12 can be further increased, the connection strength can be further increased, the reliability can be further improved, and the life can be extended.

図8は本発明配線回路基板の第4の実施例2aを示す断面図である。本実施例2aは、本発明を、両面に配線層を有する配線回路基板に適用したものである。
即ち、図1に示した第1の実施例2等は、層間絶縁膜4の半田ボール12が形成されたのと反対側にのみ配線層10があり、半田ボール12が形成された側には配線層がなかったが、本実施例2aには、層間絶縁膜4の半田ボール12が形成された側にも配線層11がある。
そして、半田ボール12は、バンプ6の頂面に直接形成するようにしても良いし、バンプ6頂面と接する配線層11(図8において2点鎖線で示す配線層11)を形成し、その配線層11上に半田ボール12を形成するようにしても良い。
FIG. 8 is a sectional view showing a fourth embodiment 2a of the wired circuit board of the present invention. In Example 2a, the present invention is applied to a printed circuit board having a wiring layer on both sides.
That is, in the first embodiment 2 and the like shown in FIG. 1, the wiring layer 10 is provided only on the side of the interlayer insulating film 4 opposite to the side on which the solder balls 12 are formed, and on the side on which the solder balls 12 are formed. Although there was no wiring layer, in Example 2a, the wiring layer 11 was also provided on the side of the interlayer insulating film 4 where the solder balls 12 were formed.
The solder ball 12 may be formed directly on the top surface of the bump 6, or the wiring layer 11 (the wiring layer 11 shown by a two-dot chain line in FIG. 8) in contact with the top surface of the bump 6 may be formed. The solder balls 12 may be formed on the wiring layer 11.

図9(A)〜(D)は図8に示す配線回路基板(本発明配線回路基板の第2の実施例)2aの製造方法を工程順に示す断面図であり、この図9を参照して配線回路基板2aの製造方法を説明する。
(A)図2、図3に示した配線回路基板2の製造方法における工程(E)が終了した状態のもの(但し、ダム18は形成しない)と、半田ボール12側の配線層11となる、銅からなる金属層19を用意し、図9(A)に示すように、該金属層19を配線回路基板2の層間絶縁膜4表面に臨ませる。
(B)次に、図9(B)に示すように、上記金属層19を配線回路基板に積層する。2aは積層後の配線回路基板を指す。
9A to 9D are cross-sectional views showing a method of manufacturing the wired circuit board 2a (second embodiment of the wired circuit board of the present invention) 2a shown in FIG. 8 in the order of steps. A method for manufacturing the printed circuit board 2a will be described.
(A) A state in which the step (E) in the method of manufacturing the wired circuit board 2 shown in FIGS. 2 and 3 is completed (however, the dam 18 is not formed) and the wiring layer 11 on the solder ball 12 side. A metal layer 19 made of copper is prepared, and the metal layer 19 is exposed to the surface of the interlayer insulating film 4 of the printed circuit board 2 as shown in FIG.
(B) Next, as shown in FIG. 9B, the metal layer 19 is laminated on the printed circuit board. 2a indicates a printed circuit board after lamination.

(C)次に、上記金属層19及び20cを同時又は所定の順で選択的にエッチングすることにより配線層10及び11を形成する。図9(C)は該配線層10、11形成後の状態を示す。
(D)次に、図9(D)に示すように、バンプ6と接続された配線層11上に半田ボール12を形成する。
尚、半田ボール12は、図9(D)に示すようにバンプ6と接続された配線層11上に形成するようにしても良いが、バンプ6上には配線膜11を形成しないように金属層19に対するパターニングを行うこととしてバンプ6頂面を露出させたままにし、その露出したバンプ6に頂面に直接半田ボール12を形成するようにしても良い。
(C) Next, the wiring layers 10 and 11 are formed by selectively etching the metal layers 19 and 20c simultaneously or in a predetermined order. FIG. 9C shows a state after the wiring layers 10 and 11 are formed.
(D) Next, as shown in FIG. 9D, a solder ball 12 is formed on the wiring layer 11 connected to the bump 6.
The solder ball 12 may be formed on the wiring layer 11 connected to the bump 6 as shown in FIG. 9 (D). By patterning the layer 19, the top surface of the bump 6 may be left exposed, and the solder ball 12 may be formed directly on the top surface of the exposed bump 6.

図10はそのように製造して得た配線回路基板、即ち、本発明配線回路基板の第5の実施例2bを示すものである。
図11(A)〜(C)は本発明配線回路基板2、2a或いは2bにバンプが形成されていない領域、即ちバンプ非形成領域40を設けてフレキシブルにし、そのフレキシブルにした部分にて曲折した回路モジュールの各別の例を示す断面図である。
このように配線回路基板にバンプ非形成領域40を設けて曲折可能にし、任意に曲折して使用できるようにした回路モジュールを形成することにより、LSI等の半導体チップ24を立体的に配置して使用することができ、限られた領域内の多数のチップ24を高密度配置することができる。尚、42はバンプ形成領域である。
尚、本実施例においても、バンプ6の頂面6aをウェットエッチングにより凹球面状に形成するという実施例を適用できる。
FIG. 10 shows a printed circuit board obtained in such a manner, that is, a fifth embodiment 2b of the printed circuit board of the present invention.
FIGS. 11 (A) to 11 (C) show a region where no bump is formed on the wired circuit board 2, 2a or 2b of the present invention, that is, a region where no bump is formed, which is made flexible, and the flexible portion is bent. It is sectional drawing which shows each another example of a circuit module.
In this way, by forming the non-bump forming area 40 on the printed circuit board to enable bending and forming a circuit module which can be used by bending arbitrarily, the semiconductor chip 24 such as an LSI can be three-dimensionally arranged. It can be used, and a large number of chips 24 in a limited area can be densely arranged. Incidentally, reference numeral 42 denotes a bump formation area.
In this embodiment, an embodiment in which the top surface 6a of the bump 6 is formed in a concave spherical shape by wet etching can be applied.

図12は本発明配線回路基板に別のフレキシブルな配線回路基板を接続することによって構成された本発明回路モジュールの別の実施例を示す断面図である。
図12において、2の符号が付された配線回路基板は、図1に示した配線回路基板2と同じであり、既に説明済みなので、特に説明はしない。
50は該配線回路基板2とは別のフレキシブルな配線回路基板であり、52はそのベースを成す層間絶縁膜、54は該層間絶縁膜52の裏面に形成された例えば銅からなる配線膜、56は該層間絶縁膜52を貫通するように形成されたバンプ、58はバンプ56の底面と上記配線膜54との間に介在するエッチングバリア層、60は上記層間絶縁膜52の表面に形成された配線膜で、少なくとも一部の配線膜60は上記バンプ56の頂面に接続された状態で形成されている。
FIG. 12 is a sectional view showing another embodiment of the circuit module of the present invention constituted by connecting another flexible printed circuit board to the printed circuit board of the present invention.
In FIG. 12, the printed circuit board denoted by reference numeral 2 is the same as printed circuit board 2 shown in FIG.
50 is a flexible printed circuit board different from the printed circuit board 2, 52 is an interlayer insulating film forming its base, 54 is a wiring film made of, for example, copper formed on the back surface of the interlayer insulating film 52, 56 Is a bump formed so as to penetrate the interlayer insulating film 52, 58 is an etching barrier layer interposed between the bottom surface of the bump 56 and the wiring film 54, and 60 is formed on the surface of the interlayer insulating film 52. In the wiring film, at least a part of the wiring film 60 is formed so as to be connected to the top surface of the bump 56.

該配線回路基板50は、配線回路基板2と略同じ方法で形成される。該配線回路基板50の配線回路基板2との違いは、配線回路基板2においては層間絶縁膜の一方の面に配線膜が形成されていないが、配線回路基板50においては両方の面に配線膜54、60が形成されていることのみである。
この配線回路基板2と配線回路基板50とは、配線回路基板2のバンプ6の頂面に配線回路基板50の配線膜54を、半田ボール12を介して接続することによって一体化されて、回路モジュールを構成している。これにより、フレキシブルな配線回路基板同士を接続した回路モジュールを容易に構成し得る。
The printed circuit board 50 is formed in substantially the same manner as the printed circuit board 2. The difference between the printed circuit board 50 and the printed circuit board 2 is that the printed circuit board 2 does not have a printed film formed on one surface of the interlayer insulating film, but the printed circuit board 50 has printed wiring films on both surfaces. It is only that 54 and 60 are formed.
The printed circuit board 2 and the printed circuit board 50 are integrated by connecting the wiring film 54 of the printed circuit board 50 to the top surface of the bumps 6 of the printed circuit board 2 via the solder balls 12 to form a circuit. Make up the module. Thus, a circuit module in which flexible printed circuit boards are connected to each other can be easily configured.

図13はガラス配線基板(リジット)に上記本発明配線回路基板の第1の実施例を接続して構成した液晶装置を成す回路モジュールを示す断面図である。
70は液晶装置(回路モジュール)で、ガラス配線基板72上に平行にシール材78を介して対向ガラス板76を配設し、該ガラス配線基板72と対向ガラス板76との間に液晶80を封入したものに、本発明配線回路基板の第1の実施例2を半田ボール12を介して接続してなるものである。74は上記ガラス配線基板72の表面に形成された透明配線膜で、ITO(インジウムテンオキサイド)膜からなる。或いは、ITO膜の表面に更に金属(例えば銅、アルミニウム、チタン、ニッケル、錫或いは銀)膜を形成してなる場合もある。
FIG. 13 is a sectional view showing a circuit module constituting a liquid crystal device constituted by connecting the first embodiment of the printed circuit board of the present invention to a glass wiring board (rigid).
Numeral 70 denotes a liquid crystal device (circuit module) in which an opposing glass plate 76 is disposed in parallel on a glass wiring substrate 72 via a sealing material 78, and a liquid crystal 80 is interposed between the glass wiring substrate 72 and the opposing glass plate 76. The sealed circuit board is obtained by connecting the first embodiment 2 of the printed circuit board of the present invention via a solder ball 12. Reference numeral 74 denotes a transparent wiring film formed on the surface of the glass wiring substrate 72, which is made of an ITO (indium oxide) film. Alternatively, a metal (for example, copper, aluminum, titanium, nickel, tin or silver) film may be further formed on the surface of the ITO film.

ガラス配線基板と配線回路基板2との接続は、具体的には、上記ガラス配線基板72の透明配線膜74の端部と本発明配線回路基板の第1の実施例2のバンプ6との間を半田ボール12を介して接続される。
このように、フレキシブルな配線回路基板2を電極引き出しに用いた液晶装置を提供することができる。このような回路モジュールにも、図5に示すようにバンプの頂面を例えばウェットエッチングにより凹球面状に形成し、その凹球面状に形成した頂面に直接に半田ボールを形成するという実施例を適用できる。
以上に述べた回路モジュールは、本発明配線回路基板2を用いた回路モジュールの一部であり、これらに本発明に係る回路モジュールが限定されてしまうものではない。
Specifically, the connection between the glass wiring board and the wiring circuit board 2 is made between the end of the transparent wiring film 74 of the glass wiring board 72 and the bump 6 of the first embodiment 2 of the wiring circuit board of the present invention. Are connected via a solder ball 12.
As described above, it is possible to provide a liquid crystal device using the flexible printed circuit board 2 for extracting electrodes. Also in such a circuit module, as shown in FIG. 5, an embodiment in which the top surface of a bump is formed into a concave spherical shape by, for example, wet etching, and a solder ball is formed directly on the concave spherical top surface. Can be applied.
The circuit module described above is a part of the circuit module using the wired circuit board 2 of the present invention, and the circuit module according to the present invention is not limited thereto.

本発明は、例えばIC、LSI等の電子デバイス実装用の配線回路基板、特に高密度実装を実現できる配線回路基板と、その製造方法と、その配線回路基板を備えた回路モジュールに適用することができ、回路モジュールの具体例としては液晶装置が挙げられるが、必ずしもそれに限定されず、種々のものに利用可能性がある。   INDUSTRIAL APPLICABILITY The present invention can be applied to a printed circuit board for mounting an electronic device such as an IC or an LSI, particularly to a printed circuit board capable of realizing high-density mounting, a method of manufacturing the same, and a circuit module including the printed circuit board. A specific example of the circuit module includes a liquid crystal device, but is not necessarily limited thereto, and may be used for various types.

本発明配線回路基板の第1の実施例を示す断面図である。FIG. 2 is a sectional view showing a first embodiment of the printed circuit board of the present invention. (A)〜(D)は上記第1の実施例の製造方法の工程(A)〜(D)を順にs示す断面図である。4A to 4D are cross-sectional views sequentially showing steps (A) to (D) of the manufacturing method of the first embodiment. (E)〜(H)は上記第1の実施例の製造方法の工程(E)〜(H)を順に示す断面図である。(E)-(H) are sectional views sequentially showing steps (E)-(H) of the manufacturing method of the first embodiment. (A)、(B)は配線回路基板への半導体チップの各別の搭載例を示す断面図である。(A), (B) is sectional drawing which shows each mounting example of the semiconductor chip to a printed circuit board. 本発明配線回路基板の第2の実施例を示す断面図である。FIG. 4 is a sectional view showing a second embodiment of the printed circuit board of the present invention. (A)〜(C)は図5に示した上記第2の実施例の製造方法におけるその凹球面形成工程とその前後の工程を工程順に示す断面図である。FIGS. 6A to 6C are cross-sectional views showing a concave spherical surface forming step and steps before and after that in the manufacturing method of the second embodiment shown in FIG. (A)〜(E)は図2(A)〜(D)及び図3(E)〜(H)に示した配線回路基板の製造方法の一部を変形させた第3の実施例の要部を工程順に示す断面図である。(A) to (E) are essential parts of the third embodiment in which a part of the method for manufacturing the printed circuit board shown in FIGS. 2A to 2D and 3E to 3H is modified. It is sectional drawing which shows a part in process order. 本発明配線回路基板の第4の実施例を示す断面図である。FIG. 9 is a sectional view showing a fourth embodiment of the wired circuit board of the present invention. (A)〜(D)は本発明配線回路基板の上記第4の実施例の製造方法を工程順に示す断面図である。7A to 7D are cross-sectional views showing a method of manufacturing the wired circuit board according to the fourth embodiment of the present invention in the order of steps. 本発明配線回路基板の第5の実施例を示すものである。9 shows a fifth embodiment of the printed circuit board of the present invention. (A)〜(C)は本発明配線回路基板にバンプ非形成領域を設けてフレキシブルにし、そのフレキシブルにした部分にて曲折して使用した各別の使用例を示す断面図である。(A)-(C) is a sectional view showing another example of use in which a non-bump forming area is provided on the printed circuit board of the present invention to make it flexible, and the flexible portion is bent and used. 本発明配線回路基板に別のフレキシブルな配線回路基板を接続することによって構成された本発明回路モジュールの第6の実施例を示す断面図である。It is a sectional view showing a sixth embodiment of the circuit module of the present invention constituted by connecting another flexible printed circuit board to the printed circuit board of the present invention. ガラス配線基板(リジット)に上記本発明配線回路基板を接続して構成した液晶装置を成す回路モジュールを示す断面図である。It is sectional drawing which shows the circuit module which comprises the liquid crystal device comprised by connecting the said wiring circuit board of this invention to a glass wiring board (rigid). 従来例の配線回路基板を示す断面図である。It is sectional drawing which shows the wiring circuit board of a prior art example.

符号の説明Explanation of reference numerals

2、2a、2b・・・配線回路基板、4・・・層間絶縁膜、6・・・バンプ、
6a・・・バンプの頂面、8・・・エッチングバリア層、10、11・・・配線層、
12・・・半田ボール、14・・・プリント回路基板、
16・・・プリント回路基板の配線層、20・・・三層金属板、24・・・半導体チップ、
40・・・バンプ非形成領域(曲折可能な領域)、42・・・バンプ形成領域、
50・・・フレキシブルな配線回路基板、70・・・液晶装置、72・・・透明基板、
74・・・透明配線膜。
2, 2a, 2b: printed circuit board, 4: interlayer insulating film, 6: bump,
6a: top surface of bump, 8: etching barrier layer, 10, 11, wiring layer,
12: solder ball, 14: printed circuit board,
16 ... wiring layer of printed circuit board, 20 ... three-layer metal plate, 24 ... semiconductor chip,
40 ... Bump non-formation area (bendable area) 42 ... Bump formation area
50: flexible printed circuit board, 70: liquid crystal device, 72: transparent substrate,
74 ... Transparent wiring film.

Claims (13)

配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、
上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、
上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成した
ことを特徴とする配線回路基板。
Forming a plurality of bumps directly on the surface of the wiring layer or via an etching barrier layer,
Forming an interlayer insulating film on a portion of the wiring layer where the bumps are not formed on the bump forming surface;
A printed circuit board, wherein a solder ball is formed directly on a top surface of the bump or via a wiring layer formed on the surface of the interlayer insulating film so as to be connected to the bump.
前記配線層及び前記バンプが銅からなる
ことを特徴とする請求項1記載の配線回路基板。
The printed circuit board according to claim 1, wherein the wiring layer and the bump are made of copper.
前記層間絶縁膜に、バンプが多数形成されたバンプ形成領域と、バンプが形成されないフレキシブルなバンプ非形成領域とを有し、
上記バンプ非形成領域が曲折可能である、又は、その少なくとも一部を曲折してなる
ことを特徴とする請求項1又は2記載の配線回路基板。
In the interlayer insulating film, having a bump forming region in which a large number of bumps are formed, and a flexible bump non-forming region in which no bump is formed,
The printed circuit board according to claim 1, wherein the non-bump-forming region is bendable, or at least a part thereof is bent.
前記各バンプの頂面が凹球面に形成され、
上記各バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなる
ことを特徴とする請求項1、2又は3記載の配線回路基板。
The top surface of each bump is formed as a concave spherical surface,
4. The printed circuit board according to claim 1, wherein a solder ball is formed directly on the top surface formed on the concave spherical surface of each of the bumps.
配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、
リジットな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成されたリジットな配線回路基板と、
からなり、
上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記リジットな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなる
ことを特徴とする回路モジュール。
A plurality of bumps are formed directly on the surface of the wiring layer or via an etching barrier layer, an interlayer insulating film is formed on a portion of the wiring layer where the bumps are not formed on the bump forming surface, and a top of the bump is formed. On the surface, directly or via a wiring layer formed to connect to the bump on the surface of the interlayer insulating film, a flexible wiring circuit board on which solder balls are formed,
A rigid wiring circuit board on which a wiring film connected to the wiring film is formed on at least one surface of a rigid insulating substrate,
Consisting of
A circuit module, wherein at least a part of the wiring film of the flexible wiring circuit board and at least a part of the wiring film of the rigid wiring circuit board are connected via the solder balls.
配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成し、上記バンプの頂面に、直接に、又は上記層間絶縁膜表面に該バンプと接続するように形成された配線層を介して、半田ボールを形成したフレキシブルな配線回路基板と、
フレキシブルな絶縁基板の少なくとも一方の表面に上記配線膜と接続される配線膜が形成された上記配線回路基板とは別のフレキシブルな配線回路基板と、
からなり、
上記フレキシブルな配線回路基板の配線膜の少なくとも一部と、上記別のフレキシブルな配線回路基板の配線膜の少なくとも一部とが、上記半田ボールを介して接続されてなる
ことを特徴とする回路モジュール。
A plurality of bumps are formed directly on the surface of the wiring layer or via an etching barrier layer, an interlayer insulating film is formed on a portion of the wiring layer where the bumps are not formed on the bump forming surface, and a top of the bump is formed. On the surface, directly or via a wiring layer formed to connect to the bump on the surface of the interlayer insulating film, a flexible wiring circuit board on which solder balls are formed,
A flexible wiring circuit board different from the wiring circuit board in which a wiring film connected to the wiring film is formed on at least one surface of a flexible insulating substrate,
Consisting of
A circuit module, wherein at least a part of the wiring film of the flexible printed circuit board and at least a part of the wiring film of the another flexible printed circuit board are connected via the solder balls. .
前記各バンプの頂面が凹球面に形成され、
上記各バンプの凹球面に形成された上記頂面に直接に半田ボールが形成されてなる
ことを特徴とする請求項5又は6記載の回路モデュール。
The top surface of each bump is formed as a concave spherical surface,
The circuit module according to claim 5, wherein a solder ball is formed directly on the top surface formed on the concave spherical surface of each of the bumps.
金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、
上記基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、
上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、
上記基板の上記各バンプの露出する頂面上に半田ボールを形成する
ことを特徴とする配線回路基板の製造方法。
Prepare a substrate with bumps formed directly on the surface of the metal layer or via an etching barrier layer,
Forming an interlayer insulating film thicker than the bumps on the portions of the metal layer of the substrate on the bump formation side where the bumps are not formed,
Polishing the interlayer insulating film of the substrate until the top surface of each of the bumps is exposed,
A method of manufacturing a printed circuit board, comprising: forming a solder ball on a top surface of each of the above-described bumps where the bumps are exposed.
金属層の表面に直接に又はエッチングバリア層を介してバンプを形成した基板を用意し、
上記基板の金属層のバンプ形成側の面のバンプが形成されていない部分にバンプより厚く層間絶縁膜を形成し、
上記基板の層間絶縁膜を上記各バンプの頂面が露出するまで研磨し、
上記基板の上記層間絶縁膜の表面に金属層を形成し、
上記層間絶縁膜表面の金属層を選択的にエッチングすることにより配線層を形成し、
各バンプの露出する頂面上に又は該バンプと接続された上記配線層上に半田ボールを形成する
ことを特徴とする配線回路基板の製造方法。
Prepare a substrate with bumps formed directly on the surface of the metal layer or via an etching barrier layer,
Forming an interlayer insulating film thicker than the bumps on the portions of the metal layer of the substrate on the bump formation side where the bumps are not formed,
Polishing the interlayer insulating film of the substrate until the top surface of each of the bumps is exposed,
Forming a metal layer on the surface of the interlayer insulating film of the substrate,
Forming a wiring layer by selectively etching the metal layer on the surface of the interlayer insulating film;
A method for manufacturing a printed circuit board, comprising: forming a solder ball on an exposed top surface of each bump or on the wiring layer connected to the bump.
前記層間絶縁膜を形成するよりも前に、各バンプを上から加圧して押し潰すことによりその頂面の径を大きくする工程を有する
ことを特徴とする請求項8又は9記載の配線回路基板の製造方法。
10. The printed circuit board according to claim 8, further comprising a step of increasing the diameter of the top surface by pressing and crushing each bump from above before forming the interlayer insulating film. Manufacturing method.
前記基板の前記層間絶縁膜を前記各バンプの頂面が露出するまで研磨した後、該バンプの露出した頂面上に前記半田ボールを形成する前に、該バンプの頂面をエッチングすることにより凹球面にする工程を有する
ことを特徴とする請求項8、9又は10記載の配線回路基板の製造方法。
After polishing the interlayer insulating film of the substrate until the top surface of each of the bumps is exposed, etching the top surface of the bump before forming the solder ball on the exposed top surface of the bump. The method for producing a printed circuit board according to claim 8, further comprising a step of forming a concave spherical surface.
配線層の表面部に直接に又はエッチングバリア層を介して複数のバンプを形成し、上記配線層のバンプ形成面の上記バンプの形成されていない部分に層間絶縁膜を形成した一つの配線回路基板と、
液晶素子の基板を成し、透明配線膜を有する液晶装置用透明基板と、
からなり、
上記一つの配線回路基板の各バンプと、上記別の液晶装置用透明基板の透明配線膜の上記各バンプと対応する部分とが、直接に或いは上記バンプの頂面に形成した配線膜及び半田ボールを介して接続されて液晶装置を成す
ことを特徴とする回路モジュール。
One wiring circuit board in which a plurality of bumps are formed directly on the surface of the wiring layer or via an etching barrier layer, and an interlayer insulating film is formed on a portion of the wiring layer where the bumps are not formed on the bump forming surface. When,
Forming a substrate of the liquid crystal element, a transparent substrate for a liquid crystal device having a transparent wiring film,
Consisting of
A wiring film and a solder ball formed directly or on the top surface of the bump by each bump of the one wiring circuit board and a portion of the transparent wiring film of the another liquid crystal device corresponding to the bump. A liquid crystal device which is connected via a liquid crystal device.
前記一つの配線回路基板の各バンプの頂面が凹球面に形成され、
その凹球面に形成された上記頂面に直接に半田ボールが形成されてなる
ことを特徴とする請求項12記載の回路モジュール
The top surface of each bump of the one printed circuit board is formed as a concave spherical surface,
13. The circuit module according to claim 12, wherein a solder ball is formed directly on the top surface formed on the concave spherical surface.
JP2003307897A 2003-03-31 2003-08-29 Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board Pending JP2004343030A (en)

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TW093107787A TW200507218A (en) 2003-03-31 2004-03-23 Layout circuit substrate, manufacturing method of layout circuit substrate, and circuit module
US10/812,349 US20040201096A1 (en) 2003-03-31 2004-03-30 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
KR1020040021668A KR20040086783A (en) 2003-03-31 2004-03-30 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
CN200810169136XA CN101408688B (en) 2003-03-31 2004-03-31 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
CNB2004100318947A CN100542375C (en) 2003-03-31 2004-03-31 The manufacture method of wired circuit board, wired circuit board and circuit module
HK05106338.3A HK1073965A1 (en) 2003-03-31 2005-07-25 Wiring circuit board, manufacturing method for the wiring circuit board, and circuit module
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