JP2009231657A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2009231657A
JP2009231657A JP2008077061A JP2008077061A JP2009231657A JP 2009231657 A JP2009231657 A JP 2009231657A JP 2008077061 A JP2008077061 A JP 2008077061A JP 2008077061 A JP2008077061 A JP 2008077061A JP 2009231657 A JP2009231657 A JP 2009231657A
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connection pad
semiconductor device
protrusion
gold
wiring board
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JP5106197B2 (en
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Keizo Sakurai
敬三 櫻井
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Kyocera SLC Technologies Corp
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Kyocera SLC Technologies Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which a connection pad of a wiring board and an electrode terminal of a semiconductor device are connected real good through a gold bump, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device in which a connection pad 7 on a wiring board 10 and a gold bump 22 arranged at an electrode terminal 21 of a semiconductor device 20 are connected is characterized in that the gold bump 22 includes a base 22a having a same diameter size connected to the electrode terminal 21 and a projection 22b having a smaller diameter size which is erected on the base 22a and connected to the connection pad 7, and the width of a portion connected to the projection 22b of the connection pad 7 is narrower than the diameter of the projection 22b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は半導体装置およびその製造方法に関し、より詳細には、配線基板上の接続パッドと半導体素子の電極端子に設けた金バンプとが接合されて成る半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which connection pads on a wiring board and gold bumps provided on electrode terminals of a semiconductor element are bonded and a manufacturing method thereof.

従来から、半導体装置として、フリップチップ型の半導体装置がある。フリップチップ型の半導体装置とは、配線基板上に設けた接続パッドと半導体素子の電極端子とを対向させ、これらを例えば半導体素子の電極端子に予め設けておいた金バンプを介して電気的に接続した半導体装置である。   Conventionally, there is a flip chip type semiconductor device as a semiconductor device. In the flip chip type semiconductor device, a connection pad provided on a wiring board is opposed to an electrode terminal of a semiconductor element, and these are electrically connected through, for example, gold bumps provided in advance on the electrode terminal of the semiconductor element. It is a connected semiconductor device.

図８は、従来のフリップチップ型の半導体装置の例を示す概略断面図であり、１１０は配線基板、１２０は半導体素子である。また図９は、配線基板１１０の上面図である。配線基板１１０は例えばガラスクロスに熱硬化性樹脂を含浸させて成る絶縁板１０１ａの両面に銅から成る配線導体１０２および熱硬化性樹脂から成る複数の絶縁層１０１ｂが積層されて成り、さらに最表層の絶縁層１０１ｂおよび配線導体１０２の上には配線導体１０２の一部を露出させるようにして熱硬化性樹脂から成るソルダーレジスト層１０３が被着されており、このソルダーレジスト層１０３から露出する配線導体１０２の一部が半導体素子１２０との電気的な接続を行なうための接続パッド１０７を形成している。接続パッド１０７は図９に示すように半導体素子１２０の外周部に対応する位置に並んだ長方形である。   FIG. 8 is a schematic cross-sectional view showing an example of a conventional flip-chip type semiconductor device, in which 110 is a wiring board and 120 is a semiconductor element. FIG. 9 is a top view of the wiring board 110. The wiring board 110 is formed by laminating a wiring conductor 102 made of copper and a plurality of insulating layers 101b made of thermosetting resin on both surfaces of an insulating plate 101a made by impregnating a glass cloth with a thermosetting resin, for example. A solder resist layer 103 made of a thermosetting resin is deposited on the insulating layer 101b and the wiring conductor 102 so as to expose a part of the wiring conductor 102, and the wiring exposed from the solder resist layer 103 is covered. A part of the conductor 102 forms a connection pad 107 for electrical connection with the semiconductor element 120. As shown in FIG. 9, the connection pad 107 is a rectangle arranged in a position corresponding to the outer peripheral portion of the semiconductor element 120.

半導体素子１２０は、下面に電極端子１２１を有しており、この電極端子１２１には金バンプ１２２が設けられている。そして、この金バンプ１２２と配線基板１１０の接続パッド１０７とが接合されることによってフリップチップ型の半導体装置が構成されている。なお、通常であれば、配線基板１１０の上面と半導体素子１２０との間に熱硬化性樹脂から成るアンダーフィル（不図示）が充填されている。   The semiconductor element 120 has an electrode terminal 121 on the lower surface, and a gold bump 122 is provided on the electrode terminal 121. Then, the gold bump 122 and the connection pad 107 of the wiring substrate 110 are joined to form a flip chip type semiconductor device. Normally, an underfill (not shown) made of a thermosetting resin is filled between the upper surface of the wiring board 110 and the semiconductor element 120.

金バンプ１２２は、図１０に図８の要部拡大図で示すように、電極端子１２１に接合された径大の基部１２２ａとこの基部１２２ａに立設された径小の突起部１２２ｂとを有しており、電極端子１２１のピッチが狭い場合には、この突起部１２２ｂが配線基板１１０の接続パッド１０７に接合されている。なお、配線基板１１０の接続パッド１０７は、金バンプ１２２の突起部１２２ｂの直径と同じかそれよりも広い幅で形成されており、その表面には金めっきが施されている。そして、金バンプ１２２の突起部１２２ｂを接続パッド１０７の上面に当接させるとともに適当な熱および荷重をかけながら超音波振動を付与することにより突起部１２２ｂと接続パッド１０７とが超音波溶着されて接合される。   As shown in the enlarged view of the main part in FIG. 8, the gold bump 122 has a large-diameter base 122 a joined to the electrode terminal 121 and a small-diameter protrusion 122 b erected on the base 122 a. When the pitch of the electrode terminals 121 is narrow, the protrusion 122b is bonded to the connection pad 107 of the wiring board 110. The connection pad 107 of the wiring board 110 is formed with a width equal to or wider than the diameter of the protrusion 122b of the gold bump 122, and the surface thereof is plated with gold. Then, the protrusion 122b of the gold bump 122 is brought into contact with the upper surface of the connection pad 107 and ultrasonic vibration is applied while applying appropriate heat and load, so that the protrusion 122b and the connection pad 107 are ultrasonically welded. Be joined.

このような方法で金バンプ１２２と接続パッド１０７とを接続する場合、超音波溶着する際の温度、荷重、超音波振動の出力等を細かく制御する必要がある。しかしながら、通常、配線基板１１０には多少の反りやうねりがあり、これらの反りやうねり等に起因して接続パッド１０７の高さにばらつきが生じている。さらに、金バンプ１２２自体も通常は金ワイヤの一端を半導体素子１２０の電極端子１２１にボールボンディングした後、これを引きちぎることにより形成されており、その高さに多少のばらつきを有している。したがって、これらを超音波溶着する際の温度、荷重、超音波振動の出力等をいかに細かく制御したとしても全ての金バンプ１２２の突起部１２２ｂと配線基板１１０の接続パッド１０７とを良好に接合することは極めて困難であり、突起部１２２ｂが接続パッド１０７との摩擦で起きる塑性変形により大きく潰れて隣接する接続パッド１０７やそれに接合された金バンプ１２２に接触して電気的な短絡を引き起こしたり、突起部１２２ｂと接続パッド１０７とが十分に接合せずに両者間で剥離が発生して電気的な断線を引き起こしたりするという問題点があった。
特開２００２−２４６４１７号公報 When the gold bump 122 and the connection pad 107 are connected by such a method, it is necessary to finely control the temperature, load, ultrasonic vibration output, and the like when ultrasonic welding is performed. However, the wiring board 110 usually has some warping and waviness, and the height of the connection pad 107 varies due to these warping and waviness. Further, the gold bump 122 itself is usually formed by ball bonding one end of a gold wire to the electrode terminal 121 of the semiconductor element 120 and then tearing it, and the height thereof has some variation. Therefore, no matter how finely controlled the temperature, load, ultrasonic vibration output, etc., when these are ultrasonically welded, all the protrusions 122b of the gold bumps 122 and the connection pads 107 of the wiring board 110 are bonded satisfactorily. It is extremely difficult, and the protrusion 122b is largely crushed by plastic deformation caused by friction with the connection pad 107, and contacts the adjacent connection pad 107 and the gold bump 122 bonded thereto, causing an electrical short circuit, There is a problem in that the protrusion 122b and the connection pad 107 are not sufficiently bonded to each other and peeling occurs between the two to cause electrical disconnection.
JP 2002-246417 A

本発明の課題は、配線基板の接続パッドと半導体素子の電極端子とが金バンプを介して良好に接続された半導体装置およびその製造方法を提供することにある。   An object of the present invention is to provide a semiconductor device in which a connection pad of a wiring board and an electrode terminal of a semiconductor element are well connected via a gold bump, and a manufacturing method thereof.

本発明者は、上記課題を解決すべく鋭意検討を重ねた結果、配線基板の接続パッドの幅を半導体素子の電極端子に設けられた金バンプの突起部の直径よりも狭いものとすることにより、半導体素子の金バンプと配線基板の接続パッドとを超音波溶着する際の温度、荷重、超音波振動の出力等を細かく制御することなく、例え配線基板の接続パッドや半導体素子の金バンプに多少の高さばらつきがあったとしても、全ての金バンプと接続パッドとを電気的な短絡や断線を引き起こすことなく良好に接合できるという新たな知見を見出し、本発明を完成するに至った。   As a result of intensive studies to solve the above problems, the present inventor has made the width of the connection pad of the wiring board narrower than the diameter of the protrusion of the gold bump provided on the electrode terminal of the semiconductor element. Without finely controlling the temperature, load, output of ultrasonic vibration, etc. when ultrasonic welding the gold bumps of the semiconductor element and the connection pads of the wiring board, for example, to the connection pads of the wiring board or the gold bumps of the semiconductor element The present inventors have completed the present invention by finding a new finding that even if there is some height variation, all gold bumps and connection pads can be joined well without causing an electrical short circuit or disconnection.

すなわち、本発明における半導体装置は、以下の構成からなる。
（１）配線基板上の接続パッドと半導体素子の電極端子に設けた金バンプとが接合されて成る半導体装置であって、前記金バンプは前記電極端子に接合された径大の基部と該基部上に立設され、前記接続パッドに接合された径小の突起部とを有し、前記接続パッドは前記突起部に接合された部位の幅が前記突起部の直径よりも狭いことを特徴とする半導体装置。
（２）前記接続パッドの表面に金めっき層が被着されており、該金めっき層と前記突起部とが直接接合されていることを特徴とする前記（１）に記載の半導体装置。
（３）前記接続パッドが前記突起部内に埋入していることを特徴とする前記（２）に記載の半導体装置。
（４）前記突起部と前記接続パッドとが半田を介して接合されていることを特徴とする前記（１）記載の半導体装置。 That is, the semiconductor device according to the present invention has the following configuration.
(1) A semiconductor device in which a connection pad on a wiring board and a gold bump provided on an electrode terminal of a semiconductor element are joined, wherein the gold bump is joined to the electrode terminal with a large diameter base and the base A protrusion having a small diameter that is erected on the connection pad and is connected to the connection pad, wherein the connection pad has a width of a portion bonded to the protrusion that is narrower than a diameter of the protrusion. Semiconductor device.
(2) The semiconductor device according to (1), wherein a gold plating layer is deposited on a surface of the connection pad, and the gold plating layer and the protrusion are directly bonded.
(3) The semiconductor device according to (2), wherein the connection pad is embedded in the protrusion.
(4) The semiconductor device according to (1), wherein the protrusion and the connection pad are joined via solder.

また、本発明における半導体装置の製造方法は、以下の構成からなる。
（５）配線基板上の接続パッドと半導体素子の電極端子に設けた金バンプとが接続されて成る半導体装置の製造方法であって、前記金バンプとして、半導体素子の電極端子に接合された径大の基部と該基部上に立設された径小の突起部とを有する金バンプを設けるとともに、前記接続パッドとして、前記突起部の直径よりも狭い幅を有する接続パッドを形成し、次に前記突起部と前記接続パッドとを接合することを特徴とする半導体装置の製造方法。
（６）前記接続パッドの表面に金めっき層を被着させておくとともに、該金めっき層と前記突起部とを直接接合することを特徴とする前記（５）に記載の半導体装置の製造方法。
（７）前記接続パッドが前記突起部内に埋入するように接合することを特徴とする前記（６）に記載の半導体装置の製造方法。
（８）前記突起部と前記接続パッドとを半田を介して接合することを特徴とする前記（５）に記載の半導体装置の製造方法。 Moreover, the manufacturing method of the semiconductor device in this invention consists of the following structures.
(5) A method of manufacturing a semiconductor device in which a connection pad on a wiring board and a gold bump provided on an electrode terminal of a semiconductor element are connected, and the diameter bonded to the electrode terminal of the semiconductor element as the gold bump Providing a gold bump having a large base and a small-diameter protrusion standing on the base, and forming a connection pad having a width smaller than the diameter of the protrusion as the connection pad; A method of manufacturing a semiconductor device, comprising bonding the protrusion and the connection pad.
(6) The method for manufacturing a semiconductor device according to (5), wherein a gold plating layer is deposited on the surface of the connection pad, and the gold plating layer and the protrusion are directly bonded. .
(7) The method for manufacturing a semiconductor device according to (6), wherein the connection pads are joined so as to be embedded in the protrusions.
(8) The method for manufacturing a semiconductor device according to (5), wherein the protruding portion and the connection pad are joined via solder.

本発明の半導体装置およびその製造方法によれば、配線基板の接続パッドが半導体素子の電極端子に設けた金バンプの突起部の直径よりも幅が狭いことから、配線基板の接続パッドに半導体素子の金バンプを超音波溶着する際に金バンプの突起部の塑性変形は主として突起部の直径よりも幅の狭い接続パッドと接する部分のみに起きるので、大きな荷重をかけた場合であっても、金バンプの突起部内に接続パッドが埋入された状態となるまで突起部が変形するものの、接続パッドの周囲では突起部に大きな塑性変形が起きることがないので、突起部がそれ以上大きく潰れることはない。
また、接続パッドの表面に金めっき層が被着されている場合は、接続パッドと金バンプとが金めっき層を介して強固に接合される。
さらに、接続パッドが突起部内に埋入している場合は、接続パッドと突起部とが立体的な接合面を介して接合されるので極めて強固に接合される。
また、突起部と接続パッドとを半田を介して接続する場合は、半田は径小の突起部と該突起部の直径よりも幅の狭い接続パッドとの間に留まるので横に大きく広がることがない。
したがって、本発明の半導体装置およびその製造方法によれば、半導体素子の金バンプと配線基板の接続パッドとを超音波溶着する際の温度、荷重、超音波振動の出力等を細かく制御することなく、例え配線基板の接続パッドや半導体素子の金バンプに多少の高さばらつきがあったとしても、全ての金バンプと接続パッドとが電気的な短絡や断線を引き起こすことなく良好に接合された半導体装置を提供することができる。 According to the semiconductor device and the manufacturing method thereof of the present invention, since the connection pad of the wiring board is narrower than the diameter of the protrusion of the gold bump provided on the electrode terminal of the semiconductor element, the semiconductor element is connected to the connection pad of the wiring board. When the gold bumps are ultrasonically welded, the plastic deformation of the protrusions of the gold bumps mainly occurs only in the portions that contact the connection pads that are narrower than the diameter of the protrusions, so even when a large load is applied, Although the protrusion is deformed until the connection pad is embedded in the protrusion of the gold bump, the protrusion does not undergo large plastic deformation around the connection pad, so that the protrusion is further crushed. There is no.
Further, when a gold plating layer is deposited on the surface of the connection pad, the connection pad and the gold bump are firmly bonded via the gold plating layer.
Furthermore, when the connection pad is embedded in the protrusion, the connection pad and the protrusion are bonded to each other via a three-dimensional bonding surface, so that the connection pad is bonded extremely firmly.
Further, when connecting the protrusion and the connection pad via solder, the solder stays between the protrusion having a small diameter and the connection pad having a width smaller than the diameter of the protrusion, so that the solder spreads widely. Absent.
Therefore, according to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to finely control the temperature, load, output of ultrasonic vibration and the like when ultrasonic welding the gold bumps of the semiconductor element and the connection pads of the wiring board. Even if there are some height variations in the connection pads of the wiring board and the gold bumps of the semiconductor element, all the gold bumps and the connection pads are well bonded without causing an electrical short circuit or disconnection. An apparatus can be provided.

以下、本発明にかかる半導体装置およびその製造方法の一実施形態について図面を参照して詳細に説明する。図１は、ペリフェラル型の半導体素子をフリップチップ接続により搭載する本実施形態にかかる半導体装置を示す概略断面図であり、図２は、図１の半導体装置における配線基板を示す上面図である。また図３は、図１における要部拡大部、図４は図２における要部拡大図である。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of a semiconductor device and a manufacturing method thereof according to the invention will be described in detail with reference to the drawings. FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to the present embodiment in which peripheral type semiconductor elements are mounted by flip-chip connection, and FIG. 2 is a top view showing a wiring board in the semiconductor device of FIG. 3 is an enlarged view of the main part in FIG. 1, and FIG. 4 is an enlarged view of the main part in FIG.

本実施形態にかかる半導体装置は、図１に示すように、配線基板１０の上面に半導体素子２０を搭載して成る。配線基板１０は、その上面から下面にかけて主として銅から成る配線導体２ａが配設された絶縁板１ａの上下面に絶縁層１ｂと主として銅めっきからなる配線導体２ｂとが交互に積層され、さらに、その最表面には保護用のソルダーレジスト層３が被着されて成る。   The semiconductor device according to the present embodiment is configured by mounting a semiconductor element 20 on the upper surface of a wiring board 10 as shown in FIG. The wiring board 10 is formed by alternately laminating insulating layers 1b and wiring conductors 2b mainly made of copper plating on the upper and lower surfaces of an insulating plate 1a on which wiring conductors 2a made mainly of copper are arranged from the upper surface to the lower surface, A protective solder resist layer 3 is deposited on the outermost surface.

絶縁板１ａは、厚みが０．３〜１．５ｍｍ程度であり、例えばガラス繊維束を縦横に織ったガラスクロスにビスマレイミドトリアジン樹脂やエポキシ樹脂等の熱硬化性樹脂を含浸させた電気絶縁材料から成り、配線基板１０のコア部材として機能する。   The insulating plate 1a has a thickness of about 0.3 to 1.5 mm. For example, an electrical insulating material obtained by impregnating a glass cloth in which glass fiber bundles are woven vertically and horizontally with a thermosetting resin such as bismaleimide triazine resin or epoxy resin. And functions as a core member of the wiring board 10.

絶縁板１ａには、その上面から下面にかけて直径が０．０５〜０．３ｍｍ程度の複数のスルーホール４が形成されており、絶縁板１ａの上下面およびスルーホール４の内面には、配線導体２ａが被着されている。配線導体２ａは、絶縁板１ａの上下面では、主として銅箔から形成されており、スルーホール４内面では、無電解銅めっきおよびその上の電解銅めっきから形成されている。   A plurality of through holes 4 having a diameter of about 0.05 to 0.3 mm are formed in the insulating plate 1a from the upper surface to the lower surface. A wiring conductor is formed on the upper and lower surfaces of the insulating plate 1a and the inner surface of the through hole 4. 2a is applied. The wiring conductor 2a is mainly formed of copper foil on the upper and lower surfaces of the insulating plate 1a, and is formed of electroless copper plating and electrolytic copper plating thereon on the inner surface of the through hole 4.

また、スルーホール４内部には、エポキシ樹脂等の熱硬化性樹脂から成る埋め込み樹脂５が充填されており、絶縁板１ａの上下面に形成された配線導体２ａ同士がスルーホール４内の配線導体２ａを介して電気的に接続されている。   The through hole 4 is filled with an embedded resin 5 made of a thermosetting resin such as an epoxy resin, and the wiring conductors 2 a formed on the upper and lower surfaces of the insulating plate 1 a are connected to each other in the through hole 4. It is electrically connected via 2a.

このような絶縁板１ａは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートの上下面に配線導体２ａ用の銅箔を貼着した後、そのシートを熱硬化させ、これに上面から下面にかけてスルーホール４用のドリル加工を施すことにより製作される。   Such an insulating plate 1a is obtained by sticking a copper foil for the wiring conductor 2a on the upper and lower surfaces of a sheet of glass fabric impregnated with an uncured thermosetting resin, and then thermally curing the sheet, The through hole 4 is drilled from the bottom to the bottom.

また配線導体２ａは、絶縁板１ａ用のシートの上下全面に、厚みが３〜５０μｍ程度の銅箔を貼着しておくとともに、これらの銅箔および絶縁板１ａにスルーホール４を穿孔した後、このスルーホール４の内面および銅箔表面に無電解銅めっきおよび電解銅めっきを順次施し、次にスルーホール４内を埋め込み樹脂５で充填した後、この上下面の銅箔および銅めっきをフォトリソグラフィ技術を用いて所定のパターンにエッチング加工することにより絶縁板１ａの上下面およびスルーホール４の内面に形成される。   In addition, the wiring conductor 2a has a copper foil having a thickness of about 3 to 50 μm adhered to the entire upper and lower surfaces of the sheet for the insulating plate 1a, and the through holes 4 are drilled in the copper foil and the insulating plate 1a. Electroless copper plating and electrolytic copper plating are sequentially applied to the inner surface of the through hole 4 and the surface of the copper foil, and then the through hole 4 is filled with the resin 5, and then the upper and lower copper foils and copper plating are photographed. The insulating plate 1a is formed on the upper and lower surfaces and the inner surface of the through hole 4 by etching into a predetermined pattern using a lithography technique.

埋め込み樹脂５は、スルーホール４を塞ぐことによりスルーホール４の直上および直下に絶縁層１ｂを形成可能とするためのものであり、未硬化のペースト状の熱硬化性樹脂をスルーホール４内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下面を略平坦に研磨することにより形成される。   The embedded resin 5 is used to form the insulating layer 1b immediately above and below the through hole 4 by closing the through hole 4. An uncured paste-like thermosetting resin is placed in the through hole 4. After filling with a screen printing method and thermosetting it, the upper and lower surfaces thereof are polished to be substantially flat.

絶縁板１ａの上下面に積層された絶縁層１ｂは、それぞれの厚みが２０〜６０μｍ程度であり、絶縁板１ａと同様にガラスクロスに熱硬化性樹脂を含浸させた電気絶縁材料や、あるいはエポキシ樹脂等の熱硬化性樹脂に酸化ケイ素等の無機フィラーを分散させた電気絶縁材料から成る。また、各絶縁層１ｂには、直径が３０〜１００μｍ程度の複数のビアホール６が形成されている。   The insulating layers 1b laminated on the upper and lower surfaces of the insulating plate 1a have a thickness of about 20 to 60 μm. Similarly to the insulating plate 1a, an electric insulating material in which a glass cloth is impregnated with a thermosetting resin, or an epoxy It consists of an electrically insulating material in which an inorganic filler such as silicon oxide is dispersed in a thermosetting resin such as a resin. Each insulating layer 1b is formed with a plurality of via holes 6 having a diameter of about 30 to 100 μm.

各絶縁層１ｂの表面およびビアホール６内面には、無電解銅めっきおよびその上の電解銅めっきから成る配線導体２ｂが被着形成されている。そして、絶縁層１ｂを挟んで上層に位置する配線導体２ｂと下層に位置する配線導体２ｂとをビアホール６内の配線導体２ｂを介して電気的に接続することにより高密度配線が立体的に形成される。   A wiring conductor 2b made of electroless copper plating and electrolytic copper plating thereon is deposited on the surface of each insulating layer 1b and the inner surface of the via hole 6. Then, the wiring conductor 2b located in the upper layer and the wiring conductor 2b located in the lower layer are electrically connected via the wiring conductor 2b in the via hole 6 with the insulating layer 1b interposed therebetween, thereby forming a high-density wiring in three dimensions. Is done.

複数の配線導体２ｂのうち、配線基板１０の上面側における最外層の絶縁層１ｂ上に被着された一部が半導体素子２０の電極端子２１と金バンプ２２を介して電気的に接続される半導体素子接続用の接続パッド７を形成し、配線基板１０の下面側における最外層の絶縁層１ｂ上に被着された一部が、外部電気回路基板の配線導体と電気的に接続される外部接続用の接続パッド８を形成している。なお、外部接続用の接続パッド８には外部電気回路基板の配線導体と接合される半田ボール９が溶着されている。   Among the plurality of wiring conductors 2 b, a part of the wiring conductor 2 b deposited on the outermost insulating layer 1 b on the upper surface side of the wiring substrate 10 is electrically connected via the electrode terminals 21 of the semiconductor element 20 and the gold bumps 22. A connection pad 7 for connecting a semiconductor element is formed, and a part of the pad 10 deposited on the outermost insulating layer 1b on the lower surface side of the wiring board 10 is electrically connected to the wiring conductor of the external electric circuit board. Connection pads 8 for connection are formed. A solder ball 9 to be bonded to the wiring conductor of the external electric circuit board is welded to the connection pad 8 for external connection.

そして、半導体素子接続用の接続パッド７は、図２に示すように、半導体素子２０の外周部に対応する位置を半導体素子２０の外周辺に対して直角な方向に延びるようにして所定のピッチで複数並んで設けられており、その中央部がくびれて細くなっている。その上に半導体素子２０の電極端子２１が金バンプ２２を介して接合されている。   As shown in FIG. 2, the connection pads 7 for connecting the semiconductor elements have a predetermined pitch so that the positions corresponding to the outer peripheral portions of the semiconductor elements 20 extend in a direction perpendicular to the outer periphery of the semiconductor elements 20. Are provided side by side, and the central part is narrowed and narrowed. An electrode terminal 21 of the semiconductor element 20 is joined to the semiconductor element 20 via a gold bump 22.

このような接続パッド７を含む配線導体２ｂは、セミアディティブ法といわれる方法により形成される。セミアディティブ法は、例えば、ビアホール６が形成された絶縁層１ｂの表面に電解めっき用の下地金属層を無電解銅めっきにより形成し、その上に配線導体２ｂに対応した開口を有するめっきレジスト層を形成し、次に、下地金属層を給電用の電極として開口から露出する下地金属層上に電解銅めっきを施し配線導体２ｂを形成し、めっきレジストを剥離した後、露出する下地金属層をエッチング除去することによって各配線導体２ｂを電気的に独立させる方法である。   The wiring conductor 2b including such connection pads 7 is formed by a method called a semi-additive method. In the semi-additive method, for example, a base metal layer for electrolytic plating is formed on the surface of the insulating layer 1b where the via hole 6 is formed by electroless copper plating, and a plating resist layer having an opening corresponding to the wiring conductor 2b thereon Next, electrolytic copper plating is performed on the underlying metal layer exposed from the opening using the underlying metal layer as a power supply electrode to form the wiring conductor 2b, and after removing the plating resist, the exposed underlying metal layer is formed. In this method, each wiring conductor 2b is electrically independent by etching away.

そして、最外層の絶縁層１ｂおよびその上の配線導体２ｂ上には、ソルダーレジスト層３が被着されている。ソルダーレジスト層３は、最外層の配線導体２ｂを熱や外部環境から保護するための保護膜であり、上面側のソルダーレジスト層３は、接続パッド７を露出させるようにして、また下面側のソルダーレジスト層３は、接続パッド８を露出させるようにして、それぞれ被着されている。   A solder resist layer 3 is deposited on the outermost insulating layer 1b and the wiring conductor 2b thereon. The solder resist layer 3 is a protective film for protecting the outermost wiring conductor 2b from heat and the external environment. The solder resist layer 3 on the upper surface side exposes the connection pads 7 and also has a lower surface side. The solder resist layers 3 are respectively deposited so as to expose the connection pads 8.

また、上面側のソルダーレジスト層３は、図２に示すように、接続パッド７を露出させるスリット状の開口部３ａを有しており、該開口部３ａの幅に対応した長さで配線導体２ｂの一部を露出させることにより所定形状の接続パッド７を画定している。   Further, as shown in FIG. 2, the solder resist layer 3 on the upper surface side has a slit-like opening 3a that exposes the connection pad 7, and has a length corresponding to the width of the opening 3a. A connection pad 7 having a predetermined shape is defined by exposing a part of 2b.

半導体素子２０は、例えば半導体集積回路素子であり、その下面の外周部に多数の電極端子２１を有しており、電極端子２１には金バンプ２２が設けられている。金バンプ２２は図３に示すように、電極端子２１に接合された直径が５０〜８０μｍ程度の径大の基部２２ａと該基部２２ａに立設された直径が２０〜４０μｍ程度の径小の突起部２２ｂとを有している。そして、この径小の突起部２２ｂと接続パッド７とが超音波溶着により接合されている。   The semiconductor element 20 is, for example, a semiconductor integrated circuit element, and has a large number of electrode terminals 21 on the outer peripheral portion of the lower surface thereof. The electrode terminals 21 are provided with gold bumps 22. As shown in FIG. 3, the gold bump 22 is joined to the electrode terminal 21 and has a large base portion 22a having a diameter of about 50 to 80 μm and a small protrusion having a diameter of about 20 to 40 μm standing on the base portion 22a. Part 22b. And this small diameter protrusion part 22b and the connection pad 7 are joined by ultrasonic welding.

本発明の半導体装置においては、図３および図４に示すように、配線基板１０の接続パッド７の金バンプ２２と接合された部位の幅が金バンプ２２の突起部２２ｂの直径よりも狭くなっており、このことが重要である。このような構成をとることにより、後述するように、配線基板１０の接続パッド７に半導体素子２０の金バンプ２２を超音波溶着する際に金バンプ２２の突起部２２ｂを大きく潰すことなく接続パッド７に良好に接合させることができる。したがって、突起部２２ｂが隣接する接続パッド７やそれに接合された金バンプ２２に接触して電気的な短絡を引き起こしたり突起部２２ｂと接続パッド７とが剥離して電気的な断線を引き起こしたりすることはない。なお、接続パッド７の金バンプ２２と接合された部位の幅が突起部２２ｂの直径の０．７倍を超えると、金バンプ２２と接続パッド７とを突起部２２ｂに大きな潰れを発生させることなく接合することが困難となる傾向にあり、０．２倍未満であると、超音波溶着の際に接続パッド７に剥がれや断線が発生する危険性が高くなる。したがって、接続パッド７の金バンプ２２と接続された部位の幅は突起部２２ｂの直径の０．２〜０．７倍の範囲であることが好ましい。さらに、接続パッド７が金バンプ２２の突起部２２ｂに埋入された状態であると、接続パッド７と突起部２２ｂとの接合面が立体的となるので両者が極めて強固に接合される。したがって接続パッド７は金バンプ２２の突起部２２ｂに埋入された状態であることが好ましい。   In the semiconductor device of the present invention, as shown in FIGS. 3 and 4, the width of the portion joined to the gold bump 22 of the connection pad 7 of the wiring board 10 is narrower than the diameter of the protrusion 22 b of the gold bump 22. This is important. By adopting such a configuration, as will be described later, when the gold bumps 22 of the semiconductor element 20 are ultrasonically welded to the connection pads 7 of the wiring substrate 10, the connection pads are not greatly crushed. 7 can be bonded satisfactorily. Therefore, the protrusion 22b contacts the adjacent connection pad 7 and the gold bump 22 bonded thereto to cause an electrical short circuit, or the protrusion 22b and the connection pad 7 are separated to cause an electrical disconnection. There is nothing. If the width of the portion of the connection pad 7 joined to the gold bump 22 exceeds 0.7 times the diameter of the protrusion 22b, the gold bump 22 and the connection pad 7 may be greatly crushed in the protrusion 22b. If it is less than 0.2 times, there is a high risk that the connection pad 7 may be peeled off or disconnected. Therefore, the width of the portion of the connection pad 7 connected to the gold bump 22 is preferably in the range of 0.2 to 0.7 times the diameter of the protrusion 22b. Furthermore, when the connection pad 7 is embedded in the protrusion 22b of the gold bump 22, the connection surface between the connection pad 7 and the protrusion 22b becomes three-dimensional, so that both are bonded extremely firmly. Therefore, the connection pad 7 is preferably in a state of being embedded in the protrusion 22 b of the gold bump 22.

このように配線基板１０の接続パッド７と半導体素子２０の金バンプ２２とを接合するには、図５（ａ）に示すように、配線基板１０の接続パッド７上に半導体素子２０の金バンプ２２の突起部２２ｂを当接させるとともに、半導体素子２０の上面側から０．１９６〜１．４７Ｎ（２０〜１５０ｇｆ）程度の荷重を加えながら振動数が４０〜６０ＫＨｚ程度で出力が０．５〜２Ｗ程度の超音波振動を水平方向に加えることにより図５（ｂ）に示すように、突起部２２ｂの接続パッド７と当接する部位を超音波振動の摩擦により塑性変形させて接続パッド７に溶着するとともに接続パッド７を突起部２２ｂ内に埋入させる方法が採用される。このとき、突起部２２ｂの塑性変形は主として突起部２２ｂの直径よりも幅の狭い接続パッド７と接する部分のみに起きるので、大きな荷重をかけて超音波溶着しても金バンプ２２の突起部２２ｂ内に接続パッド７が埋入された状態となるまで突起部２２ｂが変形するものの、接続パッド７の周囲では突起部２２ｂに大きな塑性変形が起きることがないので、突起部２２ｂはそれ以上大きく潰れることはない。したがって、本発明の半導体装置の製造方法によると半導体素子２０の金バンプ２２と配線基板１０の接続パッド７とを超音波溶着する際の温度、荷重、超音波振動の出力等を細かく制御することなく、例え配線基板１０の接続パッド７や半導体素子２０の金バンプ２２に多少の高さばらつきがあったとしても、全ての金バンプ２２と接続パッド７とが電気的な短絡や断線を引き起こすことなく良好に接合するとこができる。   In order to join the connection pads 7 of the wiring board 10 and the gold bumps 22 of the semiconductor element 20 in this way, the gold bumps of the semiconductor element 20 are formed on the connection pads 7 of the wiring board 10 as shown in FIG. The 22 projections 22b are brought into contact with each other, and a load of about 0.196 to 1.47 N (20 to 150 gf) is applied from the upper surface side of the semiconductor element 20, and the frequency is about 40 to 60 KHz and the output is 0.5 to By applying ultrasonic vibration of about 2 W in the horizontal direction, as shown in FIG. 5 (b), the portion that contacts the connection pad 7 of the projection 22 b is plastically deformed by friction of ultrasonic vibration and welded to the connection pad 7. In addition, a method of embedding the connection pad 7 in the protruding portion 22b is employed. At this time, the plastic deformation of the protrusion 22b mainly occurs only in the portion in contact with the connection pad 7 that is narrower than the diameter of the protrusion 22b. Therefore, even if a large load is applied and ultrasonic welding is performed, the protrusion 22b of the gold bump 22 Although the protruding portion 22b is deformed until the connection pad 7 is embedded therein, the protruding portion 22b is further crushed because the protruding portion 22b does not undergo large plastic deformation around the connecting pad 7. There is nothing. Therefore, according to the method for manufacturing a semiconductor device of the present invention, the temperature, load, output of ultrasonic vibration, etc. when ultrasonically welding the gold bumps 22 of the semiconductor element 20 and the connection pads 7 of the wiring substrate 10 are controlled. For example, even if there is some height variation in the connection pads 7 of the wiring substrate 10 and the gold bumps 22 of the semiconductor element 20, all the gold bumps 22 and the connection pads 7 cause an electrical short circuit or disconnection. It can be done with good bonding.

なお、配線基板１０の接続パッド７の表面に金めっき層を０．０２〜１．５μｍの厚みに被着させておくと、配線基板１０の接続パッド７と半導体素子２０の金バンプ２２との接合を金−金の金属接合により極めて強固なものとすることができる。したがって、配線基板１０の接続パッド７の表面には金めっき層を０．０２〜１．５μｍの厚みに被着させておくことが好ましい。   If a gold plating layer is deposited on the surface of the connection pad 7 of the wiring substrate 10 to a thickness of 0.02 to 1.5 μm, the connection pad 7 of the wiring substrate 10 and the gold bump 22 of the semiconductor element 20 Bonding can be made extremely strong by gold-gold metal bonding. Therefore, it is preferable to deposit a gold plating layer on the surface of the connection pad 7 of the wiring board 10 to a thickness of 0.02 to 1.5 μm.

さらに通常であれば、半導体素子２０と配線基板１０との間の隙間にエポキシ樹脂等の熱硬化性樹脂から成るアンダーフィル（不図示）を充填し、半導体素子２０が配線基板１０上に実装された半導体装置となる。   Further, under normal circumstances, the gap between the semiconductor element 20 and the wiring board 10 is filled with an underfill (not shown) made of a thermosetting resin such as an epoxy resin, and the semiconductor element 20 is mounted on the wiring board 10. It becomes a semiconductor device.

なお、本発明は、上述の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲であれば種々の変更は可能であり、例えば上述の実施形態例では、接続パッド７をその中央部がくびれた形状とし、このくびれた部位が直線状の並びとなるように各接続パッド７を形成したが、例えば図６に示すように、接続パッド７のくびれた部位が千鳥状の並びとなるように各接続パッド７を形成してもよい。   The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the above-described embodiment, the connection pad 7 The connection pads 7 are formed such that the central portions are constricted and the constricted portions are arranged in a straight line. For example, as shown in FIG. 6, the constricted portions of the connection pads 7 are staggered. The connection pads 7 may be formed so that

さらに、上述の実施形態例では配線基板１０の接続パッド７と半導体素子２０の金バンプ２２とを超音波溶着により直接接合したが、図７に示すように、配線基板１０の接続パッド７と半導体素子２０の金バンプ２２とを半田２３を介して接合してもよい。この場合、半田２３は径小の突起部２２ｂと該突起部２２ｂの直径よりも幅の狭い接続パッド７との間に留まるので横に大きく広がることがない。したがって、この場合も、全ての金バンプ２２と接続パッド７とが電気的な短絡や断線を引き起こすことなく良好に接合された半導体装置を提供することができる。   Furthermore, in the above-described embodiment, the connection pads 7 of the wiring board 10 and the gold bumps 22 of the semiconductor element 20 are directly bonded by ultrasonic welding. However, as shown in FIG. The gold bumps 22 of the element 20 may be joined via the solder 23. In this case, since the solder 23 stays between the projection 22b having a small diameter and the connection pad 7 having a width smaller than the diameter of the projection 22b, the solder 23 does not spread greatly laterally. Therefore, also in this case, it is possible to provide a semiconductor device in which all the gold bumps 22 and the connection pads 7 are well bonded without causing an electrical short circuit or disconnection.

ペリフェラル型の半導体素子をフリップチップ接続により搭載する本発明の一実施形態にかかる半導体装置を示す概略断面図である。It is a schematic sectional drawing which shows the semiconductor device concerning one Embodiment of this invention which mounts a peripheral-type semiconductor element by flip chip connection. 図１における配線基板を示す平面図である。It is a top view which shows the wiring board in FIG. 図１に示す半導体装置の要部拡大図である。FIG. 2 is an essential part enlarged view of the semiconductor device shown in FIG. 1. 図２に示す配線基板の要部拡大図である。It is a principal part enlarged view of the wiring board shown in FIG. （ａ），（ｂ）は、図１に示す半導体装置を製造する方法を説明するための概略断面図である。(A), (b) is a schematic sectional drawing for demonstrating the method to manufacture the semiconductor device shown in FIG. 本発明にかかる半導体装置の他の実施例を示す図４に相当する要部拡大図である。FIG. 5 is an enlarged view of a main part corresponding to FIG. 4 showing another embodiment of the semiconductor device according to the present invention. 本発明にかかる半導体装置のさらに他の実施形態例を示す図３に相当する要部拡大図である。FIG. 5 is an enlarged view of a main part corresponding to FIG. 3 showing still another embodiment of the semiconductor device according to the present invention. 従来の半導体装置の例を示す概略断面図である。It is a schematic sectional drawing which shows the example of the conventional semiconductor device. 図８における配線基板を示す平面図である。It is a top view which shows the wiring board in FIG. 図７の配線基板を示す平面図である。It is a top view which shows the wiring board of FIG.

符号の説明Explanation of symbols

７：接続パッド
１０：配線基板
２０：半導体素子
２１：電極端子
２２：金バンプ
２２ａ：基部
２２ｂ：突起部
２３：半田 7: Connection pad 10: Wiring board 20: Semiconductor element 21: Electrode terminal 22: Gold bump 22a: Base 22b: Protrusion 23: Solder

Claims (8)

配線基板上の接続パッドと半導体素子の電極端子に設けた金バンプとが接合されて成る半導体装置であって、前記金バンプは前記電極端子に接合された径大の基部と該基部上に立設され、前記接続パッドに接合された径小の突起部とを有し、前記接続パッドは前記突起部と接合された部位の幅が前記突起部の直径よりも狭いことを特徴とする半導体装置。   A semiconductor device in which a connection pad on a wiring board and a gold bump provided on an electrode terminal of a semiconductor element are bonded to each other, wherein the gold bump is connected to the electrode terminal and a large-diameter base is formed on the base. A semiconductor device comprising: a projection having a small diameter joined to the connection pad, wherein the connection pad has a width of a portion joined to the projection narrower than a diameter of the projection. . 前記接続パッドの表面に金めっき層が被着されており、該金めっき層と前記突起部とが直接接合されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein a gold plating layer is deposited on a surface of the connection pad, and the gold plating layer and the protrusion are directly bonded. 前記接続パッドが前記突起部内に埋入していることを特徴とする請求項２記載の半導体装置。   The semiconductor device according to claim 2, wherein the connection pad is embedded in the protrusion. 前記突起部と前記接続パッドとが半田を介して接合されていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the protrusion and the connection pad are joined via solder. 配線基板上の接続パッドと半導体素子の電極端子に設けた金バンプとが接続されて成る半導体装置の製造方法であって、前記金バンプとして、半導体素子の電極端子に接合された径大の基部と該基部上に立設された径小の突起部とを有する金バンプを設けるとともに、前記接続パッドとして、前記突起部の直径よりも狭い幅を有する接続パッドを形成し、次に前記突起部と前記接続パッドとを接合することを特徴とする半導体装置の製造方法。   A method of manufacturing a semiconductor device in which a connection pad on a wiring board and a gold bump provided on an electrode terminal of a semiconductor element are connected to each other, and the base having a large diameter bonded to the electrode terminal of the semiconductor element as the gold bump And a bump having a small diameter standing on the base, and a connection pad having a width smaller than the diameter of the protrusion is formed as the connection pad, and then the protrusion A method for manufacturing a semiconductor device, comprising: bonding a connection pad to the connection pad. 前記接続パッドの表面に金めっき層を被着させておくとともに、該金めっき層と前記突起部とを直接接合することを特徴とする請求項５記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein a gold plating layer is deposited on the surface of the connection pad, and the gold plating layer and the protrusion are directly bonded. 前記接続パッドが前記突起部内に埋入するように接合することを特徴とする請求項６記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 6, wherein the connection pads are bonded so as to be embedded in the protrusions. 前記突起部と前記接続パッドとを半田を介して接合することを特徴とする請求項５記載の半導体装置の製造方法。   6. The method of manufacturing a semiconductor device according to claim 5, wherein the protruding portion and the connection pad are joined via solder.
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JP2015060990A (en) * 2013-09-19 2015-03-30 富士通セミコンダクター株式会社 Semiconductor device and manufacturing method of the same
JP2016139733A (en) * 2015-01-28 2016-08-04 凸版印刷株式会社 Wiring board and manufacturing method of the same

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