TWI343100B - Laminate substrate and chip package utilizing the substrate - Google Patents

Laminate substrate and chip package utilizing the substrate Download PDF

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Publication number
TWI343100B
TWI343100B TW96150377A TW96150377A TWI343100B TW I343100 B TWI343100 B TW I343100B TW 96150377 A TW96150377 A TW 96150377A TW 96150377 A TW96150377 A TW 96150377A TW I343100 B TWI343100 B TW I343100B
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layer
solder mask
metal layer
mask layer
substrate
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TW96150377A
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Chinese (zh)
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TW200929452A (en
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Wen Jeng Fan
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

13431⑽ 九、發明說明： 【發明所屬之技術領域】 * 本發明係有關於一種Η卩；f i & 々丨利電路板，可運用於半導體 • 晶片封裝構造，特別係有關於一猫社a >甘α ^ . 種積層式基板（laminate substrate)以及使用該基板之晶片封裝構造。 【先前技術】 近年來，印刷電路板能往高密度化及高效能化發展 # 成微小型積層式基板’以作為半導體封裝之晶片載體。 然在習知的半導體封裝製程中，為了要將晶片設置在基 板上，應將黏晶膠體形成於基板上，並使基板通過一預 烘烤之熱處理。此外，半導體封裝製程中基板可能遭遇 各種熱處理，例如’黏晶膠體之後烘烤固化、凸塊迴銲、 或疋也、封夥體之固化等等。然而’基板於承受熱處理的 溫度變化時’與其他封裝材料之間（如封膠體與晶片）的 熱膨脹係數（coefficient of thermal expansion，CTE)不 籲 匹配的問題會導致基板勉曲變形，因而造成作業困難。 如第1圖所示，習知一種用於半導體封裝件之基板 100係以積層（laminate)方式製成，主要包含一核心層 110、一第一金屬層120、一第二金屬層130、一第一銲罩層 140以及一第二銲罩層150。該核心層11〇係為一種玻璃纖 維強化樹脂並作為位於該基板100之一中心層。對稱地，該 核心層110之下表面係壓合一第一金屬層120,該核心層110 之上表面係壓合一第二金屬層130。該些金屬層丨2〇及130 係可為一銅（copper)層，以形成多數導電跡線（c〇nductive 5 1343100 trace)。更對稱地，該基板丨〇()之最外層上下表面係各鋪設 一第一銲罩層140與一第二銲罩層15〇。該些銲罩層14〇及 150之厚度一般係為相同，並且其材質係為具有相同熱膨脹 係數之絕緣性材料，以形成一遮覆導電跡線之保護層，但顯 露出複數個外接墊121與複數個内接指131，以留做後續與 導電το件如銲球（solder ball)或銲線（b〇nding wire)電性連接 之用。由於習知基板100係為具有對稱層數之積層基板故 基板翹曲而影響晶片封裝作業的問題尚不明顯。 再如第1圖所示，在晶片封裝製程中，可將一電子元件 如半導體晶片11藉由一黏晶層12之黏貼而設置於該基板 1〇〇之上表面，該晶片n之主動面係具有複數個銲墊11A， 可利用複數個電性連接元件〗3 (例如打線形成之拜線） 電性連接該些銲墊nA至該基板1〇〇之該些内接指 1 3 1 ’使該晶片丨丨與該基板丨〇〇電性互連。之後以一 封膠體14以壓模或點膠方式設置於該基板1〇〇之上表 面，以密封該晶片丨丨與該些電性連接元件丨3，提供適 當之保護，再以複數個外接端子1 5(常見為銲球）設置於 該基板1 00之下表面，以組成球格陣列型態之晶片封裝 構造。 二而，在上述黏晶層12之黏貼、封膠體14之固化 (η§)外接端子1 5之設置或是後續熱循環試驗（thermal cycletest)等皆有加熱基板100之處理。由於該黏晶層12之 熱膨脹係數可g會與該基& 100之熱膨脹係數有著差異、 或疋存在其它封裝材料的熱膨脹係數差異時，會有熱應力 613431(10) IX. Description of the invention: [Technical field to which the invention pertains] * The present invention relates to a Η卩;fi & 々丨利电路板, which can be applied to a semiconductor/chip package structure, particularly related to a cat society a &gt a matrix substrate and a wafer package structure using the substrate. [Prior Art] In recent years, printed circuit boards have been able to be developed into high-density and high-efficiency technologies to form micro-small laminated substrates as wafer carriers for semiconductor packages. However, in the conventional semiconductor packaging process, in order to place the wafer on the substrate, the adhesive should be formed on the substrate and the substrate subjected to a pre-baking heat treatment. In addition, the substrate may be subjected to various heat treatments in the semiconductor packaging process, such as 'binder curing after paste bonding, bump reflow, or germanium, curing of the package, and the like. However, the problem that the substrate does not match the coefficient of thermal expansion (CTE) between other packaging materials (such as the sealant and the wafer) causes the substrate to be distorted and deformed. difficult. As shown in FIG. 1 , a substrate 100 for a semiconductor package is formed in a laminate manner, and mainly includes a core layer 110 , a first metal layer 120 , a second metal layer 130 , and a first metal layer 120 . The first solder mask layer 140 and a second solder mask layer 150. The core layer 11 is a glass fiber reinforced resin and serves as a central layer of the substrate 100. Symmetrically, the lower surface of the core layer 110 is pressed against a first metal layer 120, and the upper surface of the core layer 110 is pressed against a second metal layer 130. The metal layers 1302〇 and 130 can be a copper layer to form a plurality of conductive traces (c〇nductive 5 1343100 trace). More symmetrically, a first solder mask layer 140 and a second solder mask layer 15 are disposed on the upper and lower surfaces of the outermost layer of the substrate. The thicknesses of the solder mask layers 14 and 150 are generally the same, and the materials are made of an insulating material having the same thermal expansion coefficient to form a protective layer covering the conductive traces, but a plurality of external pads 121 are exposed. And a plurality of internal fingers 131 are reserved for subsequent electrical connection with a conductive member such as a solder ball or a wire bonding wire. Since the conventional substrate 100 is a laminated substrate having a symmetrical number of layers, the problem that the substrate warps and affects the wafer packaging operation is not obvious. As shown in FIG. 1 , in the wafer packaging process, an electronic component such as the semiconductor wafer 11 can be disposed on the upper surface of the substrate 1 by adhesion of a die layer 12, and the active surface of the wafer n The plurality of pads 11A are electrically connected to the pads nA to the insole fingers 1 3 1 ' of the substrate 1 by using a plurality of electrical connection elements 3 (for example, a line formed by wire bonding). The wafer is electrically interconnected with the substrate. Then, a glue body 14 is placed on the upper surface of the substrate 1 by compression molding or dispensing to seal the wafer cassette and the electrical connection elements 丨3 to provide appropriate protection, and then multiple external connections. Terminals 15 (commonly solder balls) are disposed on the lower surface of the substrate 100 to form a wafer array configuration of the ball grid array. Second, the adhesion of the above-mentioned bonding layer 12, the curing of the encapsulant 14 (n§) of the external terminal 15 or the subsequent thermal cycle test, etc., all have the treatment of heating the substrate 100. Since the thermal expansion coefficient of the viscous layer 12 may differ from the thermal expansion coefficient of the base & 100, or there is a difference in thermal expansion coefficient of other encapsulating materials, there is thermal stress 6

I34310G ， 的不平衡’故在晶片封裝製程中易有基板翹曲問題。特別 是該黏晶層12預先形成於該基板丨〇〇時，該黏晶層12的 • 體積收縮會造成該基板100上下層應力的不平衡而翹 曲，而該基板100在封裝製程前的翹曲會造成晶片封裝 製造的良率下降。 【發明内容】 本發明之主要目的係在於提供一種積層式基板以及 I 使用該基板之晶片封裝構造’藉以不同熱膨脹係數之銲罩 層佈設於基板之上下表面’於溫度變化下產生彼此抗衡 之熱應力，以抑制基板翹曲。因此，該基板可以較低製 造成本，能不需要增加額外加勁元件與改變基板厚度之 條件下達到在晶片封裝製程中抑制基板翹曲之功效。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明之一種積層式基板包含一核心 層、一第一金屬層、一第二金屬層、一第一焊罩層、一第二 Φ 銲罩層。該核心層係具有一第一表面與一第二表面。該 第一金屬層係形成於該核心層之該第一表面。該第二金 屬層係形成於該核心層之該第二表面。該第一鲜罩層係 形成於該核心層之該第一表面並覆蓋該第一金屬層。該 第二銲罩層係形成於該核心層之該第二表面並覆蓋該 第二金屬層。其中，該第一銲罩層與該第二銲罩層係具 有大致相同之厚度，並且該第一鲜罩層與該第二焊罩層 係具有不相同之熱膨脹係數，以降低該積層式基板之翹 曲度。 7 1343100 择句*採用以下技術 本發明的目的及解決其技術問題還 措施進一步實現。 黏晶層，其係 之熱膨脹係數 之熱膨脹係數 通孔，其係貫 該第二金屬層 在前述的積層式基板中，可另包含有一 局部覆蓋於該第二銲罩層上。 在前述的積層式基板中，該第一鋒輩層 係可小於該第二銲罩層之熱膨脹係數。The imbalance of I34310G, so there is a problem of substrate warpage in the wafer packaging process. In particular, when the die layer 12 is formed on the substrate, the volume shrinkage of the die layer 12 causes an imbalance in the stress of the upper and lower layers of the substrate 100, and the substrate 100 is before the packaging process. Warpage can result in a decrease in the yield of wafer package manufacturing. SUMMARY OF THE INVENTION The main object of the present invention is to provide a laminated substrate and a wafer package structure using the substrate, wherein a solder mask layer having different thermal expansion coefficients is disposed on a lower surface of the substrate to generate heat against each other under temperature change. Stress to suppress substrate warpage. Therefore, the substrate can be made at a lower cost, and the effect of suppressing substrate warpage in the wafer packaging process can be achieved without adding additional stiffening elements and changing the thickness of the substrate. The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. A laminated substrate according to the present invention comprises a core layer, a first metal layer, a second metal layer, a first solder mask layer, and a second Φ solder mask layer. The core layer has a first surface and a second surface. The first metal layer is formed on the first surface of the core layer. The second metal layer is formed on the second surface of the core layer. The first fresh mask layer is formed on the first surface of the core layer and covers the first metal layer. The second solder mask layer is formed on the second surface of the core layer and covers the second metal layer. Wherein the first solder mask layer and the second solder mask layer have substantially the same thickness, and the first fresh mask layer and the second solder mask layer have different thermal expansion coefficients to reduce the laminated substrate Warpage. 7 1343100 SELECTIONS * Adopting the following techniques The object of the present invention and solving the technical problems thereof are further implemented. a layer of a thermal expansion coefficient of a thermal expansion coefficient, the via being through the second metal layer, wherein the laminated substrate may further comprise a partial covering layer on the second solder mask layer. In the above laminated substrate, the first front layer may be smaller than the thermal expansion coefficient of the second solder mask layer.

在前述的積層式基板中，該第一銲草層 係可大於該第二銲罩層之熱膨脹係數。 在前述的積層式基板中，其係可具有/ 穿該第一銲罩層、該第一金屬層、該核心廣、In the above laminated substrate, the first soldering layer may be larger than the thermal expansion coefficient of the second solder mask layer. In the above laminated substrate, the first solder mask layer, the first metal layer, and the core may be

以及該第二銲罩層。 在前述的積層式基板中 層並連接有複數個外接墊。 在前述的積層式基板中 層並連接有複數個内接指。 在前述的積層式基板中 銅層。 該第一金廣層係可為一線路 該第二金廣廣係价線路 該第二金㈣係 <為一虛置 【實施方式】 依據本發明之第一具體實施例，具體揭承/種積層 式基板以及使用該基板之晶片封裝構造》 請參閱第2圖所示，依據本發明之一種積廣式基"板 200包含一核心層210、一第一金屬層220、z第>金屬層 230、一第一銲罩層240、一第二銲罩層250。該核心層210 係具有一第一表面211與一第二表面212。〆般積層式 8 1343100 基板200之製作原理係以該核心層21 〇為基層，並在該核心 層210之表面依序形成該些金屬層220 ' 230及該些銲罩層 240、250 °在其他實施例中，可適當地增加内部疊層或外部 積層的數目’藉以方便線路的佈局。故該核心層21 〇係作為 該基板200之一中心層，一般是玻璃纖維強化樹脂，選用的 樹脂材質可為環氧樹脂（ep〇Xy resin)、聚亞醢胺（p〇lyimide) 樹脂、BT(bismaleimide trazine)樹脂、FR4 樹脂等。該第 _ 金屬層220係形成於該核心層210之該第一表面21 (。 該第二金屬層230係形成於該核心層210之該第二表面 212。該第一金屬層220與該第二金屬層230係可為一銅 (copper)層’使銅層經曝光（exposing)、顯影（devel〇ping)、钱 刻（etching)等製程而圖案化（patterning)以形成多數導電跡 線（conductive trace) ° 該第一鋅罩層240係形成於該核心層210之該第— 表面211並覆蓋該第一金屬層220。該第二銲罩層250 係形成於該核心層210之該第二表面212並覆蓋該第二 金屬層230。該些銲罩層240及25 0即是俗稱之「綠漆」 (Solder mask or Solder Resist)，為便於肉眼檢查，加入對眼 睛有幫助的綠色顏料於主漆中，綠漆以環氧樹脂及感光樹脂 為主要組成份，主要塗佈於印刷電路板表面，以形成一遮覆 導電跡線免於受外界水氣、污染物侵害之保護層。但該些銲 罩層240及250不限定綠色，亦可為黑色、紅色、藍色或其 它任意顏色等。一般銲罩層油墨的塗佈方式大致可分為：網 印（screen printing)、簾幕塗佈（curtain coating) ' 喷霧塗佈 9 IB43100 . (spray coating)、滾輪塗佈（roller coating)等。可壓合一環氧 樹脂乾膜或是沈積一環氧樹脂液態膜利用塗佈及硬化製程 以形成該第一鲜罩層240及該第二鲜罩層25〇。其中，該第 一銲罩層240與該第二銲罩層250係具有大致相同之厚 度’並且該第一銲罩層240與該第二銲罩層250係具有 不相同之熱膨脹係數，以降低該積層式基板2〇0之輕曲 度。 • 在本實施例中’該基板200可另包含有一黏晶層26〇， 其係局部覆蓋於該第二銲罩層250上，可做為後續黏貼晶片 之用。較佳地’該黏晶層260之材質可以選自b階膠體或是 其匕可多階固化之黏晶材料’可在晶片封裝製程之前或前期 作業中，預先形成於該基板200上。在不同實施例中，該黏 晶層260之材質亦可以選用非B階之黏性膠帶或黏稠凝膠等 等。 一般來說’針對晶片、基板、鲜球、黏晶層、封膠體 # 等膨脹係數對基板翹曲程度’可藉由該第一銲罩層240 與該第二銲罩層250之熱膨脹係數差值得到適度的熱 應力平衡。如第2圖所示，在本實施例中，該黏晶層260 之熱膨脹係數係小於該第二銲罩層250’而該第一銲罩層24〇 之熱膨脹係數係可小於該第二銲罩層250之熱膨脹係數，以 得到該核心層310之上下表面之熱應力平衡效果。在不同實 施例中，該第一銲罩層之熱膨脹係數亦可大於該第二銲罩層 之熱膨脹係數。藉由控制不同熱膨脹係數之第一銲罩層 240與第二銲罩層250佈設於該基板2〇0之上下表面， 10And the second solder mask layer. A plurality of external pads are connected to the laminated substrate in the foregoing layer. In the above laminated substrate, a plurality of internal fingers are connected to each other. In the aforementioned laminated substrate, a copper layer is used. The first gold wide layer may be a line of the second gold and wide price line, the second gold (four) system < is a dummy [embodiment] according to the first embodiment of the present invention, the specific disclosure / kind of layer The substrate and the wafer package structure using the substrate. Referring to FIG. 2, a broad-based base plate 200 according to the present invention includes a core layer 210, a first metal layer 220, and a metal layer. The layer 230, a first solder mask layer 240, and a second solder mask layer 250. The core layer 210 has a first surface 211 and a second surface 212. The first layer of the substrate 1 is formed by using the core layer 21 〇 as a base layer, and the metal layers 220 230 and the solder mask layers 240 and 250 ° are sequentially formed on the surface of the core layer 210. In other embodiments, the number of internal laminates or external laminates may be appropriately increased to facilitate layout of the circuitry. Therefore, the core layer 21 is a central layer of the substrate 200, generally a glass fiber reinforced resin, and the resin material selected may be an epoxy resin (ep〇Xy resin) or a polyplylimide resin. BT (bismaleimide trazine) resin, FR4 resin, and the like. The first metal layer 220 is formed on the first surface 21 of the core layer 210. The second metal layer 230 is formed on the second surface 212 of the core layer 210. The first metal layer 220 and the first metal layer 220 The two metal layer 230 can be a copper layer 'patterning the copper layer by exposing, develing, etching, etc. to form a plurality of conductive traces ( Conductive trace) ° The first zinc cap layer 240 is formed on the first surface 211 of the core layer 210 and covers the first metal layer 220. The second solder mask layer 250 is formed on the core layer 210. The second surface 212 covers the second metal layer 230. The solder mask layers 240 and 25 0 are commonly known as "Solder mask or Solder Resist", and are added to the green pigment for the eyes to facilitate visual inspection. In the main lacquer, the green lacquer is mainly composed of epoxy resin and photosensitive resin, and is mainly coated on the surface of the printed circuit board to form a protective layer covering the conductive traces from external moisture and pollutants. However, the solder mask layers 240 and 250 are not limited to green, and may be black. , red, blue or any other color, etc. Generally, the coating method of the solder mask ink can be roughly divided into: screen printing, curtain coating ' spray coating 9 IB43100 . (spray Coating), roller coating, etc. A dry film of epoxy resin may be pressed or an epoxy resin liquid film may be deposited by a coating and hardening process to form the first fresh cover layer 240 and the second fresh layer The first solder mask layer 240 and the second solder mask layer 250 have substantially the same thickness 'and the first solder mask layer 240 and the second solder mask layer 250 are different. a thermal expansion coefficient to reduce the light curvature of the laminated substrate 2 〇 0. • In the present embodiment, the substrate 200 may further include a bonding layer 26 局部 partially covering the second bonding layer 250 . It can be used as a subsequent paste wafer. Preferably, the material of the adhesive layer 260 can be selected from the b-stage colloid or the multi-step solidified adhesive crystal material can be used before or during the wafer packaging process. Pre-formed on the substrate 200. In various embodiments, the The material of the crystal layer 260 can also be selected from non-B-stage adhesive tape or viscous gel, etc. Generally speaking, the degree of warpage of the substrate is determined by the expansion coefficient of the wafer, the substrate, the fresh ball, the adhesive layer, the sealant # and the like. A moderate thermal stress balance can be obtained by the difference in thermal expansion coefficient between the first solder mask layer 240 and the second solder mask layer 250. As shown in Fig. 2, in the present embodiment, the thermal expansion of the adhesive layer 260 The coefficient is smaller than the second solder mask layer 250' and the thermal expansion coefficient of the first solder mask layer 24 can be smaller than the thermal expansion coefficient of the second solder mask layer 250 to obtain thermal stress balance on the upper surface of the core layer 310. effect. In various embodiments, the coefficient of thermal expansion of the first shroud layer may also be greater than the coefficient of thermal expansion of the second shroud layer. The first solder mask layer 240 and the second solder mask layer 250 are controlled to be disposed on the lower surface of the substrate 2〇0 by controlling different thermal expansion coefficients, 10

IB4310G 於溫度變化下產生彼此抗衡之熱應力，以抑制該基板 200翹曲，但不會改變該基板2〇〇之厚度。為達成本實 施例中該第一銲罩層240之熱膨脹係數小於該第二銲罩層 250之熱膨脹係數。關於該第一銲罩層24〇與該第二銲罩 層250之熱膨脹係數的決定方法’可藉由一 ansys軟體 (即電腦輔助工程分析軟體），利用有限元素法（Finite element method，FEM)求解，適當調整該黏晶層26〇、該第一銲罩層 240與該第二銲罩層25 0之熱膨脹係數’使該基板2〇〇上下 表面產生彼此抗衡之熱應力，以抑制晶片封裝製程中之 該基板200翹曲。而一般來說，銲罩層之熱膨脹係數為 60〜160PPm/°C，核心層之熱膨脹係數為16ppm/£JC，線路層 之熱膨脹係數為1 6ppm/°C。值得注意的，可藉由能量擴散 光譜儀（energy dispersive spectrograph，EDS)、二次離子質譜 儀（secondary i〇n mass spectrometer, SIMS)、霍氏紅外線光 譜儀（fourier transform infrared spectroscopy, FTIR)或熱機 械分析儀（thermal mechanical analyzer，TMA)，配合顏色來 區別及判斷該第一銲罩層240與該第二銲罩層250之材質與 熱膨脹係數’以選取適合之銲罩層進行該基板2〇〇之製作。 具體而言，該第一金屬層220係可為一線路層並連接有 複數個外接墊221。該第二金屬層230係可為一線路層並連 接有複數個内接指231。該第一銲罩層240與該第二銲罩層 250係各具有多個開口以顯露出該第一金屬層220上形成之 該些外接墊221與該第二金屬層230形成之複數個内接指 231。 1643100 . 在進行後續晶片封裝製程時，如第3圖所示，以一半導 體s曰片2 1藉由該黏晶層260之黏貼而設置於該基板2〇〇之 該第二表面212，該晶片21之主動面係具有複數個銲墊 21A，可利用複數個電性連接元件23連接該晶片21之該 些銲墊21A至該基板200之第一金屬層220，使該晶片2 1 與該基板2 0 0電性互連。在本實施例中，該些電性連接 元件2 3係為打線形成之銲線。之後，以一封勝體2 4以 鲁壓模或點膠方式，設置於該基板2〇〇之該第二表面 212，以密封該晶片21與該些電性連接元件23，提供 適當之保護’再以複數個外接端子25設置於該基板200 之該第一表面2 1 1，以使該晶片2丨得與外部印刷電路 板（printed circuit board, PCB)達成電性連接關係。在本 實例中’該些外接端子2 5係包含複數個銲球。 在進行黏晶層260之黏貼、封膠體24之固化、外接端 子25之設置或是後續熱循環試驗等溫度變化環境下，該基 Φ 板200無論是在冷卻狀態或是加熱狀態，該第一銲罩層240 與該第二銲罩層250之熱膨脹係數之兩者差異值提供一輕曲 修正，藉此，可使該基板200保持形狀穩定，在晶片封裝製 程中不受溫度變化影響而翹曲。例如，當該黏晶層260之熱 膨脹係數小於該第二銲罩層250時，該第一銲罩層24〇之熱 膨脹係數應小於該第二銲罩層2 5 0之熱膨脹係數，達到熱應 力之上下平衡。 本發明之第二具體實施例揭示另一種積層式基板。 請參閱第4圖所示，該積層式基板300主要包含一核心 12 1343100 • 層310、一第一金屬層320、一第二金屬層330、一第一銲罩 層340、一第二銲罩層350。該核心層310係具有一第一表 面311與一第二表面312。該第一金屬層320係形成於該核 心層310之該第一表面311。該第二金屬層33〇係形成於該 核心層310之該第二表面312。該第一銲罩層34〇係形成於 該核心層310之該第一表面311並覆蓋該第一金屬層320。 該第二銲罩層350係形成於該核心層310之該第二表面312 0 並覆蓋該第二金屬層330。其中，該第一銲罩層340與該第 二銲罩層3 50係具有大致相同之厚度’並且該第一銲罩層 3 40與該第二銲罩層350係具有不相同之熱膨脹係數，以降 低該積層式基板3 00之翹曲度。 如第4圖所示，該基板300可另包含有一黏晶層360，其 係局部覆蓋於該第二銲罩層350上❶在本實施例中，該基板 3 00係可具有一通孔301，其係貫穿該第一銲罩層340、該第 一金屬層320、該核心層310、該第二金屬層330以及該第 鲁 二銲罩層350，以供打線通過《—般而言，該通孔3〇1係可 位於該基板3 00之中心位置或其它位置。如第4圖所示，在 本實施例中，該第一銲罩層340之熱膨脹係數係小於該第二 銲罩層350之熱膨脹係數，並且該黏晶層36〇之熱膨脹係數 係小於該第二銲罩層350,可藉由_ ANSYS軟體，利用有 限元素法求解，適當調整該第一銲罩層34〇與該第二銲罩層 350之熱膨脹係數差值，以抵消該黏晶層36〇或其它材料之 熱膨脹係數對該基板300之勉曲影響M吏得該基板3〇〇上下 表面產生彼此抗衡之熱應力，在晶片封裝製程中該基板 13 I3431Q0 • 300不會隨著溫度變化而產生嚴重的起曲。 . 具體而s ’該第一金屬層320係為一線路層並可連接有 複數個外接墊32丨，該第一銲罩層340係具有多個開口以暴 露出該第一金屬層3 20上形成之該些外接墊32丨與複數個内 接4曰322。此外1該第二金屬層330係可為一虛置銅箔層 (dummy copper foil)，以供散熱與電性屏障。 在進行後續晶片封裝製程時，如第5圖所示，以一半導 鲁 體晶片3 1藉由該黏晶層360之黏貼而設置於該基板3〇〇之 該第二表面312，該晶片31之主動面係具有複數個銲墊 3 1 A，可利用複數個電性連接元件3 3連接該些銲替3 l a 通過該通孔301至該基板300之該些内接指322，使該 曰曰片3 1與該基板3 0 0電性互連。在本實施例中，該些 電性連接元件3 3係為打線形成之銲線。之後，進行一 封膠作業，以一封膠體34填入該基板300之上方、下方 與該通孔301，以松封該晶片31、該通孔301與該些電 鲁 性連接元件3 3，提供適當之保護。再以複數個外接端 子35(如銲球）設置於該基板300之該第一表面311，以 使該晶片3 1得與外部印刷電路板（printed circu丨t b〇ard， PCB)達成電性連接關係。 在進行基板上黏晶層之預烘烤、封膠體之固化或後續熱 循環作業等等溫度變化環境下’該苐一銲罩層340與該第二 銲罩層350之厚度得維持不變，以該第一銲罩層34〇與該第 二鲜罩層350兩者之熱膨脹係數差值，可使該基板300保持 形狀穩定，不受晶片封裝製程中溫度變化影響而翹曲或變 14 形#別是適用⑤非對稱層之積層式基板 ' <、息而5之，本發明藉由不相同熱膨脹 °又於基板之上下表面，於溫度變化下產 應力，使基板無輕曲問題。因此，該基 成本加以製造，並能不需要增加額外加 板厚度之條件下達到I晶片肖裝製程’ 之功效。 • 以上所述，僅是本發明的較佳實施 本發明作任何形式上的限制，本發明技 所附申請專利範圍為準。任何熟悉本專 利用上述揭示的技術内容作出些許更j 變化的等效實施例，但凡是未脫離本發 容，依據本發明的技術實質對以上實施 單修改'等同變化與修飾，均仍屬於本 範圍内。 • 【圖式簡單說明】 第1圖：習知可運用於半導體晶片封裝 截面示意圖。 第2圖：依據本發明之第一具體實施例 板之截面示意圖。 第3圖：依據本發明之第一具體實施例 一種晶片封裝構造之戴面示意 第4圖：依據本發明之第二具體實施例 板之截面示意圖。 係數之銲罩層佈 生彼此抗衡之熱 板可以較低製造 勁元件與改變基 令抑制基板輕曲 例而已，並非對 術方案範圍當依 業的技術人員可 扮或修飾為等同 明技術方案的内 例所作的任何簡 發明技術方案的 之積層式基板之 ’ 一種積層式基 ’使用該基板之 圖。 丨’ 一種積層式基 15 1343100 第5圖：依據本發明之第二具體實施例，使用該基板之 一種晶片封裝構造之截面示意圖。 【主要元件符號說明】The IB4310G generates thermal stresses against each other under temperature changes to suppress warpage of the substrate 200, but does not change the thickness of the substrate. To achieve the thermal expansion coefficient of the first solder mask layer 240 in the embodiment, the coefficient of thermal expansion of the second solder mask layer 250 is smaller. The method for determining the thermal expansion coefficient of the first solder mask layer 24 and the second solder mask layer 250 can be performed by an ansys software (ie, computer-aided engineering analysis software) using a finite element method (FEM). Solving, appropriately adjusting the thermal expansion coefficient of the adhesive layer 26, the first solder mask layer 240 and the second solder mask layer 25 0, so that the upper and lower surfaces of the substrate 2 are thermally stressed against each other to suppress chip packaging The substrate 200 in the process is warped. In general, the thermal expansion coefficient of the solder mask layer is 60 to 160 ppm/° C, the thermal expansion coefficient of the core layer is 16 ppm/£ JC, and the thermal expansion coefficient of the wiring layer is 16 ppm/°C. It is worth noting that it can be analyzed by energy dispersive spectrograph (EDS), secondary ion mass spectrometer (SIMS), fourier transform infrared spectroscopy (FTIR) or thermomechanical analysis. A thermal mechanical analyzer (TMA) is used to distinguish and determine the material and thermal expansion coefficient of the first solder mask layer 240 and the second solder mask layer 250 to select a suitable solder mask layer for the substrate Production. Specifically, the first metal layer 220 can be a circuit layer and connected with a plurality of external pads 221. The second metal layer 230 can be a wiring layer and connected with a plurality of internal fingers 231. The first solder mask layer 240 and the second solder mask layer 250 each have a plurality of openings to expose a plurality of the outer pads 221 and the second metal layer 230 formed on the first metal layer 220. Finger 231. 1643100. When performing a subsequent wafer packaging process, as shown in FIG. 3, a semiconductor s-chip 2 is disposed on the second surface 212 of the substrate 2 by adhesion of the bonding layer 260. The active surface of the wafer 21 has a plurality of pads 21A. The plurality of electrical connection elements 23 can be used to connect the pads 21A of the wafer 21 to the first metal layer 220 of the substrate 200, so that the wafer 2 1 The substrate 200 is electrically interconnected. In this embodiment, the electrical connecting elements 23 are wire bonds formed by wire bonding. Thereafter, a second surface 212 of the substrate 2 is disposed in a die-pressing or dispensing manner to seal the wafer 21 and the electrical connecting elements 23 to provide appropriate protection. Further, a plurality of external terminals 25 are disposed on the first surface 21 of the substrate 200 to electrically connect the wafer 2 to an external printed circuit board (PCB). In the present example, the external terminals 25 comprise a plurality of solder balls. The base Φ plate 200 is in a cooling state or a heating state, in the temperature change environment such as the adhesion of the viscous layer 260, the curing of the encapsulant 24, the setting of the external terminal 25, or the subsequent thermal cycle test. The difference between the thermal expansion coefficients of the solder mask layer 240 and the second solder mask layer 250 provides a slight curvature correction, whereby the substrate 200 can be kept in a stable shape and is not affected by temperature changes during the wafer packaging process. song. For example, when the thermal expansion coefficient of the adhesive layer 260 is smaller than the second solder mask layer 250, the thermal expansion coefficient of the first solder mask layer 24 should be smaller than the thermal expansion coefficient of the second solder mask layer 250 to achieve thermal stress. Balance above and below. A second embodiment of the present invention discloses another laminated substrate. As shown in FIG. 4 , the laminated substrate 300 mainly includes a core 12 1343100 • a layer 310 , a first metal layer 320 , a second metal layer 330 , a first solder mask layer 340 , and a second solder mask . Layer 350. The core layer 310 has a first surface 311 and a second surface 312. The first metal layer 320 is formed on the first surface 311 of the core layer 310. The second metal layer 33 is formed on the second surface 312 of the core layer 310. The first solder mask layer 34 is formed on the first surface 311 of the core layer 310 and covers the first metal layer 320. The second solder mask layer 350 is formed on the second surface 312 0 of the core layer 310 and covers the second metal layer 330. The first solder mask layer 340 and the second solder mask layer 350 have substantially the same thickness 'and the first solder mask layer 340 and the second solder mask layer 350 have different thermal expansion coefficients. To reduce the warpage of the laminated substrate 300. As shown in FIG. 4, the substrate 300 may further include a die-bonding layer 360 partially covering the second solder mask layer 350. In the embodiment, the substrate 300 may have a through hole 301. Passing through the first solder mask layer 340, the first metal layer 320, the core layer 310, the second metal layer 330, and the second Lu solder mask layer 350 for threading through "Generally, The via 3〇1 can be located at the center of the substrate 300 or at other locations. As shown in FIG. 4, in the embodiment, the thermal expansion coefficient of the first solder mask layer 340 is smaller than the thermal expansion coefficient of the second solder mask layer 350, and the thermal expansion coefficient of the adhesive layer 36 is less than the first The second solder mask layer 350 can be solved by the finite element method by using the _ANSYS software, and the difference between the thermal expansion coefficients of the first solder mask layer 34 and the second solder mask layer 350 is appropriately adjusted to offset the adhesion layer 36. The thermal expansion coefficient of the crucible or other material affects the distortion of the substrate 300, so that the upper and lower surfaces of the substrate 3 are thermally stressed against each other, and the substrate 13 I3431Q0 • 300 does not change with temperature during the wafer packaging process. Produce a serious start. Specifically, the first metal layer 320 is a circuit layer and may be connected to a plurality of external pads 32, the first solder mask layer 340 having a plurality of openings to expose the first metal layer 3 20 The plurality of external pads 32 are formed with a plurality of internal contacts 4 322. In addition, the second metal layer 330 can be a dummy copper foil for heat dissipation and electrical barrier. In the subsequent wafer packaging process, as shown in FIG. 5, the semiconductor wafer 31 is disposed on the second surface 312 of the substrate 3 by adhesion of the bonding layer 310. The active surface has a plurality of pads 3 1 A, and the plurality of electrical connecting elements 3 3 are used to connect the soldering pads 3 la through the through holes 301 to the inscribed fingers 322 of the substrate 300. The die 3 1 is electrically interconnected with the substrate 300. In this embodiment, the electrical connecting elements 33 are wire bonds formed by wire bonding. Then, a glue operation is performed, and a glue 34 is filled into the upper and lower sides of the substrate 300 and the through hole 301 to loose the wafer 31, the through hole 301 and the electric connecting elements 33. Provide appropriate protection. A plurality of external terminals 35 (such as solder balls) are disposed on the first surface 311 of the substrate 300 to electrically connect the printed circuit board to an external printed circuit board (PCB). relationship. The thickness of the first solder mask layer 340 and the second solder mask layer 350 is maintained in a temperature changing environment such as prebaking of the die layer on the substrate, curing of the encapsulant or subsequent thermal cycling operation, With the difference in thermal expansion coefficient between the first solder mask layer 34 and the second fresh mask layer 350, the substrate 300 can be kept stable in shape and is not warped or deformed by temperature changes in the wafer packaging process. #别是为5层层层层层基板', <5, the present invention, by different thermal expansion ° and on the upper surface of the substrate, under the temperature change stress, so that the substrate is free of light problems. Therefore, the base cost is manufactured and can be achieved without the need to increase the thickness of the additional plate to achieve the I wafer process. • The above description is only a preferred embodiment of the present invention, and any form of the invention is defined by the scope of the appended claims. Any equivalent embodiment of the present invention that is modified by the above-discussed technical content is not limited to the present invention, and the modifications and modifications of the above embodiment are still in accordance with the technical essence of the present invention. Within the scope. • [Simple description of the diagram] Figure 1: A schematic diagram of a cross-section of a semiconductor wafer package. Fig. 2 is a schematic cross-sectional view showing a panel according to a first embodiment of the present invention. Fig. 3 is a perspective view showing a wafer package structure according to a first embodiment of the present invention. Fig. 4 is a cross-sectional view showing a panel according to a second embodiment of the present invention. The coefficient of the welding layer is used to contend with each other. The hot plate can be made with a lower manufacturing element and a modified base suppression substrate. It is not a technical solution for the technical staff to be dressed or modified to be equivalent to the technical solution. The 'one kind of laminated base' of the laminated substrate of any of the simple technical solutions made by the internal example uses a map of the substrate.丨' A laminated substrate 15 1343100 Fig. 5 is a schematic cross-sectional view showing a wafer package structure using the substrate in accordance with a second embodiment of the present invention. [Main component symbol description]

11 晶片 11A 銲墊 12 黏晶層 13 電性連接元件 14 封膠體 15 外接端子 21 晶片 21A 銲塾 23 電性連接元件 24 封膠體 25 外接端子 3 1 晶片 31A 銲墊 33 電性連接元件 34 封膠體 35 外接端子 100 積層式基板 110 核心層 120 第一金屬層 121 外接墊 130 第二金屬層 131 内接指 140 第一銲罩層 150 第二銲罩層 200 積層式基板 210 核心層 211 第一表面 212 第二表面' 220 第一金屬層 221 外接墊 230 第二金屬層 231 内接指 240 第一銲罩層 250 第二銲罩層 260 黏晶層 300 基板 301 通孔 310 核心層 311 第一表面 312 第二表面 320 第一金屬層 321 外接墊 322 内接指 330 第二金屬層 340 第一鲜罩層 350 第二銲罩層 360 黏晶層 1611 Wafer 11A Pad 12 Bonded Layer 13 Electrical Connection Element 14 Encapsulant 15 External Terminal 21 Wafer 21A Solder 23 Electrical Connection Element 24 Encapsulant 25 External Terminal 3 1 Wafer 31A Pad 33 Electrical Connection Element 34 Sealant 35 external terminal 100 laminated substrate 110 core layer 120 first metal layer 121 external pad 130 second metal layer 131 internal finger 140 first solder mask layer 150 second solder mask layer 200 laminated substrate 210 core layer 211 first surface 212 second surface '220 first metal layer 221 outer pad 230 second metal layer 231 inner finger 240 first solder mask layer 250 second solder mask layer 260 adhesive layer 300 substrate 301 through hole 310 core layer 311 first surface 312 second surface 320 first metal layer 321 external pad 322 internal finger 330 second metal layer 340 first fresh cover layer 350 second solder mask layer 360 adhesive layer 16

Claims (1)

Γ343100 . 十、申請專利範圍： , 丨、一種積層式基板，包含： —核心層，係具有一第一表面與一第二表面； —第一金屬層，係形成於該核心層之該第一表面； 一第二金屬層，其係形成於該核心層之該第二表面； 一第一銲罩層，係形成於該核心層之該第一表面並覆蓋 該第一金屬層；以及 I 一第二銲罩層，係形成於該核心層之該第二表面並覆蓋 該第二金屬層； 其中’該第一銲罩層與該第二銲罩層係具有大致相同之 厚度，並且該第一銲罩層與該第二銲罩層係具有不相同 之熱膨脹係數，以降低該積層式基板之翹曲度。 2、 如申請專利範圍第1項所述之積層式基板，另包含有一 黏晶層，其係局部覆蓋於該第二銲罩層上。 3、 如申請專利範圍第1或2項所述之積層式基板，其中該 籲 第一銲罩層之熱膨脹係數係小於該第二銲罩層之熱膨脹 係數》 4、 如申請專利範圍第1或2項所述之積層式基板，其中該 第一銲罩層之熱膨脹係數係大於該第二銲罩層之熱膨脹 係數。 5如申清專利範圍第丨項所述之積層式基板，其係具有一 通孔，其係貫穿該第一鲜罩層、該第一金屬^、該核心 層、該第二金屬層以及該第二銲罩層。 如申。青專利範圍第1項所述之積層式基板，其中該第一 17 金屬層係為一線路層並連接有複數個外接塾。 7 > 如申請專利範圍第6項所述之積層式基板’其中該第二 金屬層係為一線路層並連接有複數個内接指。 如申請專利範圍第6項所述之積層式基板，其中該第二 金屬層係為一虛置銅箔層。 種晶片封裝構造，包含： 一積層式基板，包含： 一核心層’係具有一第一表面與一第二表面； 一第一金屬層，係形成於該核心層之該第一表面； —第二金屬層，其係形成於該核心層之該第二表面 ~第一銲罩層，係形成於該核心層之該第一表面並覆 蓋該第—金屬層；以及 '第二薛罩層’係形成於該核心層之該第二表面並覆 蓋該第二金屬層； 其中，該第一銲罩層與該第二銲罩層係具有大致相同 之厚度，並且該第一銲罩層與該第二銲罩層係具有 不相同之熱膨脹係數，以降低該積層式基板之翹曲 度； —晶片，係設置於該基板之該第二表面上； 複數個電性連接元件’係電性連接該晶片至該基板之第 一金屬層；以及 封膠體’係設置於該基板之該第二表面上，以密封該 晶片。 申請專利範圍第9項所述之晶片封裝構造，其中該 1643100 積層式基板係另包含有一黏晶層 二銲罩層上，以黏接該晶片。 11、如申請專利範圍第9或1〇項所述之 ㈣兹“曰s $所述之-片封裝構造，其 鋅罩層之熱膨脹係數係小於該第二銲罩層之埶 膨脹係數。 纤卓層二… 12、如中請專利範圍第9或1G項所述之晶片封裝構造，其 中該第-銲罩層之熱膨脹係數係大於該第 膨脹係數。 + π…Γ 343100. X. Patent application scope: 丨, a laminated substrate comprising: a core layer having a first surface and a second surface; a first metal layer formed on the first layer of the core layer a second metal layer formed on the second surface of the core layer; a first solder mask layer formed on the first surface of the core layer and covering the first metal layer; a second solder mask layer formed on the second surface of the core layer and covering the second metal layer; wherein the first solder mask layer and the second solder mask layer have substantially the same thickness, and the first A solder mask layer and the second solder mask layer have different thermal expansion coefficients to reduce the warpage of the laminated substrate. 2. The laminated substrate of claim 1, further comprising a die layer partially covering the second solder mask layer. 3. The laminated substrate according to claim 1 or 2, wherein the thermal expansion coefficient of the first solder mask layer is smaller than a thermal expansion coefficient of the second solder mask layer, 4, as claimed in claim 1 or The laminated substrate according to any one of the preceding claims, wherein the first solder mask layer has a thermal expansion coefficient greater than a thermal expansion coefficient of the second solder mask layer. 5. The laminated substrate according to claim 2, wherein the laminated substrate has a through hole penetrating through the first fresh cover layer, the first metal layer, the core layer, the second metal layer, and the first Second welding cover layer. Such as Shen. The laminated substrate according to Item 1, wherein the first 17 metal layer is a circuit layer and a plurality of external turns are connected. The laminated substrate of the sixth aspect of the invention, wherein the second metal layer is a wiring layer and a plurality of internal fingers are connected. The laminated substrate according to claim 6, wherein the second metal layer is a dummy copper foil layer. The chip package structure comprises: a laminated substrate comprising: a core layer having a first surface and a second surface; a first metal layer formed on the first surface of the core layer; a second metal layer formed on the second surface of the core layer to a first solder mask layer formed on the first surface of the core layer and covering the first metal layer; and a 'second hood layer' Forming on the second surface of the core layer and covering the second metal layer; wherein the first solder mask layer and the second solder mask layer have substantially the same thickness, and the first solder mask layer and the The second solder mask layer has different thermal expansion coefficients to reduce the warpage of the laminated substrate; - the wafer is disposed on the second surface of the substrate; the plurality of electrical connecting elements are electrically connected The wafer is to the first metal layer of the substrate; and the encapsulant is disposed on the second surface of the substrate to seal the wafer. The wafer package structure of claim 9, wherein the 1643100 laminated substrate further comprises a die bond layer on the solder mask layer to adhere the wafer. 11. The method of claim 4, wherein the thermal expansion coefficient of the zinc cap layer is less than the coefficient of expansion of the second cap layer. The chip package structure of claim 9 or claim 1 wherein the coefficient of thermal expansion of the first layer is greater than the coefficient of expansion. 其係局部覆蓋於該第 …如申請專利範圍第9項所述之晶片封農構造其係具 有通孔丨係貫穿該第一輝罩層、該第—金屬層、該 核〜層、該第二金屬層以及該第二銲罩層。 14、 如申請專利範圍第9項所述之晶片封裝構造其中該 第金屬層係為一線路層並連接有複數個外接墊。 15、 如中請專利_第心所述之晶片封裝構造，其中該 第金屬層係為一線路層並連接有複數個内接指。 16、 如申請專利範圍笛η ^ 』扼圍第14項所述之晶片封裝構造，其中該 第二金屬層係為一虛置銅箔層。 17、 如:請專利範圍第14項所述之晶片封裝構造’另包含 有複數個外接端子，係接合於該些外接塾。 8、^申請專利範圍第^所述之晶片封裝構造，其中該 ‘外接端子係包含複數個銲球。 19The wafer sealing structure according to claim 9, wherein the wafer sealing structure has a through hole system extending through the first cladding layer, the first metal layer, the core layer, and the first a second metal layer and the second solder mask layer. 14. The chip package structure of claim 9, wherein the first metal layer is a circuit layer and a plurality of external pads are connected. 15. The wafer package structure of the invention, wherein the first metal layer is a circuit layer and a plurality of internal fingers are connected. The wafer package structure of claim 14, wherein the second metal layer is a dummy copper foil layer. 17. The chip package structure of claim 14 further comprising a plurality of external terminals bonded to the external ports. 8. The wafer package structure of claim 2, wherein the 'external terminal' comprises a plurality of solder balls. 19
TW96150377A 2007-12-26 2007-12-26 Laminate substrate and chip package utilizing the substrate TWI343100B (en)

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TWI399818B (en) * 2010-04-14 2013-06-21 Powertech Technology Inc Semiconductor package preventing metal ions from diffusing to chip
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