TWI399818B - Semiconductor package preventing metal ions from diffusing to chip - Google Patents

Semiconductor package preventing metal ions from diffusing to chip Download PDF

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TWI399818B
TWI399818B TW099111703A TW99111703A TWI399818B TW I399818 B TWI399818 B TW I399818B TW 099111703 A TW099111703 A TW 099111703A TW 99111703 A TW99111703 A TW 99111703A TW I399818 B TWI399818 B TW I399818B
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wafer
carrier
semiconductor package
die
package structure
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TW099111703A
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TW201135855A (en
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Chi Yuan Chung
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Powertech Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset

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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

Disclosed is a semiconductor package preventing metal ions from diffusing to chip. Disposed between a wire-bonded chip and a chip carrier is a die-adhesive tape, which comprises a metal barrier core, a die-adhesive layer on the core and a carrier-adhesive layer below the core. Therein, the die-adhesive layer is attached to the whole backside of the chip, and the carrier-adhesive layer adheres to the carrier. The core is interposed at middle of the two adhesive layers to separate the die-adhesive layer and the carrier-adhesive layer. Thereby, there can be prevent metal ions from diffusing from wiring/PTH structure in the carrier to the chip resulting in function fail of the chip. Especially, the die-adhesive tape can be attached to the chip before wafer-cutting to form an adhesive chip assembly.

Description

阻絕金屬離子散發至晶片之半導體封裝構造Semiconductor package structure for blocking metal ions from being emitted to a wafer

本發明係有關於半導體裝置之封裝構造，特別係有關於一種阻絕金屬離子散發至晶片之半導體封裝構造。The present invention relates to a package structure of a semiconductor device, and more particularly to a semiconductor package structure that blocks metal ions from being emitted to a wafer.

晶片薄化將成為未來多晶片堆疊封裝的趨勢，以期能在一規格化的有限封裝空間內堆疊更多晶片。故現有多晶片堆疊封裝架構中，堆疊的晶片與晶片黏著材料也需要愈來愈薄，但愈趨薄化(尤指厚度在4mil以下)的晶片在高頻訊號的傳輸時容易有訊號的延遲。此外，這樣的薄化晶片在高溫高濕的工作環境下，也會有晶片產生功能失效或漏電流的情形。Chip thinning will become the trend of future multi-wafer stack packaging in order to stack more wafers in a standardized limited package space. Therefore, in the existing multi-wafer stack packaging architecture, the stacked wafer and wafer bonding materials also need to be thinner and thinner, but the thinner (especially the thickness below 4 mil) wafers are prone to signal delay in the transmission of high frequency signals. . In addition, such thinned wafers may also have functional failure or leakage current in the high temperature and high humidity working environment.

經進一步分析使晶片失效或漏電流的起因，發現在習知晶片封裝構造之內部結構中，半導體之晶片係利用黏晶材料而設置在一晶片載體(chip carrier)上，並且晶片之主動面係朝上，並以打線形成之銲線電性連接晶片至晶片載體。常見的晶片載體係為多層印刷電路板，印刷電路板之上表面係形成有複數個線路，該些線路是通常是由銅箔層經微影蝕刻定義而成，為了使印刷電路板之下表面之銅線路層能夠往下表面導通，則必須在該印刷電路板之內部設置複數個貫穿該印刷電路板之上、下表面之鍍通孔(PTH)，並於該些鍍通孔內為金屬層與導電材料。然而，銅是較為活潑的金屬，對矽晶材料以及大多數之介電質材料而言，由晶片或印刷電路板散發出的銅離子都是影響性質的污染物。矽晶片的半導體層一旦受到銅離子之滲入，將使少數載子生命週期縮短及元件漏電流增加。再者，若銅離子滲入矽晶片內介電層與半導體層，也會使晶片的崩潰電場降低及漏電流增加。因此，造成訊號延遲的電容效應、晶片失效與漏電流的主因乃是晶片載體上的銅離子或其他金屬擴散至晶片中所引起。當晶片越薄將使晶片內金屬離子濃度越高，導致晶片失效或漏電流的問題更形嚴重，故目前技術無法簡單以薄化晶粒與省略間隔物的方式進行多晶片堆疊封裝。After further analysis to cause wafer failure or leakage current, it is found that in the internal structure of the conventional chip package structure, the semiconductor wafer is disposed on a chip carrier by using a die-bonding material, and the active surface of the wafer is Upward, and electrically connected to the wafer carrier by wire bonding formed by wire bonding. A common wafer carrier is a multilayer printed circuit board. The upper surface of the printed circuit board is formed with a plurality of lines, which are usually defined by photolithography of a copper foil layer, in order to make the lower surface of the printed circuit board The copper circuit layer can be turned on to the lower surface, and a plurality of plated through holes (PTH) penetrating through the upper and lower surfaces of the printed circuit board must be disposed inside the printed circuit board, and the metal is plated in the plated through holes. Layer and conductive material. However, copper is a more active metal. For twinned materials and most dielectric materials, copper ions emitted by wafers or printed circuit boards are contaminants that affect properties. Once the semiconductor layer of the germanium wafer is infiltrated by copper ions, the minority carrier life cycle is shortened and the component leakage current is increased. Furthermore, if copper ions penetrate into the dielectric layer and the semiconductor layer in the germanium wafer, the breakdown electric field of the wafer is lowered and the leakage current is increased. Therefore, the main cause of the capacitive effect of the signal delay, wafer failure and leakage current is caused by the diffusion of copper ions or other metals on the wafer carrier into the wafer. The thinner the wafer, the higher the concentration of metal ions in the wafer, and the more serious the problem of wafer failure or leakage current. Therefore, the current technology cannot simply package the multi-wafer stack by thinning the die and omitting the spacer.

請參閱第1圖所示，一種習知晶片堆疊之半導體封裝構造100係主要包含一晶片載體110、一第一晶片120、一第二晶片160以及一模封膠體150。該第一晶片120與該第二晶片160係利用一黏晶材料130而設置在該晶片載板110之上表面111。而該晶片載板110係為印刷電路板並具有複數個線路112與複數個鍍通孔結構113，並以一防銲層114覆蓋上下表面之該些線路112。Referring to FIG. 1 , a semiconductor package structure 100 of a conventional wafer stack mainly includes a wafer carrier 110 , a first wafer 120 , a second wafer 160 , and a molding compound 150 . The first wafer 120 and the second wafer 160 are disposed on the upper surface 111 of the wafer carrier 110 by using a die bonding material 130. The wafer carrier 110 is a printed circuit board and has a plurality of lines 112 and a plurality of plated through hole structures 113, and covers the lines 112 of the upper and lower surfaces with a solder resist layer 114.

該第一晶片120係具有一主動面121並包含複數個形成於該主動面121之銲墊123。該第二晶片160係具有一主動面161並包含複數個形成於該主動面161之銲墊163。該黏晶材料130係黏貼在該第一晶片120之背面122與該第二晶片160之背面162。該黏晶材料130例如為環氧樹脂(epoxy)、銀膠(sliver paste)等等。該第一晶片120與該第二晶片160之間為階梯狀以不遮蓋下方銲墊123，故能省略間隔物以降低晶片堆疊高度，但因該第一晶片120與該第二晶片160為未薄化，故晶片堆疊數量仍為有限。利用複數個第一銲線141電性連接該第一晶片120之該些銲墊123至該晶片載板110。再利用複數個第二銲線142電性連接該第二晶片160之該些銲墊163至該晶片載板110。最後再以該模封膠體150密封該第一晶片120、該第二晶片160與該些銲線141、142，以提供適當的封裝保護以防止電性短路與塵埃污染。The first wafer 120 has an active surface 121 and includes a plurality of pads 123 formed on the active surface 121. The second wafer 160 has an active surface 161 and includes a plurality of pads 163 formed on the active surface 161. The die bonding material 130 is adhered to the back surface 122 of the first wafer 120 and the back surface 162 of the second wafer 160. The die bonding material 130 is, for example, an epoxy, a silver paste, or the like. The first wafer 120 and the second wafer 160 are stepped to cover the lower pad 123, so that the spacer can be omitted to reduce the height of the wafer stack, but the first wafer 120 and the second wafer 160 are not Thinning, so the number of wafer stacks is still limited. The pads 123 of the first wafer 120 are electrically connected to the wafer carrier 110 by a plurality of first bonding wires 141. The plurality of second bonding wires 142 are electrically connected to the pads 163 of the second wafer 160 to the wafer carrier 110. Finally, the first wafer 120, the second wafer 160 and the bonding wires 141, 142 are sealed with the molding compound 150 to provide proper package protection to prevent electrical short circuit and dust pollution.

如第2圖所示，在上述之習知封裝構造中，該些線路112在高溫高濕的工作環境下會有銅離子或其他金屬離子擴散的問題，該些銅離子或其他金屬離子會往上擴散穿過黏晶材料130再往上擴散至第一晶片120，甚至擴散到第二晶片160，由於第一晶片120與第二晶片160未薄化時(厚度約在十數密爾)銅離子分散在晶片之半導體層內功能失效的問題尚不明顯。一旦意圖在一有限封裝厚度內堆疊多個晶片時，例如在1mm封裝厚度(包含基板厚度)內需要堆疊四個(含)以上晶片，則第一晶片120與第二晶片160可能需要薄化到4密爾以下，這將造成晶片120、160的電容效應、崩潰電場降低及漏電流的風險增加，而容易有晶片功能失效的問題。As shown in FIG. 2, in the above-mentioned conventional package structure, the lines 112 may have problems of diffusion of copper ions or other metal ions in a high-temperature and high-humidity working environment, and the copper ions or other metal ions may go to The upper diffusion diffuses through the die bonding material 130 and spreads up to the first wafer 120, even to the second wafer 160, since the first wafer 120 and the second wafer 160 are not thinned (thickness is about ten mils) copper The problem of functional failure of ions dispersed in the semiconductor layer of the wafer is not significant. Once it is intended to stack a plurality of wafers within a limited package thickness, such as requiring four or more wafers to be stacked within a 1 mm package thickness (including substrate thickness), the first wafer 120 and the second wafer 160 may need to be thinned to Below 4 mils, this will result in an increase in the capacitive effect of the wafers 120, 160, the collapse electric field, and the risk of leakage current, and is prone to problems with wafer function failure.

有鑒於此，本發明之主要目的係在於提供一種阻絕金屬離子散發至晶片之半導體封裝構造，可防止金屬離子從晶片載體之線路與鍍通孔結構擴散至晶片，進而避免誘發晶片的功能失效，特別適用於採用薄化晶粒且省略間隔物之多晶片封裝架構。In view of the above, the main object of the present invention is to provide a semiconductor package structure for blocking metal ions from being emitted to a wafer, which can prevent metal ions from diffusing from the wiring of the wafer carrier and the plated through hole structure to the wafer, thereby avoiding the function failure of the induced wafer. It is especially suitable for multi-chip package architectures that use thinned dies and omits spacers.

本發明之次一目的係在於提供一種阻絕金屬離子散發至晶片之半導體封裝構造，應用於多晶片堆疊結構時，能使晶片堆疊之間亦不會有金屬離子擴散污染，進而提高產品信賴度。A second object of the present invention is to provide a semiconductor package structure that blocks metal ions from being emitted to a wafer. When applied to a multi-wafer stack structure, metal ions are not diffused and contaminated between the wafer stacks, thereby improving product reliability.

本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種阻絕金屬離子散發至晶片之半導體封裝構造，包含一晶片載體、一第一晶片、一黏晶膠帶以及複數個銲線。該晶片載體係具有一上表面。該第一晶片係具有一主動面與一相對之背面，該主動面係設有複數個銲墊。該黏晶膠帶係包含一晶片黏著層、一載體黏著層以及一金屬阻障核心，其中該晶片黏著層係形成在該金屬阻障核心之一上表面並全面地貼附於該第一晶片之該背面，該載體黏著層係形成在該金屬阻障核心之一下表面並黏著至該晶片載體之該上表面，該金屬阻障核心係介設於該晶片黏著層與該載體黏著層之中間且隔離該晶片黏著層與該載體黏著層。該些銲線係電性連接該第一晶片之該些銲墊至該晶片載體。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor package structure for blocking metal ions from being emitted to a wafer, comprising a wafer carrier, a first wafer, a die bonding tape and a plurality of bonding wires. The wafer carrier has an upper surface. The first wafer has an active surface and an opposite back surface, and the active surface is provided with a plurality of pads. The adhesive tape comprises a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die attach layer is formed on an upper surface of the metal barrier core and is fully attached to the first wafer. The carrier adhesion layer is formed on a lower surface of the metal barrier core and adhered to the upper surface of the wafer carrier, and the metal barrier core is interposed between the wafer adhesion layer and the carrier adhesion layer. The adhesive layer of the wafer is isolated from the carrier. The bonding wires are electrically connected to the pads of the first wafer to the wafer carrier.

本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

在前述的半導體封裝構造中，可另包含有一模封膠體，係形成於該晶片載體之該上表面，以密封該第一晶片、該黏晶膠帶與該些銲線。In the foregoing semiconductor package structure, a mold encapsulant may be further formed on the upper surface of the wafer carrier to seal the first wafer, the die bond tape and the bonding wires.

在前述的半導體封裝構造中，該金屬阻障核心之材質係可為鎳(Ni)、鈦(Ti)與其合金之其中之一。In the foregoing semiconductor package structure, the material of the metal barrier core may be one of nickel (Ni), titanium (Ti) and its alloy.

在前述的半導體封裝構造中，該黏晶膠帶係可藉由形成一晶圓切割膠帶上而轉貼於該第一晶片，而使該黏晶膠帶與該第一晶片之該背面具有相同尺寸。In the foregoing semiconductor package structure, the die bond tape can be transferred to the first wafer by forming a wafer dicing tape, and the die bond tape has the same size as the back surface of the first wafer.

在前述的半導體封裝構造中，該金屬阻障核心之厚度係可介於10至50μm，並大於該晶片黏著層與該載體黏著層之厚度。In the foregoing semiconductor package structure, the thickness of the metal barrier core may be between 10 and 50 [mu]m and greater than the thickness of the die attach layer and the carrier adhesive layer.

在前述的半導體封裝構造中，該第一晶片係可為薄化晶粒。In the aforementioned semiconductor package construction, the first wafer system may be a thinned die.

在前述的半導體封裝構造中，可另包含至少一第二晶片，係以無間隔物方式疊設於該第一晶片上。In the foregoing semiconductor package structure, at least one second wafer may be further disposed on the first wafer in a spacer-free manner.

本發明還揭示適用於前述的一種阻絕金屬離子散發至晶片之半導體封裝構造，包含：一晶片載體、複數個黏性晶片組件以及複數個銲線。該晶片載體係具有一上表面。該些黏性晶片組件係疊設該晶片載體之該上表面上，每一黏性晶片組件係由一薄化晶粒與一黏晶膠帶所構成，該薄化晶粒係具有一主動面與一相對之背面，該主動面係設有複數個銲墊，該黏晶膠帶係與該背面具有相同尺寸並包含一晶片黏著層、一載體黏著層以及一金屬阻障核心，其中該晶片黏著層係形成在該金屬阻障核心之一上表面並全面地貼附於該背面，該載體黏著層係形成在該金屬阻障核心之一下表面，用以黏著下方鄰接之該晶片載體或薄化晶粒，該金屬阻障核心係介設於該晶片黏著層與該載體黏著層之中間且隔離該晶片黏著層與該載體黏著層。該些銲線係電性連接該些銲墊至該晶片載體。The present invention also discloses a semiconductor package structure suitable for the above-mentioned resistive metal ion emission to a wafer, comprising: a wafer carrier, a plurality of viscous wafer assemblies, and a plurality of bonding wires. The wafer carrier has an upper surface. The viscous wafer assembly is stacked on the upper surface of the wafer carrier, and each viscous wafer assembly is composed of a thinned die and an adhesive tape, the thinned die has an active surface and An opposite back surface, the active surface is provided with a plurality of solder pads, the adhesive tape having the same size as the back surface and comprising a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die attach layer Formed on an upper surface of the metal barrier core and fully attached to the back surface, the carrier adhesive layer is formed on a lower surface of the metal barrier core for adhering the wafer carrier or thinned crystal adjacent to the lower side The metal barrier core is interposed between the adhesive layer of the wafer and the adhesive layer of the carrier and isolates the adhesive layer of the wafer from the adhesive layer of the carrier. The bonding wires electrically connect the pads to the wafer carrier.

由以上技術方案可以看出，本發明之阻絕金屬離子散發至晶片之半導體封裝構造，具有以下優點與功效：It can be seen from the above technical solutions that the semiconductor package structure of the present invention for dissipating metal ions to the wafer has the following advantages and effects:

一、可藉由具有金屬阻障核心之黏晶膠帶作為其中之一技術手段，黏晶膠帶能完整覆蓋於晶片載體之線路與鍍通孔結構上，可防止金屬離子從晶片載體之線路與鍍通孔結構擴散至晶片，進而避免誘發晶片的功能失效。本發明特別適用於採用薄化晶粒且省略間隔物之多晶片封裝架構，有效解決內部薄化晶片之功能失效的問題。1. As one of the technical means by using a magnetic barrier tape with a metal barrier core, the adhesive tape can completely cover the line of the wafer carrier and the plated through hole structure, and can prevent metal ions from being routed and plated from the wafer carrier. The via structure diffuses to the wafer, thereby avoiding inducing functional failure of the wafer. The invention is particularly suitable for a multi-chip package architecture that uses thinned dies and omits spacers, effectively solving the problem of functional failure of internal thinned wafers.

二、可藉由薄化晶片背面貼附有金屬阻障核心之黏晶膠帶作為其中之一技術手段，應用於多晶片堆疊結構時，能使晶片堆疊之間不會有金屬離子擴散污染，進而提高產品信賴度。2. As a technical means by thinning the back side of the wafer with a metal barrier core attached to the metal barrier core, when applied to the multi-wafer stack structure, metal ions may not be diffused and contaminated between the wafer stacks, and further Improve product reliability.

以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

依據本發明之一具體實施例，一種阻絕金屬離子散發至晶片之半導體封裝構造舉例說明於第3圖之截面示意圖與4圖之局部放大圖。該半導體封裝構造200包含一晶片載體210、一第一晶片220、一黏晶膠帶230以及複數個第一銲線241。According to an embodiment of the present invention, a semiconductor package structure for blocking metal ions from being emitted to a wafer is illustrated in a cross-sectional view of FIG. 3 and a partial enlarged view of FIG. The semiconductor package structure 200 includes a wafer carrier 210, a first wafer 220, a die bonding tape 230, and a plurality of first bonding wires 241.

該晶片載體210係具有一上表面211與一下表面。該上表面211係可供一模封膠體250之形成，該下表面係相對於該上表面211之表面，可設置複數個外接端子(圖未繪出)，例如錫球，以供對外表面接合。該晶片載體210係可為一印刷電路板、一導線架、一電路薄膜或各種晶片載板。在本實施例中，該晶片載體210係為一高密度兩面導通之多層印刷電路板，內部形成有複數個線路212與複數個鍍通孔結構213，皆為銅材質，並以一防銲層214覆蓋上下表面之該些線路212，以形成一能遮覆線路以免於受外界水氣、污染物侵害之保護層。該些線路212係可為銅(copper)圖案層，可先使一銅箔經曝光(exposing)、顯影(developing)、蝕刻(etching)等製程而圖案化(patterning)以形成多數導電跡線(conductive trace)。該些鍍通孔結構213比如是利用機械鑽孔或雷射鑽孔方式，再經由塞孔製程形成。The wafer carrier 210 has an upper surface 211 and a lower surface. The upper surface 211 is formed by a molding compound 250. The lower surface is opposite to the surface of the upper surface 211, and a plurality of external terminals (not shown), such as solder balls, may be disposed for bonding to the outer surface. . The wafer carrier 210 can be a printed circuit board, a lead frame, a circuit film, or various wafer carriers. In this embodiment, the wafer carrier 210 is a high-density two-sided conductive printed circuit board having a plurality of lines 212 and a plurality of plated through-hole structures 213 formed therein, both of which are made of copper and have a solder resist layer. 214 covers the lines 212 of the upper and lower surfaces to form a protective layer that can cover the circuit from external moisture and contaminants. The lines 212 may be copper pattern layers, and a copper foil may be patterned by exposing, developing, etching, etc. to form a plurality of conductive traces ( Conductive trace). The plated through hole structures 213 are formed by, for example, mechanical drilling or laser drilling, and then through a plug hole process.

該第一晶片220係具有一主動面221與一相對之背面222，該主動面221係設有複數個銲墊223，可為鋁墊或銅墊。該第一晶片220之基材材質可為矽、砷化鎵或其它半導體材質，其係可具有經晶背研磨之厚度，即為一薄化晶粒，即厚度在4密爾以下，例如厚度介於1至4密爾(mil，其中1mil=25.4μm)。該主動面221上係設有積體電路元件，如微控制器、微處理器、記憶體、邏輯電路、特殊應用積體電路(如顯示器驅動電路)等或上述之組合，並電性連接至該些銲墊223。該些銲墊223係位置設置在該第一晶片220之該主動面221之單一側邊、兩對應側邊、四周側邊或是中央位置。在本實施例中，該些銲墊223係設置在該主動面221之單一側邊。The first wafer 220 has an active surface 221 and an opposite back surface 222. The active surface 221 is provided with a plurality of pads 223, which may be aluminum pads or copper pads. The substrate material of the first wafer 220 may be tantalum, gallium arsenide or other semiconductor materials, which may have a thickness of back-grained, that is, a thinned grain, that is, a thickness of 4 mil or less, such as thickness. It is between 1 and 4 mils (1 mil = 25.4 μm). The active surface 221 is provided with integrated circuit components, such as a microcontroller, a microprocessor, a memory, a logic circuit, a special application integrated circuit (such as a display driving circuit), or the like, and is electrically connected thereto. The pads 223. The pads 223 are disposed on a single side, two corresponding sides, four sides, or a central position of the active surface 221 of the first wafer 220. In the embodiment, the pads 223 are disposed on a single side of the active surface 221 .

具體而言，再如第3圖所示，在該半導體封裝構造200中，可另包含至少一第二晶片260，以達到較高之容量或達到較多之功能應用。該第二晶片260係以無間隔物方式疊設於該第一晶片220上，以顯露該第一晶片220之該些銲墊223。詳細而言，該第二晶片260係具有一主動面261與一相對之背面262，該主動面261係設有複數個銲墊263。該第一晶片220與該第二晶片260之主動面係朝上。該第二晶片260係藉由另一黏晶膠帶230而黏貼至該第一晶片220之該主動面221上。該第二晶片260之尺寸係可相同於該第一晶片220，並可為薄化晶粒。該第二晶片260之銲墊263係可設置在該第二晶片260之該主動面261之單一側邊。在本實施例中，該第二晶片260之該些銲墊263係可相對於該第一晶片220之該些銲墊223而設置在不同側邊。進一步來說，每一薄化晶粒(包含一第一晶片220與一第二晶片260)可與一黏晶膠帶230構成一黏性晶片組件22。該些黏性晶片組件22係可為非對準的「之」字形堆疊，以使該些黏性晶片組件22包含該些銲墊223、263之部位為兩側橫向突出，橫向突出之銲墊223、263可供進行後續之打線製程，藉以達到高密度的晶片堆疊。在一實施例中，該第一晶片220與該第二晶片260可為實質相同之記憶體晶片，具有相同之晶片尺寸與功能，可由同一晶圓製程中形成。Specifically, as shown in FIG. 3, in the semiconductor package structure 200, at least one second wafer 260 may be further included to achieve higher capacity or to achieve more functional applications. The second wafer 260 is stacked on the first wafer 220 in a spacer-free manner to expose the pads 223 of the first wafer 220. In detail, the second wafer 260 has an active surface 261 and an opposite back surface 262. The active surface 261 is provided with a plurality of pads 263. The active surface of the first wafer 220 and the second wafer 260 are upward. The second wafer 260 is adhered to the active surface 221 of the first wafer 220 by another adhesive tape 230. The second wafer 260 may be the same size as the first wafer 220 and may be thinned. The pad 263 of the second wafer 260 can be disposed on a single side of the active surface 261 of the second wafer 260. In the present embodiment, the pads 263 of the second wafer 260 are disposed on different sides with respect to the pads 223 of the first wafer 220. Further, each of the thinned dies (including a first wafer 220 and a second wafer 260) may form a viscous wafer assembly 22 with a die attach tape 230. The viscous wafer assembly 22 can be a non-aligned zigzag stack, such that the viscous wafer assembly 22 includes the pads 223, 263 which are laterally protruded on both sides and laterally protruding pads. 223, 263 are available for subsequent wire bonding processes to achieve high density wafer stacking. In one embodiment, the first wafer 220 and the second wafer 260 can be substantially identical memory chips, having the same wafer size and function, and can be formed in the same wafer process.

如第4圖所示，該黏晶膠帶230係作為一擴散阻絕膠層(diffusion barrier layer film)。該黏晶膠帶230係包含一晶片黏著層231、一載體黏著層232以及一金屬阻障核心233，其中該晶片黏著層231係形成在該金屬阻障核心232之一上表面233A並全面地貼附於該第一晶片220之該背面222。該載體黏著層232係形成在該金屬阻障核心233之一下表面233B並黏著至該晶片載體210之該上表面211。具體而言，該金屬阻障核心233係介設於該晶片黏著層231與該載體黏著層232之中間且隔離該晶片黏著層231與該載體黏著層232。換言之，如第3與4圖所示，該黏晶膠帶230係具有至少三層的三明治夾層結構，並且在此「隔離」所指係為該金屬阻障核心233為無孔洞結構，令該晶片黏著層231與該載體黏著層232不相接觸。故該黏晶膠帶230係呈完整片狀以全面地貼附在該第一晶片220之背面222，用以黏著該第一晶片220至該晶片載體210之該上表面211。而該金屬阻障核心233係如三明治之夾心中間層這般而介設於該晶片黏著層231與該載體黏著層232之中間，並與該晶片黏著層231與該載體黏著層232具有相同之長度與面積。該晶片黏著層231與該載體黏著層232係分別位於該金屬阻障核心233之上下表面，具有熱固化(thermosetting)或熱塑性(thermoplastic)特性，其材質可為環氧物、B階膠體或有機樹脂類，具有黏著性。具體而論，該金屬阻障核心233之材質係可為鎳(Ni)、鈦(Ti)與其合金之其中之一，或可為其他可阻絕金屬離子的非銅系金屬。較佳地，該金屬阻障核心233之厚度係可大於該晶片黏著層231與該載體黏著層232之厚度，故該金屬阻障核心233可作為該兩黏著層的形成載體，以降低黏著層厚度並確保該黏晶膠帶230有一適當之剛性。例如，該晶片黏著層231與該載體黏著層232之厚度係可約為10至25μm，而該金屬阻障核心233之厚度係可介於10至50μm，以有效阻絕金屬離子穿透。該金屬阻障核心233可先在一模板上電鍍形成，在印刷上該載體黏著層232之後，可貼上晶圓切割膠帶。當由模板剝離之後，可再印刷形成該晶片黏著層231，以構成該黏晶膠帶230。As shown in FIG. 4, the adhesive tape 230 serves as a diffusion barrier layer film. The adhesive tape 230 includes a die attach layer 231, a carrier adhesive layer 232, and a metal barrier core 233. The die attach layer 231 is formed on one of the upper surface 233A of the metal barrier core 232 and is fully attached. Attached to the back side 222 of the first wafer 220. The carrier adhesive layer 232 is formed on a lower surface 233B of the metal barrier core 233 and adhered to the upper surface 211 of the wafer carrier 210. Specifically, the metal barrier core 233 is interposed between the die attach layer 231 and the carrier adhesive layer 232 and isolates the die attach layer 231 from the carrier adhesive layer 232. In other words, as shown in FIGS. 3 and 4, the die-bonding tape 230 has a sandwich sandwich structure of at least three layers, and the term "isolation" as used herein means that the metal barrier core 233 has a non-porous structure. The adhesive layer 231 is not in contact with the carrier adhesive layer 232. Therefore, the adhesive tape 230 is in a complete sheet shape and is fully attached to the back surface 222 of the first wafer 220 for adhering the first wafer 220 to the upper surface 211 of the wafer carrier 210. The metal barrier core 233 is interposed between the die attach layer 231 and the carrier adhesive layer 232, such as a sandwich interlayer, and has the same adhesion to the carrier adhesive layer 231 and the carrier adhesive layer 232. Length and area. The die attach layer 231 and the carrier adhesive layer 232 are respectively located on the lower surface of the metal barrier core 233, and have thermosetting or thermoplastic properties, and the material may be epoxy, B-stage colloid or organic. Resin type, adhesive. Specifically, the material of the metal barrier core 233 may be one of nickel (Ni), titanium (Ti) and its alloy, or may be other non-copper metal that can block metal ions. Preferably, the thickness of the metal barrier core 233 can be greater than the thickness of the adhesive layer 231 and the carrier adhesive layer 232. Therefore, the metal barrier core 233 can serve as a carrier for the two adhesive layers to reduce the adhesive layer. The thickness ensures that the die attach tape 230 has a suitable rigidity. For example, the thickness of the die attach layer 231 and the carrier adhesive layer 232 may be about 10 to 25 μm, and the thickness of the metal barrier core 233 may be between 10 and 50 μm to effectively block metal ion penetration. The metal barrier core 233 can be formed by electroplating on a template. After the carrier adhesive layer 232 is printed, the wafer cutting tape can be attached. After being peeled off from the template, the wafer adhesive layer 231 may be reprinted to constitute the die attach tape 230.

如第4圖所示，該些線路212與鍍通孔結構213在高溫高濕的工作環境下，會產生銅離子或其他金屬離子，而銅離子或其他金屬離子會往外擴散。當往外擴散至該黏晶膠帶230時，由於該金屬阻障核心233覆蓋於該第一晶片220下方覆蓋面積的該晶片載體210之該些線路212與鍍通孔結構213之上，金屬離子會被該金屬阻障核心233有效阻絕，而可防止金屬離子從該晶片載體210之線路212擴散與鍍通孔結構213擴散至該第一晶片220之主動面221及其半導體基材層，進而避免誘發該第一晶片220的功能失效。As shown in FIG. 4, the lines 212 and the plated through hole structure 213 generate copper ions or other metal ions in a high temperature and high humidity working environment, and copper ions or other metal ions diffuse outward. When the metal barrier core 233 is overlaid on the die pad 210 and the plated via structure 213 over the first wafer 220 under the first wafer 220, the metal ions will The metal barrier core 233 is effectively blocked, and metal ions are prevented from diffusing from the line 212 of the wafer carrier 210 and the plated through hole structure 213 is diffused to the active surface 221 of the first wafer 220 and the semiconductor substrate layer thereof, thereby avoiding The function of the first wafer 220 is induced to fail.

如第3圖所示，該些第一銲線241係電性連接該第一晶片220之該些銲墊223至該晶片載體210，另以複數個第二銲線242係電性連接該第二晶片260之該些銲墊263至該晶片載體210，以形成內部電性連接。該些第一銲線241與該些第二銲線242係可利用打線製程所形成，其材質可為金線、鋁線或其他之金屬線。該模封膠體250係為一種內含矽氧填充物的絕緣性熱固性樹脂，如環氧模封化合物(EMC,epoxy molding compound)，可利用模封(或稱轉移成形)方法形成。該模封膠體250係密封該第一晶片220、該黏晶膠帶230、該些第一銲線241與該些第二銲線242，以使上述內部元件與外界隔離而免受外界衝擊或污染。As shown in FIG. 3, the first bonding wires 241 are electrically connected to the pads 223 of the first wafer 220 to the wafer carrier 210, and the second bonding wires 242 are electrically connected to the first bonding wires 242. The pads 263 of the two wafers 260 are coupled to the wafer carrier 210 to form an internal electrical connection. The first bonding wires 241 and the second bonding wires 242 can be formed by a wire bonding process, and the material thereof can be gold wires, aluminum wires or other metal wires. The molding compound 250 is an insulating thermosetting resin containing a cerium oxide filler, such as an epoxy molding compound (EMC), which can be formed by a molding (or transfer molding) method. The mold sealing body 250 seals the first wafer 220, the die bonding tape 230, the first bonding wires 241 and the second bonding wires 242 to isolate the internal components from the outside environment from external impact or pollution. .

因此，本發明的明顯進步性就是可以在一多晶片封裝架構採用薄化晶粒並且省略間隔物，達到可晶片堆疊數量增加，例如在封裝厚度1mm以下的產品內堆疊四個(含)以上晶片厚度在4密爾以下的薄化晶粒，也不會有晶片產生功能失效或漏電流的情形。Therefore, the significant advancement of the present invention is that it is possible to use thinned dies in a multi-chip package architecture and omit spacers to achieve an increase in the number of wafer stacks, for example, stacking four or more wafers in a package having a package thickness of 1 mm or less. Thinned grains with a thickness of less than 4 mils will not cause functional failure or leakage current in the wafer.

如第5圖所示，該黏晶膠帶230係可藉由形成一晶圓切割膠帶270上而轉貼於該第一晶片220之該背面222。即在晶圓階級時，將晶圓之背面研磨至適當厚度後，再將該黏晶膠帶230與該晶圓切割膠帶270貼附於晶圓背面，之後再進行切割以形成複數個薄化晶粒(即第一晶片230)。在晶圓切割成複數個薄化晶粒時，該黏晶膠帶230同時被切割也會與該第一晶片220之該背面222具有相同尺寸。具體而言，該晶圓切割膠帶270係可為一藍膜UV膠帶(blue tape)或其它光感性黏著膠帶，在切割晶圓時能固定晶粒以使其不散離。在晶圓切割完成後，可利用光照射方式使該晶圓切割膠帶270之黏性降低或喪失而脫離該黏晶膠帶230，而使該第一晶片220與該黏晶膠帶230組成為一黏性晶片組件，使薄化晶粒有一較強的結構並具有黏性，可極方便地進行黏晶作業。在此所稱之「黏性晶片組件」表示該黏晶膠帶230具有與該第一晶片220相同的切割側緣，並且該黏晶膠帶230應具有適當的厚度，至少在該第一晶片220之厚度二分之一以上，以維持一足夠的支撐強度。例如，當該第一晶片220之厚度為4密爾時，該黏晶膠帶230之厚度應在2密爾以上並且具有相同的底面積。當第二晶片260及其下方黏著材料也具有相同結構時，多個黏性晶片組件便能以無間隔物方式疊設於一晶片載體上(如第3圖所示)。As shown in FIG. 5, the adhesive tape 230 can be attached to the back surface 222 of the first wafer 220 by forming a wafer dicing tape 270. That is, in the wafer level, after the back surface of the wafer is polished to an appropriate thickness, the die bonding tape 230 and the wafer dicing tape 270 are attached to the back surface of the wafer, and then diced to form a plurality of thinned crystals. Granules (ie, first wafer 230). When the wafer is diced into a plurality of thinned dies, the dicing tape 230 is simultaneously cut to have the same size as the back surface 222 of the first wafer 220. Specifically, the wafer dicing tape 270 can be a blue film or a light-sensitive adhesive tape that can be used to fix the wafer so that it does not detach. After the wafer is cut, the adhesiveness of the wafer dicing tape 270 can be reduced or lost by the light irradiation method, and the first wafer 220 and the adhesive tape 230 are made into a sticky layer. The wafer assembly makes the thinned crystal grain have a strong structure and is viscous, which makes it easy to perform the die bonding operation. As used herein, "adhesive wafer assembly" means that the die attach tape 230 has the same cut side edge as the first wafer 220, and the die attach tape 230 should have a suitable thickness, at least in the first wafer 220. More than half of the thickness to maintain a sufficient support strength. For example, when the thickness of the first wafer 220 is 4 mils, the thickness of the die bond tape 230 should be above 2 mils and have the same bottom area. When the second wafer 260 and the adhesive material thereunder have the same structure, the plurality of viscous wafer assemblies can be stacked on a wafer carrier without spacers (as shown in FIG. 3).

如第6圖所示，該黏性晶片組件22係可設置在該晶片載體210之該上表面211上。每一黏性晶片組件22係由一薄化晶粒220與一黏晶膠帶230所構成。如第3圖所示，該晶片載體210之該上表面211由該些黏性晶片組件22所構成之覆蓋區域係設有線路212與鍍通孔結構213。應用於採用薄化晶粒與無間隔物堆疊方式之多晶片堆疊結構時，本發明藉由將具有金屬阻障核心233之黏晶膠帶230貼附在薄化晶粒22之背面，用以黏著下方鄰接之該晶片載體210或薄化晶粒220，使晶片載體210之線路212與鍍通孔213結構散發之金屬離子，能被該黏晶膠帶230之該金屬阻障核心233有效組絕，進一步能使晶片220、260堆疊之間不會有金屬離子擴散污染，進而提高產品信賴度。As shown in FIG. 6, the viscous wafer assembly 22 can be disposed on the upper surface 211 of the wafer carrier 210. Each of the viscous wafer assemblies 22 is composed of a thinned die 220 and a die attach tape 230. As shown in FIG. 3, the upper surface 211 of the wafer carrier 210 is provided with a line 212 and a plated through hole structure 213 in a covered area formed by the viscous wafer assemblies 22. When applied to a multi-wafer stack structure using a thinned die and a spacerless stack, the present invention adheres to the back side of the thinned die 22 by attaching a die attach tape 230 having a metal barrier core 233 for adhesion. The metal carrier 210 or the thinned die 220 adjacent to the wafer carrier 210 and the metal ion of the plated via 213 can be effectively eliminated by the metal barrier core 233 of the die bond tape 230. Further, there is no metal ion diffusion contamination between the stacks of the wafers 220 and 260, thereby improving product reliability.

以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

100．．．半導體封裝構造100. . . Semiconductor package construction

110．．．晶片載體110. . . Wafer carrier

111．．．上表面111. . . Upper surface

112．．．線路112. . . line

113．．．鍍通孔結構113. . . Plated through hole structure

114．．．防銲層114. . . Solder mask

120．．．第一晶片120. . . First wafer

121．．．主動面121. . . Active surface

122．．．背面122. . . back

123．．．銲墊123. . . Solder pad

130．．．黏晶材料130. . . Clay material

141．．．第一銲線141. . . First wire bond

142．．．第二銲線142. . . Second wire

150．．．模封膠體150. . . Molded sealant

160．．．第二晶片160. . . Second chip

161．．．主動面161. . . Active surface

162．．．背面162. . . back

162．．．銲墊162. . . Solder pad

200．．．半導體封裝構造200. . . Semiconductor package construction

210．．．晶片載體210. . . Wafer carrier

211．．．上表面211. . . Upper surface

212．．．線路212. . . line

213．．．鍍通孔結構213. . . Plated through hole structure

214．．．防銲層214. . . Solder mask

22．．．黏性晶片組件twenty two. . . Sticky wafer assembly

220．．．第一晶片220. . . First wafer

221．．．主動面221. . . Active surface

222．．．背面222. . . back

223．．．銲墊223. . . Solder pad

230．．．黏晶膠帶230. . . Adhesive tape

231．．．晶片黏著層231. . . Wafer adhesion layer

232．．．載體黏著層232. . . Carrier adhesive layer

233．．．金屬阻障核心233. . . Metal barrier core

233A．．．上表面233A. . . Upper surface

233B．．．下表面233B. . . lower surface

241．．．第一銲線241. . . First wire bond

242．．．第二銲線242. . . Second wire

250．．．模封膠體250. . . Molded sealant

260．．．第二晶片260. . . Second chip

261．．．主動面261. . . Active surface

262．．．背面262. . . back

263．．．銲墊263. . . Solder pad

270．．．晶圓切割膠帶270. . . Wafer cutting tape

第1圖：一種習知晶片堆疊之半導體封裝構造之截面示意圖。Figure 1 is a cross-sectional view showing a conventional semiconductor package structure of a wafer stack.

第2圖：習知晶片堆疊之半導體封裝構造在第1圖圈劃處之局部放大圖。Fig. 2 is a partially enlarged view showing the semiconductor package structure of the conventional wafer stack in the first circle.

第3圖：依據本發明之一具體實施例的一種阻絕金屬離子散發至晶片之半導體封裝構造之截面示意圖。Figure 3 is a cross-sectional view showing a semiconductor package structure for blocking metal ions from being emitted to a wafer in accordance with an embodiment of the present invention.

第4圖：依據本發明之一具體實施例的半導體封裝構造在第3圖圈劃處之局部放大圖。Figure 4 is a partial enlarged view of the semiconductor package structure according to an embodiment of the present invention taken along the circle of Figure 3.

第5圖：依據本發明之一具體實施例的半導體封裝構造中所使用黏晶膠帶貼附於一晶圓切割膠帶之截面示意圖。Figure 5 is a cross-sectional view showing a die-cut tape used in a semiconductor package structure according to an embodiment of the present invention attached to a wafer dicing tape.

第6圖：繪示本發明之一具體實施例的半導體封裝構造中使黏性晶片組件貼附於晶片載體之截面示意圖。Figure 6 is a cross-sectional view showing the bonding of a viscous wafer module to a wafer carrier in a semiconductor package structure according to an embodiment of the present invention.

210．．．晶片載體210. . . Wafer carrier

211．．．上表面211. . . Upper surface

212．．．線路212. . . line

213．．．鍍通孔結構213. . . Plated through hole structure

214．．．防銲層214. . . Solder mask

220．．．第一晶片220. . . First wafer

222．．．背面222. . . back

230．．．黏晶膠帶230. . . Adhesive tape

231．．．晶片黏著層231. . . Wafer adhesion layer

232．．．載體黏著層232. . . Carrier adhesive layer

233．．．金屬阻障核心233. . . Metal barrier core

233A．．．上表面233A. . . Upper surface

233B．．．下表面233B. . . lower surface

Claims (10)

一種阻絕金屬離子散發至晶片之半導體封裝構造，包含：一晶片載體，係具有一上表面；一第一晶片，係具有一主動面與一相對之背面，該主動面係設有複數個銲墊；一黏晶膠帶，係包含一晶片黏著層、一載體黏著層以及一金屬阻障核心，其中該晶片黏著層係形成在該金屬阻障核心之一上表面並全面地貼附於該第一晶片之該背面，該載體黏著層係形成在該金屬阻障核心之一下表面並黏著至該晶片載體之該上表面，該金屬阻障核心係介設於該晶片黏著層與該載體黏著層之中間且隔離該晶片黏著層與該載體黏著層；以及複數個銲線，係電性連接該第一晶片之該些銲墊至該晶片載體。A semiconductor package structure for dissipating metal ions to a wafer, comprising: a wafer carrier having an upper surface; a first wafer having an active surface and an opposite back surface, the active surface being provided with a plurality of pads An adhesive tape comprising a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die attach layer is formed on an upper surface of the metal barrier core and is fully attached to the first The carrier adhesive layer is formed on a lower surface of the metal barrier core and adhered to the upper surface of the wafer carrier, and the metal barrier core is disposed on the die adhesion layer and the carrier adhesion layer. Intermediately separating the adhesion layer of the wafer and the carrier adhesion layer; and a plurality of bonding wires electrically connecting the pads of the first wafer to the wafer carrier. 根據申請專利範圍第1項之阻絕金屬離子散發至晶片之半導體封裝構造，另包含有一模封膠體，係形成於該晶片載體之該上表面，以密封該第一晶片、該黏晶膠帶與該些銲線。The semiconductor package structure for dissipating metal ions to the wafer according to claim 1 of the patent application, further comprising a molding compound formed on the upper surface of the wafer carrier to seal the first wafer, the die bonding tape and the Some wire bonds. 根據申請專利範圍第1項之阻絕金屬離子散發至晶片之半導體封裝構造，其中該金屬阻障核心之材質係為鎳(Ni)、鈦(Ti)與其合金之其中之一。The semiconductor package structure for dissipating metal ions to the wafer according to the first aspect of the patent application, wherein the metal barrier core is made of one of nickel (Ni), titanium (Ti) and an alloy thereof. 根據申請專利範圍第1項之阻絕金屬離子散發至晶片之半導體封裝構造，其中該黏晶膠帶係藉由形成一晶圓切割膠帶上而轉貼於該第一晶片，而使該黏晶膠帶與該第一晶片之該背面具有相同尺寸。The semiconductor package structure for dissipating metal ions to a wafer according to the first aspect of the patent application, wherein the die bond tape is transferred to the first wafer by forming a wafer dicing tape, and the die bond tape is The back side of the first wafer has the same size. 根據申請專利範圍第1項之阻絕金屬離子散發至晶片之半導體封裝構造，其中該金屬阻障核心之厚度係介於10至50μm，並大於該晶片黏著層與該載體黏著層之厚度。The semiconductor package structure for dissipating metal ions to a wafer according to the first aspect of the patent application, wherein the metal barrier core has a thickness of 10 to 50 μm and is larger than a thickness of the adhesion layer of the wafer and the carrier adhesion layer. 根據申請專利範圍第1項之阻絕金屬離子散發至晶片之半導體封裝構造，其中該第一晶片係為薄化晶粒。A semiconductor package structure in which a metal ion is emitted to a wafer according to the first aspect of the patent application, wherein the first wafer is a thinned crystal grain. 根據申請專利範圍第1或6項之阻絕金屬離子散發至晶片之半導體封裝構造，另包含至少一第二晶片，係以無間隔物方式疊設於該第一晶片上。According to the semiconductor package structure of the first or sixth aspect of the patent application for dissipating metal ions to the wafer, at least one second wafer is further disposed on the first wafer in a spacer-free manner. 一種阻絕金屬離子散發至晶片之半導體封裝構造，包含：一晶片載體，係具有一上表面；複數個黏性晶片組件，係以無間隔物方式疊設該晶片載體之該上表面上，每一黏性晶片組件係由一薄化晶粒與一黏晶膠帶所構成，該薄化晶粒係具有一主動面與一相對之背面，該主動面係設有複數個銲墊，該黏晶膠帶係與該背面具有相同尺寸並包含一晶片黏著層、一載體黏著層以及一金屬阻障核心，其中該晶片黏著層係形成在該金屬阻障核心之一上表面並全面地貼附於該背面，該載體黏著層係形成在該金屬阻障核心之一下表面，用以黏著下方鄰接之該晶片載體或薄化晶粒，該金屬阻障核心係介設於該晶片黏著層與該載體黏著層之中間且隔離該晶片黏著層與該載體黏著層；以及複數個銲線，係電性連接該些銲墊至該晶片載體。A semiconductor package structure for blocking emission of metal ions to a wafer, comprising: a wafer carrier having an upper surface; and a plurality of viscous wafer assemblies stacked on the upper surface of the wafer carrier in a spacer-free manner The viscous wafer assembly is composed of a thinned die and an adhesive tape, the thinned die has an active surface and an opposite back surface, and the active surface is provided with a plurality of solder pads, the adhesive tape The same size as the back surface and comprising a die attach layer, a carrier adhesive layer and a metal barrier core, wherein the die attach layer is formed on an upper surface of the metal barrier core and is fully attached to the back surface The carrier adhesive layer is formed on a lower surface of the metal barrier core for adhering the wafer carrier or thinned crystal grains adjacent to the lower surface, and the metal barrier core layer is disposed on the adhesion layer of the wafer and the carrier adhesion layer And separating the adhesion layer of the wafer and the carrier adhesion layer; and a plurality of bonding wires electrically connecting the pads to the wafer carrier. 根據申請專利範圍第8項之阻絕金屬離子散發至晶片之半導體封裝構造，其中該些黏性晶片組件係為非對準的「之」字形堆疊，以使該些黏性晶片組件包含該些銲墊之部位為兩側橫向突出。The semiconductor package structure for dissipating metal ions to the wafer according to claim 8 of the patent application, wherein the viscous wafer components are non-aligned zigzag stacks, so that the viscous wafer assemblies include the solders The parts of the pad are laterally protruded on both sides. 根據申請專利範圍第8項之阻絕金屬離子散發至晶片之半導體封裝構造，其中該晶片載體之該上表面由該些黏性晶片組件所構成之覆蓋區域係設有線路與鍍通孔結構。The semiconductor package structure for dissipating metal ions to the wafer according to the eighth aspect of the patent application, wherein the upper surface of the wafer carrier is covered by the viscous wafer assembly with a line and a plated through hole structure.
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TW200616115A (en) * 2004-11-05 2006-05-16 Advanced Semiconductor Eng Wafer structure, chip structure and bumping process
TW200834832A (en) * 2006-12-18 2008-08-16 Nitto Denko Corp Adhesive sheet for fabricating semiconductor device and fabricating method of semiconductor using the adhesive sheet
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* Cited by examiner, † Cited by third party
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TW200522232A (en) * 2003-12-19 2005-07-01 Nitto Denko Corp Manufacturing method of semiconductor equipment
TW200613431A (en) * 2004-05-21 2006-05-01 Sharp Kk Semiconductor device
TW200616115A (en) * 2004-11-05 2006-05-16 Advanced Semiconductor Eng Wafer structure, chip structure and bumping process
TW200834832A (en) * 2006-12-18 2008-08-16 Nitto Denko Corp Adhesive sheet for fabricating semiconductor device and fabricating method of semiconductor using the adhesive sheet
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