TWI394259B - Bga package stacked with multiple substrates - Google Patents
Bga package stacked with multiple substrates Download PDFInfo
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- TWI394259B TWI394259B TW097127224A TW97127224A TWI394259B TW I394259 B TWI394259 B TW I394259B TW 097127224 A TW097127224 A TW 097127224A TW 97127224 A TW97127224 A TW 97127224A TW I394259 B TWI394259 B TW I394259B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Wire Bonding (AREA)
- Combinations Of Printed Boards (AREA)
Description
本發明係有關於一種半導體裝置，特別係有關於一種多基板堆疊之球格陣列封裝構造。The present invention relates to a semiconductor device, and more particularly to a ball grid array package structure for a multi-substrate stack.
現今電子產品係朝多功能與輕薄短小之方向發展，為配合此一發展方向，半導體業者積極研發能整合多個晶片或封裝件之半導體封裝構造，藉以符合電子產品之要求。Today's electronic products are moving toward versatility, lightness and shortness. To cope with this development direction, semiconductor companies are actively developing semiconductor package structures that can integrate multiple wafers or packages to meet the requirements of electronic products.
請參閱第1圖所示，一種習知球格陣列封裝構造100主要係由一第一半導體封裝件101以及一第二半導體封裝件102所堆疊組成，通常這類裝置被稱之為堆疊式封裝(POP,Packag－On－Package)裝置。該第一半導體封裝件101主要包含一第一基板110、複數個第一晶片120、一第一封膠體131以及複數個第一銲線181。該第二半導體封裝件102主要包含一第二基板140、一第二晶片150、一第二封膠體132以及複數個第二銲線182。Referring to FIG. 1 , a conventional ball grid array package structure 100 is mainly composed of a first semiconductor package 101 and a second semiconductor package 102. Generally, such devices are called stacked packages (POP). , Packag-On-Package) device. The first semiconductor package 101 mainly includes a first substrate 110, a plurality of first wafers 120, a first encapsulant 131, and a plurality of first bonding wires 181. The second semiconductor package 102 mainly includes a second substrate 140, a second wafer 150, a second encapsulant 132, and a plurality of second bonding wires 182.
該第一基板110係具有一第一上表面111與一第一下表面112，其係以積層(laminate)方式製成，通常包含一第一核心層114以及在第一核心層114上下兩表面各有一層的第一防焊層115。該第一核心層114係為一種玻璃纖維強化樹脂並作為位於該第一基板110之一基礎層。該第一核心層114之上下表面係壓合有線路層(圖 未繪出)，以形成多數導電跡線(conductive trace)。該些第一防焊層115係為絕緣性材料，以形成一遮覆導電跡線之保護層，但顯露出複數個第一球墊116與複數個第一連接墊117。該些第一晶片120係設於該第一基板110之該第一上表面111。每一第一晶片120之主動面係包含有複數個第一銲墊121，並利用該些第一銲線181電性連接至該第一基板110之該些第一連接墊117，以達到電性連接。再以該第一封膠體131密封該些第一晶片120與該些第一銲線181，而形成該第一半導體封裝件101。該第二基板140係具有一第二上表面141與一第二下表面142，其亦以積層方式製成，並包含一第二核心層144以及上下表面各有一層之第二防焊層145。該第二基板140之結構大致相同於該第一基板110，故該第一基板110與該第二基板140為雙面皆具有防焊層與線路層之結構。該第二基板140之該第二下表面142係具有複數個第二球墊146，該第二上表面141係具有複數個第二轉接墊147。該第二晶片150係設於該第二基板140之該第二上表面141。該第二晶片150之主動面係包含有複數個第二銲墊153，並利用該些第二銲線182連接至該第二基板140，以達到電性連接。再以該第二封膠體132密封該些第二晶片150與該些第二銲線182，而形成該第二半導體封裝件102。另在該第二基板140之該第二下表面142可設置複數個外接銲球170，以對外表面接合。The first substrate 110 has a first upper surface 111 and a first lower surface 112. The first substrate 110 is formed in a laminate manner, and generally includes a first core layer 114 and upper and lower surfaces on the first core layer 114. Each has a first solder mask layer 115. The first core layer 114 is a glass fiber reinforced resin and serves as a base layer on the first substrate 110. The upper surface of the first core layer 114 is press-bonded with a circuit layer (Fig. Not drawn) to form a plurality of conductive traces. The first solder mask layers 115 are made of an insulating material to form a protective layer covering the conductive traces, but a plurality of first ball pads 116 and a plurality of first connection pads 117 are exposed. The first wafers 120 are disposed on the first upper surface 111 of the first substrate 110 . The active surface of each of the first wafers 120 includes a plurality of first pads 121 electrically connected to the first connection pads 117 of the first substrate 110 by the first bonding wires 181 to achieve electricity. Sexual connection. The first wafer 120 and the first bonding wires 181 are sealed by the first sealing body 131 to form the first semiconductor package 101. The second substrate 140 has a second upper surface 141 and a second lower surface 142. The second substrate 140 is also formed in a laminated manner and includes a second core layer 144 and a second solder resist layer 145 having a layer on each of the upper and lower surfaces. . The structure of the second substrate 140 is substantially the same as that of the first substrate 110. Therefore, the first substrate 110 and the second substrate 140 have a structure of a solder resist layer and a circuit layer on both sides. The second lower surface 142 of the second substrate 140 has a plurality of second ball pads 146, and the second upper surface 141 has a plurality of second transfer pads 147. The second wafer 150 is disposed on the second upper surface 141 of the second substrate 140. The active surface of the second wafer 150 includes a plurality of second pads 153 and is connected to the second substrate 140 by the second bonding wires 182 to achieve electrical connection. The second wafer 150 and the second bonding wires 182 are sealed by the second encapsulant 132 to form the second semiconductor package 102. In addition, the second lower surface 142 of the second substrate 140 may be provided with a plurality of external solder balls 170 for bonding to the outer surface.
在該第一半導體封裝件101與該第二半導體封裝件102在製成之後在進行堆疊以達成兩者電性連接，利用複數個中介銲球160設置在該些第二轉接墊147與該些第一球墊116上。由於該第二晶片150與該第二封膠體132的空間佔用，該些中介銲球160只能為周邊配置。當該些中介銲球160過小，則無法順利作為上下基板之間電性連接。當該些中介銲球160過大，球與球之間會接觸短路並使堆疊厚度增加。After the first semiconductor package 101 and the second semiconductor package 102 are fabricated, they are stacked to achieve electrical connection therebetween, and the plurality of intermediate solder balls 160 are disposed on the second transfer pads 147 and the Some of the first ball pads 116. Due to the space occupied by the second wafer 150 and the second encapsulant 132, the intermediate solder balls 160 can only be disposed in the periphery. When the intermediate solder balls 160 are too small, they cannot be electrically connected as the upper and lower substrates. When the intermediate solder balls 160 are too large, a short circuit is contacted between the balls and the balls to increase the thickness of the stack.
此外，在封膠體之固化(curing)、外接端子之設置或是後續熱循環試驗(thermal cycle test)等皆有昇降溫之條件變化，又第一封膠體131與第二封膠體132具有不相同的表面覆蓋面積，故導致不同封裝件之間的上下基板翹曲度不同之問題。基板翹曲產生的應力會集中少數的中介銲球160導致斷裂(crack)，故而影響封裝之產品可靠度。In addition, in the curing of the sealant, the setting of the external terminal or the subsequent thermal cycle test, the conditions of the temperature rise and fall are changed, and the first sealant 131 and the second sealant 132 are different. The surface coverage area causes problems in the warpage of the upper and lower substrates between different packages. The stress generated by the warpage of the substrate concentrates a small number of intermediate solder balls 160 causing cracks, thus affecting the reliability of the packaged product.
有鑒於此，本發明之主要目的係在於提供一種多基板堆疊之球格陣列封裝構造，能使封裝構造更為薄化並降低上下堆疊基板之翹曲度差異，更可節省基板之成本與簡化封裝製造流程。In view of this, the main object of the present invention is to provide a multi-substrate stacked ball grid array package structure, which can make the package structure thinner and reduce the warpage difference between the upper and lower stacked substrates, thereby saving the cost and simplifying the substrate. Packaging manufacturing process.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。依據本發明所揭示之一種多基板堆疊之球格陣列封裝構造，主要包含一第一基板、至少一第一晶片、一封膠體、一第二基板、一第二晶片、一異方性導電膠層以及複數個銲球。該第一基板係具有一第一上表 面與一第一下表面，其中該第一基板之側邊係設有複數個由該第一上表面延伸到該第一下表面之第一導通電極。該第一晶片係設於該第一基板之該第一上表面。該封膠體係形成於該第一基板之該第一上表面，以密封該第一晶片。該第二基板係具有一第二上表面與一第二下表面，該第二基板係疊設於該第一基板之下方，其中該第二基板之側邊係設有複數個由該第二上表面延伸到該第二下表面之第二導通電極，該第二下表面係設有複數個陣列配置之球墊。該第二晶片係設於該第一基板之該第一下表面與該第二基板之該第二上表面之間。該異方性導電膠層係設於該第一基板之該第一下表面與該第二基板之該第二上表面之間，該異方性導電膠層係包含複數個導電顆粒，其中至少一導電顆粒係電性接觸在該些第一導通電極與對應之該些第二導通電極之間。該些銲球係結合於該些球墊。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. According to the present invention, a multi-substrate stacked ball grid array package structure mainly includes a first substrate, at least a first wafer, a gel, a second substrate, a second wafer, and an anisotropic conductive adhesive. Layer and a plurality of solder balls. The first substrate has a first upper surface And a first lower surface, wherein the side of the first substrate is provided with a plurality of first conductive electrodes extending from the first upper surface to the first lower surface. The first wafer is disposed on the first upper surface of the first substrate. The encapsulation system is formed on the first upper surface of the first substrate to seal the first wafer. The second substrate has a second upper surface and a second lower surface. The second substrate is stacked under the first substrate, wherein the second substrate is provided with a plurality of second sides. The upper surface extends to the second conductive electrode of the second lower surface, and the second lower surface is provided with a plurality of ball pads arranged in an array. The second wafer is disposed between the first lower surface of the first substrate and the second upper surface of the second substrate. The anisotropic conductive adhesive layer is disposed between the first lower surface of the first substrate and the second upper surface of the second substrate, wherein the anisotropic conductive adhesive layer comprises a plurality of conductive particles, wherein at least A conductive particle is electrically connected between the first conductive electrodes and the corresponding second conductive electrodes. The solder balls are bonded to the ball pads.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述球格陣列封裝構造中，該異方性導電膠層係可密封該第二晶片。In the aforementioned ball grid array package configuration, the anisotropic conductive adhesive layer can seal the second wafer.
在前述球格陣列封裝構造中，該些第一導通電極係可具有複數個突出於該第一下表面之接觸表面。In the foregoing ball grid array package configuration, the first conductive electrodes may have a plurality of contact surfaces protruding from the first lower surface.
在前述球格陣列封裝構造中，該第一下表面可即為該第一基板之一核心層之外露表面。In the foregoing ball grid array package configuration, the first lower surface may be an exposed surface of one of the core layers of the first substrate.
在前述球格陣列封裝構造中，該第二晶片係可具有 一背面，其係貼附於該第一基板之該核心層。In the foregoing ball grid array package configuration, the second wafer system may have a back surface attached to the core layer of the first substrate.
在前述球格陣列封裝構造中，該第二晶片係可覆晶接合至該第二基板。In the foregoing ball grid array package configuration, the second wafer can be flip-chip bonded to the second substrate.
在前述球格陣列封裝構造中，該第二晶片係可具有一主動面，其係貼附於該第二基板之該第二上表面，該球格陣列封裝構造另包含複數個銲線，其係通過該第二基板之一槽孔並電性連接該第二晶片與該第二基板。In the foregoing ball grid array package structure, the second wafer system may have an active surface attached to the second upper surface of the second substrate, the ball grid array package structure further comprising a plurality of bonding wires, Passing through a slot of the second substrate and electrically connecting the second wafer and the second substrate.
在前述球格陣列封裝構造中，可另包含有一第二封膠體，係形成於該槽孔內以密封該些銲線。In the foregoing ball grid array package structure, a second encapsulant may be further included in the slot to seal the bonding wires.
在前述球格陣列封裝構造中，該些第二導通電極係可具有複數個突出於該第二上表面之接觸表面。In the foregoing ball grid array package configuration, the second conductive electrodes may have a plurality of contact surfaces protruding from the second upper surface.
在前述球格陣列封裝構造中，該第二上表面係可即為該第二基板之一核心層之外露表面。In the foregoing ball grid array package configuration, the second upper surface may be an exposed surface of one of the core layers of the second substrate.
在前述球格陣列封裝構造中，該第二晶片係可具有一背面，其係貼附於該第二基板之核心層。In the foregoing ball grid array package configuration, the second wafer system may have a back surface attached to the core layer of the second substrate.
在前述球格陣列封裝構造中，該第二晶片係可覆晶接合至該第一基板。In the foregoing ball grid array package configuration, the second wafer can be flip-chip bonded to the first substrate.
在前述球格陣列封裝構造中，更可包含複數個第一銲線，其係可電性連接該第一晶片與該第一基板並被該封膠體所密封。In the foregoing ball grid array package structure, a plurality of first bonding wires may be further included, which are electrically connected to the first substrate and sealed by the sealing body.
在前述球格陣列封裝構造中，該第一基板與該第二基板係可具有相同尺寸。In the foregoing ball grid array package configuration, the first substrate and the second substrate may have the same size.
在前述球格陣列封裝構造中，該異方性導電膠層係可包含封膠材料。In the foregoing ball grid array package construction, the anisotropic conductive adhesive layer may comprise a sealant material.
由以上技術方案可以看出，本發明之多基板堆疊之球格陣列封裝構造，具有以下優點與功效：一、藉由異方性導電膠層密封基板之間的晶片並電性導接基板之側邊導通電極，以使晶片嵌埋在多基板之間的堆疊結構更為薄化並降低上下堆疊基板之翹曲度差異。此外，能減少在基板兩相對內表面的元件，例如僅需要至多一層的線路層與一層覆蓋線路層之防焊層並可省略基板之間封膠體與中介銲球，以節省其板成本與簡化封裝製造流程。It can be seen from the above technical solutions that the multi-substrate stacked ball grid array package structure of the present invention has the following advantages and effects: 1. The wafer between the substrates is sealed by the anisotropic conductive adhesive layer and electrically connected to the substrate. The side electrodes are turned on to make the stack structure in which the wafer is embedded between the plurality of substrates thinner and reduce the difference in warpage of the upper and lower stacked substrates. In addition, the components on the opposite inner surfaces of the substrate can be reduced, for example, only one layer of the wiring layer and one layer of the soldering layer covering the wiring layer are required, and the sealing body and the intermediate solder ball between the substrates can be omitted, thereby saving the cost and simplifying the board. Packaging manufacturing process.
二、藉由將異方性導電膠膜填充在上下之基板間，可將基板電性導通，並且由於其柔軟性，可減少應力並提供適當的彈性緩衝之功效，使得在基板翹曲時不會影響電性連接。2. The substrate can be electrically connected by filling the anisotropic conductive film between the upper and lower substrates, and due to its softness, the stress can be reduced and the elastic buffering effect can be provided, so that the substrate is not warped. Will affect the electrical connection.
依據本發明之第一具體實施例，一種多基板堆疊之球格陣列封裝構造舉例說明於第2圖之截面示意圖。該球格陣列封裝構造200主要包含一第一基板210、至少一第一晶片220、一第一封膠體231、一第二基板240、一第二晶片250、一異方性導電膠層260以及複數個銲球270，其中該第一基板210與該第二基板240係為相互疊合，該第二晶片250係位於該第一基板210與該第二基板240之間並且被該異方性導電膠層260密封。According to a first embodiment of the present invention, a multi-substrate stacked ball grid array package structure is illustrated in a cross-sectional view of FIG. The ball grid array package structure 200 mainly includes a first substrate 210, at least one first wafer 220, a first encapsulant 231, a second substrate 240, a second wafer 250, an anisotropic conductive adhesive layer 260, and a plurality of solder balls 270, wherein the first substrate 210 and the second substrate 240 are overlapped with each other, and the second wafer 250 is located between the first substrate 210 and the second substrate 240 and is anisotropic The conductive adhesive layer 260 is sealed.
該第一基板210係具有一第一上表面211與一第一下表面212，其中該第一基板210之側邊係設有複數個由該第一 上表面211延伸到該第一下表面212之第一導通電極213。在本實施例中，該第一下表面212可即為該第一基板210之一第一核心層214之外露表面，以節省一層防焊材料。由於該第一下表面212係為在兩基板堆疊之間的內表面而被該異方性導電膠層260覆蓋，即使節省防焊層亦不會影響產品可靠度。該第一基板210係具有一層以上的線路層，可為硬質的印刷電路板或是軟質的電路薄膜。以該第一核心層214作為該第一基板210之一中心層，一般是玻璃纖維強化樹脂，選用的樹脂材質可為環氧樹脂(epoxy resin)、聚亞醯胺(polyimide)樹脂、BT(bismaleimide trazine)樹脂、FR4樹脂等。該些第一導通電極213之材質係可為銅、鎳、金或其他具有導電功能之材質，其係可具有開口橫向朝內之ㄇ形截面以夾附著該第一核心層214。具體而言，該些第一導通電極213係可等距地分散排列在該第一基板210之兩對應側邊或四周側邊。該些第一導通電極213係可利用基板表面電鍍或是夾具扣合的方式形成。The first substrate 210 has a first upper surface 211 and a first lower surface 212. The first substrate 210 has a plurality of sides defined by the first substrate 210. The upper surface 211 extends to the first conductive electrode 213 of the first lower surface 212. In this embodiment, the first lower surface 212 may be an exposed surface of the first core layer 214 of the first substrate 210 to save a layer of solder resist material. Since the first lower surface 212 is covered by the anisotropic conductive adhesive layer 260 on the inner surface between the two substrate stacks, the reliability of the product is not affected even if the solder resist layer is saved. The first substrate 210 has more than one circuit layer, and may be a hard printed circuit board or a soft circuit film. The first core layer 214 is used as a central layer of the first substrate 210, generally a glass fiber reinforced resin, and the selected resin material may be an epoxy resin, a polyimide resin, or a BT ( Bismaleimide trazine) resin, FR4 resin, and the like. The material of the first conductive electrodes 213 may be copper, nickel, gold or other conductive material, and may have a cross-shaped laterally inwardly-shaped cross section to sandwich the first core layer 214. Specifically, the first conductive electrodes 213 are equally spaced and arranged on the opposite sides or the peripheral sides of the first substrate 210. The first conductive electrodes 213 can be formed by plating the substrate surface or by clamping the clips.
此外，該第一基板210可另包含一第一防焊層215，其係形成於該第一核心層214之上表面。該第一防焊層215即是俗稱之「綠漆」(solder mask或可稱為solder resist)，為便於肉眼檢查，加入對眼睛有幫助的綠色或其它有色顏料於主漆中，綠漆以環氧樹脂及感光樹脂為主要組成份，主要塗佈於印刷電路板表面，以形成一遮覆線路層免於受外界水氣、污染物侵害之保護層。但該第一防焊層215不限定為綠色，亦可為黑色、紅色、藍色或其它任意顏色等。一般防焊 層油墨的塗佈方式大致可分為：網印(screen printing)、簾幕塗佈(curtain coating)、噴霧塗佈(spray coating)、滾輪塗佈(roller coating)等。通常一習知基板係包含有上下二層之防焊層。由於該異方性導電膠層260的覆蓋與該些第一導通電極213在基板側邊之設置，該第一基板210可以僅具有單一防焊層(即該第一防焊層215)在該第一上表面211，該第一基板210之該第一下表面212可省略防焊層與線路層。因此，可節省該第一基板210之成本。In addition, the first substrate 210 may further include a first solder resist layer 215 formed on the upper surface of the first core layer 214. The first solder resist layer 215 is commonly known as a "solder mask" or "solder resist". For the purpose of visual inspection, a green or other colored pigment which is helpful to the eyes is added to the main paint, and the green paint is The epoxy resin and the photosensitive resin are main components, and are mainly coated on the surface of the printed circuit board to form a protective layer covering the circuit layer from the external moisture and pollutants. However, the first solder resist layer 215 is not limited to green, and may be black, red, blue, or any other color. General anti-welding The coating method of the layer ink can be roughly classified into: screen printing, curtain coating, spray coating, roller coating, and the like. Generally, a conventional substrate includes a solder resist layer having two upper and lower layers. Since the covering of the anisotropic conductive adhesive layer 260 and the first conductive electrodes 213 are disposed on the side of the substrate, the first substrate 210 may have only a single solder resist layer (ie, the first solder resist layer 215). The first upper surface 211, the first lower surface 212 of the first substrate 210 may omit the solder resist layer and the wiring layer. Therefore, the cost of the first substrate 210 can be saved.
如第2圖所示，該第一晶片220係設於該第一基板210之該第一上表面211，可藉由傳統的黏晶或覆晶製程達到設置。在本實施例中，該第一晶片220之主動面係設有複數個第一銲墊221，並可利用複數個第一銲線281電性連接該些第一銲墊221至位在該第一基板210側邊之該些第一導通電極213，使該第一晶片220與該第一基板210電性互連。在本實施例中，該第一基板210之該第一上表面211可設有被該第一防焊層215所覆蓋之線路層，因此，在一變化例中，該些第一銲線281可不需要直接連接到該些第一導通電極213。此外，複數個第一晶片220係可往上堆疊設置，以達到較高之容量或達到較多之功能應用。As shown in FIG. 2, the first wafer 220 is disposed on the first upper surface 211 of the first substrate 210, and can be disposed by a conventional die bonding or flip chip process. In this embodiment, the active surface of the first wafer 220 is provided with a plurality of first pads 221, and the first pads 281 are electrically connected to the first pads 221 in the first The first conductive electrodes 213 on the side of the substrate 210 electrically interconnect the first wafer 220 and the first substrate 210. In this embodiment, the first upper surface 211 of the first substrate 210 may be provided with a circuit layer covered by the first solder resist layer 215. Therefore, in a variant, the first bonding wires 281 It may not be necessary to directly connect to the first conductive electrodes 213. In addition, a plurality of first wafers 220 can be stacked one on top of the other to achieve higher capacity or to achieve more functional applications.
該第一封膠體231係形成於該第一基板210之該第一上表面211，以密封該第一晶片220與該些第一銲線281，以提供適當之保護。該第一封膠體231係為一環氧模封化合物(epoxy molding compound,EMC)，其是以轉移成型(transfer molding)或稱壓模的技術加以形成，對熟習該 項技術者，該封膠體231亦可使用其他的注模製程。在本實施例中，該封膠體231係完全覆蓋該第一基板210之該第一上表面211。The first encapsulant 231 is formed on the first upper surface 211 of the first substrate 210 to seal the first wafer 220 and the first bonding wires 281 to provide proper protection. The first encapsulant 231 is an epoxy molding compound (EMC), which is formed by a technique of transfer molding or compression molding. The sealant 231 can also use other injection molding processes. In the embodiment, the encapsulant 231 completely covers the first upper surface 211 of the first substrate 210.
如第2圖所示，該第二基板240係具有一第二上表面241與一第二下表面242，該第二基板240係疊設於該第一基板210之下方，其中該第二基板240之側邊係設有複數個由該第二上表面241延伸到該第二下表面242之第二導通電極243，該第二下表面242係設有複數個陣列配置之球墊246。As shown in FIG. 2 , the second substrate 240 has a second upper surface 241 and a second lower surface 242 . The second substrate 240 is stacked under the first substrate 210 , wherein the second substrate The side of the 240 is provided with a plurality of second conductive electrodes 243 extending from the second upper surface 241 to the second lower surface 242. The second lower surface 242 is provided with a plurality of ball pads 246 arranged in an array.
具體而言，該第二基板240係具有一第二核心層244以及至少一第二防焊層245。該第二防焊層245係形成於該第二基板240之該第二下表面242並具有複數個開孔以顯露出該些球墊246。在本實施例中，另一第二防焊層245係形成於該第二基板240之該第二上表面241並具有複數個開孔以顯露出複數個位於該第二上表面241之連接墊247。該第二核心層244係作為該第二基板240之一基礎層，該第二防焊層245係為絕緣性材料，以形成一遮覆導電跡線之保護層。具體而言，該第一基板210與該第二基板240係可具有相同尺寸，以達到完全重疊。Specifically, the second substrate 240 has a second core layer 244 and at least one second solder resist layer 245. The second solder mask 245 is formed on the second lower surface 242 of the second substrate 240 and has a plurality of openings to expose the ball pads 246. In this embodiment, another second solder resist layer 245 is formed on the second upper surface 241 of the second substrate 240 and has a plurality of openings to expose a plurality of connection pads on the second upper surface 241. 247. The second core layer 244 is a base layer of the second substrate 240. The second solder resist layer 245 is an insulating material to form a protective layer covering the conductive traces. Specifically, the first substrate 210 and the second substrate 240 may have the same size to achieve complete overlap.
該第二晶片250係設於該第一基板210之該第一下表面212與該第二基板240之該第二上表面241之間。較佳地，該第二晶片250係可具有一背面251，其係貼附於該第一基板210之該第一核心層214。該背面251與該第一核心層214之間可不需要黏著層，以達到實質薄化並增進導散熱。在本實施例中，採用覆晶接合製程，該第二晶片250之一主動面 252則朝向該第二基板240之該第二上表面241，可利用複數個凸塊253而與該第二基板240的該些連接墊247作接合。該些凸塊253之材質可為金、鎳金、錫鉛或銅，可利用電鍍、無電鍍、打線、印刷或植接等方法形成。The second wafer 250 is disposed between the first lower surface 212 of the first substrate 210 and the second upper surface 241 of the second substrate 240. Preferably, the second wafer 250 can have a back surface 251 attached to the first core layer 214 of the first substrate 210. An adhesive layer may not be required between the back surface 251 and the first core layer 214 to achieve substantial thinning and enhance heat dissipation. In this embodiment, a flip chip bonding process is used, and one active surface of the second wafer 250 is used. 252 is opposite to the second upper surface 241 of the second substrate 240, and the plurality of bumps 253 are used to engage the connection pads 247 of the second substrate 240. The bumps 253 may be made of gold, nickel gold, tin-lead or copper, and may be formed by electroplating, electroless plating, wire bonding, printing or grafting.
該異方性導電膠層(Anisotropic Conductive Film,ACF)260係設於該第一基板210之該第一下表面212與該第二基板240之該第二上表面241之間，並可密封該第二晶片250。較佳地，該些第一導通電極213係可具有複數個突出於該第一下表面212之接觸表面213A，以利異方性導電接觸。在本實施例中，可利用該第一基板210在該第一下表面242的防焊層省略，以確保該些接觸表面213A突出於該第一下表面212。此外，該些第二導通電極243係可具有複數個外露於該第二上表面241之接觸表面243A，並與該些第一導通電極213之接觸表面213A在位置上為垂直對應。該異方性導電膠層260係包含複數個導電顆粒261，通常該些導電顆粒261係具有相等粒徑與適當均勻的散佈密度，在進行該第一基板210與該第二基板240堆疊時，其中至少一導電顆粒261係電性接觸在該些第一導通電極213與對應之該些第二導通電極243之間。即該些第一導通電極213之該些接觸表面213A與該些第二導通電極243之該些接觸表面213A間係填充有部分之該些導電顆粒261，以使該第一基板210與該第二基板240達到電性接觸的連通，故不會有直接焊接導致金屬擴散(metal diffusion)的問題。在本實施例中，該異方性導電膠層260 係實質覆蓋該第一基板210之該第一下表面212與該第二基板240之該第二上表面241。The anisotropic conductive film (ACF) 260 is disposed between the first lower surface 212 of the first substrate 210 and the second upper surface 241 of the second substrate 240, and can seal the The second wafer 250. Preferably, the first conductive electrodes 213 may have a plurality of contact surfaces 213A protruding from the first lower surface 212 to facilitate anisotropic conductive contact. In this embodiment, the solder resist layer of the first substrate 210 on the first lower surface 242 can be omitted to ensure that the contact surfaces 213A protrude from the first lower surface 212. In addition, the second conductive electrodes 243 may have a plurality of contact surfaces 243A exposed on the second upper surface 241 and vertically correspond to the contact surfaces 213A of the first conductive electrodes 213. The anisotropic conductive adhesive layer 260 includes a plurality of conductive particles 261. Generally, the conductive particles 261 have an equal particle diameter and a proper uniform dispersion density. When the first substrate 210 and the second substrate 240 are stacked, The at least one conductive particle 261 is electrically connected between the first conductive electrode 213 and the corresponding second conductive electrode 243. That is, the contact surfaces 213A of the first conductive electrodes 213 and the contact surfaces 213A of the second conductive electrodes 243 are filled with a portion of the conductive particles 261 to make the first substrate 210 and the first substrate 210 The two substrates 240 are in electrical contact, so there is no problem of direct metal welding resulting in metal diffusion. In this embodiment, the anisotropic conductive adhesive layer 260 The first lower surface 212 of the first substrate 210 and the second upper surface 241 of the second substrate 240 are substantially covered.
因此，該異方性導電膠層260係填滿在該第一基板210之該第一下表面212與該第二基板240之該第二上表面241之間的無晶片空隙。當進行熱循環試驗(thermal cycle test)或銲球270之設置等有加熱基板之動作時，而使該兩基板210與240的翹曲程度大致相近。又，該異方性導電膠層260可具有適當低之楊氏係數，可比該第一基板210與該第二基板240的楊氏係數更低，可減少應力並提供適當的彈性緩衝之功效。即使該第一基板210與該第二基板240發生翹曲時仍不會影響電性連接。Therefore, the anisotropic conductive adhesive layer 260 fills the wafer-free void between the first lower surface 212 of the first substrate 210 and the second upper surface 241 of the second substrate 240. When the operation of heating the substrate is performed by performing a thermal cycle test or a solder ball 270, the degree of warpage of the two substrates 210 and 240 is substantially similar. Moreover, the anisotropic conductive adhesive layer 260 can have a suitably low Young's modulus, can be lower than the Young's modulus of the first substrate 210 and the second substrate 240, can reduce stress and provide appropriate elastic buffering effect. Even when the first substrate 210 and the second substrate 240 are warped, the electrical connection is not affected.
該些銲球270係結合於該些球墊246。在不同實施例中，可利用錫膏、金屬球或金屬柱置換該些銲球270以供作為輸入端及/或輸出端，以使該球格陣列封裝構造200與外部印刷電路板形成電性連接關係。The solder balls 270 are bonded to the ball pads 246. In various embodiments, the solder balls 270 may be replaced with solder paste, metal balls or metal posts for use as inputs and/or outputs to electrically form the ball grid array package structure 200 with the external printed circuit board. Connection relationship.
因此，該第一基板210之該第一下表面212與該第二基板240之該第二上表面241之間僅需要至多一層之線路層與至多一層以覆蓋該線路層之防焊層(即第二防焊層245)並省略基板之間封膠體與中介銲球，以使該第二晶片250嵌埋在多基板之間的堆疊結構更為薄化，並可節省基板之成本與簡化封裝製造流程。換言之，本發明之多基板堆疊之球格陣列封裝構造200係將該第二晶片250嵌埋在兩疊合基板210與240之間，由該兩疊合基板210與240組合成一複合式積層基板，其中嵌埋該第二晶片250 的材料是選用該異方性導電膠層260。較佳地，在該兩疊合基板210與240組合之後並在該異方性導電膠層260完全固化之前可再灌入封膠材料，以減少該兩疊合基板210與240之間無電性接觸使用之導電顆粒261。其中可先利用周邊加熱或UV照射使該異方性導電膠層260為兩側邊固化，以固定在該些第一導通電極213與該些第二導通電極243之間的導電顆粒261。最後再以加熱方式使得該異方性導電膠層260與封膠材料完全固化。因此，在一較佳的實施例中，該異方性導電膠層260係包含封膠材料，即該異方性導電膠層260混有封膠材料，而使在第一基板210之該第一下表面212與該第二基板240之該第二上表面241之間的導電顆粒261的分散密度降低，相對低於在該些第一導通電極213與該些第二導通電極243之間的導電顆粒261的分散密度，以降低電性短路的風險並改變該異方性導電膠層260的性質，可調整變得更堅硬或具有其它的有益特性。Therefore, only one layer of the circuit layer and at most one layer between the first lower surface 212 of the first substrate 210 and the second upper surface 241 of the second substrate 240 are required to cover the solder resist layer of the circuit layer (ie, The second solder resist layer 245) omits the sealant and the intermediate solder ball between the substrates, so that the stack structure of the second wafer 250 embedded between the plurality of substrates is thinner, and the cost of the substrate can be saved and the package can be simplified. Manufacturing process. In other words, the multi-substrate stacked ball grid array package structure 200 of the present invention embeds the second wafer 250 between the two stacked substrates 210 and 240, and the two stacked substrates 210 and 240 are combined into a composite laminated substrate. Inserting the second wafer 250 The material is selected from the anisotropic conductive adhesive layer 260. Preferably, after the two stacked substrates 210 and 240 are combined and before the anisotropic conductive adhesive layer 260 is completely cured, the sealing material may be refilled to reduce the electrical continuity between the two laminated substrates 210 and 240. Contact conductive particles 261 for use. The anisotropic conductive adhesive layer 260 may be cured on both sides by peripheral heating or UV irradiation to fix the conductive particles 261 between the first conductive electrodes 213 and the second conductive electrodes 243. Finally, the anisotropic conductive adhesive layer 260 and the sealant material are completely cured by heating. Therefore, in a preferred embodiment, the anisotropic conductive adhesive layer 260 comprises a sealant material, that is, the anisotropic conductive adhesive layer 260 is mixed with a sealant material, so that the first substrate 210 is The dispersion density of the conductive particles 261 between the lower surface 212 and the second upper surface 241 of the second substrate 240 is lower than that between the first conductive electrodes 213 and the second conductive electrodes 243. The dispersion density of the conductive particles 261, to reduce the risk of electrical shorts and to change the properties of the anisotropic conductive adhesive layer 260, can be adjusted to become harder or have other beneficial properties.
依據本發明之第二具體實施例，另一種多基板堆疊之球格陣列封裝構造舉例說明於第3圖之截面示意圖。該球格陣列封裝構造300主要包含一第一基板210、至少一第一晶片220、一第一封膠體231、一第二基板240、一第二晶片250、一異方性導電膠層260以及複數個銲球270。其中與第一實施例相同的主要元件將以相同符號標示，故可以理解亦具有上述功效，不再予以贅述。According to a second embodiment of the present invention, another multi-substrate stacked ball grid array package configuration is illustrated in a cross-sectional view of FIG. The ball grid array package structure 300 mainly includes a first substrate 210, at least one first wafer 220, a first encapsulant 231, a second substrate 240, a second wafer 250, an anisotropic conductive adhesive layer 260, and A plurality of solder balls 270. The same elements as those in the first embodiment will be denoted by the same reference numerals, and it is understood that they have the above-mentioned effects and will not be described again.
該第一基板210之側邊係設有複數個由該第一上表面211延伸到該第一下表面212之第一導通電極213。該第二 基板240之側邊係設有複數個由該第二上表面241延伸到該第二下表面242之第二導通電極243，並以該異方性導電膠層260密封該第二晶片250並以其內含的導電顆粒電性接觸該些第一導通電極213與對應之該些第二導通電極243。在本實施例中，該些第二導通電極243之該些接觸表面243A係突出於該第二上表面241。此外，該第一基板210與該第二基板240皆有具有單一層之防焊層。更具體地，該第二基板240之該第二上表面241以及該第一基板210之該第一下表面212都不需要形成線路層也不需要覆蓋線路層之防焊層。在本實施例中達成晶片與基板的電性連接具體結構如下說明，該第二基板240係更具有一槽孔348，該槽孔348係貫穿過該第二核心層244與該第二防焊層245，該第二晶片250之該主動面252係設有複數個第二銲墊354，該些第二銲墊354係可為單排或多排排列在該第二晶片250之該主動面252之一中心線位置。該第二晶片250之該主動面252係貼附於該第二基板240之該第二上表面241，可利用習知黏晶方法進行晶片固著黏貼。該球格陣列封裝構造300另包含複數個第二銲線382，其係通過該第二基板240之該槽孔348以電性連接該第二晶片250之該些第二銲墊354至該第二基板240在該第二下表面242的複數個連接墊247，其中該些連接墊247可與該些球墊246形成於同一線路層。另以一第二封膠體332形成於該槽孔348內以密封該些第二銲線382。如上第一實施例所述，該異方性導 電膠層260可混有封膠材料。在本實施例中，第二封膠體332可與被混入的封膠材料為相同材質，以節省半導體封裝製程。A plurality of first conductive electrodes 213 extending from the first upper surface 211 to the first lower surface 212 are disposed on a side of the first substrate 210. The second The second side of the substrate 240 is provided with a plurality of second conductive electrodes 243 extending from the second upper surface 241 to the second lower surface 242, and the second wafer 250 is sealed by the anisotropic conductive adhesive layer 260. The conductive particles contained therein electrically contact the first conductive electrodes 213 and the corresponding second conductive electrodes 243. In this embodiment, the contact surfaces 243A of the second conductive electrodes 243 protrude from the second upper surface 241. In addition, the first substrate 210 and the second substrate 240 both have a single layer of solder resist layer. More specifically, the second upper surface 241 of the second substrate 240 and the first lower surface 212 of the first substrate 210 do not need to form a wiring layer or a solder resist layer covering the wiring layer. In the embodiment, the electrical connection between the wafer and the substrate is as follows. The second substrate 240 further has a slot 348 extending through the second core layer 244 and the second solder resist. The layer 245, the active surface 252 of the second wafer 250 is provided with a plurality of second pads 354, and the second pads 354 may be arranged in a single row or a plurality of rows on the active surface of the second wafer 250. One of the centerline locations of 252. The active surface 252 of the second wafer 250 is attached to the second upper surface 241 of the second substrate 240, and the wafer can be adhered by a conventional die bonding method. The ball grid array structure 300 further includes a plurality of second bonding wires 382 electrically connected to the second pads 354 of the second wafer 250 through the slots 348 of the second substrate 240 to the first The plurality of connection pads 247 of the second substrate 240 are disposed on the second lower surface 242, wherein the connection pads 247 are formed on the same circuit layer as the ball pads 246. A second sealing body 332 is formed in the slot 348 to seal the second bonding wires 382. As described in the first embodiment, the anisotropy The glue layer 260 can be mixed with a sealant material. In this embodiment, the second encapsulant 332 can be the same material as the encapsulating material to be mixed to save the semiconductor packaging process.
因此，該第二晶片250亦可以打線方式形成並能與該第二基板240達成電性連接。並透過該些第一導通電極213與該些第二導通電極243達成該第一基板210與該第二基板240之電性導通，該第二基板240之該第二上表面241以及該第一基板210之該第一下表面212都不需形成線路層與覆蓋線路層之防焊層(即該第一基板210與第二基板240僅需具有一層防焊層與一層線路層)，並可使該第二晶片250嵌埋在多基板之間的堆疊結構更為薄化，可節省成本與減少基板之製程。Therefore, the second wafer 250 can also be formed in a wire bonding manner and can be electrically connected to the second substrate 240. And electrically connecting the first substrate 210 and the second substrate 240 through the first conductive electrodes 213 and the second conductive electrodes 243, the second upper surface 241 of the second substrate 240 and the first The first lower surface 212 of the substrate 210 does not need to form a solder resist layer of the circuit layer and the cover circuit layer (ie, the first substrate 210 and the second substrate 240 only need to have a solder resist layer and a layer of circuit layer), and The stack structure in which the second wafer 250 is embedded between the plurality of substrates is thinner, which can save cost and reduce the process of the substrate.
此外，該第二晶片250之該背面251可不貼附該第一基板210之該第一下表面212，而由該異方性導電膠層260填充並完全覆蓋該背面251與該第一下表面212，以密封該第二晶片250。其中，該背面251與該第一下表面212之間隙可大於該些導電顆粒261之球徑也大於該些第一導通電極213與該些第二導通電極243之間隙，以防止該些導電顆粒261壓觸該第二晶片250並有助於非用以電性接觸的多餘導電顆粒261的排出。In addition, the back surface 251 of the second wafer 250 may not be attached to the first lower surface 212 of the first substrate 210, and the anisotropic conductive adhesive layer 260 is filled and completely covers the back surface 251 and the first lower surface. 212 to seal the second wafer 250. The gap between the back surface 251 and the first lower surface 212 may be larger than the gap between the conductive particles 261 and the gap between the first conductive electrodes 213 and the second conductive electrodes 243 to prevent the conductive particles. The 261 is pressed against the second wafer 250 and facilitates the discharge of excess conductive particles 261 that are not electrically contacted.
依據本發明之第三具體實施例，另一種多基板堆疊之球格陣列封裝構造舉例說明於第4圖之截面示意圖。該球格陣列封裝構造400主要包含一第一基板210、至少一第一晶片220、一第一封膠體231、一第二基板240、一第二晶片250、 一異方性導電膠層260以及複數個銲球270。其中與第一實施例相同的主要元件將以相同符號標示，不再予以贅述。In accordance with a third embodiment of the present invention, another multi-substrate stacked ball grid array package configuration is illustrated in cross-sectional view in FIG. The ball grid array package structure 400 mainly includes a first substrate 210, at least one first wafer 220, a first encapsulant 231, a second substrate 240, and a second wafer 250. An anisotropic conductive adhesive layer 260 and a plurality of solder balls 270. The same elements as those in the first embodiment will be designated by the same reference numerals and will not be described again.
在本實施例中，該第一基板210係具有上下二層之第一防焊層215，亦具有上下二層之線路層。而該第二基板240可具有單一防焊層，即只有第二防焊層245形成在該第二基板240之下表面。上層與下層之第一防焊層215係各具有多個開口，以分別顯露出複數個位於該第一上表面211之第一上連接墊416與複數個位於該第一下表面212之第一下連接墊417。In the embodiment, the first substrate 210 has a first solder resist layer 215 of two upper and lower layers, and also has a circuit layer of two upper and lower layers. The second substrate 240 may have a single solder resist layer, that is, only the second solder resist layer 245 is formed on the lower surface of the second substrate 240. The upper and lower first solder resist layers 215 each have a plurality of openings to respectively expose a plurality of first upper connection pads 416 on the first upper surface 211 and a plurality of first ones on the first lower surface 212 Lower connection pad 417.
其中之一的該些第一晶片220具有複數個凸塊422，以覆晶接合至該第一基板210之該些第一上連接墊416。該第二晶片250係覆晶接合至該第一基板210，該第二晶片250之該背面251係可利用一黏晶層490黏貼在該第二基板240之該第二核心層244，並利用複數個凸塊253而使該第二晶片250覆晶接合至該第一基板210之該些第一下連接墊417。並透過該些第一導通電極213、該些第二導通電極243以及該異方性導電膠層260之導電顆粒261，以使該第一基板210與該第二基板240達成電性連接。The first wafers 220 of the first substrate 220 have a plurality of bumps 422 for flip-chip bonding to the first upper connection pads 416 of the first substrate 210. The second wafer 250 is flip-chip bonded to the first substrate 210. The back surface 251 of the second wafer 250 can be adhered to the second core layer 244 of the second substrate 240 by using a bonding layer 490, and utilized. The plurality of bumps 253 are used to flip-chip the second wafer 250 to the first lower connection pads 417 of the first substrate 210. The first conductive substrate 213, the second conductive electrodes 243, and the conductive particles 261 of the anisotropic conductive adhesive layer 260 are electrically connected to the first substrate 210 and the second substrate 240.
因此，該第二基板240可省略製作在該第二上表面241之防焊層與線路層，該第二上表面241係可即為該第二基板240之該第二核心層244之外露表面，具有降低基板成本與封裝薄化的功效。Therefore, the second substrate 240 can omit the solder resist layer and the circuit layer formed on the second upper surface 241, and the second upper surface 241 can be the exposed surface of the second core layer 244 of the second substrate 240. It has the effect of reducing the cost of the substrate and thinning the package.
總而言之，本發明可以達成在第一基板之第一下表 面與第二基板之第二上表面之間的間隙縮小、晶片嵌埋、元件減少與翹曲度差異縮小之功效，以使晶片嵌埋在多基板之間的堆疊結構更為薄化，並可節省成本與提高可靠度。In summary, the present invention can achieve the first table on the first substrate The gap between the surface and the second upper surface of the second substrate is reduced, the wafer is embedded, the component is reduced, and the difference in warpage is reduced, so that the stacked structure in which the wafer is embedded between the plurality of substrates is thinner, and Save costs and increase reliability.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，本發明技術方案範圍當依所附申請專利範圍為準。任何熟悉本專業的技術人員可利用上述揭示的技術內容作出些許更動或修飾為等同變化的等效實施例，但凡是未脫離本發明技術方案的內容，依據本發明的技術實質對以上實施例所作的任何簡單修改、等同變化與修飾，均仍屬於本發明技術方案的範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention.
100‧‧‧球格陣列封裝構造100‧‧‧Spherical Array Encapsulation Construction
101‧‧‧第一半導體封裝件101‧‧‧First semiconductor package
102‧‧‧第二半導體封裝件102‧‧‧Second semiconductor package
110‧‧‧第一基板110‧‧‧First substrate
111‧‧‧第一上表面111‧‧‧First upper surface
112‧‧‧第一下表面112‧‧‧First lower surface
114‧‧‧第一核心層114‧‧‧First core layer
115‧‧‧第一防焊層115‧‧‧First solder mask
116‧‧‧第一球墊116‧‧‧First ball mat
117‧‧‧第一連接墊117‧‧‧First connection pad
120‧‧‧第一晶片120‧‧‧First chip
121‧‧‧第一銲墊121‧‧‧First pad
131‧‧‧第一封膠體131‧‧‧First gel
132‧‧‧第二封膠體132‧‧‧Second seal
140‧‧‧第二基板140‧‧‧second substrate
141‧‧‧第二上表面141‧‧‧Second upper surface
142‧‧‧第二下表面142‧‧‧Second lower surface
144‧‧‧第二核心層144‧‧‧ second core layer
145‧‧‧第二防焊層145‧‧‧Second solder mask
146‧‧‧第二球墊146‧‧‧second ball mat
147‧‧‧第二轉接墊147‧‧‧Second transfer pad
150‧‧‧第二晶片150‧‧‧second chip
153‧‧‧第二銲墊153‧‧‧Second pad
160‧‧‧中介銲球160‧‧‧Intermediate solder balls
170‧‧‧外接銲球170‧‧‧External solder balls
181‧‧‧第一銲線181‧‧‧First wire bond
182‧‧‧第二銲線182‧‧‧second welding line
200‧‧‧球格陣列封裝構造200‧‧‧Spherical Array Encapsulation Construction
210‧‧‧第一基板210‧‧‧First substrate
211‧‧‧第一上表面211‧‧‧ first upper surface
212‧‧‧第一下表面212‧‧‧First lower surface
213‧‧‧第一導通電極213‧‧‧First conduction electrode
213A‧‧‧接觸表面213A‧‧‧ contact surface
214‧‧‧第一核心層214‧‧‧ first core layer
215‧‧‧第一防焊層215‧‧‧First solder mask
220‧‧‧第一晶片220‧‧‧First chip
221‧‧‧第一銲墊221‧‧‧First pad
231‧‧‧第一封膠體231‧‧‧First gel
240‧‧‧第二基板240‧‧‧second substrate
241‧‧‧第二上表面241‧‧‧Second upper surface
242‧‧‧第二下表面242‧‧‧Second lower surface
243‧‧‧第二導通電極243‧‧‧Second conduction electrode
243A‧‧‧接觸表面243A‧‧‧ contact surface
244‧‧‧第二核心層244‧‧‧ second core layer
245‧‧‧第二防焊層245‧‧‧Second solder mask
246‧‧‧球墊246‧‧‧ ball mat
247‧‧‧連接墊247‧‧‧Connecting mat
250‧‧‧第二晶片250‧‧‧second chip
251‧‧‧背面251‧‧‧ back
252‧‧‧主動面252‧‧‧ active face
253‧‧‧凸塊253‧‧‧Bumps
260‧‧‧異方性導電膠層260‧‧‧ anisotropic conductive adhesive layer
261‧‧‧導電顆粒261‧‧‧Electrical particles
270‧‧‧銲球270‧‧‧ solder balls
281‧‧‧第一銲線281‧‧‧First wire bond
300‧‧‧球格陣列封裝構造300‧‧‧Spherical Array Encapsulation Construction
332‧‧‧第二封膠體332‧‧‧Second seal
348‧‧‧槽孔348‧‧‧Slots
354‧‧‧第二銲墊354‧‧‧Second pad
382‧‧‧第二銲線382‧‧‧second welding line
400‧‧‧球格陣列封裝構造400‧‧‧Spherical Array Encapsulation Construction
416‧‧‧第一上連接墊416‧‧‧First upper connection pad
417‧‧‧第一下連接墊417‧‧‧First lower connection pad
422‧‧‧凸塊422‧‧‧Bumps
490‧‧‧黏晶層490‧‧‧Mastic layer
第1圖：習知球格陣列封裝構造之截面示意圖。Figure 1: Schematic cross-sectional view of a conventional ball grid array package structure.
第2圖：依據本發明第一具體實施例的一種多基板堆疊之球格陣列封裝構造之截面示意圖。2 is a cross-sectional view showing a multi-substrate stacked ball grid array package structure according to a first embodiment of the present invention.
第3圖：依據本發明第二具體實施例的另一種多基板堆疊之球格陣列封裝構造之截面示意圖。Figure 3 is a cross-sectional view showing another multi-substrate stacked ball grid array package structure in accordance with a second embodiment of the present invention.
第4圖：依據本發明第三具體實施例的另一種多基板堆疊之球格陣列封裝構造之截面示意圖。4 is a cross-sectional view showing another multi-substrate stacked ball grid array package structure in accordance with a third embodiment of the present invention.
200‧‧‧球格陣列封裝構造200‧‧‧Spherical Array Encapsulation Construction
210‧‧‧第一基板210‧‧‧First substrate
211‧‧‧第一上表面211‧‧‧ first upper surface
212‧‧‧第一下表面212‧‧‧First lower surface
213‧‧‧第一導通電極213‧‧‧First conduction electrode
213A‧‧‧接觸表面213A‧‧‧ contact surface
214‧‧‧第一核心層214‧‧‧ first core layer
215‧‧‧第一防焊層215‧‧‧First solder mask
220‧‧‧第一晶片220‧‧‧First chip
221‧‧‧第一銲墊221‧‧‧First pad
231‧‧‧第一封膠體231‧‧‧First gel
240‧‧‧第二基板240‧‧‧second substrate
241‧‧‧第二上表面241‧‧‧Second upper surface
242‧‧‧第二下表面242‧‧‧Second lower surface
243‧‧‧第二導通電極243‧‧‧Second conduction electrode
243A‧‧‧接觸表面243A‧‧‧ contact surface
244‧‧‧第二核心層244‧‧‧ second core layer
245‧‧‧第二防焊層245‧‧‧Second solder mask
246‧‧‧球墊246‧‧‧ ball mat
247‧‧‧連接墊247‧‧‧Connecting mat
250‧‧‧第二晶片250‧‧‧second chip
251‧‧‧背面251‧‧‧ back
252‧‧‧主動面252‧‧‧ active face
253‧‧‧凸塊253‧‧‧Bumps
260‧‧‧異方性導電膠層260‧‧‧ anisotropic conductive adhesive layer
261‧‧‧導電顆粒261‧‧‧Electrical particles
270‧‧‧銲球270‧‧‧ solder balls
281‧‧‧第一銲線281‧‧‧First wire bond
Claims (16)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097127224A TWI394259B (en) | 2008-07-17 | 2008-07-17 | Bga package stacked with multiple substrates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW097127224A TWI394259B (en) | 2008-07-17 | 2008-07-17 | Bga package stacked with multiple substrates |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201005913A TW201005913A (en) | 2010-02-01 |
| TWI394259B true TWI394259B (en) | 2013-04-21 |
Family
ID=44826476
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW097127224A TWI394259B (en) | 2008-07-17 | 2008-07-17 | Bga package stacked with multiple substrates |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI394259B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101640078B1 (en) * | 2014-10-08 | 2016-07-15 | 앰코 테크놀로지 코리아 주식회사 | Package on package and method for manufacturing the same |
| TWI620258B (en) * | 2017-03-09 | 2018-04-01 | 力成科技股份有限公司 | Package structure and manufacturing process thereof |
| CN114660844A (en) * | 2020-12-22 | 2022-06-24 | 群创光电股份有限公司 | Electronic device and method for manufacturing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213427A (en) * | 1995-02-07 | 1996-08-20 | Sharp Corp | Semiconductor chip and multi-chip semiconductor module |
| JP2001156245A (en) * | 1999-11-25 | 2001-06-08 | Seiko Epson Corp | Semiconductor device |
| JP2002368189A (en) * | 2001-06-11 | 2002-12-20 | Oki Electric Ind Co Ltd | Semiconductor-stacked package and method for manufacturing the same |
| JP2003204135A (en) * | 2002-09-20 | 2003-07-18 | Canon Inc | Multichip module and display panel |
| JP2003249606A (en) * | 2002-02-25 | 2003-09-05 | Sony Corp | Semiconductor device and interposer |
-
2008
- 2008-07-17 TW TW097127224A patent/TWI394259B/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08213427A (en) * | 1995-02-07 | 1996-08-20 | Sharp Corp | Semiconductor chip and multi-chip semiconductor module |
| JP2001156245A (en) * | 1999-11-25 | 2001-06-08 | Seiko Epson Corp | Semiconductor device |
| JP2002368189A (en) * | 2001-06-11 | 2002-12-20 | Oki Electric Ind Co Ltd | Semiconductor-stacked package and method for manufacturing the same |
| JP2003249606A (en) * | 2002-02-25 | 2003-09-05 | Sony Corp | Semiconductor device and interposer |
| JP2003204135A (en) * | 2002-09-20 | 2003-07-18 | Canon Inc | Multichip module and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201005913A (en) | 2010-02-01 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |