CN101562169A - Lamination type base plate and chip packaging structure using same - Google Patents
Lamination type base plate and chip packaging structure using same Download PDFInfo
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- CN101562169A CN101562169A CNA2008100937023A CN200810093702A CN101562169A CN 101562169 A CN101562169 A CN 101562169A CN A2008100937023 A CNA2008100937023 A CN A2008100937023A CN 200810093702 A CN200810093702 A CN 200810093702A CN 101562169 A CN101562169 A CN 101562169A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
The invention discloses a lamination type base plate which mainly comprises a core layer. The upper surface and the lower surface of the core layer are sequentially formed into a metal layer and a welding and covering layer, wherein the two welding and covering layers on the different surfaces are provided with different thermal expansion coefficients, and a correction for warpage for repelling thermal stress under the change of temperature is generated by means of the difference of the different thermal expansion coefficients of the upper welding and covering layer and the lower welding and covering layer so as to restrain the wrapping degree of the base plate. The invention also discloses a chip packaging structure using the lamination type base plate, comprising the lamination type base plate, a chip, two or more electrically connected elements and an adhesive body, therefore, the base plate can be manufactured with lower cost and can achieve the effect of restraining the wrapping degree of the base plate in the chip packaging process under the condition of not adding additional stiffening elements and not changing the thickness of the base plate.
Description
Technical field
The present invention is relevant for a kind of printed circuit board (PCB), can apply to the semiconductor die package structure, particularly relevant for a kind of lamination type substrate (laminate substrate) and the chip encapsulation construction that uses this substrate.
Background technology
In recent years, printed circuit board (PCB) develops into microminiature lamination formula substrate toward densification and high-effectization, with the chip carrier as semiconductor packages.So in known semiconductor packaging process,, should be formed on the substrate gluing brilliant colloid, and make the heat treatment of substrate by prebake conditions for chip being arranged on the substrate.In addition, substrate may meet with various heat treatments in the semiconductor packaging process, for example, and baking-curing, projection reflow or curing of sealed colloid or the like after the sticking brilliant colloid.Yet, substrate is when bearing heat treated variations in temperature, and the unmatched problem of the thermal coefficient of expansion of (as adhesive body and chip) between other encapsulating material (CTE, coefficient ofthermal expansion) can cause the substrate warp distortion, thereby causes operational difficulty.
Known a kind of substrate 100 that is used for semiconductor packages is as shown in Figure 1 made in lamination (laminate) mode, mainly comprises core layer 110, the first metal layer 120, second metal level 130, first welding cover layer 140 and second welding cover layer 150.This core layer 110 is a kind of glass fiber-reinforced resin and as the central core of this substrate 100.Symmetrically, the lower surface pressing the first metal layer 120 of this core layer 110, upper surface pressing second metal level 130 of this core layer 110.These the first metal layers 120, second metal level 130 can be copper (copper) layer, to form most bar conductive traces (conductive trace).More symmetrically, upper surface is respectively laid first welding cover layer 140 and second welding cover layer 150 under the outermost layer of this substrate 100.The thickness of these first welding cover layers 140 and second welding cover layer 150 is generally identical; and its material is the insulating properties material with same coefficient of thermal expansion; cover the protective layer of conductive trace with formation; but manifest two or more outer connection pads 121 with two or more in connect fingers (finger) 131, do usefulness follow-up and conducting element such as soldered ball (solder ball) or bonding wire (bonding wire) electric connection to stay.Because the laminated substrate of known substrate 100, so substrate warp and to influence the problem of Chip Packaging operation still not obvious for having the symmetrical number of plies.
Again as shown in Figure 1, in chip package process, electronic component such as semiconductor chip 11 can be arranged at the upper surface of this substrate 100 by the stickup of sticking crystal layer 12, the active surface of this chip 11 has two or more weld pads 11A, can utilize two or more to electrically connect elements 13 (for example routing form bonding wire) and electrically connect these weld pads 11A and connect to these of this substrate 100 and refer to 131, make this chip 11 and these substrate 100 electrical interconnects.Afterwards; be arranged at the upper surface of this substrate 100 with pressing mold or some glue mode with adhesive body 14; electrically connect element 13 to seal this chip 11 with these; suitable protection is provided; be arranged at the lower surface of this substrate 100 again with two or more external terminals 15 (common is soldered ball), to form the chip encapsulation construction of ball grid array form.
Yet, the processing of heated substrates 100 is all arranged in the setting of the curing (curing) of the stickup of above-mentioned sticking crystal layer 12, adhesive body 14, external terminal 15 or subsequent thermal cyclic test (thermal cycle test) etc.In the time of may difference being arranged with the thermal coefficient of expansion of this substrate 100 or have the thermal expansion coefficient difference of other encapsulating material owing to the thermal coefficient of expansion that should glue crystal layer 12, have the imbalance of thermal stress, in chip package process so the substrate warp problem is easily arranged.Particularly should be pre-formed when this substrate 100 by sticking crystal layer 12, the volume contraction of this sticking crystal layer 12 can cause the imbalance of these substrate 100 levels stress and warpage, and the decrease in yield that the warpage of this substrate 100 before packaging technology can cause Chip Packaging to make.
Summary of the invention
Main purpose of the present invention is the chip encapsulation construction that a kind of lamination type substrate is provided and uses this substrate, can be issued to the effect that suppresses substrate warp in chip package process with the condition that changes substrate thickness not needing to increase additional stiffening elements.
The object of the invention to solve the technical problems realizes by the following technical solutions.A kind of lamination type substrate according to the present invention comprises core layer, the first metal layer, second metal level, first welding cover layer, second welding cover layer.This core layer has first surface and second surface.This first metal layer is formed at this first surface of this core layer.This second metal level is formed at this second surface of this core layer.This first welding cover layer is formed at this first surface of this core layer and covers this first metal layer.This second welding cover layer is formed at this second surface of this core layer and covers this second metal level.Wherein, this first welding cover layer and this second welding cover layer have roughly the same thickness, and this first welding cover layer and this second welding cover layer have thermal coefficient of expansion inequality, to reduce the angularity of this lamination type substrate.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
In aforesaid lamination type substrate, can include sticking crystal layer in addition, its part is covered on this second welding cover layer.
In aforesaid lamination type substrate, the thermal coefficient of expansion of this first welding cover layer is less than the thermal coefficient of expansion of this second welding cover layer.
In aforesaid lamination type substrate, the thermal coefficient of expansion of this first welding cover layer is greater than the thermal coefficient of expansion of this second welding cover layer.
In aforesaid lamination type substrate, it can have through hole, and it runs through this first welding cover layer, this first metal layer, this core layer, this second metal level and this second welding cover layer.
In aforesaid lamination type substrate, this first metal layer can be line layer and is connected with two or more outer connection pads.
In aforesaid lamination type substrate, this second metal level can be line layer and is connected with and connects finger in two or more.
In aforesaid lamination type substrate, this second metal level can be void and puts copper foil layer.
The present invention also provides a kind of chip encapsulation construction that uses the lamination type substrate, and it comprises:
The lamination type substrate comprises:
Core layer, it has first surface and second surface;
The first metal layer, it is formed at this first surface of this core layer;
Second metal level, it is formed at this second surface of this core layer;
First welding cover layer, it is formed at this first surface of this core layer and covers this first metal layer; And
Second welding cover layer, it is formed at this second surface of this core layer and covers this second metal level;
This first welding cover layer and this second welding cover layer have roughly the same thickness, and this first welding cover layer and this second welding cover layer have thermal coefficient of expansion inequality, to reduce the angularity of this lamination type substrate;
Chip, it is arranged at the upper surface of this second welding cover layer;
Two or more electrically connect element, electrically connect the first metal layer of this chip to this substrate; And
Adhesive body, it is arranged on the upper surface of this second welding cover layer of this substrate, to seal this chip.
Lamination type substrate of the present invention and the chip encapsulation construction that uses this substrate are laid in the upper and lower surface of substrate so as to the welding cover layer of different heat expansion coefficient, produce the thermal stress of contending with each other under variations in temperature, to suppress substrate warp.Therefore, this substrate can hang down manufacturing cost, can be issued to the effect that suppresses substrate warp in chip package process in the condition that does not need to increase additional stiffening elements and change substrate thickness.
Description of drawings
Fig. 1 is the known schematic cross-section that applies to the lamination type substrate of semiconductor die package;
Fig. 2 is the schematic cross-section according to the lamination type substrate of first specific embodiment of the present invention;
Fig. 3 is the schematic cross-section according to the chip encapsulation construction of this substrate of use of first specific embodiment of the present invention;
Fig. 4 is the schematic cross-section according to the lamination type substrate of second specific embodiment of the present invention;
Fig. 5 is the schematic cross-section according to the chip encapsulation construction of this substrate of use of second specific embodiment of the present invention.
Description of reference numerals
11 chip 11A weld pads, 12 sticking crystal layers
13 electrically connect element 14 adhesive bodies 15 external terminals
100 substrates, 110 core layers
120 the first metal layers, 121 outer connection pads
Connect finger in 130 second metal levels 131
140 first welding cover layers, 150 second welding cover layers
21 chip 21A weld pads
23 electrically connect element 24 adhesive bodies 25 external terminals
200 substrates, 210 core layers, 211 first surfaces
212 second surfaces
220 the first metal layers, 221 outer connection pads
Connect finger in 230 second metal levels 231
240 first welding cover layers, 250 second welding cover layers, 260 sticking crystal layers
300 substrates, 301 through holes
310 core layers, 311 first surfaces, 312 second surfaces
Connect finger in 320 the first metal layers, the 321 outer connection pads 322
330 second metal levels
340 first welding cover layers, 350 second welding cover layers, 360 sticking crystal layers
31 chip 31A weld pads
33 electrically connect element 34 adhesive bodies 35 external terminals
Embodiment
According to first specific embodiment of the present invention, the chip encapsulation construction that specifically discloses a kind of lamination type substrate and use this substrate.
See also shown in Figure 2ly, a kind of lamination type substrate 200 according to the present invention comprises core layer 210, the first metal layer 220, second metal level 230, first welding cover layer 240, second welding cover layer 250.This core layer 210 has first surface 211 and second surface 212.The making principle of general lamination type substrate 200 is to be basic unit with this core layer 210, and form these the first metal layers 220 in regular turn on the surface of this core layer 210, second metal level 230 and these first welding cover layers 240, second welding cover layer 250.In other embodiments, can suitably increase the number of inner lamination or outside lamination, so as to making things convenient for the layout of circuit.So this core layer 210 is as the central core of this substrate 200, it generally is glass fiber-reinforced resin, the resin material of selecting for use can be epoxy resin (epoxy resin), pi (polyimide) resin, Bismaleimide Triazine (BT, bismaleimide triazine) resin, FR4 resin etc.This first metal layer 220 is formed at this first surface 211 of this core layer 210.This second metal level 230 is formed at this second surface 212 of this core layer 210.This first metal layer 220 can be copper (copper) layer with this second metal level 230, make the copper layer through exposure (exposing), develop (developing), etching technologies such as (etching) and patterning (patterning) to be to form multi-conducting trace (conductive trace).
This first welding cover layer 240 is formed at this first surface 211 of this core layer 210 and covers this first metal layer 220.This second welding cover layer 250 is formed at this second surface 212 of this core layer 210 and covers this second metal level 230.These first welding cover layers 240 and second welding cover layer 250 promptly are " green lacquer " (Solder mask or the Solder Resist) that is commonly called as; it also is anti-welding lacquer; for ease of visual inspection; adding to the helpful viridine green of eyes in main lacquer; green lacquer is main constituent with epoxy resin and photosensitive resin; mainly coat printed circuit board surface, cover the protective layer that conductive trace avoids being subjected to extraneous aqueous vapor, pollutant infringement with formation.But these first welding cover layers 240 and second welding cover layer 250 do not limit green, can be black, redness, blueness or other random color etc. yet.The coating method of general welding cover layer printing ink is broadly divided into: wire mark (screen printing), heavy curtain coating (curtain coating), spraying coating (spray coating), roller coating (roller coating) etc.But pressing epoxy resin dry film or the utilization coating of deposition ring epoxy resins liquid film and hardening process are to form this first welding cover layer 240 and this second welding cover layer 250.Wherein, this first welding cover layer 240 has roughly the same thickness with this second welding cover layer 250, and this first welding cover layer 240 has thermal coefficient of expansion inequality with this second welding cover layer 250, to reduce the angularity of this lamination type substrate 200.
In the present embodiment, this substrate 200 can include sticking crystal layer 260 in addition, and its part is covered on this second welding cover layer 250, can be used as the usefulness of follow-up stickup chip.Preferably, the material of this sticking crystal layer 260 can be selected from the sticking brilliant material that B rank colloid or other can multistage curing, can be pre-formed on this substrate 200 before chip package process or in the operation in early stage.In different embodiment, the material of this sticking crystal layer 260 also can be selected the adhesive tape on non-B rank or viscous gel or the like for use.
In general, to the substrate warp degree, can obtain the thermal stress balance of appropriateness at coefficients of expansion such as chip, substrate, soldered ball, sticking crystal layer, adhesive bodies by this first welding cover layer 240 and the difference of thermal expansion coefficient of this second welding cover layer 250.As shown in Figure 2, in the present embodiment, thermal coefficient of expansion that should sticking crystal layer 260 is less than this second welding cover layer 250, and the thermal coefficient of expansion of this first welding cover layer 240 can be less than the thermal coefficient of expansion of this second welding cover layer 250, with the thermal stress counterbalance effect of the upper and lower surface that obtains this core layer 210.In different embodiment, the thermal coefficient of expansion of this first welding cover layer 240 also can be greater than the thermal coefficient of expansion of this second welding cover layer 250.By first welding cover layer 240 and the upper and lower surface that second welding cover layer 250 is laid in this substrate 200 of control different heat expansion coefficient, the thermal stress that generation contends with each other under variations in temperature suppressing this substrate 200 warpages, but can not change the thickness of this substrate 200.Be the thermal coefficient of expansion of realizing this first welding cover layer 240 in the present embodiment thermal coefficient of expansion less than this second welding cover layer 250.About the determining method of this first welding cover layer 240 with the thermal coefficient of expansion of this second welding cover layer 250, can be computer-aided engineering analysis software by ANSYS software, utilize finite element method (FEM) (FEM, Finite element method) finds the solution, suitably adjust the thermal coefficient of expansion of this sticking crystal layer 260, this first welding cover layer 240 and this second welding cover layer 250, make these substrate 200 upper and lower surfaces produce the thermal stress of contending with each other, to suppress these substrate 200 warpages in the chip package process.And in general, the thermal coefficient of expansion of welding cover layer is 60～160ppm/ ℃, and the thermal coefficient of expansion of core layer is 16ppm/ ℃, and the thermal coefficient of expansion of metal level is 16ppm/ ℃.Noticeable, can be by energy dissipation spectrometer (EDS, energy dispersive spectrograph), ion microprobe (SIMS, secondary ion mass spectrometer), FTIS (FTIR, fouriertransform infrared spectroscopy) or thermomechanical analyzer (TMA, thermal mechanicalanalyzer), cooperate color to distinguish and judge the material and the thermal coefficient of expansion of this first welding cover layer 240 and this second welding cover layer 250, to choose the making that suitable welding cover layer carries out this substrate 200.
Particularly, this first metal layer 220 can be line layer and is connected with two or more outer connection pads 221.This second metal level 230 can be line layer and is connected with to connect in two or more and refers to 231.This first welding cover layer 240 and this second welding cover layer 250 respectively have a plurality of openings and connect finger 231 to manifest in two or more that these outer connection pads 221 of forming on this first metal layer 220 and this second metal level 230 form.
When carrying out follow-up chip package process, as shown in Figure 3, semiconductor chip 21 is by the stickup of this sticking crystal layer 260 and stick on the upper surface of second welding cover layer 250, the active surface of this chip 21 has two or more weld pads 21A, can utilize two or more these weld pads 21A that electrically connect element 23 these chips 21 of connection to this second metal level 230, to connect finger 231, make this chip 21 and these substrate 200 electrical interconnects.In the present embodiment, these electrically connect the bonding wire that element 23 forms for routing.Afterwards; with adhesive body 24 with pressing mold or some glue mode; be arranged at the upper surface of second welding cover layer 250 of this substrate 200; electrically connect element 23 to seal this chip 21 with these; suitable protection is provided; this chip 21 is arranged at these outer connection pads 221 of this first metal layer 220 again with two or more external terminals 25, so that must be realized electrical connection with external printed circuit board (PCB, printed circuit board).In this example, these external terminals 25 comprise two or more soldered balls.
Under the setting or subsequent thermal cyclic test equitemperature changing environment of the curing of the stickup of gluing crystal layer 260, adhesive body 24, external terminal 25, no matter this substrate 200 is at the state of cooling or heated condition, this first welding cover layer 240 provides the warpage correction with both difference value of the thermal coefficient of expansion of this second welding cover layer 250, whereby, can make this substrate 200 keep dimensionally stable, in chip package process, not be subjected to influence of temperature change and warpage.For example, when the thermal coefficient of expansion of this sticking crystal layer 260 during less than this second welding cover layer 250, the thermal coefficient of expansion of this first welding cover layer 240 should reach the balance up and down of thermal stress less than the thermal coefficient of expansion of this second welding cover layer 250.
Second specific embodiment of the present invention discloses another kind of lamination type substrate.See also shown in Figure 4ly, this lamination type substrate 300 mainly comprises core layer 310, the first metal layer 320, second metal level 330, first welding cover layer 340, second welding cover layer 350.This core layer 310 has first surface 311 and second surface 312.This first metal layer 320 is formed at this first surface 311 of this core layer 310.This second metal level 330 is formed at this second surface 312 of this core layer 310.This first welding cover layer 340 is formed at this first surface 311 of this core layer 310 and covers this first metal layer 320.This second welding cover layer 350 is formed at this second surface 312 of this core layer 310 and covers this second metal level 330.Wherein, this first welding cover layer 340 has roughly the same thickness with this second welding cover layer 350, and this first welding cover layer 340 has thermal coefficient of expansion inequality with this second welding cover layer 350, to reduce the angularity of this lamination type substrate 300.
As shown in Figure 4, this substrate 300 can include sticking crystal layer 360 in addition, and its part is covered on this second welding cover layer 350.In the present embodiment, this substrate 300 can have through hole 301, and it runs through this first welding cover layer 340, this first metal layer 320, this core layer 310, this second metal level 330 and this second welding cover layer 350, passes through for routing.Generally speaking, this through hole 301 can be positioned at center or other position of this substrate 300.As shown in Figure 4, in the present embodiment, the thermal coefficient of expansion of this first welding cover layer 340 is less than the thermal coefficient of expansion of this second welding cover layer 350, and should glue the thermal coefficient of expansion of crystal layer 360 less than this second welding cover layer 350, can be by ANSYS software, utilize finite element method (FEM) to find the solution, suitably adjust the difference of thermal expansion coefficient of this first welding cover layer 340 and this second welding cover layer 350, to offset the warpage influence of this sticking crystal layer 360 or other material coefficient of thermal expansion coefficient to this substrate 300, make these substrate 300 upper and lower surfaces produce the thermal stress of contending with each other, this substrate 300 can not produce serious warpage along with variations in temperature in chip package process.
Particularly, this the first metal layer 320 is for line layer and can be connected with two or more outer connection pads 321, and this first welding cover layer 340 has a plurality of openings and connects finger 322 to expose in these outer connection pads 321 of forming on this first metal layer 320 and two or more.In addition, this second metal level 330 can be void and puts copper foil layer (dummy copper foil), for heat radiation and electrical barrier.
When carrying out follow-up chip package process, as shown in Figure 5, with semiconductor chip 31 by the stickup of this sticking crystal layer 360 and be arranged at the upper surface of this second welding cover layer 350, the active surface of this chip 31 has two or more weld pads 31A, can utilize two or more to electrically connect elements 33 and connect these weld pads 31A and connect to these of this substrate 300 by this through hole 301 and refer to 322, make this chip 31 and these substrate 300 electrical interconnects.In the present embodiment, these electrically connect the bonding wire that element 3 forms for routing.Afterwards, carry out the sealing operation, insert top, below and this through hole 301 of this substrate 300 with adhesive body 34, with seal this chip 31, this through hole 301 electrically connects element 33 with these, and suitable protection is provided.This chip 31 is arranged at this first surface 311 of this substrate 300 again with two or more external terminals 35 (as soldered ball), so that must be realized electrical connection with external printed circuit board (PCB, printed circuit board).
Under the curing of the prebake conditions of carrying out on the substrate sticking crystal layer, adhesive body or subsequent thermal cycle operation or the like variations in temperature environment, this first welding cover layer 340 remains unchanged with the thickness of this second welding cover layer 350, with both difference of thermal expansion coefficient of this first welding cover layer 340 and this second welding cover layer 350, can make this substrate 300 keep dimensionally stable, be not subjected to influence of temperature change in the chip package process and warpage or distortion, particularly be applicable to the lamination type substrate of asymmetric layer.
Generally speaking, the present invention is laid in the upper and lower surface of substrate by the welding cover layer of thermal coefficient of expansion inequality, produces the thermal stress of contending with each other under variations in temperature, makes substrate not have warpage issues.Therefore, this substrate can low manufacturing cost be made, and can be issued to the effect that suppresses substrate warp in chip package process in the condition that does not need to increase additional stiffening elements and change substrate thickness.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction, and the technical solution of the present invention scope is when being as the criterion according to appended claims.Any those of ordinary skill in the art can utilize the technology contents of above-mentioned announcement to make the equivalent embodiment that changes or be modified to equivalent variations, in every case be the content that does not break away from technical solution of the present invention,, all still belong in the scope of technical solution of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (16)
1, a kind of lamination type substrate is characterized in that, comprises:
Core layer, it has first surface and second surface;
The first metal layer, it is formed at this first surface of this core layer;
Second metal level, it is formed at this second surface of this core layer;
First welding cover layer, it is formed at this first surface of this core layer and covers this first metal layer; And
Second welding cover layer, it is formed at this second surface of this core layer and covers this second metal level;
This first welding cover layer and this second welding cover layer have roughly the same thickness, and this first welding cover layer and this second welding cover layer have thermal coefficient of expansion inequality, to reduce the angularity of this lamination type substrate.
2, lamination type substrate as claimed in claim 1 is characterized in that, this lamination type substrate also includes sticking crystal layer, and its part is covered on this second welding cover layer.
3, as claim the 1 or 2 described lamination type substrates, it is characterized in that the thermal coefficient of expansion of described first welding cover layer is less than the thermal coefficient of expansion of this second welding cover layer.
4, lamination type substrate as claimed in claim 1 or 2 is characterized in that, the thermal coefficient of expansion of described first welding cover layer is greater than the thermal coefficient of expansion of this second welding cover layer.
5, lamination type substrate as claimed in claim 1 is characterized in that, this lamination type substrate also has through hole, and it runs through this first welding cover layer, this first metal layer, this core layer, this second metal level and this second welding cover layer.
As claim 1 or 5 described lamination type substrates, it is characterized in that 6, described the first metal layer is line layer and is connected with two or more outer connection pads.
7, lamination type substrate as claimed in claim 6 is characterized in that, described second metal level is line layer and is connected with and connects finger in two or more.
8, lamination type substrate as claimed in claim 6 is characterized in that, described second metal level is that void is put copper foil layer, and this first metal layer is connected with and connects finger in two or more.
9, a kind of chip encapsulation construction that uses the lamination type substrate is characterized in that, comprises:
The lamination type substrate comprises:
Core layer, it has first surface and second surface;
The first metal layer, it is formed at this first surface of this core layer;
Second metal level, it is formed at this second surface of this core layer;
First welding cover layer, it is formed at this first surface of this core layer and covers this first metal layer; And
Second welding cover layer, it is formed at this second surface of this core layer and covers this second metal level;
This first welding cover layer and this second welding cover layer have roughly the same thickness, and this first welding cover layer and this second welding cover layer have thermal coefficient of expansion inequality, to reduce the angularity of this lamination type substrate;
Chip, it is arranged at the upper surface of this second welding cover layer;
Two or more electrically connect element, electrically connect the first metal layer of this chip to this substrate; And
Adhesive body, it is arranged on the upper surface of this second welding cover layer of this substrate, to seal this chip.
10, the chip encapsulation construction of use lamination type substrate as claimed in claim 9 is characterized in that, described lamination type substrate also includes sticking crystal layer, and its part is covered on this second welding cover layer, with bonding this chip.
11, as the chip encapsulation construction of claim 9 or 10 described use lamination type substrates, it is characterized in that the thermal coefficient of expansion of described first welding cover layer is less than the thermal coefficient of expansion of this second welding cover layer.
12, as the chip encapsulation construction of claim 9 or 10 described use lamination type substrates, it is characterized in that the thermal coefficient of expansion of described first welding cover layer is greater than the thermal coefficient of expansion of this second welding cover layer.
13, the chip encapsulation construction of use lamination type substrate as claimed in claim 9 is characterized in that, described lamination type substrate has through hole, and it runs through this first welding cover layer, this first metal layer, this core layer, this second metal level and this second welding cover layer
As the chip encapsulation construction of claim 9 or 13 described use lamination type substrates, it is characterized in that 14, described the first metal layer is line layer and is connected with two or more outer connection pads.
15, the chip encapsulation construction of use lamination type substrate as claimed in claim 14 is characterized in that, described second metal level is line layer and is connected with and connects finger in two or more.
16, the chip encapsulation construction of use lamination type substrate as claimed in claim 14 is characterized in that, described second metal level is that void is put copper foil layer, and this first metal layer is connected with and connects finger in two or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100937023A CN101562169A (en) | 2008-04-16 | 2008-04-16 | Lamination type base plate and chip packaging structure using same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2008100937023A CN101562169A (en) | 2008-04-16 | 2008-04-16 | Lamination type base plate and chip packaging structure using same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101562169A true CN101562169A (en) | 2009-10-21 |
Family
ID=41220895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2008100937023A Pending CN101562169A (en) | 2008-04-16 | 2008-04-16 | Lamination type base plate and chip packaging structure using same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101562169A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194803A (en) * | 2010-03-01 | 2011-09-21 | 南茂科技股份有限公司 | Semiconductor structure |
| CN102843877A (en) * | 2011-06-24 | 2012-12-26 | 揖斐电株式会社 | A printed wiring board and a method for manufacturing the printed wiring board |
| CN114449792A (en) * | 2020-10-30 | 2022-05-06 | Oppo广东移动通信有限公司 | Shell, manufacturing method thereof and electronic equipment |
| CN115621242A (en) * | 2022-12-15 | 2023-01-17 | 北京唯捷创芯精测科技有限责任公司 | Substrate with low warping stress, preparation method, packaging structure and electronic product |
-
2008
- 2008-04-16 CN CNA2008100937023A patent/CN101562169A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194803A (en) * | 2010-03-01 | 2011-09-21 | 南茂科技股份有限公司 | Semiconductor structure |
| CN102843877A (en) * | 2011-06-24 | 2012-12-26 | 揖斐电株式会社 | A printed wiring board and a method for manufacturing the printed wiring board |
| US8945329B2 (en) | 2011-06-24 | 2015-02-03 | Ibiden Co., Ltd. | Printed wiring board and method for manufacturing printed wiring board |
| CN114449792A (en) * | 2020-10-30 | 2022-05-06 | Oppo广东移动通信有限公司 | Shell, manufacturing method thereof and electronic equipment |
| CN115621242A (en) * | 2022-12-15 | 2023-01-17 | 北京唯捷创芯精测科技有限责任公司 | Substrate with low warping stress, preparation method, packaging structure and electronic product |
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Open date: 20091021 |