TWI309549B - Printed circuit board with improved thermal dissipating structure and electronic device with the same - Google Patents

Printed circuit board with improved thermal dissipating structure and electronic device with the same Download PDF

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TWI309549B
TWI309549B TW094129461A TW94129461A TWI309549B TW I309549 B TWI309549 B TW I309549B TW 094129461 A TW094129461 A TW 094129461A TW 94129461 A TW94129461 A TW 94129461A TW I309549 B TWI309549 B TW I309549B
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metal layer
heat dissipation
circuit board
substrate
electronic device
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TW094129461A
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TW200709774A (en
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Chih Hsiung Lin
Nai Shung Chang
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Via Tech Inc
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Priority to TW094129461A priority Critical patent/TWI309549B/zh
Priority to US11/292,631 priority patent/US20070045804A1/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0209—External configuration of printed circuit board adapted for heat dissipation, e.g. lay-out of conductors, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0207—Cooling of mounted components using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/066—Heatsink mounted on the surface of the PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09309—Core having two or more power planes; Capacitive laminate of two power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Description

•1309549 五、發明說明（1) •【發明所屬之技術領域】 本發明係有關於一種電子裝置，特別是有關於一種具 -有改善散熱結構以及多重封裝模組（mu 11 i - package module，MPM )之電子裝置。 【先萷技術】 可攜式電子產品，例如手機（ce 1 1 phone )、行動電 細（mobile computing)及其他消費性產品需要在厚度 薄、重量輕及低成本的限制因素下呈現高效能 (performance)及功能（functionality)，因而驅使製 造業者必須增加半導體晶片的集積度。亦即，製造業者開 始轉向三維（3D )封裝，藉由打線（wire b〇nding )法或 覆晶（Π i p ch i p )法等組裝技術而將多重晶片疊置於— 封裝中。
因此，多重封裝模組（mul ti_package m〇dule，MpM ^近，越來越受到矚目’其可在一封裝基板上整合不同功 月=4 B曰片 例如被處理益或§己憶體、邏輯及光學積體電路 等，取代了將個別的晶片放置於較大尺寸的印刷電路板 (Printed circuit board，PCB )上的方式。殃而，相較 <個別的單晶封裝而言，多重封裝模組具有較高的功率密 度，而使得熱管理（thermal management )變的更為重要 且成為其成功發展之關鍵因素。 ” 第1圖係繪示出傳統的具有多重封裴模紐之電子妒置 100剖面示意圖。A電子裝置100包括一多重封裝模組;〇， 其，、且衣於一印刷電路板（PCB) 101上，且其包括一封裝基
1309549 五、發明說明（2) 板12。封裝基板12之上异而芬下2 曰芬1/1品德a々表面及下表面各組裝有不同功能之 日曰片1 6及1 4而構成多重封裝模組2〇。 由一封裝基板12,之凸换f或锡玻）1ηΐ例而3日日片16猎 19 ^ ^ η凸塊（或錫球）1 0而組裝於封裝基板 # Γ: Γ片14則藉由覆晶法組裝於封裝基板1 2之下 ΐ刷電路板Γοι反表面具有複數凸塊10，其對應連接至 印刷電路板101上的烊墊（b〇nding pad) 晶片16及14與印刷電路板1〇1作電性連接。在多s重封)穿模 二"’晶片16所產生的熱可藉由輻射“adiaUon;和 對洲_ (convection )兩種方式將其排出。然而， •u與印刷電路板1G1之間的間隙狹小的關係，使得晶、曰^ 所產生的熱難以藉由輻射（r a d丨a t丨〇 n )和對流 (convection )兩種方式將其排出。因此，L 处 由傳導（con—)方式進行散熱。—般而言， 路板m上對應晶片14的位置會形成—金屬層1Q2，Μ# 政熱貧（heat conduct ive paste ) 22而與晶片η連接。 因此，晶片14可藉由散熱膏22、金屬層1〇2及印刷 _ 1 0 1所構成的熱傳導路徑來進行散熱。 =，對於會產生高熱的高功率晶片而言，上 产政熱（passive⑶0ling)是無法提供較佳的散埶 以及較高的散熱速率。亦即，將晶片所產生的赦破’、> 貧及金屬層傳導至印刷電路板並無法有效且及時^:^散 0 【發明内容】 有鑑於此，本發明之目的在於提供_種具有改善散熱 0608-A40469twf(n2);VIT05-0083;SPIN.ptd 第7頁 1309549 圖式簡單說明 -【圖示簡單說明】 第1圖係繪示出傳統的具有多重封裝模組之電子裝置 -剖面示意圖。 第2A圖係繪示出根據本發明實施例之具有改善散熱結 構之電子裝置之平面示意圖。 第2B圖係繪示出沿第2A圖中2B-2B線之剖面示意圖。 第2C圖係繪示出根據本發明實施例之具有交替排列之 鰭部之散熱片平面示意圖。 第2D圖係繪示出根據本發明實施例之具有三角形鰭部 _之散熱片平面示意圖。 第2E圖係繪示出根據本發明實施例之具有矩形鰭部之 散熱片平面示意圖。 第3 A圖係繪示出根據本發明實施例之具有改善散熱結 構之電子裝置之平面示意圖。 - 第3B圖係繪示出沿第3A圖中3B-3B線之剖面示意圖。 第3C圖係繪示出根據本發明實施例之具有交替排列之 鰭部之頂層金屬層平面示意圖。 第3D圖係繪示出根據本發明實施例之具有三角形鰭部 φ之頂層金屬層平面示意圖。 第3E圖係繪示出根據本發明實施例之具有矩形鰭部之 頂層金屬層平面示意圖。 【主要元件符號說明】 習知 1 0、1 0 ’〜凸塊；
0608-A40469twf(n2);VIT05-0083;SPIN.ptd 第15頁 1309549 圖式簡單說明 • 12、12’〜封裝基板； 1 4 、1 6〜晶片； 2 0〜多層封裝模組； 2 2〜散熱膏； 1 0 0〜電子裝置； 1 0 1 ~印刷電路板， 1 0 2 ~金屬層。 本發明 3 0〜凸塊； . 32&~晶片區， 32〜封裝基板； 34 、 36〜晶片； 4 0〜多層封裝模組； 42〜散熱膏； 2 0 0〜電路板； 2 01〜基板； 2 0 2 ~焊墊； 204~導熱層； > 2 Q 5 ~散熱部件； 2 0 6 ~散熱片； 20 6a、212a〜鰭部； 2 0 7 ~風扇；2 0 8 ~散熱模組； 2 0 9〜第二頂層金屬層； 210〜第一頂層金屬層；
0608-A40469twf(n2);VIT05-0083;SPIN.ptd 第16頁 1309549

Claims (1)

  1. 工3〇9549 麵剛 六、申請專利範圍 1. 一種具有改善散熱結構之電子裝置，包括： 一封裝基板，其包括： 一基板’具有一晶片區，以及 複數凸塊’依陣列排置於該基板上且圍繞該晶片區， 一電路板，位於該封裝基板下方，其包括： 複數焊墊，對應連接至該等凸塊；以及 内層金屬層（inner metal layer ); 一導熱層1設置於該封裝基板之晶片區與該電路板之 間，且與該内層金屬層作熱接觸；以及 | 一散熱片，設置於該封裝基板外侧的該電路板上且與 該内層金屬層作熱接觸，其中該散熱片具有至少一鰭部， 且該散熱片及其鰭部朝該電路板表面大體平行地延伸。 2. 如申請專利範圍第1項所述之具有改善散熱結構之 電子裝置，其中該鰭部為圓形、三角形、矩形或多邊形。 3. 如申請專利範圍第1項所述之具有改善散熱結構之 電子裝置，其中該散熱片具有複數鰭部對稱或交替地排列 於其兩相對側。 4. 如申請專利範圍第1項所述之具有改善散熱結構之 電子裝置，更包括一散熱模組，設置於該散熱片上方。 > 5.如申請專利範圍第4項所述之具有改善散熱結構之 電子裝置，其中該散熱模組包括一熱板或一熱管。 6.如申請專利範圍第1項所述之具有改善散熱結構之 電子裝置，其中該散熱片或該導熱層係由金、銀或銅金屬 所構成。
    0608-A40469twfl(n2);VIT05-0083;SPIN.ptc 第18頁 丨,-一............. C(r\#·((月i{日修(p正潛‘| 1309549 六、申請專利範圍 中7 申請專利範圍第1項所述之具有改善散熱結構之 電子装置，盆+ 〃干遠電路板更包括複數導熱插塞，熱連接該 内層金屬層、該導熱層及該散熱片。 8 種具有改善散熱結構之電子裝置，包括： 一封裝基板，其包括： 二基板，具有一晶片區；以及 複數凸塊’依陣列排置於該基板上且圍繞該晶片區； 、印刷電路板，位於該封裝基板下方，其包括： 複^焊塾’對應連接至該等凸塊； f 頂層金屬層，對應於該封裝基板之晶片區； 一第二頂層金屬層，位於該封装基板外側，並 二頂層金屬層具有至少一鰭部，錢第二頂層全屬玄弟 部朝該印刷電路板表面大體平行地延伸；卩及、’屬及其鰭 一内層金屬層，分別與該第一頂層金屬層 層金屬層作熱接觸。 邊弟二頂 9.如申請專利範圍第9項所述之具有改善散熱纟士構 電子裝置，其中該鰭部為圓形、三角形、矩形或多邊形。 1 0.如申請專利範圍第8項所述之具有改善散熱結構 電子裝置，其中該第二頂層金屬層具有複數鰭部對 丨替地排列於其兩相對側。 一父 11.如申請專利範圍第8項所述之具有改善散熱結 電子裝置，其中該第—或第二頂層金屬層係由金、^ 金屬所構成。 ’’ 1 2.如申請專利範圍第8項所述之具有改善散熱結構之
    0608-Α40469 twf1(n2);VIΤ05- 0083;SPIN.p t 第19貢 ，卜芝((月，修曰味陶、备， ~-~—_- 電。置更包括—散熱模組，設置於該第二頂層金屬層 上万。 .^ 申請/利範圍第12項所述之具有改善散熱結構 - 裝置，其中該散熱模組包括一熱板或一熱管。 愈+=.¥如申請專利範圍第8項所述之具有改善散熱結構之 電^ 、置’其中該印刷電路板更包括複數導熱插塞，熱連 接該内層金屬層、該第—頂層金屬層及該第二頂層金屬 層。 1 5. —種具有改善散熱結構之印刷電路板，適用於一 _多重封裝模組之封裝基板，包括·· —基板； 弟一頂層金屬層，設置於該基板上，且對應於該封 裝基板； 第一頂層金屬層’設置於該基板上，且位於該封裝 基板外側’其中該第二頂層金屬層具有至少一鰭部，且該 弟一頂層金屬及其鰭部朝該印刷電路板表面大體平行地延 -伸； 一内層金屬層，設置於該基板中； 複數第一導熱插塞，設置於該基底中，以熱連接該第 一頂層金屬層與該内層金屬層；以及 複數第二導熱插塞，設置於該基底中，以熱連接該第 二頂層金屬層與該内層金屬層。 1 6.如申請專利範圍第1 5項所述之具有改善散熱結構之印 -刷電路板，其中該鰭部為圓形、三角形、矩形或多邊形。
    0608-A40469twfl(n2);VIT05-0083;SPIN.ptc 第 20 頁
    案號 94129461 1309549 六、申請專利範圍 1·7.如申請專利範圍第1 5項所述之具有改善散熱結構 之印刷電路板，其中該第二頂層金屬層具有複數鰭部對稱 或交替地排列於其兩相對側。 1 8.如申請專利範圍第1 5項所述之具有改善散熱結構 之印刷電路板，其中該第一或第二頂層金屬層係由金、銀 或銅金屬所構成。
    0608-A40469twfl(n2);VIT05-0083;SPIN.ptc 第21頁
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4308797B2 (ja) * 2005-05-02 2009-08-05 株式会社アドバンストシステムズジャパン 半導体パッケージおよびソケット付き回路基板
JP2010211179A (ja) * 2009-02-13 2010-09-24 Hitachi Ltd 光電気複合配線モジュールおよびその製造方法
EP2790474B1 (en) 2013-04-09 2016-03-16 Harman Becker Automotive Systems GmbH Thermoelectric cooler/heater integrated in printed circuit board
DE102014104976B4 (de) * 2013-04-29 2017-07-06 Toyota Jidosha Kabushiki Kaisha Gedruckte Leiterplatinen mit Temperaturmanagementeigenschaften und diese aufweisende Temperaturmanagementvorrichtungen
DE102014104970A1 (de) * 2013-04-29 2014-10-30 Toyota Motor Engineering & Manufacturing North America, Inc. Kompositlaminat mit Temperaturmanagementeigenschaften und dieses aufweisende Temperaturmanagementvorrichtungen
US9433074B2 (en) * 2013-04-29 2016-08-30 Toyota Motor Engineering & Manufacturing North America, Inc. Printed wiring boards having thermal management features and thermal management apparatuses comprising the same
US20150116944A1 (en) * 2013-10-29 2015-04-30 Delphi Technologies, Inc. Electrical assembly with a solder sphere attached heat spreader
GB2520952A (en) * 2013-12-04 2015-06-10 Ibm Flip-chip electronic device with carrier having heat dissipation elements free of solder mask
US10028413B2 (en) 2014-07-25 2018-07-17 Toyota Motor Engineering & Manufacturing North America, Inc. Heat transfer management apparatuses having a composite lamina
KR20160036945A (ko) * 2014-09-26 2016-04-05 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 전자부품 패키지
CN107256850B (zh) * 2017-07-25 2023-03-31 厦门大学 一种内嵌金属微通道的转接板及其制备方法
WO2020061920A1 (zh) * 2018-09-27 2020-04-02 西门子（中国）有限公司 电路板散热***、电路板以及机器人关节
KR20210073151A (ko) * 2019-12-10 2021-06-18 엘지디스플레이 주식회사 인쇄회로기판 및 이를 포함하는 표시장치
CN113311548A (zh) * 2020-02-27 2021-08-27 华为终端有限公司 光学模组及电子设备
KR20220017171A (ko) * 2020-08-04 2022-02-11 엘지이노텍 주식회사 칩 온 필름용 연성 회로기판 및 이를 포함하는 칩 패키지, 및 이를 포함하는 전자 디바이스

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5708566A (en) * 1996-10-31 1998-01-13 Motorola, Inc. Solder bonded electronic module
US5933324A (en) * 1997-12-16 1999-08-03 Intel Corporation Apparatus for dissipating heat from a conductive layer in a circuit board
US6657296B2 (en) * 2001-09-25 2003-12-02 Siliconware Precision Industries Co., Ltd. Semicondctor package

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