TW201820468A - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TW201820468A TW201820468A TW106129638A TW106129638A TW201820468A TW 201820468 A TW201820468 A TW 201820468A TW 106129638 A TW106129638 A TW 106129638A TW 106129638 A TW106129638 A TW 106129638A TW 201820468 A TW201820468 A TW 201820468A
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- Prior art keywords
- layer
- sintered
- nano metal
- circuit element
- alloy
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims abstract description 85
- 238000005538 encapsulation Methods 0.000 claims abstract description 32
- 239000010410 layer Substances 0.000 claims description 417
- 239000002923 metal particle Substances 0.000 claims description 99
- 229910045601 alloy Inorganic materials 0.000 claims description 81
- 239000000956 alloy Substances 0.000 claims description 81
- 238000004806 packaging method and process Methods 0.000 claims description 65
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 30
- 239000012790 adhesive layer Substances 0.000 claims description 23
- 230000008878 coupling Effects 0.000 claims description 18
- 238000010168 coupling process Methods 0.000 claims description 18
- 238000005859 coupling reaction Methods 0.000 claims description 18
- 239000000203 mixture Substances 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 229910052759 nickel Inorganic materials 0.000 claims description 15
- 229910000756 V alloy Inorganic materials 0.000 claims description 14
- HBVFXTAPOLSOPB-UHFFFAOYSA-N nickel vanadium Chemical compound [V].[Ni] HBVFXTAPOLSOPB-UHFFFAOYSA-N 0.000 claims description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052709 silver Inorganic materials 0.000 claims description 12
- 239000004332 silver Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 7
- 239000011651 chromium Substances 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000010936 titanium Substances 0.000 claims description 7
- 239000002985 plastic film Substances 0.000 claims description 6
- 229920006255 plastic film Polymers 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000002105 nanoparticle Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 19
- 230000017525 heat dissipation Effects 0.000 description 15
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000004033 plastic Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 241000209094 Oryza Species 0.000 description 2
- 235000007164 Oryza sativa Nutrition 0.000 description 2
- 239000000084 colloidal system Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012785 packaging film Substances 0.000 description 2
- 229920006280 packaging film Polymers 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 235000009566 rice Nutrition 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- CNQCVBJFEGMYDW-UHFFFAOYSA-N lawrencium atom Chemical compound [Lr] CNQCVBJFEGMYDW-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
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- H—ELECTRICITY
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4871—Bases, plates or heatsinks
- H01L21/4882—Assembly of heatsink parts
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H01L23/3733—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon having a heterogeneous or anisotropic structure, e.g. powder or fibres in a matrix, wire mesh, porous structures
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- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Abstract
本發明披露一種半導體裝置及製造方法,該裝置包括層疊的電路元件及散熱片,及位於電路元件及散熱片間的熱介面材料層;其中,電路元件側壁上環繞設置有封裝層;熱介面材料層的第一面與電路元件及封裝層熱耦合,第二面與散熱片熱耦合。封裝層及電路元件均與熱介面材料層熱耦合,增加了電路元件與熱介面材料層接觸面積,電路元件側壁的熱可通過封裝層傳到熱介面材料層,再傳到散熱片,進而提高散熱效果。通過在電路元件外側環繞的封裝層,增大熱介面材料層的鋪設面積,增加熱介面材料層接觸面積,降低了介面應力,並相應提升了組件可靠度。
Description
本發明涉及半導體技術領域,尤其涉及一種電路半導體裝置及製造方法。
第1A圖所示為現有技術中積體電路晶片及其部分封裝結構的截面示例圖。該結構包括積體電路晶片1A02、熱介面材料層1A04及散熱器1A06。其中,熱介面材料層1A04中具有以分散相形式分佈的多個金屬顆粒1A08,積體電路晶片1A02於工作過程中產生的熱通過晶片背面的熱介面材料層1A04傳導至散熱器1A06,但現有技術中,由於積體電路晶片1A02的尺寸的限定,導致傳遞熱量的效果較差,已很難滿足大功率晶片的散熱需求。
本發明實施例提供一種半導體裝置及製造方法。該半導體裝置中,通過設置的封裝層增大熱介面材料層與電路元件的接觸面積,大幅度提高了整體熱通路的熱導效能,能更好地滿足大功耗電路元件的散熱需求。
第一方面,本發明實施例提供了一種半導體裝置,包括:層疊設置的電路元件及散熱片,以及位於所述電路元件及所述散熱片之間的熱介面材料層;其中,所述電路元件側壁上環繞設置有封裝層;所述電路元件包括積體電路晶片,所述積體電路晶片具有接腳,所述積體電路晶片上設置所述接腳的一面為安裝面,所述電路元件側壁為所述積體電路晶片上與所述安裝面相鄰的壁;所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面,且所述第一面與所述電路元件及所述封裝層熱耦合,所述第二面與所述散熱片熱耦合。
在上述方案中,由於採用封裝層環繞電路元件設置,並且封裝層及電路元件均與熱介面材料層熱耦合,從而增大了電路元件與熱介面材料層的接觸面積,同時,電路元件側壁上產生的熱量可以通過封裝層傳遞到熱介面材料層上,再傳遞到散熱片上,進而提高半導體裝置的散熱效果。同時,通過在電路元件的外側環繞的一層封裝層,來增大熱介面材料層的鋪設面積,增大了熱介面材料層接觸面的面積,降低了介面應力,並相應的提升了組件可靠度。
其中的封裝層採用塑封膜層,該塑封膜層具有良好的傳熱效果,可以快速的將電路元件側壁上的熱量傳遞到熱介面材料層上,進而提高了電路元件的散熱效率。
其中的熱介面材料層包括:第一合金層,與所述電路元件及所述封裝層熱耦合;奈米金屬顆粒層,與所述第一合金層熱耦合,所述奈米金屬顆粒層包括相互耦合的多個奈米金屬顆粒及中間混合物,所述中間混合物填充於所述多個奈米金屬顆粒之間;及第二合金層,與所述奈米金屬顆粒層及所述散熱片熱耦合。由於採用的熱介面材料層中不再包含銀膠類材料中的高分子類較低熱導材料,而是包含奈米金屬顆粒,本發明實施例中的熱介面材料具有較高導熱率,大幅度提高了整體熱通路的熱導效能,能更好地滿足大功耗晶片的散熱需求。
在具體設置時,所述第一合金層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構,所述多個奈米金屬顆粒之間的接觸處形成燒結連續相結構,且所述第二合金層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。通過形成的燒結連續相結構提高了兩者之間連接效果,並且提高了兩者之間熱傳遞的效果。
在一個具體的實施方案中,所述奈米金屬顆粒包括銀。具有良好的傳熱效果。並且在具體設置時,所述奈米金屬顆粒的直徑處於50-200奈米之間。
本實施例提供的半導體裝置用於覆晶球柵格陣列封裝結構。
其中,第一合金層包括第一接著層及第一共燒結層,所述第一接著層與所述電路元件及所述封裝層熱耦合,所述第一共燒結層與所述奈米金屬顆粒層耦合,且所述第一共燒結層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。採用上述結構,提高了第一合金層與電路元件及封裝層熱耦合的連接強度,並且具有良好的熱傳遞效果。
在具體設置時,第一接著層可以包含鈦、鉻、鎳或鎳釩合金,所述第一共燒結層可以包含銀、金或銅。上述材料均具有較好的熱傳遞效果。
此外,作為一個優選的方案,所述第一合金層還包括第一緩衝層,位於所述第一接著層與所述第一共燒結層之間,所述第一緩衝層可以包含鋁、銅、鎳或鎳釩合金。
在具體設置時,所述第二合金層包括第二接著層及第二共燒結層,所述第二接著層與所述散熱片熱耦合,所述第二共燒結層與所述奈米金屬顆粒層熱耦合,且所述第二共燒結層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。採用上述結構,提高了第二合金層與散熱片熱耦合的連接強度,並且具有良好的熱傳遞效果。
且在具體設置時,其中的第二接著層可以包含鈦、鉻、鎳或鎳釩合金,所述第二共燒結層可以包含銀、金或銅。上述材料均具有較好的熱傳遞效果。
作為一個優選的方案,所述第二合金層還包括第二緩衝層,位於所述第二接著層與所述第二共燒結層之間,所述第二緩衝層可以包含鋁、銅、鎳或鎳釩合金。
其中的奈米金屬顆粒的直徑不大於1微米。
中間混合物可以選擇不同的材料,在一個具體的實施方式中所述中間混合物可以包含空氣或樹脂。
本發明實施例提供了一種製造半導體裝置的方法,包括:在電路元件的側壁上環繞設置封裝層;其中,所述電路元件包括積體電路晶片,所述積體電路晶片具有接腳,所述積體電路晶片上設置所述接腳的一面為安裝面,所述電路元件側壁為所述積體電路晶片上與所述安裝面相鄰的壁;
生成熱介面材料層,所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面;
將第一面與所述電路元件及所述封裝層熱耦合,所述第二面與所述散熱片熱耦合。
在上述方案中,由於採用封裝層環繞電路元件設置,並且封裝層及電路元件均與熱介面材料層熱耦合,從而增大了電路元件與熱介面材料層的接觸面積,同時,電路元件側壁上產生的熱量可以通過封裝層傳遞到熱介面材料層上,再傳遞到散熱片上,進而提高半導體裝置的散熱效果。同時,通過在電路元件的外側環繞的一層封裝層,來增大熱介面材料層的鋪設面積,增大了熱介面材料層接觸面的面積,降低了介面應力,並相應的提升了組件可靠度。
在具體製備時,所述生成熱介面材料層,所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面;具體為:
生成第一合金層;
由相互耦合的多個奈米金屬顆粒與中間混合物生成奈米金屬顆粒層,使所述中間混合物填充於所述多個奈米金屬顆粒之間;
生成第二合金層,
使所述奈米金屬顆粒層分別與所述第一合金層及第二合金層熱耦合;其中,所述第一合金層背離所述奈米顆粒層一面為第一面,所述第二合金層背離所述奈米金屬顆粒層的一面為第二面。
還包括:使所述第一合金層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構,使所述奈米金屬顆粒之間的接觸處形成燒結連續相結構,且使所述第二合金層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。
其中的奈米金屬顆粒的直徑不大於1微米。
其中的中間混合物可以包含空氣或樹脂。
在具體製備第一合金層時,生成第一接著層及第一共燒結層,並使所述第一接著層與所述電路元件及所述封裝層熱耦合,使所述第一共燒結層與所述奈米金屬顆粒層耦合,且使所述第一共燒結層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。
在具體製備第二合金層時:生成第二接著層及第二共燒結層,並使所述第二接著層與所述散熱片熱耦合,使所述第二共燒結層與所述奈米金屬顆粒層熱耦合,且使所述第二共燒結層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。
其中的,所述在電路元件的側壁上環繞設置封裝層包括以塑封膜作為製造所述封裝層的材料,以在所述側壁上環繞設置所述封裝層。塑封膜具有良好的熱傳遞效果,通過設置的塑封膜製備封裝層提高了電路元件的散熱效率。
下面將結合本發明實施例中的附圖,對本發明實施例中的技術方案進行清楚、完整地描述,顯然,所描述的實施例僅僅是本發明一部分實施例,而不是全部的實施例。基於本發明中的實施例,本領域普通技術人員在沒有作出創造性勞動前提下所獲得的所有其他實施例,均屬於本發明保護的範圍。
為了方便描述,本實施例定義了電路元件的側壁,在本實施例中電路元件的側壁是指,電路元件上與設置有接腳的一面(安裝面)相鄰的壁,在第1B圖中,第1B圖為本發明第一實施例提供的半導體裝置的截面示例圖,以半導體裝置的放置方向為參考方向,該電路元件的側壁為第1B圖中示出的在豎直方向的一面。
本發明實施例提供了一種半導體裝置,該半導體裝置包括:層疊設置的電路元件及散熱片105,以及位於所述電路元件及所述散熱片105之間的熱介面材料層104;其中,所述電路元件側壁上環繞設置有封裝層120;其中,所述電路元件包括積體電路晶片103,所述積體電路晶片103具有接腳,所述積體電路晶片103上設置所述接腳的一面為安裝面,所述電路元件側壁為所述積體電路晶片103上與所述安裝面相鄰的壁;所述熱介面材料層104具有朝向所述電路元件及所述封裝層120的第一面以及朝向所述散熱片105的第二面,且所述第一面與所述電路元件及所述封裝層120熱耦合,所述第二面與所述散熱片105熱耦合。
一併參考第1B圖及第2圖,第1B圖是本發明第一實施例包括半導體裝置的截面示例圖,第2圖為本實施例中電路元件與封裝層結合的俯視圖。第2圖為以第1B圖所示的元件的放置方向為參考方向,從上向下看到的電路元件(積體電路晶片103)與封裝層120結構的示意圖。在第2圖中,電路元件採用規則的矩形形狀,應當理解的是,第2圖僅僅是為了示意電路元件與封裝層120之間的位置關係,其中的電路元件的形狀不僅限於上述第2圖中的矩形形狀,還可以是其他的任意形狀。結合第1B圖及第2圖可以看出,本實施例提供的封裝層120環繞電路元件的側壁設置,即封裝層120可以看成圍繞電路元件轉一周形成的一個包裹電路元件側壁的結構。即如第1B圖所示,在電路元件包括積體電路晶片103及底部填充物101時,封裝層120包裹住積體電路晶片103及底部填充物101的側壁,並且封裝層120的頂面(第2圖中能夠看到的封裝層的一面)與積體電路晶片103的頂面(第2圖中能夠看到的積體電路晶片103的一面)齊平,並與積體電路晶片103的頂面共同組成與熱介面材料層104連接的接觸面。散熱片105通過黏合膠106固定在基板107上,積體電路晶片103的接腳與基板107上的電路連接。熱介面材料層104與積體電路晶片103及散熱片105熱耦合。在具體設置時,熱介面材料層104覆蓋在積體電路晶片103及封裝層120的頂面(即第2圖中示出的一面)並熱耦合,由於封裝層120具有一定的厚度d(即框形面的寬度),因此,封裝層120形成一個與熱介面材料層104進行熱耦合的框形的接觸面(如第2圖所示),且在具體設置時,封裝層120具有設定厚度d以保證能夠封裝住電路元件,因此,框形接觸面的框邊具有一定的寬度(該寬度等於封裝層120的厚度),具體的,在沒有封裝層120時,耦合面積僅為積體電路晶片103的頂面面積,在增加上封裝層120後,如第2圖所示,耦合面積為積體電路晶片103的頂面的面積加上封裝層120頂面的面積,增大了熱介面材料層104在與積體電路晶片103熱耦合面的面積。此外,由於耦合面積的增大,進而增加了熱介面材料層104與積體電路晶片103的連接強度,並且降低了介面應力(整體應力不變,但接觸面積增大,降低單位面積下應力影響),提升組件可靠度表現。
此外,在具體設置時,由於封裝層120貼附在電路元件的側壁上,因此,在散熱時,電路元件中側壁上的熱量可以通過封裝層120傳遞到熱介面材料層104上,進而擴散到散熱片105上,在採用上述結構時,可以看出,電路元件的散熱方式為:電路元件的頂面的熱量通過熱介面材料層104—散熱片105的路徑進行散熱,電路元件的側壁上的熱量通過封裝層120—熱介面材料層104—散熱片105的路徑進行散熱,從而增大了電路元件的散熱面積,進而提高了電路元件的散熱效果。
在一個具體的實施方式中,封裝層120採用塑封膜層,塑封膜層具有良好的封裝效果以及熱傳遞效果,從而可以快速的將熱量傳遞到熱介面材料層,進而提高電路元件的散熱效果。
如第1B圖及第2圖所示,整個半導體裝置在採用覆晶球柵格陣列封裝結構時,包括焊球108,基板107,黏合膠106,金屬凸塊(BUMP)102,電路元件(如積體電路晶片103),環繞電路元件103的封裝層120(如塑封膜層),熱介面材料層104及散熱片105。積體電路晶片103通過金屬凸塊102與基板107耦合。金屬凸塊102由底部填充物101保護,封裝層120環繞積體電路晶片103設置,且在具體設置時,本實施例中,熱耦合包括不同層次,不同結構,或不同裝置間有熱傳導的情形。更詳細地,熱介面材料層104可位於積體電路晶片103及散熱片105之間,且積體電路晶片103的基底與熱介面材料層104熱耦合,封裝層也與熱介面材料層104熱耦合。積體電路晶片103的熱量通過熱介面材料層104達到散熱片105。
其中,積體電路晶片103、環繞積體電路晶片103的封裝層120、熱介面材料層104及散熱片105可作為一種半導體裝置的部分或全部元件,且該半導體裝置可用於但不限於如圖所示的覆晶球柵格陣列封裝結構。
第3圖是第一實施例中熱介面材料層與電路元件及封裝層熱耦合的截面示例圖;其中,第3圖中僅示出了第1B圖中熱介面材料層104與積體電路晶片103連接的上半部分結構,封裝層120也僅示出了封裝層120的上半部分結構,該上半部分結構不包括底部填充物101。熱介面材料層104與積體電路晶片103、封裝層120及散熱片105熱耦合,包括第一合金層109、奈米金屬顆粒層110及第二合金層112。
第一合金層109將積體電路晶片103及封裝層120與奈米金屬顆粒層110熱耦合。更具體地,如第3圖所示,第一合金層109可位於積體電路晶片103及封裝層120之上,奈米金屬顆粒層110之下。即,第一合金層109可位於積體電路晶片103與奈米金屬顆粒層110之間。第一合金層109增加積體電路晶片103與奈米金屬顆粒層110之間的接著強度,並通過設置的封裝層120增大了第一合金層109的覆蓋面積,即增大了形成的第一合金層109的面積,進而提高了形成的熱介面材料層的面積104。
奈米金屬顆粒層110包括奈米金屬顆粒及中間混合物。中間混合物可以包含空氣或樹脂。中間混合物用於填充於多個奈米金屬顆粒之間,使多個奈米金屬顆粒形成整體。奈米金屬顆粒包括但不限於銀。奈米金屬顆粒的直徑不大於1微米。在一個實施例中,奈米金屬顆粒的直徑處於50-200奈米之間。奈米金屬顆粒層110熱阻較低,形成較好的導熱通路。
第二合金層112與奈米金屬顆粒層110及散熱片105熱耦合。更具體地,如圖所示,第二合金層112可位於奈米金屬顆粒層110之上,散熱片105之下。即,第二合金層112可位於奈米金屬顆粒層110與散熱片105之間。第二合金層112增加奈米金屬顆粒層110與散熱片105之間的接著強度。
在一個實施例中,第一合金層109與奈米金屬顆粒層110的接觸處形成燒結連續相結構,奈米金屬顆粒之間的接觸處形成燒結連續相結構,且第二合金層112與奈米金屬顆粒層110的接觸處形成燒結連續相結構。本文中的燒結連續相結構包括但不限於:因金屬顆粒產生燒結行為,金屬顆粒介面附近的金屬原子擴散至金屬顆粒介面融合在一起,使得金屬顆粒形成一個整體的結構。
第4圖是第3圖中第一合金層109的第一實施例的截面示例圖。第4圖也僅示出了封裝層120與積體電路晶片103的上半部分結構,如圖所示,第一合金層109包括第一接著層114及第一共燒結層115。本文中的共燒結層包括但不限於:在封裝加工過程中產生的與熱介面材料層互融的金屬層,該金屬層與熱介面材料層中的顆粒共同燒結形成熱流通路。第一接著層114與積體電路晶片103及封裝層120熱耦合。第一共燒結層115與奈米金屬顆粒層110熱耦合。第一共燒結層115與奈米金屬顆粒層110的接觸處形成燒結連續相結構。具體地,第一接著層114可位於積體電路晶片103及封裝層120之上,第一共燒結層115可位於第一接著層114之上,奈米金屬顆粒層110之下。第一接著層114可以包含鈦、鉻、鎳或鎳釩合金。第一接著層114增加積體電路晶片103與第一共燒結層115之間的結合強度。第一共燒結層115可以包含銀、金或銅。
第5圖是第3圖中第一合金層109的第二實施例的截面示例圖。第5圖也僅示出了封裝層120與積體電路晶片103的上半部分結構,與第3圖相比,第4圖中的第一合金層109還包括第一緩衝層116,位於所述第一接著層114與第一共燒結層115之間。第一緩衝層116可以包含鋁、銅或鎳。第一緩衝層116在因熱處理產生的形變中提供應力緩衝功能,降低積體電路晶片103與熱介面材料層114間或熱介面材料層114中間產生裂縫的風險,增加該半導體裝置的可靠性。
第6圖是第3圖中第二合金層112的第一實施例的截面示例圖。如圖所示,第二合金層112包括第二共燒結層118及第二接著層117。第二共燒結層118與奈米金屬顆粒層110熱耦合。第二共燒結層118與奈米金屬顆粒層110的接觸處形成燒結連續相結構。第二接著層117與散熱片105熱耦合。具體地,第二共燒結層118可位於奈米金屬顆粒層110之上,第二接著層117可位於第二共燒結層118之上,散熱片105之下。第二共燒結層118可以包含銀、金或銅。第二接著層117可以包含鈦、鉻、鎳或鎳釩合金。第二接著層117增加第二共燒結層115與散熱片105之間的結合強度。
第7圖是第3圖中第二合金層112的第二實施例的截面示例圖。與第6圖相比,第7圖中的第二合金層112還包括第二緩衝層119,位於第二接著層117與第二共燒結層118之間。第二緩衝層119可以包含鋁、銅、鎳或鎳釩合金。第二緩衝層119在因熱處理產生的形變中提供緩衝功能,降低熱介面材料層與散熱片105間或熱介面材料層114中間產生裂縫的風險,增加該半導體裝置的可靠度。
綜上,由於本發明實施例中的熱介面材料層中不再包含銀膠類材料中的高分子類較低熱導材料,而是包含奈米金屬顆粒,本發明實施例中的熱介面材料具有較高導熱率,大幅度提高了整體熱通路的熱導效能,能更好地滿足大功耗晶片的散熱需求,同時,通過在積體電路晶片103的外側環繞一層封裝層120,來增大熱介面材料層的鋪設面積,增大了熱介面材料層接觸面的面積,降低了介面應力,並相應的提升了組件可靠度。
第8圖是本發明第二實施例的一種製造半導體裝置的方法的流程圖700。如圖所示,在步驟702中,在電路元件的側壁上環繞設置封裝層,其中,所述電路元件包括積體電路晶片,所述積體電路晶片具有接腳,所述積體電路晶片上設置所述接腳的一面為安裝面,所述電路元件側壁為所述積體電路晶片上與所述安裝面相鄰的壁;在步驟704中,生成熱介面材料層,所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面;在步驟706中,將第一面與所述電路元件及所述封裝層熱耦合,所述第二面與所述散熱片熱耦合。
此外,所述在電路元件的側壁上環繞設置封裝層包括以塑封膜作為製造所述封裝層的材料,以在所述側壁上環繞設置所述封裝層。塑封膜具有良好的傳熱效果,可以快速的將電路元件側壁上的熱量傳遞到熱介面材料層上,進而提高了電路元件的散熱效率。
在具體製備時,生成熱介面材料層,所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面;具體為:
生成第一合金層。由相互耦合的奈米金屬顆粒與中間混合物生成奈米金屬顆粒層。奈米金屬顆粒的直徑不大於1微米,例如,奈米金屬顆粒的直徑處於50-200奈米之間。中間混合物可以包含空氣或樹脂。在一個實施例中,奈米金屬顆粒包括但不限於銀。生成第二合金層。使第一合金層將奈米金屬顆粒層與電路元件及封裝層熱耦合。使第二合金層與奈米金屬顆粒層及散熱片熱耦合。
在一個實施例中,使第一合金層與奈米金屬顆粒層的接觸處形成燒結連續相結構,使奈米金屬顆粒之間的接觸處形成燒結連續相結構,且使第二合金層與奈米金屬顆粒層的接觸處形成燒結連續相結構。
在一個實施例中,該方法可用於但不限於覆晶球柵格陣列封裝結構。
在一個實施例中,生成第一合金層包括生成第一接著層及第一共燒結層,並使第一接著層與電路元件及封裝層熱耦合,使第一共燒結層與奈米金屬顆粒層耦合,且使第一共燒結層與奈米金屬顆粒層的接觸處形成燒結連續相結構。第一接著層可以包含鈦、鉻、鎳或鎳釩合金。第一共燒結層可以包含銀、金或銅。在另一個實施例中,生成第一合金層還包括在第一接著層與第一共燒結層之間生成第一緩衝層。第一緩衝層可以包含鋁、銅、鎳或鎳釩合金。
在一個實施例中,生成第二合金層包括生成第二接著層及第二共燒結層,並使第二接著層與散熱片熱耦合,使第二共燒結層與奈米金屬顆粒層熱耦合,且使所述第二共燒結層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。第二接著層可以包含鈦、鉻、鎳或鎳釩合金。第二共燒結層可以包含銀、金或銅。在另一個實施例中,生成第二合金層還包括在第二接著層與第二共燒結層之間生成第二緩衝層。第二緩衝層可以包含鋁、銅、鎳或鎳釩合金。
電路元件可包括積體電路晶片。使第一合金層與電路元件及封裝層熱耦合包括使第一合金層與積體電路晶片中的基底及封裝層熱耦合。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。
1A02‧‧‧積體電路晶片
1A04‧‧‧熱介面材料層
1A06‧‧‧散熱器
1A08‧‧‧金屬顆粒
101‧‧‧底部填充物
102‧‧‧金屬凸塊(BUMP)
103‧‧‧積體電路晶片(電路元件)
104‧‧‧熱介面材料層
105‧‧‧散熱片
106‧‧‧黏合膠
107‧‧‧基板
108‧‧‧焊球
109‧‧‧第一合金層
110‧‧‧奈米金屬顆粒層
112‧‧‧第二合金層
114‧‧‧第一接著層
115‧‧‧第一共燒結層
116‧‧‧第一緩衝層
117‧‧‧第二接著層
118‧‧‧第二共燒結層
119‧‧‧第二緩衝層
120‧‧‧封裝層
700‧‧‧流程圖
702、704、706‧‧‧步驟
d‧‧‧厚度
為了更清楚地說明本發明實施例或現有技術中的技術方案,下面將對實施例或現有技術描述中所需要使用的附圖作簡單地介紹,顯而易見地,下面描述中的附圖僅僅是本發明的一些實施例,對於本領域普通技術人員來講,在不付出創造性勞動的前提下,還可以根據這些附圖獲得其他的附圖。 第1A圖是現有技術中包括半導體裝置的封裝結構的截面示例圖; 第1B圖是本發明第一實施例的包括半導體裝置的截面示例圖; 第2圖是本發明第一實施例提供的半導體裝置的電路元件與封裝層結合的示意圖; 第3圖是第一實施例中熱介面材料層與電路元件及封裝層熱耦合的截面示例圖; 第4圖是第3圖中的第一合金層的第一實施例的截面示例圖; 第5圖是第3圖中的第一合金層的第二實施例的截面示例圖; 第6圖是第3圖中的第二合金層的第一實施例的截面示例圖; 第7圖是第3圖中第二合金層的第二實施例的截面示例圖; 第8圖是本發明第二實施例的一種製造半導體裝置的方法的流程圖。
Claims (17)
- 一種半導體裝置,包含: 層疊設置的電路元件及散熱片,以及位於所述電路元件及所述散熱片之間的熱介面材料層; 其中,所述電路元件側壁上環繞設置有封裝層;所述電路元件包括積體電路晶片,所述積體電路晶片具有接腳,所述積體電路晶片上設置所述接腳的一面為安裝面,所述電路元件側壁為所述積體電路晶片上與所述安裝面相鄰的壁; 所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面,且所述第一面與所述電路元件及所述封裝層熱耦合,所述第二面與所述散熱片熱耦合。
- 如請求項1所述的半導體裝置,其中所述封裝層為塑封膜層。
- 如請求項1或2所述的半導體裝置,其中所述熱介面材料層包含: 第一合金層,與所述電路元件及所述封裝層熱耦合; 奈米金屬顆粒層,與所述第一合金層熱耦合,所述奈米金屬顆粒層含相互耦合的多個奈米金屬顆粒及中間混合物,所述中間混合物填充於所述多個奈米金屬顆粒之間;及 第二合金層,與所述奈米金屬顆粒層及所述散熱片熱耦合。
- 如請求項3所述的半導體裝置,其中所述第一合金層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構,所述多個奈米金屬顆粒之間的接觸處形成燒結連續相結構,且所述第二合金層與所述奈米金屬顆粒層的接觸處具有燒結連續相結構。
- 如請求項1或2所述的半導體裝置,其中所述半導體裝置係用於覆晶球柵格陣列封裝結構。
- 如請求項3所述的半導體裝置,其中所述第一合金層包含第一接著層及第一共燒結層,所述第一接著層與所述電路元件及所述封裝層熱耦合,所述第一共燒結層與所述奈米金屬顆粒層耦合,且所述第一共燒結層與所述奈米金屬顆粒層的接觸處具有燒結連續相結構。
- 如請求項6所述的半導體裝置,其中所述第一接著層包含鈦、鉻、鎳或鎳釩合金,所述第一共燒結層包含銀、金或銅。
- 如請求項6所述的半導體裝置,其中所述第一合金層還包括第一緩衝層,位於所述第一接著層與所述第一共燒結層之間,所述第一緩衝層包含鋁、銅、鎳或鎳釩合金。
- 如請求項3所述的半導體裝置,其中所述第二合金層包括第二接著層及第二共燒結層,所述第二接著層與所述散熱片熱耦合,所述第二共燒結層與所述奈米金屬顆粒層熱耦合,且所述第二共燒結層與所述奈米金屬顆粒層的接觸處具有燒結連續相結構。
- 如請求項9所述的半導體裝置,其中所述第二合金層還包括第二緩衝層,位於所述第二接著層與所述第二共燒結層之間,所述第二緩衝層包含鋁、銅、鎳或鎳釩合金。
- 如請求項3所述的半導體裝置,其中所述中間混合物包含空氣或樹脂。
- 一種半導體裝置的製造方法,包含: 在電路元件的側壁上環繞設置封裝層;其中,所述電路元件包括積體電路晶片,所述積體電路晶片具有接腳,所述積體電路晶片上設置所述接腳的一面為安裝面,所述電路元件側壁為所述積體電路晶片上與所述安裝面相鄰的壁; 生成熱介面材料層,所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面; 將第一面與所述電路元件及所述封裝層熱耦合,所述第二面與所述散熱片熱耦合。
- 如請求項12所述的製造方法,其中,所述生成熱介面材料層,所述熱介面材料層具有朝向所述電路元件及所述封裝層的第一面以及朝向所述散熱片的第二面,包含: 生成第一合金層; 由相互耦合的多個奈米金屬顆粒與中間混合物生成奈米金屬顆粒層,使所述中間混合物填充於所述多個奈米金屬顆粒之間; 生成第二合金層;及 使所述奈米金屬顆粒層分別與所述第一合金層及第二合金層熱耦合;其中,所述第一合金層背離所述奈米顆粒層一面為第一面,所述第二合金層背離所述奈米金屬顆粒層的一面為第二面。
- 如請求項13所述的製造方法,其中另包含使所述第一合金層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構,使所述奈米金屬顆粒之間的接觸處形成燒結連續相結構,且使所述第二合金層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。
- 如請求項13或14所述的製造方法,其中所述生成第一合金層包含:生成第一接著層及第一共燒結層,並使所述第一接著層與所述電路元件及所述封裝層熱耦合,使所述第一共燒結層與所述奈米金屬顆粒層耦合,且使所述第一共燒結層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。
- 如請求項13或14所述的製造方法,其中所述生成第二合金層包含:生成第二接著層及第二共燒結層,並使所述第二接著層與所述散熱片熱耦合,使所述第二共燒結層與所述奈米金屬顆粒層熱耦合,且使所述第二共燒結層與所述奈米金屬顆粒層的接觸處形成燒結連續相結構。
- 如請求項12-14所述的製造方法,其中所述在電路元件的側壁上環繞設置封裝層包括以塑封膜作為製造所述封裝層的材料,以在所述側壁上環繞設置所述封裝層。
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US20060285480A1 (en) * | 2005-06-21 | 2006-12-21 | Janofsky Eric B | Wireless local area network communications module and integrated chip package |
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-
2016
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-
2017
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